Hybrid-bonded crackstop structure with air gap

Abstract

The hybrid bonded semiconductor structure includes a first substrate and a second substrate each having a hybrid bonded interface, each substrate having a die portion and a crackstop structure adjacent to the die portion, one or more voids in the first substrate and the second substrate formed within or around a portion of the periphery of each crackstop structure, and at least some of the one or more voids in the first substrate and the second substrate substantially aligned to form a unified void with an air gap across the hybrid bond interface.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates generally to integrated circuit structures having crackstops, and more particularly to hybrid bonded structures having crackstops. [Background technology]

[0002] During the manufacturing process of integrated circuits on a wafer, operations such as dicing of the substrate and dielectric layers create external stresses that can cause microcracks during the manufacturing process. In addition, microcracks can exist or form from stresses due to internal factors. The microcracks can propagate in both the substrate and the dielectric layers, causing circuit failure. While crackstops are used to prevent the propagation of microcracks, hybrid bonded structures present additional challenges in preventing the propagation of microcracks, such as in areas where hybrid bonding occurs. Summary of the Invention

[0003] According to one embodiment, a hybrid bonded semiconductor structure includes a first substrate and a second substrate, each having a hybrid bonded interface. Each substrate has a die portion and a crackstop structure adjacent to the die portion. One or more voids in the first substrate and the second substrate are formed in or around a portion of the periphery of each crackstop structure. At least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a consolidated void with an air gap across the hybrid bond interface. The voids prevent the propagation of microcracks, particularly across the bonding interface, which could cause catastrophic failure of the semiconductor device.

[0004] In one embodiment, the crackstop structures of the first and second substrates are bonded at a hybrid bond interface. Extending the crackstop structures to the hybrid bond interface reduces the likelihood of microcracks propagating along the interface below the interface and damaging the die.

[0005] In one embodiment, at least some of the voids formed in each of the first and second substrates have different shapes, which can create air gaps of different volumes that can inhibit the propagation of microcracks.

[0006] In one embodiment, the one or more voids include a plurality of voids, at least some of which have different sizes, whereby voids of different sizes can aid in alignment, with some voids being more effective at preventing microcracks caused by internal stresses, while other sizes are more effective at preventing microcracks caused by external stresses, such as wafer dicing.

[0007] In one embodiment, multiple voids are arranged in a series that extends across the hybrid bond interface. The series of voids reduces the likelihood that a crack can bypass a single void.

[0008] In one embodiment, each hybrid bond interface includes a back-end-of-line (BEOL) interconnect level, and the integrated voids are at least partially filled with a dielectric or polysilicon material that is different from the material of the hybrid bond interface, where filling the voids with a dielectric has a different effect on preventing crack propagation.

[0009] In one embodiment, the one or more voids in the first and second substrates are ring-shaped. Different shapes provide different amounts of microcrack inhibition.

[0010] In one embodiment, the one or more voids in the first and second substrates are arranged as discontinuous rings with connected voids to control microcrack propagation.

[0011] In one embodiment, the one or more voids in the first and second substrates are circular. Circular voids may provide a larger surface area to stop the propagation of microcracks.

[0012] In one embodiment, one or more voids are filled with a material different from the material forming the crackstop structure and / or hybrid bonding interface. The voids provide an air gap to prevent microcracks. However, because the air gap is susceptible to temperature and humidity changes, filling the voids with a dielectric material may provide more stable operation.

[0013] In one embodiment, a first plurality of devices on a first substrate are connected to first pads, and a second plurality of devices on a second substrate are connected to second pads, the first and second pads being connected at a bonding interface, which provides an ideal means for forming hybrid bonds.

[0014] In one embodiment, the third substrate includes a die portion, a crackstop structure, and a hybrid bond interface. The hybrid bond interface of the third substrate faces the hybrid bond interface of the first substrate adjacent to the second substrate to form a hybrid bond with the first substrate. A structure having a base substrate and two additional substrate structures bonded to the base substrate may provide greater flexibility in the placement of voids for microcrack arrest.

[0015] According to one embodiment, a bonded semiconductor device includes a first wafer and a second wafer, each wafer having a bonding surface and a bond pad. A plurality of void patterns are formed in the first wafer and / or the second wafer adjacent to the bond pad. The first wafer and the second wafer are hybrid bonded to each other at the bond pad. The use of the void patterns can enhance the microcrack arrest capability of the semiconductor structure.

[0016] In one embodiment, at least some of the void patterns are formed on the bonding surfaces of the first wafer and / or the second wafer, and the placement of the void patterns on the bonding surfaces can inhibit microcrack propagation along the interface.

[0017] In one embodiment, the multiple void patterns alternate between the bonding surfaces of the first wafer and the second wafer, and the spread of the void pattern provides microcrack arrest over a larger area.

[0018] In one embodiment, at least some of the void patterns are located adjacent to the bond pads and are smaller than the height of the bond pads, with smaller void patterns being particularly effective against internal stresses.

[0019] In one embodiment, the bond pads are metallic bond pads and the void pattern has different depths into the back end of line (BEOL) stack of each of the bond surfaces, which can create air gaps of different sizes to inhibit micro-cracking from different stresses, such as internally generated stresses.

[0020] According to an embodiment, a method for fabricating a hybrid bonded crackstop structure with voids includes providing a first substrate and a second substrate, each of the first substrate and the second substrate including a die portion and at least one crackstop structure adjacent to the die portion. A hybrid bond interface is formed between top surfaces of the first substrate and the second substrate. The first substrate and the second substrate are hybrid bonded at the hybrid bond interface. One or more voids are patterned adjacent to the hybrid bond interface. Patterning the voids after the structure is hybrid bonded may facilitate easier construction than first creating voids in each of the first and second substrates.

[0021] In one embodiment, prior to hybrid bonding of the first and second substrates, a resist layer is placed on each hybrid bonding interface, and substantially aligned first voids are patterned on the top surface of the first substrate and second voids on the second substrate. The resist layer is then removed, and the first and second substrates are hybrid bonded. A single integrated void with an air gap is formed from the substantially aligned first and second voids. The single integrated void with an air gap extends across the hybrid bonding interface. This structure provides a means for aligning two void-containing structures to create the integrated void, preventing microcracks from propagating along the interface and damaging the die.

[0022] In one embodiment, a pattern of voids is created around each metallic bond pad by creating a topography on the surface of each substrate prior to hybrid bonding. A macroscopic hybrid bond pattern is created that includes metal pad surfaces bonded to metal pad surfaces, dielectric surfaces bonded to dielectric surfaces, and voids bonded to voids. The patterned voids can more effectively inhibit the propagation of microcracks. [Brief explanation of the drawings]

[0023] The drawings illustrate example embodiments. Not all embodiments are shown. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for a more effective illustration. Some embodiments may be practiced using additional components or steps and / or without all components or steps that are shown. The same reference numerals in different drawings refer to the same or similar components or steps.

[0024] [Figure 1A] 1 shows a bonded semiconductor structure having at least one microcrack.

[0025] [Figure 1B] 1 shows a hybrid bonded semiconductor structure with an enlarged portion of the hybrid bond junction showing the path of a microcrack.

[0026] [Figure 2] 1 illustrates a structure of a hybrid bond crackstop with voids for air gaps according to an example embodiment.

[0027] [Figure 3] 1 illustrates a structure of a hybrid bond crackstop having multiple voids for air gaps according to an example embodiment.

[0028] [Figure 4] 1 illustrates a hybrid bonded crackstop structure having multiple voids for air gaps and an extended crackstop structure according to an exemplary embodiment.

[0029] [Figure 5A] 1 illustrates various types of voids within a crackstop architecture of a hybrid bonded semiconductor structure, according to an example embodiment. [Figure 5B]1 illustrates various types of voids within a crackstop architecture of a hybrid bonded semiconductor structure, according to an example embodiment. [Figure 5C] 1 illustrates various types of voids within a crackstop architecture of a hybrid bonded semiconductor structure, according to an example embodiment.

[0030] [Figure 5D] 1 illustrates a continuous circular void pattern according to an example embodiment. [Figure 5E] 10 illustrates a dashed circle void pattern in accordance with an example embodiment. [Figure 5F] 1 illustrates a gridded circle void pattern in accordance with an example embodiment.

[0031] [Figure 5G] 5D according to an exemplary embodiment. [Figure 5H] 5E shows a rotated view of the arrangement of the patterns in FIG. 5E, according to an exemplary embodiment. [Figure 5I] 5F shows a rotated view of the arrangement of the patterns in FIG. 5F, according to an exemplary embodiment.

[0032] [Figure 5J] 10 illustrates another pattern with 3D and rotated views in accordance with an illustrative embodiment;

[0033] [Figure 6A] 10 illustrates a void pattern in each semiconductor bridging across the bonding interface according to the illustrated embodiment. [Figure 6B] 10 illustrates a void pattern in each semiconductor bridging across the bonding interface according to the illustrated embodiment.

[0034] [Figure 6C] 10 illustrates a gap etched across and out of the mating bond interface in accordance with an exemplary embodiment.

[0035] [Figure 6D] 10 illustrates an alternative placement of a new gap in the hybrid junction area, according to an example embodiment.

[0036] [Figure 7] 10A-10C illustrate various pattern configurations and hybrid bond pads having different types of voids incorporated into the bond pattern, according to exemplary embodiments.

[0037] [Figure 8] 1 illustrates a process flow for creating a semiconductor structure with hybrid junctions and voids to create air gaps, according to an example embodiment.

[0038] [Figure 9] 5 is a flowchart illustrating some of the operations for a method of making a semiconductor structure having hybrids and voids for air gaps, according to an example embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0039] In the following detailed description, numerous specific details are set forth by way of example to provide a thorough understanding of the relevant teachings. However, it should be understood that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components, and / or circuits have been described at a relatively high level without detailed description to avoid unnecessarily obscuring aspects of the present teachings. It should also be understood that the present disclosure is not limited to the depictions in the figures, as there may be fewer or more elements than shown and described.

[0040] In discussing the present technology, it may be useful to explain various notable terms. In one aspect, spatially related terms such as "front," "back," "top," "bottom," "below," "lower," "upper," "above," "side," "left," and "right" are used with reference to the orientation of the figures being described. Because components of the embodiments of the present disclosure can be positioned in many different orientations, directional terminology is used for illustrative purposes and is in no way limiting. It will therefore be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is rotated, elements described as "below" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, for example, the term "below" can encompass both an orientation that is above and an orientation that is below. The device may be oriented differently (rotated 90 degrees, viewed or referenced in other directions), and the spatially relative descriptors used herein should be interpreted accordingly.

[0041] As used herein, the terms "lateral" and "horizontal" describe an orientation parallel to the first surface of the chip.

[0042] As used herein, the term "vertical" describes an orientation that is disposed perpendicular to the first surface of the chip, chip carrier, or semiconductor body.

[0043] As used herein, the terms "coupled" and / or "electrically coupled" are not intended to imply that elements must be directly coupled together; intervening elements may be provided between "coupled" or "electrically coupled" elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. The term "electrically connected" refers to a low resistance electrical connection between elements that are electrically connected together.

[0044] Although terms such as "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not necessarily indicative of the actual shape of, or limiting the scope of, a region of a device.

[0046] It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments.

[0047] As used herein, certain terms are used to describe openings created to inhibit the development of microcracks. Those skilled in the art should understand that the terms void, cavity, and trench all refer to spaces at the bonding interface, substrate, or dielectric surface. For ease of explanation, this disclosure uses the term "void" throughout.

[0048] In this specification, terms such as first, second, and third may be used to describe various elements, but these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0049] Example embodiments are described herein with reference to schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not necessarily indicative of the actual shape of, or limiting the scope of, a region of a device.

[0050] It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. The description of the embodiments is not intended to be limiting. In particular, elements of the embodiments described below may be combined with elements of different embodiments. overview

[0051] The present disclosure presents structures and methods for hybrid bond crackstops with air gaps. The present disclosure also discloses structures and methods for hybrid bond interface with air gaps built into the pattern.

[0052] 1A shows an example of a bonded semiconductor structure 100A, in which a first substrate 101 and a second substrate 102 have respective dielectric layers 105, 110 thereon. The first substrate 101 and the second substrate 102 are bonded by a hybrid bond. An interface 115 exists at the bonding interface between two crackstops 125 and two rows of devices 120 (sometimes referred to as dies). In the current hybrid bond, an interface 115 exists at the junction / interface between the crackstops 125 (shown as dashed boxes) and between the two devices 120. As shown, this interface 115 may be enlarged in size by a microcrack 130, separating the first and second bonded substrates, or may serve as an access entry point from which the microcrack 130 may propagate, bypassing the crackstop 125 structure, to the stack of dies in the prime active area. The microcrack 130 shown in FIG. 1A can propagate far enough to reach the device 120, resulting in catastrophic die failure.

[0053] Embodiments of the present disclosure are directed to creating air gaps by placing trenches, cavities, or voids (hereinafter collectively referred to as "voids") across a hybrid bond to prevent crack propagation along the hybrid bond junction of two substrates. The voids can prevent / reduce crack initiation caused by both external stresses (e.g., from wafer dicing and from heat, humidity, and bonding pressure) and internal stresses (e.g., initial cracks from the manufacturing process), and can be placed in various sizes adjacent to the crackstop and device to prevent the propagation of microcracks. The growth and propagation of microcracks is prevented by the air gaps created by the voids.

[0054] 1B shows a hybrid bonded semiconductor 100B structure with an enlarged portion of the hybrid bond junction 135 showing the path of the microcrack 130. Although some crackstops 125 are present, the microcracks 130 can still propagate between the metal-to-metal and oxide-to-oxide junctions shown. Exemplary Architecture

[0055] Figure 2 shows a hybrid bond crackstop structure 200 with an air gap, according to an example embodiment. Similar to Figure 1A, the structure in Figure 2 shows a first substrate 101 and a second substrate 102 having dielectric layers 105, 110 thereon. The first substrate 101 and the second substrate 102 are bonded together by a hybrid bond. There is also an interface 115 (partially circled) at the bond interface between the two crackstops 125 and the two rows of devices 120.

[0056] 2, an example of a void 240 located across the junction between a first substrate and a second substrate is shown. The void 240 creates an air gap that prevents the microcrack 130 from propagating across the structure. The circle with the hatched portion indicates that the microcrack 130 is blocked and does not propagate further due to the void 240. Illustrative Embodiments

[0057] 3 shows a hybrid bond crackstop structure 300 with multiple voids for air gaps, according to an example embodiment. In FIG. 3, the basic concept of placing voids 240 across the hybrid bond junction is to remove material through which a crack can propagate and prevent its forward progression. Note that the crackstop 125 remains in front of the hybrid bond, and therefore, the voids 240 can prevent the crack from propagating along the hybrid bond, as shown in FIGS. 1B and 1C.

[0058] 4 shows a hybrid bond crackstop structure 400 having multiple voids for air gaps and an extended crackstop structure, according to an example embodiment. Figure 4 differs from Figure 3 at least in that the crackstops 125 of the first substrate 301 and the second substrate 301 are connected across the hybrid bond junction 135. However, the additional voids 240 add an extra measure of protection against the possibility of microcracks passing beyond the crackstops and damaging the device 120, because the air gaps created by the voids 240 along with the crackstops 125 arrest more cracks than the crackstops 125 alone.

[0059] 5A, 5B, and 5C illustrate various types of voids incorporated into a crackstop design surrounding the periphery of a hybrid-bonded semiconductor structure, according to an example embodiment. The voids shown are ring-shaped 545, discontinuous 547, and circular shaped 549. It should be understood that the present disclosure is not limited to only the voids shown and described, and the different shapes in FIGS. 5A, 5B, and 5C are presented for illustrative purposes.

[0060] Figures 5D, 5E, and 5F show continuous circle, dashed circle, and circle with grid void patterns according to example embodiments. Figure 5D shows a continuous circle void pattern. Figure 5E shows a non-continuous circle pattern 553. Figure 5F shows a circular pattern within a grid 555.

[0061] Figures 5G, 5H, and 51 show rotated views of the arrangement of the patterns in Figures 5D, 5E, and 5F, respectively, according to an exemplary embodiment. A continuous circle 5510 is shown in Figure 5G. Figure 5H shows a non-continuous pattern 5530. Figure 51 shows a circular pattern 5550 within a grid.

[0062] 5J shows a deformed circular void pattern 557 along with a three-dimensional view 557 and a rotated view 559, according to an example embodiment. Gaps in the circular pattern are shown in the rotated view 559.

[0063] Figures 6A and 6B show void patterns in each semiconductor build located within a bonded crackstop design, bridging across the mating bond interface and surrounding the periphery of the active device region of a hybrid-bonded adjacent semiconductor build. Figure 6A shows voids 240 patterned in each individual bonded semiconductor build to create a single, unified void bridging across the mating bond interface. Figure 6B shows voids 240 of different sizes to aid in alignment. In Figure 6B, two voids 240 appear to be connected, a small void and a large void, to form the unified void.

[0064] 6C shows an etched-out gap across the mating interface according to an example embodiment. Gap 640 is etched out across the mating interface after die-to-die bonding. The gap can be filled with underfill and / or overmold, etc.

[0065] 6D shows an alternative placement of the new gap in the hybrid junction area, according to an example embodiment. New gap 650 is placed in the hybrid junction area. Gap 650 can be, for example, etched into the hybrid junction area.

[0066] FIG. 7 shows a structure having various pattern arrangements and different types of voids positioned around and around the hybrid bond pads, according to an exemplary embodiment. It should be understood that in this embodiment, the voids are positioned around the electrically connected hybrid bond pads of the active device prime region. These voids are provided to address inherent defects resulting from the bonding process and the structure itself. While the previously shown and described voids addressed external extrinsic cracks / defects resulting from external forces, such as dicing, in contrast to voids addressing externally induced and / or extrinsic cracks / defects, the voids surrounding the die periphery surrounding the active prime region are more discrete and located around and around the active electrical connections of the device. The voids 240 have various shapes and patterns, each with a different air gap to prevent microcracks from both external and internal stresses. For example, structure 702 shows a symmetrically shaped void 240. Structure 704 shows a void 240 in which some portions have different sizes than others. Structure 706 shows that the voids are arranged in alternating orientations (compared to structure 704). The different sizes of the voids 240 shown in structures 702, 704, and 706 are intended to facilitate alignment of the hybrid bonded structures.

[0067] 7, the voids 240 in structure 708 are much thinner than the voids 240 in, for example, structures 702, 704, and 706. Structure 710 shows voids 240 located in only one of the bonded structures, while structure 712 shows an alternating arrangement.

[0068] Structures 714, 716, and 718 show voids 240 that have been partially etched in the top dielectric layer. For example, structure 714 has relatively shorter voids 240 than those used in structure 708. Structures 716 and 718 have a similar void placement than structures 710 and 712, but the voids 240 in structures 716 and 718 are shorter than those in structures 710 and 712. Example Process

[0069] Given the foregoing overview of an exemplary architecture, it may be beneficial to now provide a high-level discussion of an exemplary process. To that end, FIG. 8 is a process flow for creating a semiconductor structure with hybrid junctions and voids to create air gaps, according to an exemplary embodiment. FIG. 9 is a flowchart 900 illustrating some of the operations for a method of making a semiconductor structure with voids for hybrid junctions and air gaps, according to an exemplary embodiment. It should be understood that the process shown and described is provided for illustrative purposes, and the present disclosure is not limited to creating voids in the manner described in the process of FIG. 9. For example, voids may be created by other means (including, but not limited to, etching), and thus illustrates one particular, non-limiting technique or process flow that may be used.

[0070] Referring to Figure 8, structure 802 includes a substrate with a dielectric layer, crackstops, and devices on the substrate. Structure 804 shows a resist layer 855 added on top of the bonded junction. Structure 806 shows the resist layer 855 and a void 240 created in the underlying semiconductor. Structure 808 shows the resist layer 855 removed from the bonded junction. Structures 810 and 812 show a first substrate and a second substrate aligned with the void 240. Structure 814 shows a two-substrate structure that is hybrid bonded. The void 240 is shown bridging across the hybrid bonded junction.

[0071] FIG. 9 is illustrated as a collection of blocks in a logical order that represents the sequence of operations that may be implemented in combination.

[0072] In operation 902, a first substrate and a second substrate are provided, each of the first substrate and the second substrate including a die and at least one crackstop structure adjacent to a die portion. Figure 8 shows an example of a structure 802 having a die and a crackstop.

[0073] In operation 904, a hybrid bond interface is disposed on the top surfaces of the first substrate and the second substrate. The hybrid bond interface can be similar to the example shown in Figure 1B. The hybrid bond interface can have an oxide portion and a metallic portion.

[0074] A resist layer is placed at each hybrid bond interface in operation 906. Figure 8 shows resist layer 855 placed on the hybrid bond interfaces in structure 804.

[0075] In operation 908, first voids are patterned on the top surface of the first substrate, and second voids are patterned on the second substrate. The first voids and second voids are substantially aligned. Structures 810 and 812 show one non-limiting example of aligned substrates. It should be understood that operation 908 is optional. For example, the structures may be hybrid bonded in operation 910 (described below), and then voids may be etched into the substrates. Placing the voids after hybrid bonding may facilitate hybrid bonded structures with less alignment effort than if the voids were first patterned on the substrate surfaces before bonding.

[0076] The resist layer is removed and the first and second substrates are hybrid bonded in operation 910. Figure 8 shows structure 814, a hybrid bonded structure with a void disposed between the crackstops bridging the hybrid bond interface.

[0077] The method ends after operation 910. It should be understood that there may be additional voids of various sizes and locations located on the first and second substrates prior to the hybrid bonding operation. conclusion

[0078] The description of various embodiments of the present teachings has been presented for illustrative purposes and is not intended to be exhaustive or limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments over technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0079] While the foregoing describes what is considered to be the best mode and / or alternative embodiments, it is understood that various modifications may be made thereto, that the subject matter disclosed herein may be implemented in various forms and embodiments, and that the present teachings may be applied to numerous applications, only a few of which have been described herein. It is intended by the following claims to claim all such applications, modifications, and variations that fall within the true scope of the present teachings.

[0080] The components, operations, steps, features, objects, benefits, and advantages discussed herein are merely exemplary. Neither they nor the descriptions associated therewith are intended to limit the scope of protection. While various advantages have been discussed herein, it will be understood that not all embodiments necessarily include all advantages. Unless otherwise expressly stated, all measurements, values, ratings, positions, dimensions, sizes, and other specifications set forth in this specification, including the following claims, are approximate and not exact. They are intended to have a reasonable range consistent with the functions to which they relate and that which is customary in the art to which they pertain.

[0081] Numerous other embodiments are contemplated, including those having fewer, additional, and / or different components, steps, features, objects, benefits, and advantages, as well as those in which the components and / or steps are arranged and / or ordered differently.

[0082] While the foregoing has been described in conjunction with exemplary embodiments, it is understood that the term "exemplary" is meant merely as exemplary, not as best or optimal. Except as noted immediately above, nothing described or illustrated is intended to, or should be construed to, generally dedicate any component, step, feature, object, benefit, advantage, or the like, whether or not claimed.

[0083] Terms and phrases used herein will be understood to have the ordinary meanings ascribed to such terms and phrases with respect to their respective corresponding fields of study and research, unless otherwise specifically stated herein. Relative terms such as first, second, etc. may be used solely to distinguish one entity or act from another and do not necessarily require or imply an actual relationship or sequence between such entities or acts. The terms "comprises," "comprising," or other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements may include not only those elements, but also other elements not inherent in or expressly listed within such process, method, article, or apparatus. An element preceded by "a" or "an" does not, in the absence of further constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0084] An Abstract is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. It can also be seen that in the foregoing Detailed Description, various features are grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. a first substrate and a second substrate each having an interface joined by a hybrid bond; Each substrate includes a die portion and a crackstop structure adjacent to the die portion; and One or more voids formed around a portion of the periphery of each crack stop structure in the first substrate and the second substrate. wherein at least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a consolidated void having an air gap across the hybrid bond interface. Hybrid-bonded semiconductor structures.

2. The semiconductor structure of claim 1 , wherein the crackstop structures of the first substrate and the second substrate are bonded at the hybrid bond interface.

3. 10. The semiconductor structure of claim 1, wherein at least some of the voids formed in each of the first substrate and the second substrate have different shapes.

4. The semiconductor structure of claim 1 , wherein the one or more voids comprise a plurality of voids, at least some of which comprise different sizes.

5. The semiconductor structure of claim 1 further comprising a plurality of voids arranged in series extending across said hybrid bond interface.

6. Each hybrid bond interface includes a back-end-of-line (BEOL) interconnect level; The integrated void is at least partially filled with a dielectric or polysilicon material different from the material of the hybrid bond interface. The semiconductor structure of claim 1 .

7. The semiconductor structure of claim 1 , wherein the one or more voids in the first substrate and the second substrate are ring-shaped.

8. The semiconductor structure of claim 1 , wherein the one or more voids in the first substrate and the second substrate are arranged as non-continuous rings.

9. The semiconductor structure of claim 1 , wherein the one or more voids in the first substrate and the second substrate are circular in shape.

10. The semiconductor structure of claim 1 , wherein the one or more voids are filled with a material different from a material forming the crackstop structure and / or hybrid bond interface.

11. 10. The semiconductor structure of claim 1, further comprising: a first plurality of devices on the first substrate connected to first pads; and a second plurality of devices on the second substrate connected to second pads, the first pads and the second pads connected at the hybrid junction interface.

12. 10. The semiconductor structure of claim 1, further comprising a third substrate including a die portion, a crackstop structure, and a hybrid bond interface, wherein the hybrid bond interface of the third substrate faces the hybrid bond interface of the first substrate adjacent the second substrate to form a hybrid bond with the first substrate.

13. a first wafer and a second wafer, each wafer having a bonding surface and a bonding pad, and a plurality of void patterns formed in the first wafer and / or the second wafer adjacent to the bonding pad; The first wafer and the second wafer are hybrid bonded to each other at the bond pads. Bonded semiconductor devices.

14. The bonded semiconductor device of claim 13 , wherein at least some of the plurality of void patterns are formed on the bonding surfaces of the first wafer and / or the second wafer.

15. 14. The bonded semiconductor device of claim 13, wherein the plurality of void patterns alternate between the bonding surface of the first wafer and the bonding surface of the second wafer.

16. The bonded semiconductor device of claim 13 , wherein at least some of the void patterns are located adjacent to the bond pads and are smaller than the height of the bond pads.

17. the interface pads include metallic interface pads; The void patterns have different depths into a back end of line (BEOL) stack of each of the bonding surfaces. The bonded semiconductor device of claim 13.

18. providing a first substrate and a second substrate, each of the first substrate and the second substrate including a die portion and at least one crackstop structure adjacent to the die portion; disposing a hybrid bonding interface on top surfaces of the first substrate and the second substrate; hybrid bonding the first substrate and the second substrate; and patterning one or more voids adjacent to said hybrid bond interface; A method for manufacturing a hybrid bonded crackstop structure having a void, comprising:

19. Prior to the step of hybrid bonding of the first substrate and the second substrate: disposing a resist layer on each hybrid bond interface; patterning first voids in the top surface of the first substrate and second voids in the second substrate, wherein the first voids and the second voids are substantially aligned; removing the resist layer; and forming a single integrated void having an air gap from the substantially aligned first and second voids, wherein the single integrated void having an air gap extends across the hybrid bond interface.

20. The method of claim 18, further comprising:

20. Prior to the hybrid bonding step, patterning voids around individual metallic bond pads by creating a topography on the surface of each substrate; and creating a macroscopic hybrid bonding pattern including metal pad surfaces bonding to metal pad surfaces, dielectric surfaces bonding to dielectric surfaces, and voids bonding to voids; 20. The method of claim 18, further comprising:

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