Arithmetic device, arithmetic device load balancing method, and computer system

Abstract

The present invention relates to a computing device (1) including a processor unit (2) with a plurality of interacting processor cores (2.1), a plurality of storage elements (2.2) assigned to the processor cores (2.1), at least one first input interface (3) for receiving information processed by the processor cores (2.1), and at least one first output interface (4) for outputting information processed by the processor cores (2.1). The computing device according to the present invention is characterized in that the storage elements (2.2) are formed by dual-port RAM, each processor core (2.1) has exactly two inputs (E) for receiving information and exactly one output (1) for outputting information, each input (E) and each output (A) being formed by a storage element (2.2), and the physical distances (d) from each processor core (2.1) to the storage elements (2.2) connected to the processor core (2.1) are equal.

Description

[Technical Field]

[0001] The present invention relates to a computing device of the kind precisely defined in the preamble of claim 1, to a method for load balancing of such a computing device, and to a computer system comprising such a computing device.

[0002] A processor is a fundamental component of computer equipment. Processors exist in various forms, such as the central processing unit (CPU) of a PC, or as an integrated circuit in the form of a microprocessor or microcontroller in an embedded system. CPUs are characterized by a relatively small number of high-performance computing or processing cores, which allow the execution of relatively complex, CPU-intensive programs. Likewise, parallelization of program sequences is possible. CPUs are designed to solve a wide variety of tasks and problems.

[0003] Processors are also designed in the form of so-called graphics processors, or GPUs for short. Compared to CPUs, modern GPUs are characterized by a large number of computing cores, measured in the thousands per chip. These are relatively low-performance computing cores optimized for solving a small number of specialized tasks. GPUs are primarily used to calculate matrices and tensors, for example for graphics calculations or to provide / accelerate artificial intelligence. GPUs are therefore particularly suited to task parallel processing.

[0004] The provision of information to be processed by the processor core of the graphics processor, and in particular the connection to the CPU, is typically via a bus system such as PCI Express (PCIe). To process the corresponding information by the processor core of the graphics processor, this information must be temporarily stored before, during, and after processing. For this purpose, multiple internal and external processor storage elements (but located on a common printed circuit board) are known.

[0005] Typically, these storage elements are arranged in a two-dimensional structure within or on the graphics processor, with the individual components generally arranged at right angles. This results in different physical distances between the processor cores and the interfaces used to transmit information (e.g., the aforementioned storage elements, bus connections, and / or other processor cores). Therefore, more time is required to transmit information over correspondingly long data cables. This results in increased latency, which reduces the operating efficiency of the graphics processor.

[0006] US Patent Application Publication No. 2015 / 0255130 discloses a DDR4-SSD dual-port DIMM device. This device can be used as both a working memory and a main memory, i.e., a mass memory such as a hard disk or SSD. This device can be connected to the bus system of a mainboard via a RAM slot or a PCIe slot. The memory elements used are designed as dual-port memory elements, allowing simultaneous write and read access to the device from two host systems. Here, too, the memory elements are arranged along parallel or orthogonal lines, i.e., in a square or rectangle.

[0007] Furthermore, it is common for those skilled in the art to use computing units with multi-core processors to process multiple tasks in parallel and thus more efficiently. This is exemplified by the multi-core processor. Source: Wikipedia, the free encyclopedia. Last updated: September 4, 2022. URL: https: / / en.wikipedia.org / w / index.php?title=Multi-core_processor&oldid=1108514820.

[0008] A typical connection between memory elements and individual processor cores of a processor is well known, for example, from CPU caches. Source: Wikipedia, the free encyclopedia. Last updated: September 30, 2022. URL: https: / / en.wikipedia.org / w / index.php?title=CPU_cache&oldid=1113266567.

[0009] For example, it is common to maintain multi-level caches, where each processor core is assigned its own L1 cache, and multiple processor cores may share an L2 or L3 cache, where the corresponding cache may be designed as a multi-ported cache.

[0010] Furthermore, US Patent Application Publication No. 2009 / 0216924 discloses a composite system with processor cores arranged in a hexagonal honeycomb pattern.

[0011] Such an arrangement of processor cores is also known from US Patent Application Publication No. 2020 / 0243154.

[0012] The present invention aims to provide an improved computing device characterized by increased computing efficiency.

[0013] According to the invention, this object is achieved by a computing device with the features of claim 1. Advantageous embodiments and developments, as well as a method for load balancing a computing device and a computer system comprising such a computing device, result from the claims dependent on this independent claim.

[0014] The invention develops a general arithmetic device comprising a processor unit comprising a plurality of interacting processor cores and a plurality of storage elements assigned to the processor cores, and comprising at least one input interface (first input interface) for receiving information to be processed by the processor cores and at least one output interface (first output interface) for outputting information processed by the processor cores, wherein the storage elements are formed by dual-port RAMs, and each processor core has exactly two inputs for receiving information and exactly one output for outputting information and is connected to exactly three storage elements, the first two of which form one of the two inputs of the processor core and the third storage element forms the output of the processor core, the three storage elements being arranged around the processor core in a star shape at an angle of 120° to each other, and the physical distance from each processor core to the storage element connected to it is equidistant.

[0015] The computing device according to the present invention is based on the idea that the physical distance of the memory connections of each processor core is equalized, thereby making the distance between each processor core and the storage elements connected to it the same. Therefore, the time required to supply information to a processor core to be processed or to send processed information out of a processor core is the same for each processor core. This improves the efficiency of the processor unit, because information is passed from one processor core to another at the same speed. Therefore, a processor core receiving information from two processor cores located upstream in the data flow direction does not have to wait for information sent from the second processor core after receiving information from the first processor core, since the two pieces of information arrive simultaneously. This allows for particularly fast data processing.

[0016] The processor unit may be, for example, a central processing unit, abbreviated as CPU, or a graphics processor, abbreviated as GPU. The computing device may be a circuit board or a printed circuit board, such as a corresponding chip or card (e.g., a graphics card). The bottom of the processor unit may be square or rectangular. Any polygonal surface shape is also conceivable. In particular, the processor cores are designed identically and particularly preferably have the same geometric shape, i.e., the same geometric shape and the same surface area.

[0017] The computing device may be integrated into a higher-level computer system. The computing device and / or other components of the corresponding computer system may also have direct memory access, i.e., write access and / or read access, to the input or output interfaces. This is also called direct memory access (DMA).

[0018] Depending on the implementation, each processor core may process a fixed program, for example a program read from a read-only memory (ROM), which may be part of the computing device or a higher-level computer system, or the processor core may read and interpret information from a random access memory (RAM), thereby executing the code contained in the RAM as instructions.

[0019] Each processor core has two inputs and one output, and each function being processed can be executed directly in parallel, because each processor core can read two operands simultaneously.

[0020] According to the present invention, each processor core and the storage elements forming its two inputs and one output are arranged in a star shape on the processor unit, with the angle between each storage element being 120 degrees. This allows for a particularly effective distribution of the processor cores on the processor unit. By maintaining the solid angle between the storage elements at 120 degrees as described above, a symmetrical arrangement of the processor cores can be achieved, which makes it particularly easy to ensure that the physical distance between each storage element and the processor core is equal.

[0021] In this case, preferably, the six processor cores are arranged in a hexagonal honeycomb pattern on the processor unit. This allows the aforementioned 120-degree solid angle of each processor core relative to its respective storage element to be easily and reliably maintained while maintaining the same distance between the processor cores and the storage element. A further particular advantage here is that the length of the corresponding data cables can be reduced compared to embodiments known from the prior art, in particular compared to the longest data cable between a processor core in a rectangular arrangement and its assigned storage element. This allows for a further reduction in latency in data processing.

[0022] Individual processor cores of the same hexagonal honeycomb may be part of the adjacent hexagonal honeycomb. The distribution of processor cores on the processor unit can thus be likened to the honeycomb structure of a beehive. Particularly preferably, the processor unit also has a hexagonal honeycomb cross-section. This allows the processor unit to be designed particularly compact, while the individual processor cores can be sufficiently spaced apart from one another, ensuring a sufficiently large surface area for heat dissipation. This improves the thermal management of the computing device, making it possible to dispense with particularly large and complex cooling devices. Cooling can therefore be achieved by passive or simple active cooling devices.

[0023] A further advantageous embodiment of the computing device further comprises at least one input interface (first input interface) and at least one output interface (first output interface) formed by a dual-port RAM, with the at least one input interface (first input interface) forming an input for an input core arranged at the periphery of the interconnection chain of processor cores, and the at least one output interface (first output interface) forming an output for an output core arranged at the periphery of the interconnection chain. The input and output interfaces are readable or writable by the processor unit. Furthermore, further components of the computing device or further components of a computer system higher than the computing device can have write and / or read access to the input and output interfaces. Implemented as a dual-port RAM, simultaneous write or read access by the processor unit and corresponding other components is possible.

[0024] Preferably, at least one input interface (first input interface) and at least one output interface (first output interface) are arranged on two opposite sides of the processor unit. To solve a task, i.e. to process information, for example by executing a program, information is processed by the processor cores of the processor unit. To do this, the processor unit is provided with information via the input interface and the processed information is output at the output interface. This is a directed graph along which information is passed via the interconnected chain of processor cores. By arranging the input interface and the output interface at the two end points of the directed graph, a particularly easy and therefore quickly traversable directed graph can be constructed.

[0025] In a further advantageous embodiment of the computing device, the computing device is provided with at least one second input interface and / or at least one output interface. Thus, information can be fed in or out at multiple points in the data flow graph provided by the processor core. This facilitates parallelization of multiple tasks processed by the processor unit. The additional input or output interface may also be accessible via DMA.

[0026] According to a further advantageous embodiment of the computing device, the at least one second input interface and / or the at least one second output interface are arranged on a different side of the processor unit from the first input interface and the first output interface. The inventive structure of the computing device allows information to flow not only one-dimensionally along lines through the interconnected chain of processor cores, i.e., the corresponding directed data flow graph, but also two-dimensionally. This allows information to be fed into or fed out of the corresponding data flow graph, for example, at the center or at another intermediate position. This, on the one hand, allows the execution of particularly complex programs, and, on the other hand, allows for massive parallelization, since it is necessary to distribute a large number of relatively easily solvable tasks to a small number of processor cores, and therefore it is not necessary to integrate all processor cores of the data flow graph into one and the same task. This allows the corresponding additional processor cores to be used to solve additional tasks.

[0027] Thus, within the interconnected chain of processor cores within a processor unit, "islands" of linked processor cores can be created, each island handling a different task, with each island having separate input and output interfaces located to the side, allowing for separate information feeds and information feeds. These islands can also be referred to as groupings or clusters.

[0028] The geographical distribution of the processor cores grouped into islands on the processor unit is then adjusted to the complexity of the respective tasks. In this case, complex tasks requiring a relatively large number of processor cores can be located geographically in the central area of ​​the processor unit, since this area is far from connections to input and output interfaces and is therefore particularly suitable for tasks that do not require new information to be input into the processor chain over a long period of time or for numerous calculations, but only provide a result at the end. Next, simpler tasks can be appropriately located in processor islands located in the peripheral area of ​​the processor unit, which allows for easy input and output of information via the aforementioned input and output interfaces.

[0029] Furthermore, in an advantageous development of the invention, all processor cores are provided to operate at substantially the same clock rate, which further improves the efficiency of the computing device according to the invention. As already mentioned, the corresponding data cables for transferring information to the interconnection chain of processor cores are the same length, so that information is exchanged between the processor cores at the same speed. The processor cores themselves also have substantially the same clock rate, which further reduces the latency of data processing by the processor unit, assuming that each requires the same amount of time to process information to solve a task. If a processor core requires information from two upstream processor cores, these two upstream processor cores simultaneously receive and process input data, making the data available to the processor cores simultaneously for further processing.

[0030] Preferably, the processor cores are configured to alternate between a sleep mode and an active mode, with each processor core not processing information in the sleep mode and capable of processing information in the active mode. This allows for improving the energy efficiency of the processor unit. Depending on the complexity of the tasks to be processed, it may be necessary to have a certain number of processor cores participate in the tasks. If the execution time cannot be extended using additional processor cores or if no further tasks need to be solved, individual processor cores of the processor unit can be put into a sleep mode. As these processor cores are no longer "active", the energy consumption of the processor unit can be reduced.

[0031] According to the present invention, the load balancing method for a computing device described above is provided in which a compiler determines a usable data flow graph by connecting multiple processor cores of a processor unit, and then applies pattern matching according to the determined data flow graph to distribute the load of information processed by the processor cores to solve a task to each processor core. This achieves particularly even and efficient load balancing. Accordingly, the effectiveness of the computing device according to the present invention is further improved, since programs can be executed with particularly short execution times. Since each processor core has two inputs and one output, when the processor cores are arranged in a hexagonal honeycomb, the two inputs of two adjacent processor cores may partially overlap. This situation is appropriately taken into account by the compiler when determining the data flow graph, so that unidirectional information transfer through the data flow graph is avoided at this stage. Each storage element is designed as a dual-port RAM, allowing reading or writing from both sides. Therefore, two processor cores connected to each other via their inputs can be used to pass information within a single circuit within the interconnected chain of processor cores. This further improves the efficiency of the computing device according to the present invention, since no processor cores are left unused when processing information.

[0032] According to the present invention, the aforementioned computing device is integrated into a computer system. The computer system may be, for example, a PC, an embedded system, or another information technology system. The computing device according to the present invention may be implemented, for example, as a plug-in card for the main board of a PC. All currently available variations of connector connections and corresponding communication protocols are conceivable, such as a PCIe interface. The computer system may also be formed, for example, by a vehicle or a vehicle-integrated computing unit. The computing device according to the present invention can be used, in particular in connection with a vehicle, for accelerating artificial intelligence, for example using artificial neural networks. Thus, the computing device according to the present invention can be integrated into a vehicle to provide automated or autonomous driving functions.

[0033] Further advantageous embodiments of the computing device according to the invention will become apparent from the examples which are explained in more detail below with reference to the drawings. [Brief explanation of the drawings]

[0034] [Figure 1] 1 is a schematic diagram of a processor core with inputs and outputs each formed by a dual-port RAM. [Figure 2] 1 is a schematic diagram of a portion of multiple processor cores connected together to form an interconnect chain in the shape of a hexagonal honeycomb. [Figure 3] 1 is a schematic diagram of a computing device according to the present invention;

[0035] 1 shows the relative arrangement of a processor core 2.1 and a storage element 2.2 of a processor unit 2 shown in FIG. 3 of a computing device 1 according to the present invention. In this case, the exact shapes of the processor core 2.1 and the storage element 2.2 are merely symbolic. For example, the processor core 2.1 may have a shape other than circular, and the storage element 2.2 may have a shape other than rectangular.

[0036] Each processor core 2.1 of the processor unit 2 is connected to exactly three dual-port RAMs, two of which form inputs E for feeding information to the respective processor core 2.1, and one of which forms an output A for feeding information processed by the processor core 2.1.

[0037] As can be seen from FIG. 1, the storage elements 2.2 are arranged in a star shape, each at an angle α of 120°, around the respective processor core 2.1. The distance d between the processor core 2.1 and each storage element 2.2 is designed to be equidistant. Therefore, the distance d is the same for each storage element 2.2 shown in FIG. 1. Furthermore, according to the embodiment shown in FIG. 1, all storage elements 2.2 have the same length and, in particular, the same geometric shape. This allows the processor cores 2.1 and storage elements 2.2 to be symmetrically arranged on the processor unit 2 according to the specific pattern shown in FIG. 2.

[0038] Figure 2 shows multiple configurations of the processor cores 2.1 and storage elements 2.2. The processor cores 2.1 and storage elements 2.2 are interconnected in a hexagonal honeycomb pattern, forming a data flow graph. This structure has the advantage that the length of the data cable between each storage element 2.2 and the adjacent processor core 2.1 is the same, so the time required to transfer information from the storage element 2.2 to the processor core 2.1 is always the same. Furthermore, the processor core 2.1 can simultaneously read two different pieces of information, such as different variables, which facilitates parallel processing of various tasks.

[0039] In particular, all processor cores 2.1 calculate at the same clock rate, allowing for more efficient data processing. In particular, information is simultaneously provided to the individual processor cores 2.1 and processed by them simultaneously. Information can thus be simultaneously provided from a processor core 2.1 via its respective output A and simultaneously provided to each subsequent processor core 2.1 via its respective input E. A corresponding network or data flow graph formed by this concatenation of processor cores 2.1 can be traversed in a particularly efficient manner.

[0040] In Figure 2, the dots "..." indicate that the network of processor cores 2.1 and storage elements 2.2 continues to expand in a corresponding shape. In addition, the direction of data flow at each output A is indicated by small arrows, making it easier to see which output A is assigned to which processor core 2.1. For clarity, not all elements are labeled with reference numbers.

[0041] FIG. 3 shows a more comprehensive view of the computing device 1. Only the main components are shown. Common components, such as a memory controller, are omitted. FIG. 3 also shows an input interface 3 located on a first side S1 of the processor unit 2 and an output interface 4 located on a second, opposite side S2 of the processor unit 2. The input interface 3 and the output interface 4 are also formed by dual-port RAM. This allows simultaneous read and write access to the input interface 3 and the output interface 4 from both the processor unit 2 and a higher-level computing unit of the computing device 1. This higher-level computing unit or computer system has direct memory access or direct memory access (DMA) to the aforementioned interfaces, such as the input interface 3 shown in FIG. 3. To control the computing device 1, the corresponding computer system does not need to bypass a main processor, such as a CPU, and can provide information directly to the computing device 1 without bypassing the CPU. This further improves the execution time of the tasks to be performed, i.e., the programs.

[0042] In this case, the processor cores 2.1 located at the ends of the interconnection chain of processor cores 2.1, i.e., on the periphery, may be connected directly to the respective input interface 3 or output interface 4, i.e., without an intermediate storage element 2.2, as shown in Figure 3. The processor core 2.1 directly connected to the input interface 3 is also called input core 2.E, and the processor core 2.1 directly connected to the output interface 4 is also called output core 2.A. Any number of processor cores 2.1 can be connected to each input interface 3 or output interface 4, for example, one, two, three, four, or more processor cores 2.1.

[0043] Furthermore, the computing device 1 may include at least one second input interface 3.2 and / or at least one second output interface 4.2. In particular, the second input interface 3.2 and the second output interface 4.2 may be located on sides S3 and S4, which are different from the first and second sides S1 and S2. Alternatively, multiple second input interfaces 3.2 or output interfaces 4.2 may be located on the same side. This facilitates the provision or transmission of information even in intermediate regions of the interconnection chain of the processor cores 2.1. The interconnection chain of the processor cores 2.1 is also connected to the respective second input interfaces 3.2 and second output interfaces 4.2 (not shown) via the input core 2.E and output core 2.A. [Prior art documents] [Patent documents]

[0044] [Patent Document 1] US Patent Application Publication No. 2015 / 0255130 [Patent Document 2] US Patent Application Publication No. 2009 / 0216924 [Non-patent literature]

[0045] [Non-Patent Document 1] Free encyclopedia "Wikipedia" [Searched on September 4, 2022], Internet<URL:https: / / en.wikipedia.org / w / index.php?title=Multi-core_processor&oldid=1108514820.> [Non-patent document 2] Free encyclopedia "Wikipedia" [Searched on September 30, 2022], Internet<URL:https: / / en.wikipedia.org / w / index.php?title=CPU_cache&oldid=1113266567.>

Claims

1. A computing device (1) comprising a processor unit (2) with a plurality of interacting processor cores (2.1), a plurality of storage elements (2.2) assigned to said processor cores (2.1), at least one first input interface (3) for receiving information to be processed by said processor cores (2.1), and at least one first output interface (4) for outputting information processed by said processor cores (2.1), The memory element (2.2) is formed by a dual-port RAM (Random Access Memory), Each of said processor cores (2.1) has exactly two inputs (E) for receiving information and exactly one output (A) for outputting information, and is connected to exactly three of said storage elements (2.2); The first two of these three storage elements (2.2) each form one of the two inputs (E) of the processor core (2.1), and the third storage element (2.2) forms the output (A) of the processor core (2.1). The three storage elements (2.2) are arranged around the processor core (2.1) in a star shape at angles of 120° to each other, and the physical distance (d) from each processor core (2.1) to the storage element (2.2) connected to the processor core (2.1) is equal. A computing device (1).

2. The six processor cores (2.1) are arranged in a hexagonal honeycomb pattern on the processor unit (2). A computing device (1) according to claim 1, characterized in that it

3. At least one of the first input interfaces (3) and at least one of the first output interfaces (4) are formed by a dual-port RAM, At least one of the first input interfaces (3) forms an input (E) of an input core (2.E) arranged on the periphery of an interconnection chain connecting a plurality of the processor cores (2.1), At least one of the first output interfaces (4) forms an output (A) of an output core (2.A) arranged on the periphery of the interconnection chain. A computing device (1) according to claim 1 or 2, characterized in that it

4. The at least one first input interface (3) and the at least one first output interface (4) are arranged on two opposite sides (S1, S2) of the processor unit (2). A computing device (1) according to any one of claims 1 to 3, characterized in that it

5. At least one second input interface (3.2) and / or at least one second output interface (4.2) A computing device (1) according to any one of claims 1 to 4, characterized in that it

6. At least one of the second input interfaces (3.2) and / or at least one of the second output interfaces (4.2) In the processor unit (2), the first input interface (3) and the first output interface (4) are arranged on different sides (S3, S4). A computing device (1) according to claim 5, characterized in that it

7. All of said processor cores (2.1) operate at substantially the same clock rate. A computing device (1) according to any one of claims 1 to 6, characterized in that it

8. The processor cores (2.1) are configured to alternate between a sleep mode and an active mode, and each processor core (2.1) does not process information in the sleep mode and can process information in the active mode. A computing device (1) according to any one of claims 1 to 7, characterized in that it

9. A load balancing method for a computing device (1) according to any one of claims 1 to 8, comprising: The compiler determines a data flow graph that can be used by connecting the multiple processor cores (2.1) of the processor unit (2), and distributes the load distribution of information to be processed by the processor cores (2.1) to solve a task to each of the processor cores (2.1) by applying pattern matching according to the determined data flow graph. A method characterized by:

10. Equipped with at least one computing device (1) according to any one of claims 1 to 8 A computer system comprising:

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