Method for producing porous silicon structures

Abstract

The present disclosure provides methods for fabricating porous silicon structures with controlled size, shape, and porosity by using a series of protective layers and selective etching steps. An advantage of the methods disclosed herein is that they may provide micro- and nano-fabrication methods that can provide porous silicon structures with more tightly controlled size, shape, and porosity by avoiding inadvertent etching of portions of the silicon structure during the fabrication process.

Description

[Technical Field]

[0001] Government support This invention was made with government support under grants W81XWH-12-1-0414 and W81XWH-17-1-0389 from the Department of Defense, and U54CA151668 from the National Institutes of Health. The government has certain rights in this invention.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This PCT application claims priority to U.S. Provisional Patent Application No. 63 / 409,601, filed September 23, 2022, which is incorporated by reference in its entirety.

[0003] The present disclosure relates generally to the field of micro- and nano-fabrication of porous silicon structures for applications in micro- and nanomedicine, such as drug delivery. [Background technology]

[0004] In the field of micromedicine and nanomedicine, particles can be designed to circumvent the limitations of traditional drug delivery. For example, porous silicon particles and porous silica particles have several applications, including being used as drug delivery carriers. These particles have been the subject of inventive research due to their biocompatibility, biodegradability, ease of fabrication, tunable nanostructures, and porous networks. For example, porous silicon particles and methods for their preparation are disclosed in the following documents: U.S. Patent Nos. 10,253,424, 6,355,270 and 6,107,102; U.S. Patent Publication No. 2006 / 0251562; Chiappini et al., Phys. Status Solidi, C, Current Topics in Solid State Physics, 8(6), 1826-1832 (2010); Cohen et al., Biomedical Microdevices 5:3, 253-259 (2003); Meade et al., Advanced Materials, 16(20), 1811-1814 (2004); Thomas et al., Lab Chip, 6, 782-787 (2006); Meade et al., phys.stat.sol. (RRL) 1(2), R71-R-73 (2007); Salonen et al. al., Journal of Pharmaceutical Sciences 97(2), 632-653 (2008); Salonen et al., Journal of Controlled Release 108, 362-374 (2005). However, the development of porous silicon particles for applications in nanomedicine is only as good as the ability to control size, shape, and porosity.

[0005] To date, conventional microfabrication methods have several limitations, such as deformation of the shape and size of the resulting porous silicon structures.

[0006] There is a need to develop new and improved methods for preparing porous silicon structures that can avoid or reduce accidental deformation or loss of control during fabrication. Summary of the Invention

[0007] The present disclosure provides a method for fabricating a porous silicon structure. In some embodiments, the method for fabricating a porous silicon structure includes providing a silicon substrate having a silicon surface; forming a first protective layer on the silicon surface, the first protective layer having a protective layer surface; depositing a second protective layer on the protective layer surface; patterning the second protective layer to form protected and unprotected regions on the first protective layer surface; performing a first etch of the unprotected regions of the first protective layer to form first protective layer pillars; and performing a second etch of the silicon substrate to form silicon pillars. forming a silicon pillar located below the first protective layer pillar, the silicon pillar having a silicon pillar top, a silicon pillar sidewall, a silicon pillar height, and a silicon pillar width, wherein adjacent silicon pillar sidewalls are separated by a silicon trench having a silicon pillar spacing; depositing a dielectric layer to cover the first protective layer pillar, the silicon pillar sidewall, and the silicon trench; exposing the dielectric layer to a third etch to remove a portion of the dielectric layer from the top of the protective layer pillar and pattern the dielectric layer; and exposing the protective layer pillar to a fourth etch to remove the protective layer pillar.

[0008] In some embodiments, the silicon surface comprises boron. In some embodiments, the first protective layer comprises silicon oxide, aluminum oxide, chromium, nickel, copper, or any combination thereof. In some embodiments, the second protective layer comprises photoresist. In some embodiments, the dielectric layer comprises silicon nitride.

[0009] In some embodiments, the first protective pillar has a protective pillar width of about 200 nm to about 5.0 micrometers and a protective pillar height of about 100 nm to about 600 nm, hi some embodiments, the first protective pillar has a protective pillar width of about 600 nm to about 4.0 micrometers and a protective pillar height of about 150 nm to about 500 nm.

[0010] In some embodiments, the silicon pillar height is about 2.0 micrometers to about 50.0 micrometers, the silicon pillar width is about 200 nm to about 5.0 micrometers, and the silicon pillar spacing is about 200 nm to about 1000 nm. In some embodiments, the silicon pillar height is about 6.0 micrometers to about 15.0 micrometers, the silicon pillar width is about 600 nm to about 4.0 micrometers, and the silicon pillar spacing is about 300 nm to about 800 nm.

[0011] In some embodiments, the ratio of silicon pillar height to silicon pillar spacing is between about 60:1 and about 20:1, in some embodiments, the ratio of silicon pillar height to silicon pillar spacing is between about 55:1 and about 45:1.

[0012] In some embodiments, the method further comprises forming porous silicon pillars by applying a current to the silicon substrate. In some embodiments, the method further comprises forming porous silicon pillars by applying a current to the silicon substrate through a solution in an electrolytic cell, the current being about 1 mA / cm. 2 ~about 50mA / cm 2 has a current density of

[0013] In some embodiments, the method further comprises forming a porous silicon structure by removing the dielectric layer. In some embodiments, the method further comprises forming the porous silicon structure and separating the porous silicon structure from the silicon substrate by applying a current to the silicon substrate. In some embodiments, the current is about 100 mA / cm.2 ~about 200mA / cm 2 A current having a current density in the range of 0.1 to 1.5 is applied to the silicon substrate while the silicon substrate is immersed in a fifth etching solution comprising HF.

[0014] In some embodiments, the first protective layer comprises silicon oxide, and the first etch comprises etching in an atmosphere of CF4 and / or CHF3, or exposing the unprotected areas of the first protective layer to a first etchant comprising HF, NH4HF, NaF, KF, or any combination or mixture thereof. In some embodiments, the first protective layer comprises aluminum oxide, and the first etch comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HF, NH4OH, tetramethylammonium hydroxide, H3PO, Br2, or any combination or mixture thereof. In some embodiments, the first protective layer comprises chromium, and the first etch comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HO, HCl, H2SO4, and HO, or any combination or mixture thereof. In some embodiments, the first protective layer comprises nickel, and the first etch comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HNO, FeCl, Ce(NH)(NO), HF, and HO, HPO, or any combination or mixture thereof. In some embodiments, the first protective layer comprises copper, and the first etch comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HNO, FeCl, KCN, HO, or any combination or mixture thereof.

[0015] In some embodiments, the second etch comprises reactive ion etching. In some embodiments, the second etch comprises reactive ion etching in an atmosphere of SF. In some embodiments, the second etch comprises inductively coupled plasma reactive ion etching. In some embodiments, the second etch comprises inductively coupled plasma reactive ion etching in an atmosphere of SF.

[0016] In some embodiments, the third etch comprises a reactive ion etch. In some embodiments, the third etch comprises a reactive ion etch in an atmosphere of CF4, CHF3, or SF6.

[0017] In some embodiments, the fourth etch includes exposing the first protective layer pillar to a fourth etchant. In some embodiments, the first protective layer pillar includes silicon oxide, and the fourth etchant includes HF, NHHF, NaF, KF, or any combination or mixture thereof. In some embodiments, the first protective layer pillar includes aluminum oxide, and the fourth etchant includes HF, NHOH, HPO, Br, or any combination or mixture thereof. In some embodiments, the first protective layer pillar includes chromium, and the fourth etchant includes NaOH, HO, HCl, or any combination or mixture thereof. In some embodiments, the first protective layer pillar includes nickel, and the fourth etchant includes HNO, FeCl, Ce(NH)(NO), HF, HPO, or any combination or mixture thereof. In some embodiments, the first protective layer pillars comprise copper and the fourth etchant comprises HNO, FeCl, KCN, HO, or any combination or mixture thereof. In some embodiments, the first etchant and the second etchant are the same or different.

[0018] In some embodiments, the porous silicon structure has a first side, a second side, and a side surface, and at least one of the first side and the second side is planar or flat. In some embodiments, the porous silicon structure has a first side, a second side, and a side surface, and at least one of the first side or the second side has a longest side measurement across the first side or the second side of about 500 nm to about 5.0 micrometers, or the side surface has a longest side measurement across the side of about 100 nm to about 800 nm, or any combination thereof.

[0019] In some embodiments, between about 30% and 100% of the porous silicon structures within the sample are characterized as having a first side, a second side, and a side surface, where at least one of the first side and the second side is planar or flat. In some embodiments, between about 30% and 100% of the porous silicon structures within the sample are characterized as having a first side, a second side, and a side surface, where at least one of the first side or the second side has a longest side average measurement across the first side or the second side of between about 500 nm and about 5.0 micrometers, or the side surface has a longest side average measurement across the side of between about 100 nm and about 800 nm, or any combination thereof.

[0020] In some embodiments, the first protective layer is deposited by chemical vapor deposition, physical vapor deposition, vacuum deposition, sputtering, or by heating the silicon substrate to a temperature of about 800°C to about 1,200°C. In some embodiments, the second protective layer is deposited by spin coating or spraying. In some embodiments, the dielectric layer is deposited by chemical vapor deposition. [Brief explanation of the drawings]

[0021] The foregoing summary, as well as the following detailed description of the embodiments, will be better understood when read in conjunction with the accompanying drawings. For purposes of illustration, there are shown in the drawings certain embodiments which may be preferred. It should be understood that the embodiments shown are not limited to the precise details shown. Unless otherwise indicated, the drawings are not to scale.

[0022] [Figure 1] 1 shows a schematic diagram of a conventional method for fabricating a porous silicon structure. [Figure 2] 1A and 1B illustrate a schematic representation of a portion of one embodiment of a method for making a porous microstructure according to the present disclosure. [Figure 3] We conclude by presenting an embodiment of a method for fabricating the porous microstructure shown in FIG. [Figure 4] A-D show exemplary scanning electron microscope (SEM) images of silicon pillars and porous silicon structures with modified shapes and sizes prepared according to conventional methods, as shown in FIG. [Figure 5] 1A-D show exemplary SEM images of silicon pillars and porous silicon structures with controlled shapes prepared according to embodiments of the disclosed methods. DETAILED DESCRIPTION OF THE INVENTION

[0023] All measurements are in standard metric units unless otherwise stated.

[0024] Unless otherwise stated, all instances of the words "a," "an," or "the" may refer to one or more of the words they modify.

[0025] Unless otherwise specified, the phrase "at least one of" means one or more of the objects. For example, "at least one of the first surface and the second surface is flat" means either a single first surface is flat, two or more first surfaces are flat, one second surface is flat, two or more second surfaces are flat, or any combination thereof.

[0026] Unless otherwise specified, the term "about" refers to ±10% of a stated non-percentage numerical value, rounded to the nearest numerical value to the stated precision. For example, about 105.3 mm includes 94.8 to 115.8 mm. Unless otherwise specified, the term "about" refers to ±5% of a percentage numerical value. For example, about 20% includes 15 to 25%. When the term "about" is used in relation to a range, it refers to the appropriate amount less than the lower limit and more than the upper limit. For example, about 100 mm to about 200 mm would include 90 mm to 220 mm.

[0027] Unless otherwise specified, when a range of numbers refers to numbers that are easily and routinely changed in a laboratory environment, such as weight, mass, concentration, temperature, charge density, or pressure, the range of numbers or measurements may be all values ​​within that range. For example, 100 mA / cm 2 ~about 200mA / cm 2 The range includes 105, 110, 120, 130, 140, 150, 160, 170, 180, 190, and any subranges / numbers therein.

[0028] Unless otherwise specified, the terms "for example" or "eg," as used herein, are used merely as examples and should not be construed as limiting the disclosure to only those items expressly mentioned herein.

[0029] Unless otherwise specified, the term "microparticle" means a particle having a maximum characteristic size of less than 1000 microns and a minimum characteristic size of greater than 50 nm.

[0030] Unless otherwise specified, the term "micron" means "micrometer" and the term "microns" means "micrometers." These terms are interchangeable.

[0031] Unless otherwise specified, "nanoporous" or "nanopores" refers to pores having an average size of less than 1 micron.

[0032] Unless otherwise specified, "biodegradable" refers to a material that can be dissolved or broken down in a physiological medium or a biocompatible polymeric material that can be broken down under physiological conditions by physiological enzymes and / or chemical conditions.

[0033] Unless otherwise specified, "structure" refers to particles having a maximum characteristic size of less than about 1000 microns, or less than about 100 microns, preferably less than about 10 microns. The porous silicon structures of the present disclosure should have a relatively high porosity to allow loading of the active agent into the pores of the porous silicon structure.

[0034] Unless otherwise specified, all reactions, procedures, and preparations were or can be carried out at normal temperature and pressure, i.e., 20° C. and 1 atmosphere.

[0035] Unless otherwise stated, all elements may be abbreviated using their atomic symbol, for example, platinum may be designated as Pt.

[0036] Unless otherwise specified, the terms "provide," "provided," or "providing" refer to the supplying, producing, purchasing, manufacturing, assembling, forming, selecting, configuring, converting, introducing, adding to, or incorporating any element, amount, component, reagent, quantity, measurement, or analysis of any method or system of any embodiment herein.

[0037] Unless otherwise stated, properties (height, width, length, ratios, etc.) described herein are understood to be averaged measurements.

[0038] The conventional method for preparing porous silicon structures uses conventional microfabrication methods to generate porous microstructures from crystalline silicon wafers, which are the silicon wafers used throughout the semiconductor industry. In fact, the final step in the conventional method for generating porous microstructures is to form nanopores and then separate the porous microstructure from the silicon wafer by applying a strong electric current in an HF solution.

[0039] However, as explained in more detail below, during this final step of generating porous microstructures from the silicon wafer, i.e., the application of electric current in the HF bath, the silicon microstructure formation process has been found to be sensitive to defects due to the shape of the pillars, so that even minor defects in the shape, surface, or edge of the pillars can cause unintended deformations in the generated porous microstructures. These size and shape defects can then significantly limit the usefulness of the porous microstructures as drug delivery carriers.

[0040] More specifically, conventional methods for preparing porous silicon structures have several limitations, including the fact that the porous silicon structures obtained by following such conventional methods are deformed in shape and size. As illustrated in FIG. 1 , such a conventional manufacturing method 100 includes obtaining a silicon substrate 102, such as a silicon wafer, and depositing a protective layer 104, such as a photoresist. Using conventional photolithography, the protective layer 104 can be patterned to provide protected regions 106 that cover the underlying silicon substrate and unprotected regions 108 that expose the silicon substrate for further processing. In theory, the unprotected regions can be safely etched using an anisotropic or directionally selective etching technique, such as reactive ion etching (RIE), without etching the protected regions. In FIG. 1 , an anisotropic etching technique is applied to the unprotected regions 108 of the silicon substrate 102 to form silicon pillars 110 beneath the protected regions 106 of the protective layer 104. The protective layer 104 on top of the silicon pillars 110 may then be removed by applying a suitable stripping process, such as dissolving the photoresist using a compatible solvent. A dielectric layer 112, such as silicon nitride, may then be added to the entire surface of the substrate, coating the silicon pillars 110 and the spaces 114 between them.

[0041] Ideally, the dielectric layer 112 is carefully etched using inductively coupled plasma reactive ion etching (RIE) to selectively remove the dielectric material covering the tops of the silicon pillars while leaving the dielectric material filling the sidewalls and spaces between the pillars. A successful step leaves a dielectric layer surrounding each silicon pillar, connected across the entire surface of the silicon substrate. Next, a mixture of hydrofluoric acid (HF) and ethanol (3:7 v / v) is used to etch the silicon pillars at an applied current density of 80 mA / cm. 2Electrochemical etching is then performed at 0 V for 25 seconds to form the first porous layer 116 and the second porous layer 118, and more as needed. Once pores of the desired size, shape, and density are created, a higher current density can be applied to widen the porous band until the silicon microstructures can be separated from one another. Finally, the dielectric material can be removed using a suitable or compatible stripping agent, e.g., hot phosphoric acid for silicon nitride, allowing the silicon pillars to be completely separated into a group porous silicon microstructure 120 or smaller, individual porous microstructures 122 for further processing.

[0042] However, referring to FIG. 1 , it has been discovered that the top or upper surface of the silicon pillars 104 becomes distorted during the RIE etching during the removal of the protective layer 104 and / or the removal of the dielectric layer 112. In particular, the edges at the top of the silicon pillars 124 become rounded instead of remaining sharp. Upon application of current, this defect at the top of the pillars propagates defects within the forming silicon microstructure as a deformed band of pores forms through the silicon pillars. FIG. 4A shows a scanning electron microscope (SEM) image of silicon pillars covered with a first protective layer, i.e., photoresist. It can be seen that the photoresist is thicker in the center of each pillar and thinner toward the sides. After the RIE etching is performed and the photoresist is removed, the top of the silicon pillars has deformed, rounded edges, as shown in FIG. 4B. This small defect, the rounded edges of the defective rounded top shape, was found to propagate into significantly deformed bands of pores formed in the silicon pillar (shown in Figure 4C). These deformed pore bands produce the deformed silicon microstructure shown in Figure 4D. While such deformations may appear small and subtle, these deformed shapes exhibit top edges or spikes, thereby rendering them unusable for drug delivery. This is because the top edges or spikes could cause the microstructures to clump within blood vessels or damage blood vessels by severing them.

[0043] Disclosed herein is a method that solves the above-mentioned problems associated with conventional methods by providing a sequence of adding and removing protective layers to provide a porous silicon structure without any deformation to its shape, size, and structure.

[0044] 2 , in an embodiment of the method disclosed herein, manufacturing method 200A includes obtaining a silicon substrate 202. A first protective layer 204 including silicon dioxide is deposited on the silicon surface (top) of the silicon substrate 202 in a deposition step 250. Next, a second protective layer 206 is deposited on the protective layer surface (top) of the first protective layer 204 in a second deposition step 252. The second protective layer 206 may be photoresist. Next, the second protective layer 206 is patterned during a patterning step 254 to form protected regions 208 and unprotected regions 210 on the protective layer surface of the first protective layer 202 using conventional photolithography to provide a defined shape and dimension of the silicon structure to be fabricated.

[0045] A first etching step 256 is performed on the unprotected regions 210 of the first protective layer 204 to form first protective layer pillars 212 beneath the protected regions 208. The first etching step 256 uses an etchant that is compatible with the first protective layer material selection. For example, if the first protective layer is silicon oxide, the first etching step can be performed by reactive ion etching in an atmosphere of CF4 and / or CHF3, or by contacting the first protective layer with a solution including HF, NH4HF, NaF, KF, or any combination or mixture thereof.

[0046] A second etching step 258 is then performed on the silicon substrate in the exposed unprotected areas 210 to form silicon pillars 214 directly below the first protective layer pillars 212. Before or after the second etching step, the second protective layer 206 on top of the first protective layer pillars 212 may be removed in a removal step 260 by applying an appropriate treatment to remove the protective layer. In this example, if the second protective layer is photoresist, a solvent or developer provided by the photoresist manufacturer may be used to remove the second protective layer.

[0047] Referring to Figure 3, an embodiment of the method 200B disclosed herein is shown, which continues from the method 200A shown in Figure 2. As illustrated in Figure 3, a silicon pillar 214 is located below the first protective layer pillar 212 and has a silicon pillar top 218, a silicon pillar sidewall 220, a silicon pillar height 222, and a silicon pillar width 224. Additionally, adjacent silicon pillar sidewalls are separated by a silicon trench 216 having a silicon pillar spacing 228.

[0048] As illustrated in FIG. 3 , a dielectric layer 226 is deposited on the first protective layer pillar 212, the silicon pillar sidewall 220, and the silicon trench 216 in a deposition step 262. The dielectric layer 226 includes a material capable of conducting and directing current through the silicon pillar, such as silicon nitride. In a third etching step 264, the dielectric layer 226 is removed from the top of the first protective layer pillar 212 by exposing the dielectric layer 226 to a selective etching step, such as reactive ion etching (RIE) with inductively coupled plasma. After removing the dielectric layer from the top of the first protective layer pillar, the dielectric layer 226 remains intact, covering the silicon pillar sidewall 220 and the silicon trench 216. Next, the first protective layer pillar 212 is removed by exposing the first protective layer pillar 212 to an etch (fourth etching step 266). The fourth etch also needs to be compatible with the type of material used for the first protective layer. In this example, the first protective layer is silicon dioxide, therefore a compatible etching medium such as an HF bath is used to selectively remove the first protective layer pillars without removing the silicon nitride layer.

[0049] Thereafter, a current (e.g., a DC current) is applied to the silicon substrate 202 in a pore-forming step 268 through a solution in an electrolytic bath to obtain a porous silicon pillar 230, which contains a band of horizontal nanopores 232 therein. The applied DC current may be, for example, about 1 mA / cm. 2 ~about 50mA / cm 2 The current density may be selected to form pores of a desired size, such as a current density of about 100 mA / cm. The porous silicon pillars 230 may then be formed by applying a higher current density, for example, about 100 mA / cm. 2 ~about 200mA / cm 2to form a porous silicon structure, and the silicon substrate is immersed in an etchant such as HF. The steps of applying a current with a lower current density and a current with a higher current density can be repeated a desired number of times to form a periodic layered or stacked porous silicon structure 236 including multiple first porous layers 238 (i.e., porous silicon structures) separated by second porous layers 232 or distinct porous silicon microstructures 240.

[0050] In a dielectric layer removal step 270, the porous silicon structures 236 may be released into solution by removing the dielectric layer that held them on the surface of the silicon substrate. The dielectric layer removal step 270 or release step may be assisted by mechanical means, such as by subjecting the silicon substrate 202 with the stack to ultrasonic vibrations.

[0051] 5A-5D show exemplary SEM images of silicon pillars and porous silicon structures with defined shapes (flat or planar top surfaces and flat or planar bottom surfaces) and sizes prepared according to the methods of the present disclosure. As can be seen from FIGS. 5A and 5B, the tops of the silicon pillars are adequately protected by the first protective layer. This difference in the shape and surface of the tops of the pillars, when subjected to the pore-forming step, produces porous silicon structures with flat or planar top surfaces and flat or planar bottom surfaces of standard sizes, as shown in FIGS. 5C and 5D.

[0052] The present disclosure provides methods for fabricating a porous silicon structure. In some embodiments, the method for fabricating a porous silicon structure includes providing a silicon substrate having a silicon surface. In some embodiments, the method for fabricating a porous silicon structure includes forming a first protective layer on the silicon surface, the first protective layer having a protective layer surface. In some embodiments, the method for fabricating a porous silicon structure includes depositing a second protective layer on the protective layer surface. In some embodiments, the method for fabricating a porous silicon structure includes forming protected and unprotected regions on the first protective layer surface by patterning the second protective layer. In some embodiments, the method for fabricating a porous silicon structure includes forming first protective layer pillars by performing a first etch of the unprotected regions of the first protective layer. In some embodiments, the method for fabricating a porous silicon structure includes forming silicon pillars by performing a second etch of the silicon substrate, the silicon pillars being located below the first protective layer pillars, the silicon pillars having a silicon pillar top, silicon pillar sidewalls, a silicon pillar height, and a silicon pillar width, and adjacent silicon pillar sidewalls being separated by a silicon trench having a silicon pillar spacing. In some embodiments, the method for fabricating a porous silicon structure includes depositing a dielectric layer to cover the first protective layer pillar, the silicon pillar sidewall, and the silicon trench. In some embodiments, the method for fabricating a porous silicon structure includes patterning the dielectric layer by exposing the dielectric layer to a third etch to remove portions of the dielectric layer from above the protective layer pillar. In some embodiments, the method for fabricating a porous silicon structure includes removing the protective layer pillar by exposing the protective layer pillar to a fourth etch.

[0053] In some embodiments, in this method, the silicon substrate has at least one flat surface (usually a polished surface of the silicon surface) on which one or more layers can be patterned. In some embodiments, the substrate is a crystalline substrate, such as a wafer. In particular embodiments, the substrate may be a semiconductor substrate, i.e., a substrate comprising one or more semiconductor materials, such as silicon. In some embodiments, the surface of the substrate may be optionally roughened by treatments such as KOH immersion or reactive ion etching (RIE). In some embodiments, roughening the surface may help remove or prevent the formation of a nucleation layer at the surface. In some embodiments, the silicon substrate may be etched by wet etching techniques, such as electrochemical etching. In some embodiments, the properties of the substrate, such as doping level, resistivity, and surface crystallographic orientation, can be selected to obtain the desired characteristics of the pores. In some embodiments, the substrate is a heavily doped p-type silicon substrate having a resistivity in the range of about 0.003 ohm-cm to about 0.007 ohm-cm. ++ In some embodiments, the silicon surface comprises boron.

[0054] In some embodiments, the first protective layer comprises silicon oxide, aluminum oxide, chromium, nickel, copper, or any combination thereof. In some embodiments, the second protective layer comprises photoresist. In some embodiments, the dielectric layer comprises silicon nitride.

[0055] In some embodiments, the first protective pillar has a protective pillar width of about 200 nm to about 5.0 micrometers. In some embodiments, the first protective pillar has a protective pillar width of about 300 nm to about 4.8 micrometers, including about 400 nm to about 4.6 micrometers, including about 500 nm to about 4.4 micrometers, including about 550 nm to about 4.2 micrometers, or about 600 nm to about 4.2 micrometers. In some embodiments, the first protective pillar has a protective pillar width of about 600 nm to about 4.0 micrometers.

[0056] In some embodiments, the first protective pillar has a protective pillar height of about 100 nm to about 600 nm. In some embodiments, the first protective pillar has a protective pillar height of about 120 nm to about 550 nm, including about 140 nm to about 520 nm, including about 180 nm to about 450 nm, or including about 200 nm to about 400 nm. In some embodiments, the first protective pillar has a protective pillar height of about 150 nm to about 500 nm.

[0057] In some embodiments, the silicon pillar height is about 2.0 micrometers to about 50.0 micrometers. In some embodiments, the silicon pillar height is about 3.0 micrometers to about 45.0 micrometers, including about 4.0 micrometers to about 40.0 micrometers, including about 4.0 micrometers to about 35.0 micrometers, or including about 5.0 micrometers to about 25.0 micrometers. In some embodiments, the silicon pillar height is about 6.0 micrometers to about 15.0 micrometers.

[0058] In some embodiments, the silicon pillar width is about 200 nm to about 5.0 micrometers. In some embodiments, the silicon pillar width is about 300 nm to about 4.8 micrometers, including about 400 nm to about 4.6 micrometers, including about 500 nm to about 4.4 micrometers, including about 550 nm to about 4.2 micrometers, or including about 600 nm to about 4.2 micrometers. In some embodiments, the silicon pillar height is about 600 nm to about 4.0 micrometers.

[0059] In some embodiments, the silicon pillar spacing is about 200 nm to about 1000 nm. In some embodiments, the silicon pillar spacing is about 220 nm to about 980 nm, including about 230 nm to about 950 nm, about 250 nm to about 900 nm, about 270 nm to about 880 nm, or about 290 nm to about 850 nm. In some embodiments, the silicon pillar spacing is about 300 nm to about 800 nm. The silicon pillar spacing is important because it controls the ability of the dielectric layer to form a uniform coating between the silicon pillars for the final pore formation step. Silicon pillar spacings less than about 200 nanometers result in non-uniform dielectric layers and uncontrollable pore size and deformation of the silicon structure. Silicon pillar spacings greater than 1000 nanometers result in a low number of microstructures produced for the amount of work put into the process, making it impractical.

[0060] In some embodiments, the ratio of silicon pillar height to silicon pillar spacing is about 60:1 to about 20:1. In some embodiments, the ratio of silicon pillar height to silicon pillar spacing is about 55:1 to about 45:1. In some embodiments, the ratio of silicon pillar height to silicon pillar spacing is about 55:1 to about 25:1, including about 52:1 to about 48:1, about 50:1 to about 30:1, or about 45:1 to about 35:1. An advantage of the ratio of silicon pillar height to silicon pillar spacing is that it can provide more porous silicon structures per unit area, thereby controlling the number of particles formed per area of ​​high aspect ratio silicon substrates. This ratio is also important because it controls the ability of the dielectric layer to form a uniform coating between the silicon pillars for the final pore formation step. A ratio of silicon pillar height to silicon pillar spacing greater than 60:1 can result in non-uniform dielectric layers and uncontrollable pore size and deformation of the silicon structures. A silicon pillar height to silicon pillar spacing ratio below 20:1 produces too few microstructures for the amount of work put in and becomes impractical.

[0061] The formation of porous silicon pillars or porous silicon structures, including various porous layers, can be formed on a substrate using several techniques. In some embodiments of the present method, the porous layers are formed using wet etching techniques, i.e., by exposing the substrate to an etching solution including at least one etching solution, such as a strong acid. In some embodiments of the present method, the formation of the porous layers is carried out using an electrochemical etching process, during which an etching current is passed through the substrate. Electrochemical etching of silicon substrates to form porous silicon layers is described in detail, for example, in U.S. Pat. No. 8,920,625. In some embodiments, the present method includes electrochemically etching the silicon substrate using an etching solution including water and / or ethanol in addition to HF.

[0062] In some embodiments, during the electrochemical etching process, the silicon substrate serves as one of the electrodes. For example, during electrochemical etching of silicon, the silicon substrate may serve as the anode, and the cathode may be an inert metal such as platinum (Pt). In such cases, a porous layer is formed on the side of the silicon substrate facing away from the inert metal cathode. Furthermore, in some other embodiments, during electrochemical etching, the silicon substrate may be placed between two electrodes, and each electrode may comprise an inert metal or a noble metal.

[0063] In some embodiments of the present method, the electrochemical etching process can be carried out in a reactor or cell that is resistant to the etchant. For example, if the etchant is HF, the electrochemical etching process can be carried out in a reactor or cell that includes an HF-resistant material. Examples of HF-resistant materials include fluoropolymers such as polytetrafluoroethylene (PTFE). In some embodiments of the present method, the electrochemical etching can be carried out by monitoring the current at one of the electrodes, for example, by monitoring the anodic current (galvanostatically) or voltage (potentially). In some embodiments, it may be preferable to perform the electrochemical etching at a constant current density, which may allow for better control of the formed porous layer properties and / or better reproducibility between samples.

[0064] In some embodiments, if it is desired to form two different stable porous regions, two different constant currents can be applied. For example, a first current density can be applied to form a first porous layer, and then a second current density can be applied to form a second porous layer, which can differ in pore size and / or porosity from the first porous layer.

[0065] In some embodiments, parameters of the formed porous layer, and thus of the respective parameters of the fabricated structure, such as pore size, porosity, thickness, pore profile and / or pore shape, can be adjusted by selecting parameters of the electrochemical etching process, such as the concentration and composition of the etching solution, the applied current (and potential), the etching time, the temperature, the stirring conditions, the presence or absence of illumination (and parameters of the illumination, such as intensity and wavelength), and parameters of the etched substrate, such as the composition of the substrate, the resistivity of the substrate, the crystallographic orientation of the substrate, and the level and type of doping of the substrate.

[0066] In some embodiments, the pores in the formed porous layer have a predetermined longitudinal profile that is perpendicular or substantially perpendicular to the surface of the substrate. Such a longitudinal profile can be created by varying the current density during electrochemical etching. For longitudinal pores in the porous layer, both the porosity and the pore size can be varied. Thus, in some embodiments, the profiled pores in the porous layer and the fabricated porous substrate can have smaller sizes at the top, i.e., at the substrate surface, and larger pores at the bottom, i.e., deeper in the substrate. Furthermore, in some embodiments, the profiled pores in the porous layer and the fabricated porous substrate can have larger sizes at the top and smaller sizes at the bottom. In some embodiments, the profiled pores in the porous layer and the fabricated substrate can also have different porosities at the top and bottom.

[0067] In many embodiments, the electrochemical etching can begin with a short, higher current pulse to prevent or reduce the formation of a nucleation layer. In some embodiments of the present method, the nucleation layer can also be removed by etching the nucleation layer after the porous layer is formed. Such etching can be performed by a dry etching technique, such as RIE. In some embodiments, appropriate steps can be taken to protect the underlying region. For example, a photoresist can be placed on the surface, solidified by baking, and then a plasma etch can be applied to expose the portion of the surface of the substrate that needs to be etched.

[0068] For electrochemical etching, the backside of the substrate, i.e., the side of the substrate opposite the side on which the porous layer is formed, can be coated with a conductive layer, such as a metal layer, to ensure electrical contact. Such conductive layers can be coated using several techniques, including thermal evaporation and sputtering.

[0069] During electrochemical etching, the etching solution can initiate pore formation through the formation of a nucleation layer, which is a surface layer of the substrate whose pores have properties different from the desired properties of the porous layer. The nucleation layer can be characterized by irregularities in its pore properties and associated surface roughness, which can be on a scale larger than the pore size.

[0070] In many applications, a nucleation layer on the surface of porous particles is undesirable. For example, when silicon porous particles are used to support smaller particles inside them, a nucleation layer on the surface of the larger particles can reduce the support efficiency. In some embodiments, the nucleation layer is removed or prevented from forming. In some embodiments, during electrochemical etching, a larger current can be applied before applying a current to generate the desired pores in the porous layer to prevent the formation of the nucleation layer. Furthermore, in some embodiments, after the formation of the porous layer, the nucleation layer can be removed by dry etching such as RIE.

[0071] In some embodiments of the present method, for example, patterning on the surface of the substrate using the second protective layer can be performed using any of several techniques, such as lithography techniques, such as photolithography, X-ray lithography, deep UV lithography, nanoimprint lithography, or dip-pen lithography. In some embodiments, the photolithography technique can be, for example, contact aligner lithography, scanner lithography, or immersion lens lithography. In the case of photolithography or molding, different masks can be used to design structures having several predetermined regular shapes, i.e., non-random shapes, such as spheres, squares, rectangles, ellipses, disks, and hemispheres. In some embodiments, patterning can be used to define the lateral shape and dimensions of the particles, i.e., the shape and dimensions of the particles in a cross section parallel to the surface of the substrate. If the formation of the porous layer occurs before patterning, the lateral dimensions of the fabricated structure are substantially the same as the lateral dimensions of the patterned features. When patterning occurs prior to the formation of the porous layer, the lateral dimensions of the fabricated structures may be larger than the lateral dimensions of the patterned features. Patterning can produce structures with predetermined, regular, i.e., non-random, lateral shapes. For example, in photolithographic patterning, masks of various shapes can be used to produce the desired predetermined shape, while in nanoimprint lithography, molds or stamps of various shapes can be used for the same purpose. The predetermined, non-random lateral shape of the structures is not particularly limited. For example, the structures can have circular, square, polygonal, and elliptical shapes. In some embodiments, the porous silicon structures have shapes including, but not limited to, hemispherical, bowl-shaped, frustum-shaped, pyramidal, disc-shaped, etc.

[0072] In some embodiments, the porous silicon structure may be released from the substrate after the patterning and porous layer formation steps via electropolishing, which may involve applying a sufficiently high current density to the substrate. Furthermore, in some embodiments, releasing the porous silicon structure from the substrate may involve the formation of an additional porous layer having greater porosity than the already formed porous layer. This highly porous layer is referred to as an release layer. The release layer may have a sufficiently large porosity so that it can be easily broken when desired using mechanical techniques, such as, for example, exposing the substrate to ultrasonic energy. At the same time, the release layer may be strong enough to hold the previously formed porous layer intact with the substrate.

[0073] Any of several techniques can be used to modify the surface properties of the structure, i.e., the surface properties of the outer surface of the structure and / or the surface properties of the pores of the structure. In many embodiments, surface modification of the fabricated structure can be performed while the structure is still intact with the substrate before it is released. Types of surface modification of the structure include, but are not limited to, chemical modification, including polymer modification and oxidation; plasma treatment; metal or metal ion coating; chemical vapor deposition (CVD) coating, physical vapor deposition (PVD); atomic layer deposition (ALD); evaporated and sputtered films, and ion implantation. In some embodiments, the surface treatment is biological, as opposed to biomedical targeted and controlled degradation.

[0074] Surface modification of the structure can be performed before the structure is released from the substrate, allowing for asymmetric surface modification. Asymmetric surface modification means that the surface modification on one side of the structure is different from the surface modification on the other side of the structure. For example, one side of the structure's surface can be modified, while the other side of the structure's surface can remain unmodified. For example, the pores of the structure can be completely or partially filled with a sacrificial material, such as a sacrificial photoresist. Thus, only the outer surface of the structure is processed during surface modification. After selective removal of the sacrificial material, only the outer surface of the structure is modified, i.e., the pore surfaces of the structure remain unmodified. In some embodiments, the outer surface can be patterned, for example, by photolithography, so that one portion of the outer surface can have one modification and another portion of the outer surface can have a different modification.

[0075] In some embodiments, the method further comprises forming porous silicon pillars by applying an electric current to the silicon substrate. In some embodiments, the method further comprises forming porous silicon pillars or porous silicon structures by applying an electric current to the silicon substrate through a solution in an electrolytic bath. In some embodiments, the electric current is about 1 mA / cm 2 ~about 50mA / cm 2 In some embodiments, the current density is about 8 mA / cm 2 ~about 40mA / cm 2 Including, approximately 2mA / cm 2 ~about 40mA / cm 2 Including, approximately 10mA / cm 2 ~Approx. 35mA / cm 2 or about 5mA / cm 2 ~about 30mA / cm 2 Including, approximately 5mA / cm 2 ~Approx. 45mA / cm 2 has a current density of

[0076] In some embodiments, the method further comprises forming a porous silicon structure by removing the dielectric layer. In some embodiments, the method further comprises forming the porous silicon structure and separating the porous silicon structure from the silicon substrate by applying a current to the silicon substrate. In some embodiments, the current is about 100 mA / cm 2 ~about 200mA / cm 2 while the silicon substrate is immersed in a fifth etchant containing HF.

[0077] In some embodiments, the first protective layer is deposited by chemical vapor deposition, physical vapor deposition, vacuum deposition, sputtering, or by heating the silicon substrate to a temperature of about 800°C to about 1,200°C. In some embodiments, the second protective layer, such as a photoresist, is deposited by spin coating or spraying. In some embodiments, the dielectric layer is deposited by chemical vapor deposition.

[0078] In some embodiments, the first protective layer comprises silicon oxide, and the first etch comprises reactive ion etching in an atmosphere of CF4 and / or CHF3, or comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HF, NH4HF, NaF, KF, or any combination or mixture thereof. In some embodiments, the first protective layer comprises aluminum oxide, and the first etch comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HF, NH4OH, tetramethylammonium hydroxide, H3PO, Br2, or any combination or mixture thereof. In some embodiments, the first protective layer comprises chromium, and the first etch comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HO, HCl, H2SO4, and HO2, or any combination or mixture thereof. In some embodiments, the first protective layer comprises nickel, and the first etch comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HNO, FeCl, Ce(NH)(NO), HF, and HO, HPO, or any combination or mixture thereof. In some embodiments, the first protective layer comprises copper, and the first etch comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HNO, FeCl, KCN, HO, or any combination or mixture thereof.

[0079] In some embodiments, the second etch comprises reactive ion etching. In some embodiments, the second etch comprises reactive ion etching in an atmosphere of SF. In some embodiments, the second etch comprises inductively coupled plasma reactive ion etching. In some embodiments, the second etch comprises inductively coupled plasma reactive ion etching in an atmosphere of SF.

[0080] In some embodiments, the third etch comprises a reactive ion etch. In some embodiments, the third etch comprises a reactive ion etch in an atmosphere of CF4, CHF3, or SF6.

[0081] In some embodiments, the fourth etch includes exposing the first protective layer pillar to a fourth etchant. In some embodiments, the first protective layer pillar includes silicon oxide, and the fourth etchant includes HF, NHHF, NaF, KF, or any combination or mixture thereof. In some embodiments, the first protective layer pillar includes aluminum oxide, and the fourth etchant includes HF, NHOH, HPO, Br, or any combination or mixture thereof. In some embodiments, the first protective layer pillar includes chromium, and the fourth etchant includes NaOH, HO, HCl, or any combination or mixture thereof. In some embodiments, the first protective layer pillar includes nickel, and the fourth etchant includes HNO, FeCl, Ce(NH)(NO), HF, HPO, or any combination or mixture thereof. In some embodiments, the first protective layer pillar includes copper, and the fourth etchant includes HNO, FeCl, KCN, HO, or any combination or mixture thereof. In some embodiments, the first etchant and the second etchant are the same or different.

[0082] In some embodiments, the porous silicon structure has a first side, a second side, and a side surface, and at least one of the first side and the second side is planar or flat. In some embodiments, the porous silicon structure has a first side, a second side, and a side surface, and at least one of the first side or the second side has a longest side measurement across the first side or the second side of about 500 nm to about 5.0 micrometers, or the side surface has a longest side measurement across the side of about 100 nm to about 800 nm, or any combination thereof.

[0083] In some embodiments, between about 30% and 100% of the porous silicon structures within the sample are characterized as having a first side, a second side, and a side surface, where at least one of the first side and the second side is planar or flat. In some embodiments, between about 30% and 100% of the porous silicon structures within the sample are characterized as having a first side, a second side, and a side surface, where at least one of the first side or the second side has a longest side average measurement across the first side or the second side of between about 500 nm and about 5.0 micrometers, or the side surface has a longest side average measurement across the side of between about 100 nm and about 800 nm, or any combination thereof.

[0084] In general, porous silicon substrates can be bioinert, bioactive, or biodegradable depending on their porosity and pore size, and the rate or speed of biodegradation of porous silicon can depend on its porosity and pore size.

[0085] In some embodiments, the substrate may be a top-down fabricated substrate, i.e., a substrate produced using top-down microfabrication or nanofabrication techniques such as photolithography, electron beam lithography, X-ray lithography, deep UV lithography, nanoimprint lithography, or dip-pen nanolithography. Such fabrication methods may allow for the scale-up production of particles that are uniform or substantially identical in dimensions.

[0086] In some embodiments, the maximum feature size of the porous silicon structure may be less than about 100 microns, or less than about 50 microns, or less than about 20 microns, or less than about 10 microns, or less than about 5 microns, or less than about 4 microns, or less than about 3 microns, or less than about 2 microns, or less than about 1 micron. Further, in some embodiments, the maximum feature size of the porous silicon structure may be between 500 nm and 3 microns, or between 700 nm and 2 microns. Further, in some embodiments, the maximum feature size of the structure may be greater than about 2 microns, or greater than about 5 microns, or greater than about 10 microns.

[0087] In some embodiments, the porous silicon structure has a pore size of about 1 nm to about 1 micron, or about 1 nm to about 800 nm, or about 1 nm to about 500 nm, or about 1 nm to about 300 nm, or about 1 nm to about 200 nm, or about 2 nm to about 100 nm. In some embodiments, the pores in the porous silicon structure can be straight pores or sponge pores.

[0088] In some embodiments, the first porous layer can have a different pore size than the second porous layer, i.e., the pore size of the pores in the first porous layer can be larger than the pore size in the second layer, or vice versa. For example, the pore size in one of the first and second porous layers can be at least 2 times, or at least 5 times, or at least 10 times, or at least 20 times, or at least 50 times, or 2 to 50 times, or 5 to 50 times, or 2 to 20 times, or 5 to 20 times larger than the pore size in the other of the first and second porous layers.

[0089] In many embodiments, at least one of the first and second porous layers can be a nanoporous layer, and in certain embodiments, both the first and second porous layers can be nanoporous layers.

[0090] In some embodiments, the pore size in at least one of the first and second porous layers can be from about 1 nm to about 1 micron, or from about 1 nm to about 800 nm, or from about 1 nm to about 500 nm, or from about 1 nm to about 300 nm, or from about 1 nm to about 200 nm, or from about 2 nm to about 100 nm.

[0091] In some embodiments, at least one of the first and second porous layers can have an average pore size of 1 micron or less, or 800 nm or less, or 500 nm or less, or 300 nm or less, or 200 nm or less, or 100 nm or less, or 80 nm or less, or 50 nm or less. In some embodiments, both the first and second porous layers can each have an average pore size of 1 micron or less, or 800 nm or less, or 500 nm or less, or 300 nm or less, or 200 nm or less, or 100 nm or less, or 80 nm or less, or 50 nm or less. In some embodiments, at least one of the first and second porous layers can have an average pore size of about 10 to about 60 nm or about 20 to about 40 nm.

[0092] In some embodiments, at least one of the first and second porous layers can have an average pore size of about 1 nm to about 10 nm, or about 3 nm to about 10 nm, or about 3 nm to about 7 nm.

[0093] In some embodiments, one of the first and second porous layers may have an average pore size of about 10 to about 60 nm, or about 20 to about 40 nm, and the other of the first and second porous layers may have an average pore size of about 1 nm to about 10 nm, or about 3 nm to about 10 nm, or about 3 nm to about 7 nm.

[0094] In some embodiments, the pores of the first porous layer and the second porous layer may have similar or substantially similar orientations, but different average sizes.

[0095] Further description of the embodiments

[0096] Embodiment 1. 1. A method for manufacturing a porous silicon structure, comprising: providing a silicon substrate having a silicon surface; forming a first protective layer on the silicon surface, the first protective layer having a protective layer surface; depositing a second protective layer on the protective layer surface; patterning the second protective layer to form protected and unprotected regions on a surface of the first protective layer; forming first protective layer pillars by performing a first etch of unprotected areas of the first protective layer; forming silicon pillars by performing a second etching of the silicon substrate, the silicon pillars being located below the first protective layer pillars, the silicon pillars having a silicon pillar top, a silicon pillar sidewall, a silicon pillar height, and a silicon pillar width, and adjacent silicon pillar sidewalls being separated by a silicon trench having a silicon pillar spacing; depositing a dielectric layer to cover the first protective layer pillar, the silicon pillar sidewall, and the silicon trench; patterning the dielectric layer by exposing the dielectric layer to a third etch to remove portions of the dielectric layer from above the protective layer pillars; removing the protective layer pillars by exposing the protective layer pillars to a fourth etch.

[0097] Embodiment 2. forming porous silicon pillars by applying an electric current to a silicon substrate; or applying a current to the silicon substrate through a solution in an electrolytic bath to form porous silicon pillars, the current being about 1 mA / cm 2 ~about 50mA / cm 2 16. The method according to one or more of embodiments 1-15, wherein the current density is

[0098] Embodiment 3. forming a porous silicon structure by removing the dielectric layer; or To form a porous silicon structure, the silicon substrate is immersed in a fifth etching solution containing HF at a current of about 100 mA / cm. 2 ~about 200mA / cm 2 16. The method according to one or more of embodiments 1-15, further comprising separating the porous silicon structure from the silicon substrate by applying a current of

[0099] Embodiment 4. the silicon surface contains boron; or the first protective layer comprises silicon oxide, aluminum oxide, chromium, nickel, copper, or any combination thereof; or the second protective layer comprises a photoresist; or 16. The method according to one or more of embodiments 1-15, wherein the dielectric layer comprises silicon nitride.

[0100] Embodiment 5. the first protective pillar has a protective pillar width of about 200 nm to about 5.0 micrometers and a protective pillar height of about 100 nm to about 600 nm; or 16. The method of one or more of embodiments 1-15, wherein the first protective pillar has a protective pillar width of about 600 nm to about 4.0 micrometers and a protective pillar height of about 150 nm to about 500 nm.

[0101] Embodiment 6. the silicon pillar height is between about 2.0 micrometers and about 50.0 micrometers, the silicon pillar width is between about 200 nm and about 5.0 micrometers, and the silicon pillar spacing is between about 200 nm and about 1000 nm; or 16. The method according to one or more of embodiments 1 to 15, wherein the silicon pillar height is from about 6.0 micrometers to about 15.0 micrometers, the silicon pillar width is from about 600 nm to about 4.0 micrometers, and the silicon pillar spacing is from about 300 nm to about 800 nm.

[0102] Embodiment 7. the ratio of silicon pillar height to silicon pillar spacing is from about 60:1 to about 20:1; or 16. The method according to one or more of embodiments 1-15, wherein the ratio of silicon pillar height to silicon pillar spacing is from about 55:1 to about 45:1.

[0103] Embodiment 8. the first protective layer comprises silicon oxide, and the first etch comprises reactive ion etching in an atmosphere of CF4 and / or CHF3, or comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HF, NH4HF, NaF, KF, or any combination or mixture thereof; or the first protective layer comprises aluminum oxide, and the first etch comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HF, NH4OH, tetramethylammonium hydroxide, H3PO, Br2, or any combination or mixture thereof; or the first protective layer comprises chromium, and the first etch comprises exposing the unprotected areas of the first protective layer to a first etchant comprising H2O2, HCl, H2SO4, and H2O2, or any combination or mixture thereof; or the first protective layer comprises nickel, and the first etch comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HNO, FeCl, Ce(NH)(NO), HF, and H0, HPO, or any combination or mixture thereof; or 16. The method of one or more of embodiments 1-15, wherein the first protective layer comprises copper, and the first etch comprises exposing the unprotected areas of the first protective layer to a first etchant comprising HNO, FeCl, KCN, HO, or any combination or mixture thereof.

[0104] Embodiment 9. The second etch comprises a reactive ion etch; or the second etch comprises an inductively coupled plasma reactive ion etch; or The second etch comprises reactive ion etching in an atmosphere of SF6; or 16. The method according to one or more of embodiments 1-15, wherein the second etching comprises inductively coupled plasma reactive ion etching under an atmosphere of SF6.

[0105] Embodiment 10. 16. The method according to one or more of embodiments 1-15, wherein the third etching comprises reactive ion etching; or the third etching comprises reactive ion etching under an atmosphere of CF, CHF, or SF.

[0106] Embodiment 11. the fourth etching includes exposing the first protective layer pillars to a fourth etchant; the first protective layer pillars comprise silicon oxide and the fourth etchant comprises HF, NH4HF, NaF, KF, or any combination or mixture thereof; or the first protective layer pillars comprise aluminum oxide and the fourth etchant comprises HF, NH4OH, H3PO, Br2, or any combination or mixture thereof; the first protective layer pillars comprise chromium; and the fourth etchant comprises NaOH, HO, HCl, or any combination or mixture thereof; the first protective layer pillars comprise nickel and the fourth etching solution comprises HNO, FeCl, Ce(NH)(NO), HF, HPO, or any combination or mixture thereof; or the first protective layer pillar comprises copper and the fourth etchant comprises HNO3, FeCl3, KCN, H2O2, or any combination or mixture thereof; or 16. The method according to one or more of embodiments 1 to 15, wherein the first etching solution and the second etching solution are the same or different.

[0107] Embodiment 12. the porous silicon structure has a first end, a second end, and a side surface, and at least one of the first surface and the second surface is planar or flat; or 16. The method of one or more of embodiments 1-15, wherein the porous silicon structure has a first side, a second side, and a side surface, and at least one of the first side or the second side has a longest side measurement across the first side or the second side of about 500 nm to about 5.0 micrometers, or the side surface has a longest side measurement across the side of about 100 nm to about 800 nm, or any combination thereof.

[0108] Embodiment 13. between about 30% and 100% of the porous silicon structures within the sample are characterized as having a first end, a second end, and a side surface, wherein at least one of the first and second surfaces is planar or flat; or 16. The method of one or more of embodiments 1-15, wherein about 30% to 100% of the porous silicon structures in the sample are characterized as having a first end, a second end, and a side, wherein at least one of the first or second sides has a longest side average measurement across the first or second side of about 500 nm to about 5.0 micrometers, or the side has a longest side average measurement across the side of about 100 nm to about 800 nm, or any combination thereof.

[0109] Embodiment 14. the first protective layer is deposited by chemical vapor deposition, physical vapor deposition, vacuum evaporation, sputtering, or by heating the silicon substrate to a temperature of about 800°C to about 1,200°C; or the second protective layer is deposited by spin coating or spraying; or 16. The method according to one or more of embodiments 1 to 15, wherein the dielectric layer is deposited by chemical vapor deposition. [Example]

[0110] The present disclosure will now be described using examples, which are intended to illustrate the function of the present disclosure and are not intended to imply any restrictive limitations on the scope of the present disclosure. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. Although methods and materials similar or equivalent to those described herein can be used in the practice of the methods and compositions of the present disclosure, exemplary methods, devices, and materials are described herein. It should be understood that the present disclosure is not limited to the specific methods and experimental conditions described, and that such methods and conditions may vary.

[0111] Without further elaboration, it is believed that one skilled in the art can, using the description herein, utilize the present invention to its fullest extent. The embodiments described herein are to be construed as illustrative, and not as limiting in any way to the remainder of the disclosure. Moreover, while certain preferred embodiments of the present invention have been shown and described, many changes and modifications thereof can be made by those skilled in the art without departing from the spirit and teachings of the present invention. Accordingly, the scope of protection is not limited by the above-set description, but is limited only by the claims, including all equivalents of the subject matter of the claims. The disclosures of all patents, patent applications, and publications cited herein, to the extent that they provide procedural details or other details consistent with and supplementary to those set forth herein, are hereby incorporated by reference.

[0112] To produce porous silicon particles, a heavily doped p++ silicon wafer (Silicon Quest Inc., CA) with a resistivity of 0.005 ohm-cm is used. A first protective layer of silicon dioxide is deposited on the wafer. A second protective layer of photoresist is deposited on the first protective layer. The second protective layer is then patterned to form protected and unprotected regions of the protective layer. Etching (first etching) is performed on the unprotected regions of the first protective layer by subjecting the unprotected regions of the first protective layer to reactive ion etching in an atmosphere of CF4 and CHF3 to form first protective layer pillars.

[0113] Next, etching (second etching) is performed by inductively coupled plasma reactive ion etching under an SF6 atmosphere to form silicon pillars. Next, the second protective layer on top of the first protective layer pillars is removed using piranha solution (1 volume of H2O2 and 2 volumes of H2SO4), and the fluorinated polymer residues on the sidewalls are washed in a solvent such as NMP (N-methyl-2-pyrrolidone) or 3M® Novec™ 7200 Engineered Fluid (ethoxy-nonafluorobutane).

[0114] A silicon nitride dielectric layer is then deposited on the first protective layer pillar, the sidewalls of the silicon pillar, and the silicon trench. The top of the pillar is then exposed by removing portions of the dielectric layer by RIE under an SF6 atmosphere. After such removal, the dielectric layer remains intact on the sides and bottom of the etched areas.

[0115] Next, the first protective layer pillars are removed by exposing them to an etching solution (fourth etching) containing HF, followed by a current of about 20 mA / cm to form a first porous layer, which is a stable porous layer in which particles are formed. 2 Nanopores (porous silicon pillars) were formed by electrochemical etching using a mixture of hydrofluoric acid (HF) and ethanol (1:3 v / v) at an applied current density of 120 mA / cm. 2By applying a current density of 1000 .mu.m, a high-emission porous layer is formed, which is an emissive porous layer having a greater porosity than the first porous layer.

[0116] The steps of forming a stable porous layer and forming an emissive layer are then repeated multiple times to form a periodic layered or stacked porous silicon structure defining multiple first porous layers (i.e., porous silicon structures) separated by second porous layers. Figures 5A and 5B show exemplary SEM images of silicon pillars. Figures 5C and 5D show exemplary SEM images of porous silicon structures (particles) with defined shapes (flat or planar top surfaces and flat or planar bottom surfaces) and sizes.

Claims

1. 1. A method for manufacturing a porous silicon structure, comprising: providing a silicon substrate having a silicon surface; forming a first protective layer on the silicon surface, the first protective layer having a protective layer surface; depositing a second protective layer on the surface of the protective layer; patterning the second protective layer to form protected and unprotected regions on a surface of the first protective layer; forming first protective layer pillars by performing a first etch of the unprotected areas of the first protective layer; forming silicon pillars by performing a second etching of the silicon substrate, the silicon pillars being located below the first protective layer pillars, the silicon pillars having a silicon pillar top, a silicon pillar sidewall, a silicon pillar height, and a silicon pillar width, and adjacent silicon pillar sidewalls being separated by a silicon trench having a silicon pillar spacing; depositing a dielectric layer to cover the first protective layer pillar, the silicon pillar sidewall, and the silicon trench; patterning the dielectric layer by exposing the dielectric layer to a third etch to remove portions of the dielectric layer from above the protective layer pillars; removing the protective layer pillars by exposing the protective layer pillars to a fourth etch.

2. forming porous silicon pillars by applying an electric current to the silicon substrate; or forming porous silicon pillars by applying a current to the silicon substrate through a solution in an electrolytic bath, wherein the current is about 1 mA / cm ２ ~Approx. 50mA / cm ２ The method of claim 1 , further comprising forming the conductive layer with a current density of

3. forming a porous silicon structure by removing the dielectric layer; or forming a porous silicon structure, and applying a current of about 100 mA / cm while the silicon substrate is immersed in a fifth etching solution containing HF; ２ ~Approx. 200mA / cm ２ 3. The method of claim 2, further comprising separating the porous silicon structure from the silicon substrate by applying a current of 0.1 V to the silicon substrate.

4. the silicon surface comprises boron; or the first protective layer comprises silicon oxide, aluminum oxide, chromium, nickel, copper, or any combination thereof; or the second protective layer comprises a photoresist; or The method of claim 1 , wherein the dielectric layer comprises silicon nitride.

5. the first protective pillar has a protective pillar width of about 200 nm to about 5.0 micrometers and a protective pillar height of about 100 nm to about 600 nm; or The method of claim 1 , wherein the first protective pillar has a protective pillar width of about 600 nm to about 4.0 micrometers and a protective pillar height of about 150 nm to about 500 nm.

6. the silicon pillar height is from about 2.0 micrometers to about 50.0 micrometers, the silicon pillar width is from about 200 nm to about 5.0 micrometers, and the silicon pillar spacing is from about 200 nm to about 1000 nm; or 2. The method of claim 1, wherein the silicon pillar height is between about 6.0 micrometers and about 15.0 micrometers, the silicon pillar width is between about 600 nm and about 4.0 micrometers, and the silicon pillar spacing is between about 300 nm and about 800 nm.

7. the ratio of silicon pillar height to silicon pillar spacing is from about 60:1 to about 20:1; or 10. The method of claim 1, wherein the ratio of silicon pillar height to silicon pillar spacing is between about 55:1 and about 45:

1.

8. The first protective layer comprises silicon oxide, and the first etch is performed using a CF ４ and / or CHF ３ or by reactive ion etching the unprotected areas of the first protective layer in an atmosphere of HF, NH ４ or exposing to a first etchant comprising HF, NaF, KF, or any combination or mixture thereof; or The first protective layer comprises aluminum oxide, and the first etch removes the unprotected areas of the first protective layer with HF, NH ４ OH, tetramethylammonium hydroxide, H ３ P.O., Br. ２ or any combination or mixture thereof; The first protective layer comprises chromium, and the first etch removes the unprotected areas of the first protective layer by etching with H ２ O ２ , HCl, H ２ SO ４ , and H ２ O ２ or any combination or mixture thereof; The first protective layer comprises nickel, and the first etch removes the unprotected areas of the first protective layer using a fluorine-containing solution such as HNO ３ , FeCl ３ , Ce(NH ４ ) ２ (NO ３ ) ６ , HF and H ２ O ２ , H ３ P.O. ４ or any combination or mixture thereof; or The first protective layer comprises copper, and the first etch removes the unprotected areas of the first protective layer using a fluorine-containing solution such as HNO ３ , FeCl ３ , KCN, H ２ O ２ 10. The method of claim 1, comprising exposing the substrate to a first etchant comprising:

9. The second etch comprises a reactive ion etch; or the second etch comprises an inductively coupled plasma reactive ion etch; or The second etching is performed by SF ６ or The second etching is performed by SF ６ 10. The method of claim 1, comprising inductively coupled plasma reactive ion etching in an atmosphere of

10. the third etch comprises a reactive ion etch; or the third etch comprises a CF ４ , CHF ３ , or SF ６ 10. The method of claim 1, comprising reactive ion etching in an atmosphere of

11. the fourth etching includes exposing the first protective layer pillars to a fourth etchant; The first protective layer pillar includes silicon oxide, and the fourth etching solution is a mixture of HF, NH ４ HF, NaF, KF, or any combination or mixture thereof; or The first protective layer pillar includes aluminum oxide, and the fourth etchant is a mixture of HF, NH ４ OH, H ３ P.O., Br. ２ or any combination or mixture thereof; The first protective layer pillars include chromium, and the fourth etching solution is a mixture of NaOH, H ２ O ２ , HCl, or any combination or mixture thereof; The first protective layer pillars include nickel, and the fourth etching solution is HNO ３ , FeCl ３ , Ce(NH ４ ) ２ (NO ３ ) ６ , H.F., H. ３ P.O. ４ or any combination or mixture thereof; or The first protective layer pillar includes copper, and the fourth etchant is HNO ３ , FeCl ３ , K.C.N., H. ２ O ２ or any combination or mixture thereof; or The method of claim 1 , wherein the first etchant and the second etchant are the same or different.

12. the porous silicon structure has a first end, a second end, and a side surface, and at least one of the first surface and the second surface is planar or flat; or 4. The method of claim 3, wherein the porous silicon structure has a first end, a second end, and a side surface, and at least one of the first or second surfaces has a longest side measurement across the first or second surface of from about 500 nm to about 5.0 micrometers, or the side surface has a longest side measurement across the side of from about 100 nm to about 800 nm, or any combination thereof.

13. Between about 30% and 100% of the porous silicon structures within a sample are characterized by having a first end, a second end, and a side surface, wherein at least one of the first surface and the second surface is planar or flat; or 4. The method of claim 3, wherein about 30% to 100% of the porous silicon structures within a sample are characterized as having a first side, a second side, and a side, wherein at least one of the first side or the second side has a longest side average measurement across the first side or the second side of about 500 nm to about 5.0 micrometers, or the side has a longest side average measurement across the side of about 100 nm to about 800 nm, or any combination thereof.

14. the first protective layer is deposited by chemical vapor deposition, physical vapor deposition, vacuum deposition, sputtering, or by heating the silicon substrate to a temperature of about 800° C. to about 1,200° C.; or the second protective layer is deposited by spin coating or spraying; or The method of claim 1 , wherein the dielectric layer is deposited by chemical vapor deposition.

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