High-power seed layer patterning on piezoelectric thin films for piezoelectric device fabrication
High-power seed layer deposition and laser etching optimize the grain size and orientation match in piezoelectric materials, addressing the patterning challenges and enhancing piezoelectric device performance by reducing the dissipation factor (LT) and improving throughput.
Patent Information
- Application Number
- JP2025525033
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-10-31
- Filing Date
- 2023-10-27
- Publication Date
- 2025-10-24
AI Technical Summary
Patterning piezoelectric materials in piezoelectric devices is challenging due to their brittle nature, which affects the low dissipation factor (LT) and throughput.
A method involving high-power seed layer deposition and laser etching is used to pattern piezoelectric materials, optimizing the grain size and orientation match between the seed layer and piezoelectric layer, reducing the dissipation factor (LT) and improving throughput.
The method achieves a lower dissipation factor (LT) of less than 1500 ppm, resulting in improved piezoelectric device performance with higher efficiency and reduced signal loss.
Smart Images
Figure 2025535522000001_ABST
Abstract
Description
[Technical Field]
[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to piezoelectric devices. More particularly, embodiments disclosed herein relate to methods for patterning piezoelectric layers for fabricating piezoelectric devices. [Background technology]
[0002] Piezoelectric materials are materials that store an electric charge when mechanically stressed and are frequently used in sensors and transducers for piezoelectric devices, such as gyro sensors, inkjet printer heads, ultrasonic technology, and other microelectromechanical systems (MEMS) devices, including acoustic resonators for cell phones and other wireless electronics. Patterning piezoelectric materials during the fabrication of piezoelectric devices can be difficult due to the brittle nature of piezoelectric materials.
[0003] Therefore, what is needed in the art are improved methods for forming piezoelectric materials. Summary of the Invention
[0004] In one embodiment, a method for forming a piezoelectric element is disclosed. The method includes disposing a bottom electrode on a substrate. A high-power seed layer is disposed on the bottom electrode by physical vapor deposition at a target bias power of 3 kW or greater. A piezoelectric layer is disposed on the bottom electrode. A top electrode is formed on the piezoelectric layer in a top electrode pattern.
[0005] In another embodiment, a piezoelectric element is disclosed. The piezoelectric element includes a bottom electrode disposed on a substrate, a high-power seed layer disposed on the bottom electrode, a piezoelectric layer disposed on the high-power seed layer, and a top electrode disposed on the piezoelectric layer. The high-power seed layer has a high-power seed layer grain size and a high-power seed layer grain orientation. The piezoelectric layer has a piezoelectric grain size and a piezoelectric grain orientation. The high-power seed layer grain size matches the piezoelectric grain size, and the high-power seed layer grain orientation matches the piezoelectric grain orientation.
[0006] In yet another embodiment, a method of forming a piezoelectric device is disclosed. The method includes disposing a bottom electrode on a substrate. A high-power seed layer is disposed on the bottom electrode at a target bias power greater than 3 kW. A piezoelectric layer is disposed on the bottom electrode. An intermediate electrode is disposed on the piezoelectric layer. A second high-power seed layer is disposed on the intermediate electrode at a target bias power greater than 3 kW. A second piezoelectric layer is disposed on the bottom electrode. An upper electrode is disposed on the piezoelectric layer.
[0007] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that since the present disclosure may admit of other equally effective embodiments, the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered limiting in scope. [Brief explanation of the drawings]
[0008] [Figure 1] 1 is a schematic top view of a piezoelectric element according to embodiments described herein. [Figure 2A] 1 is a schematic cross-sectional view of a piezoelectric element according to an embodiment described herein. [Figure 2B] 1 is a schematic cross-sectional view of a piezoelectric element according to an embodiment described herein. [Figure 3] FIG. 1 is a flow diagram of a method for forming a piezoelectric element according to embodiments described herein. [Figure 4A] 4 is a schematic side view of the substrate during the method of FIG. 3 for forming a piezoelectric element according to embodiments described herein. [Figure 4B] 4 is a schematic side view of the substrate during the method of FIG. 3 for forming a piezoelectric element according to embodiments described herein. [Figure 4C] 4 is a schematic side view of the substrate during the method of FIG. 3 for forming a piezoelectric element according to embodiments described herein. [Figure 4D]4 is a schematic side view of the substrate during the method of FIG. 3 for forming a piezoelectric element according to embodiments described herein. [Figure 4E] 4 is a schematic side view of the substrate during the method of FIG. 3 for forming a piezoelectric element according to embodiments described herein. [Figure 4F] 4 is a schematic side view of the substrate during the method of FIG. 3 for forming a piezoelectric element according to embodiments described herein. [Figure 4G] 4 is a schematic side view of the substrate during the method of FIG. 3 for forming a piezoelectric element according to embodiments described herein. [Figure 4H] 4 is a schematic side view of the substrate during the method of FIG. 3 for forming a piezoelectric element according to embodiments described herein. [Figure 4I] 4 is a schematic side view of the substrate during the method of FIG. 3 for forming a piezoelectric element according to embodiments described herein. [Figure 5] 1 is a schematic cross-sectional view of a laser etching system according to embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION
[0009] For ease of understanding, wherever possible, like reference numerals have been used to designate like elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
[0010] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to piezoelectric elements. More particularly, embodiments disclosed herein relate to piezoelectric elements and methods of fabricating piezoelectric layers for fabricating piezoelectric elements.
[0011] Patterning piezoelectric materials in piezoelectric devices can be challenging due to the brittle and hard nature of piezoelectric materials. For piezoelectric devices, it is beneficial to pattern the piezoelectric material to achieve a low dissipation factor (LT) for the device. The LT of a piezoelectric device is a measure of the signal loss associated with the actuation of the piezoelectric material. Improved patterning of piezoelectric materials, and therefore improved LT, can be achieved by the methods disclosed herein. The methods disclosed herein can pattern piezoelectric materials with higher throughput. In certain embodiments, a laser etching system is utilized to pattern the piezoelectric material. For example, the laser etching system includes laser process tuning to adjust laser parameters to improve patterning performance and throughput.
[0012] FIG. 1 is a schematic top view of a piezoelectric element 100 according to embodiments described herein. The piezoelectric element 100 can be fabricated according to methods described herein. The piezoelectric element 100 shown in FIG. 1 may be partially fabricated, or other processing operations may be used to form a functional element. The piezoelectric element 100 can be utilized in sensing applications (e.g., gyro sensors), ultrasonic technology, inkjet printing, or microelectromechanical systems (MEMS) devices, including acoustic resonators for cell phones and other wireless electronics.
[0013] Piezoelectric element 100 includes substrate 102 (shown in FIG. 2), primary seed layer 101 (shown in FIG. 2), bottom electrode 104, high-power seed layer 109 (shown in FIG. 2), piezoelectric layer 106, and top electrode 108. Substrate 102 can have a diameter ranging from about 100 mm to about 750 mm and can be formed from a variety of materials, including silicon (Si), silicon carbide (SiC), SiC-coated graphite, or silicon oxide (SiO2). In one example, substrate 102 has a diameter of about 1,000 cm 2 For example, about 2,000 cm 2 For example, about 4,000 cm 2 It has a surface area of more than 10 ...
[0014] The primary seed layer 101 is disposed on a substrate 102. The bottom electrode 104 is disposed on the substrate 102. As shown in FIGS. 2A and 2B, the bottom electrode 104 is disposed on the primary seed layer 101. The bottom electrode 104 is the bottom electrode of the piezoelectric element 100. The bottom electrode 104 includes a conductive material such as platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, or LaSrMnO3. The bottom electrode 104 can have a thickness of about 5 nm to about 350 nm, for example, about 50 nm to about 200 nm, for example, about 75 nm to about 175 nm, for example, about 100 nm to about 150 nm, or for example, about 125 nm.
[0015] A high-power seed layer 109 is disposed on the bottom electrode 104. A piezoelectric layer 106 is disposed on the bottom electrode 104. As shown in FIGS. 2A and 2B, the piezoelectric layer 106 is disposed on the high-power seed layer 109. In certain embodiments, the piezoelectric layer 106 may be formed of one or more layers including one or more of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), magnesium niobate-lead titanate (PMN-PT), or LiNbO (LNO). The piezoelectric layer 106 may have a thickness of about 100 nm to about 3000 nm, e.g., about 750 nm to about 1500 nm, e.g., about 1000 nm. In some embodiments that can be combined with other embodiments described herein, the thickness of the piezoelectric layer 106 may vary across the high-power seed layer 109. In other embodiments, which can be combined with other embodiments described herein, the thickness of the piezoelectric layer 106 is constant across the high-power seed layer 109. The piezoelectric layer 106 and the high-power seed layer 109 are selectively etched via a laser etching process to form exposed portions 112 of the bottom electrode 104. The exposed portions 112 provide access to the bottom electrode 104.
[0016] A top electrode 108 is disposed on the piezoelectric layer 106. In one embodiment, the top electrode 108 is disposed on the piezoelectric layer 106. The top electrode 108 is configured to be the top electrode of the completed piezoelectric element. In certain embodiments, the top electrode 108 may be formed of the same material as the bottom electrode 104 or a different material. The top electrode 108 includes a conductive material such as platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, or LaSrMnO3. The top electrode 108 can have a thickness of about 5 nm to about 3000 nm, for example, about 50 nm to about 150 nm, for example, about 100 nm.
[0017] As shown in FIG. 1 , the top electrode 108 may be patterned on the piezoelectric layer 106 as desired. The top electrode 108 may be formed with a top electrode pattern 110. The top electrode pattern 110 may be predetermined before manufacturing to meet the specifications of the piezoelectric element 100. The top electrode pattern 110 of the top electrode 108 is not limited to the pattern shown in FIG. 1 and may be adjusted as desired. For example, the top electrode pattern 110 may include a circular, rectangular, square, or irregular pattern.
[0018] 2A is a schematic cross-sectional view of a piezoelectric element 100 taken along section line AA. In the illustrated embodiment, the piezoelectric element 100 includes a primary seed layer 101 and a high-power seed layer 109. The primary seed layer 101 is disposed on a substrate 102. In one embodiment, the primary seed layer 101 is disposed on the substrate 102. A bottom electrode 104 is disposed on the primary seed layer 101. The primary seed layer 101 can include a material such as aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), or the like. The primary seed layer 101 can have a thickness of about 1 nm to about 100 nm, for example, about 5 nm to about 50 nm, for example, about 30 nm.
[0019] A high-power seed layer 109 is disposed on the bottom electrode 104. In one embodiment, the high-power seed layer 109 is disposed on the bottom electrode 104. A piezoelectric layer 106 is disposed on the high-power seed layer 109. In some embodiments that can be combined with other embodiments described herein, the thickness of the piezoelectric layer 106 can vary across the top surface of the high-power seed layer 109. In other embodiments that can be combined with other embodiments described herein, the thickness of the piezoelectric layer 106 is constant across the top surface of the high-power seed layer 109. The piezoelectric layer 106 and the high-power seed layer 109 are selectively etched via a laser etching process to form an exposed portion 112 of the bottom electrode 104. The exposed portion 112 provides access to the bottom electrode 104.
[0020] In certain embodiments, the high-power seed layer 109 may be formed of the same or a different material as the primary seed layer 101. The high-power seed layer 109 may include materials such as aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), etc., although other materials are also contemplated by the present disclosure. The high-power seed layer 109 may have a thickness of about 1 nm to about 50 nm, e.g., about 5 nm to about 25 nm, e.g., about 10 nm.
[0021] A top electrode 108 is disposed on top of the piezoelectric layer 106. The top electrode 108 is configured to be the top electrode 108 of the completed piezoelectric element.
[0022] FIG. 2B is a schematic cross-sectional view of an alternative piezoelectric element 200 taken along section line AA. The alternative piezoelectric element 200 further includes an intermediate electrode 208, a second high-power seed layer 209, and a second piezoelectric layer 206. The intermediate electrode 208 is disposed on the piezoelectric layer 106. In certain embodiments, the intermediate electrode 208 may be formed of the same or a different material as the bottom electrode 104 or the top electrode 108. The intermediate electrode 208 may include a conductive material such as platinum (Pt), molybdenum (Mo), SrRuO, LaNiO, CaRuO, or LaSrMnO. The intermediate electrode 208 may have a thickness of about 5 nm to about 500 nm, e.g., about 50 nm to about 150 nm, e.g., about 100 nm.
[0023] The second high-power seed layer 209 is disposed on the intermediate electrode 208. The second high-power seed layer 209 may be formed of the same material as the primary seed layer 101 or a different material. The second high-power seed layer 209 may include a material such as aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), or the like. The second high-power seed layer 209 may have a thickness of about 1 nm to about 50 nm, for example, about 5 nm to about 25 nm, for example, about 10 nm.
[0024] The second piezoelectric layer 206 is disposed on the second high-power seed layer 209. In certain embodiments, the second piezoelectric layer 206 may be formed of the same material as the piezoelectric layer 106 or a different material. In certain embodiments, the second piezoelectric layer 206 may be formed of one or more layers including one or more of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), magnesium niobate-lead titanate (PMN-PT), or LiNbO (LNO). The second piezoelectric layer 206 can have a thickness of about 100 nm to about 3000 nm, e.g., about 750 nm to about 1500 nm, e.g., about 1000 nm. In some embodiments that can be combined with other embodiments described herein, the thickness of the second piezoelectric layer 206 can vary across the top surface of the second high-power seed layer 209. In other embodiments, which can be combined with other embodiments described herein, the thickness of the second piezoelectric layer 206 is constant across the top surface of the second high-power seed layer 209. The second piezoelectric layer 206 and the second high-power seed layer 209 are selectively etched via a laser etching process to form exposed portions of the intermediate electrode 208. The exposed portions provide access to the intermediate electrode 208.
[0025] A top electrode 108 is disposed on the second piezoelectric layer 206. The top electrode 108 is configured to be the top electrode of the completed piezoelectric element.
[0026] Figure 3 is a flow diagram of a method 300 for forming the piezoelectric elements 100 and 200 shown in Figures 4A to 4H. Figures 4A to 4H are schematic cross-sectional views of a substrate 102 in the method 300 for forming the piezoelectric elements 100 and 200.
[0027] As shown in FIG. 4A, in operation 301, a primary seed layer 101 is disposed on a substrate 102. The primary seed layer can be disposed using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), inkjet printing, or other deposition process performed in a suitable chamber. In certain embodiments, the deposition process is performed at about 25° C. to about 600° C., e.g., about 400° C. to about 600° C., e.g., about 500° C. In certain embodiments, the deposition is a PVD process, and the target in the chamber is negatively biased during the deposition process by a pulsed or continuous power supply providing DC power at a power level of about 400 W to about 3000 W, e.g., about 1000 W to about 2000 W, or e.g., about 600 W to about 800 W.
[0028] As shown in FIG. 4B , in operation 302, a bottom electrode 104 is disposed on the primary seed layer 101. The bottom electrode 104 is disposed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition process carried out in a suitable chamber. In certain embodiments, the deposition process is carried out at a temperature between about 25° C. and about 600° C., e.g., between about 400° C. and about 600° C., e.g., about 500° C. In certain embodiments, the deposition is a PVD process, and the target in the deposition chamber is negatively biased during the deposition process by a pulsed or continuous power supply providing DC power at a power level between about 400 W and about 1000 W, e.g., between about 600 W and about 800 W.
[0029] As shown in FIG. 4C , in operation 303, a high-power seed layer 109 is disposed on the bottom electrode 104. The high-power seed layer 109 is disposed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition process performed in a suitable chamber. In certain embodiments, the deposition process is performed at about 25° C. to about 600° C., e.g., about 400° C. to about 600° C., e.g., about 500° C. In certain embodiments, the high-power seed layer 109 is deposited on the bottom electrode 104 when a target in the deposition chamber is negatively biased by a pulsed or continuous power supply providing DC power. The high-power seed layer 109 is deposited when the target in the deposition chamber is biased at a power level greater than about 3 kW, e.g., about 6 kW to about 20 kW, e.g., about 8 kW. The high-power seed layer 109 comprises a high-power seed layer grain size and a high-power seed layer grain orientation.
[0030] As shown in FIG. 4D , in operation 304, a piezoelectric layer 106 is disposed on the high-power seed layer 109. The piezoelectric layer 106 is disposed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition process performed in a suitable chamber. In certain embodiments, the deposition process is performed at about 25° C. to about 600° C., e.g., about 400° C. to about 600° C., e.g., about 500° C. In certain embodiments, the deposition is a PVD process, and the target in the deposition chamber is negatively biased during the deposition process by a pulsed or continuous power supply providing DC power at a power level of about 400 W to about 1000 W, e.g., about 600 W to about 800 W. In one embodiment, the high-power seed layer grain size matches the piezoelectric grain size, and the high-power seed layer grain orientation matches the piezoelectric grain orientation.
[0031] High-power deposition of the high-power seed layer 109 can reduce the dissipation factor (LT) of the piezoelectric element 100. Reducing the LT of the piezoelectric element 100 improves the efficiency of the piezoelectric element. High-power deposition of the high-power seed layer 109 promotes nucleation of the piezoelectric layer 106, improves surface adhesion between the piezoelectric layer 106 and the high-power seed layer 109, improves grain size and lattice orientation matching between the high-power seed layer 109 and the piezoelectric layer 106, and promotes crystal growth of the piezoelectric layer 106, resulting in improved performance. This improves the material property matching between the high-power seed layer 109 and the piezoelectric layer 106, resulting in an LT of less than about 1500 ppm, such as about 1300 ppm. For example, compared to a conventional piezoelectric element in which the layer is deposited at 3 kW, the LT of the conventional element is about 1500 ppm, while the LT of the high-power seed layer element deposited at 6 kW is about 1300 ppm (about 13% better than the conventional element). High power piezoelectric elements show improvements over conventional elements, and can reduce LT losses by 7% or more, such as 13% or more, such as 15% or more.
[0032] As shown in FIG. 4E, in operation 305, the top electrode 108 is disposed on the piezoelectric layer 106. The top electrode 108 is disposed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition process carried out in a suitable chamber. In certain embodiments, the deposition process is carried out at a temperature between about 25° C. and about 600° C., e.g., between about 400° C. and about 600° C., e.g., about 500° C. In certain embodiments, the deposition is a PVD process, and the target in the deposition chamber is negatively biased during the deposition process by a pulsed or continuous power supply providing DC power at a power level between about 400 W and about 1000 W, e.g., between about 600 W and about 800 W.
[0033] As shown in FIG. 4F, in alternative operation 306, an intermediate electrode 208 is disposed on the piezoelectric layer 106 prior to deposition of the top electrode 108, forming an alternative piezoelectric element 200. The intermediate electrode 208 is disposed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition process performed in a suitable chamber. In certain embodiments, the deposition process is performed at a temperature between about 25° C. and about 600° C., e.g., between about 400° C. and about 600° C., e.g., about 500° C. In certain embodiments, the deposition is a PVD process, and the target in the deposition chamber is negatively biased during the deposition process by a pulsed or continuous power supply providing DC power at a power level between about 400 W and about 1000 W, e.g., between about 600 W and about 800 W.
[0034] In alternative operation 307, as shown in FIG. 4G, a second high-power seed layer 209 is deposited on the intermediate electrode 208. The second high-power seed layer 209 is deposited via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition process performed in a suitable chamber. In certain embodiments, the deposition process is performed at about 25°C to about 600°C, e.g., about 400°C to about 600°C, e.g., about 500°C. In certain embodiments, the deposition is a PVD process, and the second high-power seed layer 209 is deposited on the intermediate electrode 208 when a target in the second deposition chamber is negatively biased by a pulsed or continuous power supply providing DC power. The second high-power seed layer 209 is deposited when the target in the deposition chamber is at a power level greater than about 3 kW, e.g., about 6 kW to about 20 kW, e.g., about 8 kW. The second high-power seed layer 209 comprises a second high-power seed layer grain size and a second high-power seed layer grain orientation.
[0035] In alternative operation 308, as shown in FIG. 4H, a second piezoelectric layer 206 is deposited on the second high-power seed layer 209. The second piezoelectric layer 206 is deposited via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition process performed in a suitable chamber. In certain embodiments, the deposition process is performed at about 25°C to about 600°C, e.g., about 400°C to about 600°C, e.g., about 500°C. In certain embodiments, the deposition is a PVD process, and the target in the deposition chamber is negatively biased during the deposition process by a pulsed or continuous power supply providing DC power at a power level of about 400 W to about 1000 W, e.g., about 600 W to about 800 W. The second piezoelectric layer includes a second piezoelectric grain size and a second piezoelectric grain orientation. In one embodiment, the second high-power seed layer grain size matches the second piezoelectric grain size, and the second high-power seed layer grain orientation matches the second piezoelectric grain orientation.
[0036] The high-power deposition of the second high-power seed layer 209 can reduce the dissipation factor (LT) of the alternative piezoelectric element 200. Reducing the LT of the piezoelectric element 200 improves the efficiency of the piezoelectric element. The high-power deposition of the second high-power seed layer 209 promotes nucleation of the second piezoelectric layer 206, improves surface adhesion between the second piezoelectric layer 206 and the second high-power seed layer 209, improves grain size and grain orientation matching between the second high-power seed layer 209 and the second piezoelectric layer 206, and promotes crystal growth of the second piezoelectric layer 206, resulting in improved performance. This improves the material property matching between the high-power seed layer 109 and the piezoelectric layer 106, resulting in an LT of less than about 1500 ppm, such as about 1300 ppm. For example, compared to a conventional piezoelectric element where the layers are deposited at 3 kW, the LT of the conventional element is about 1500 ppm, while the LT of the high-power seed layer element deposited at 6 kW is about 1300 ppm (about 13% better than the conventional element). The high-power piezoelectric element shows an improvement over the conventional element, reducing LT losses by 7% or more, e.g., 13% or more, e.g., 15% or more.
[0037] As shown in FIG. 4I, in alternative operation 309, the top electrode 108 is disposed on the second piezoelectric layer 206. The top electrode 108 is disposed via PVD, CVD, PECVD, ALD, inkjet printing, or other deposition process performed in a suitable chamber. In certain embodiments, the deposition process is performed at about 25° C. to about 600° C., e.g., about 400° C. to about 600° C., e.g., about 500° C. In certain embodiments, the deposition is a PVD process, and the target in the deposition chamber is negatively biased during the deposition process by a pulsed or continuous power supply providing DC power at a power level of about 400 W to about 1000 W, e.g., about 600 W to about 800 W.
[0038] The user can repeat the deposition of subsequent electrodes, high power seed layers, and piezoelectric layers in alternate operations 306-309 to achieve the desired thickness and functionality of the piezoelectric element.
[0039] 5 is a schematic cross-sectional view of a laser etching system 500. The laser etching system is utilized in a method for patterning a piezoelectric layer using the laser etching system 500 during the fabrication of a piezoelectric element 100.
[0040] The laser etching system 500 includes a substrate 102 disposed on a surface of a stage 502. The substrate 102 may also include a bottom electrode 104 and a piezoelectric layer 106 disposed thereon. In some embodiments, a top electrode 108 is also disposed on the bottom electrode 104. In some embodiments, a primary seed layer 101 is disposed between the bottom electrode 104 and the substrate 102. In some embodiments, a high-power seed layer 109 is disposed between the piezoelectric layer 106 and the bottom electrode 104. In some embodiments, an intermediate electrode 208 is disposed on the piezoelectric layer 106. A second high-power seed layer 209 is disposed on the intermediate electrode 208. A second piezoelectric layer 206 is disposed on the second high-power seed layer 209. The top electrode 108 is disposed on the second piezoelectric layer 206.
[0041] The stage 502 is positioned within the laser etching system 500 such that a surface of the stage 502 is positioned opposite a scanner 504. The scanner 504 includes a laser source 514, an optical array 516, and a laser 506 positioned from the optical array 516. The laser etching system 500 is operable to etch the piezoelectric layer 106 or the second piezoelectric layer 206 to expose the bottom electrode 104 or the middle electrode 208. The laser etching system 500 is operable to provide laser pulses toward the substrate 102 such that the piezoelectric layer 106 is etched. The laser etching system 500 includes a controller 508. The controller 508 is in communication with the stage 502 and the scanner 504.
[0042] The controller 508 is generally designed to facilitate control and automation of aspects of the methods described herein. The controller 508 can be coupled to or in communication with the laser light source 514, the optical array 516, the stage 502, and the scanner 504. The stage 502 and the scanner 504 can provide the controller 508 with information regarding the method and the alignment of the substrate 102. The controller 508 can be in communication with or coupled to a CPU (i.e., a computer system). The CPU can be a hardware unit or combination of hardware units capable of executing software applications and processing data. In some configurations, the CPU includes a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), and / or a combination of such units. The CPU is generally configured to execute one or more software applications and process stored media data. The controller 508 can include a non-transitory computer-readable medium for storing instructions for forming a dicing path along a substrate as described herein. The non-transitory computer-readable medium may be part of the CPU.
[0043] Laser 506 is a fiber optic laser. In one embodiment that can be combined with other embodiments described herein, laser 506 includes a Gaussian beam profile. In another embodiment that can be combined with other embodiments described herein, laser 506 is an ultraviolet (UV) laser. In another embodiment that can be combined with other embodiments described herein, laser 506 is an infrared laser. In another embodiment that can be combined with other embodiments described herein, laser 506 has a Bessel beam profile. In yet another embodiment, laser 506 is a multi-focus laser and uses a bifocal lens as part of optical array 516. Multiple lenses can also be used in optical array 516 to diffract laser 506 and form multiple focal points within substrate 102. Laser 506 is in communication with controller 508. Controller 508 can control other input or output parameters of laser 506.
[0044] The stage 502 includes a stage actuator 510 that allows the stage 502 to scan in the X, Y, and Z directions, as shown in the coordinate system illustrated in Figure 5. The stage 502 is coupled to the controller 508 to provide position information for the stage 502 to the controller 508. The stage 502 is further in communication with the controller 508 so that the stage 502 can move in desired directions to etch the piezoelectric layer 106.
[0045] Scanner 504 includes a scanner actuator 512. Scanner actuator 512 enables scanner 504 to scan in the X, Y, and Z directions as shown in the coordinate system illustrated in FIG. 5. Laser source 514 and optical array 516 are located within or on scanner 504. Scanner 504 is coupled to controller 508 to provide position information of scanner 504 to controller 508. In one embodiment, which can be combined with other embodiments described herein, scanner 504 is a galvo scanner.
[0046] In one embodiment, which may be combined with other embodiments described herein, the laser etching system 500 performing the method for etching may utilize both the scanner 504 and the stage 502 to direct the laser 506 at the substrate 102. In another embodiment, which may be combined with other embodiments described herein, the laser etching system 500 performing the method for etching may utilize only the scanner 504 to direct the laser 506 at the substrate 102. In yet another embodiment, which may be combined with other embodiments described herein, the laser etching system 500 performing the method for etching may utilize only the stage 502 to direct the laser 506 at the substrate 102.
[0047] In summary, provided herein are piezoelectric devices and methods for patterning piezoelectric layers for device fabrication. The loss tangent (LT) characteristics of a piezoelectric device significantly affect device performance. By depositing a high-power seed layer at high power, the property match between the high-power seed layer and the piezoelectric layer is optimized, leading to lower LT and significantly improved performance.
[0048] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of the present disclosure being determined by the claims that follow.
Claims
1. disposing a bottom electrode on a substrate; disposing a high power seed layer on the bottom electrode by physical vapor deposition at a target bias power greater than 3 kW; disposing a piezoelectric layer over the bottom electrode; forming an upper electrode on the piezoelectric layer with an upper electrode pattern; 1. A method of forming a piezoelectric element, comprising:
2. The method of claim 1 , further comprising disposing a primary seed layer between the substrate and the bottom electrode.
3. 3. The method of claim 2, wherein the primary seed layer, bottom electrode, piezoelectric layer, and top electrode are deposited using one of physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or inkjet printing.
4. 10. The method of claim 1, wherein the piezoelectric element has a dissipation factor (LT) of less than 1500 ppm.
5. 10. The method of claim 1, wherein the piezoelectric element has a dissipation factor (LT) of less than 1300 ppm.
6. The method of claim 1 , wherein the high-power seed layer comprises aluminum nitride (AlN) or scandium-doped aluminum nitride (ScAlN).
7. disposing an intermediate electrode on the piezoelectric layer; disposing a second high power seed layer on the intermediate electrode at a target bias power greater than 3 kW; disposing a second piezoelectric layer over the bottom electrode; The method of claim 1 further comprising:
8. The lower electrode, the intermediate electrode, and the upper electrode are made of platinum (Pt), molybdenum (Mo), SrRuO 3 , LaNiO 3 , CaRuO 3 , or LaSrMnO 3 The method of claim 7, comprising one or more of:
9. The method of claim 7 , wherein the second high-power seed layer comprises aluminum nitride (AlN) or scandium-doped aluminum nitride (ScAlN).
10. The piezoelectric layer and the second piezoelectric layer are made of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-titanate (PMN-PT), or LiNbO 3 8. The method of claim 7, comprising one or more of: (LNO).
11. a bottom electrode disposed on the substrate; a high-power seed layer disposed on the bottom electrode, the high-power seed layer having a high-power seed layer grain size and a high-power seed layer grain orientation; a piezoelectric layer disposed on the high-power seed layer, the piezoelectric layer having a piezoelectric grain size and a piezoelectric grain orientation, the high-power seed layer grain size matching the piezoelectric grain size and the high-power seed layer grain orientation matching the piezoelectric grain orientation; an upper electrode disposed on the piezoelectric layer; A piezoelectric element comprising:
12. The piezoelectric layer an intermediate electrode disposed on the piezoelectric layer; a second high-power seed layer disposed on the intermediate electrode, the second high-power seed layer having a second high-power seed layer grain size and a second high-power seed layer grain orientation; a second piezoelectric layer disposed on the second high-power seed layer, the second piezoelectric layer having a second piezoelectric grain size and a second piezoelectric grain orientation, the second high-power seed layer grain size matching the second piezoelectric grain size and the second high-power seed layer grain orientation matching the second piezoelectric grain orientation; The piezoelectric element of claim 11 further comprising:
13. 13. The piezoelectric element of claim 12, wherein the piezoelectric element has a dissipation factor (LT) of less than 1500 ppm.
14. 13. The piezoelectric element of claim 12, wherein the piezoelectric element has a dissipation factor (LT) of less than 1300 ppm.
15. disposing a bottom electrode on a substrate; disposing a high power seed layer on the bottom electrode at a target bias power greater than 3 kW; disposing a piezoelectric layer over the bottom electrode; disposing an intermediate electrode on the piezoelectric layer; disposing a second high power seed layer on the intermediate electrode at a target bias power greater than 3 kW; disposing a second piezoelectric layer over the bottom electrode; disposing a top electrode on the piezoelectric layer; 1. A method of forming a piezoelectric element, comprising:
16. The method of claim 15 further comprising disposing a primary seed layer between the substrate and the bottom electrode.
17. 17. The method of claim 16, wherein the primary seed layer, bottom electrode, piezoelectric layer, middle electrode, second piezoelectric layer, and top electrode are deposited using one of physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or inkjet printing.
18. The lower electrode, the intermediate electrode, and the upper electrode are made of platinum (Pt), molybdenum (Mo), SrRuO 3 , LaNiO 3 , CaRuO 3 , or LaSrMnO 3 16. The method of claim 15, comprising one or more of:
19. 16. The method of claim 15, wherein the high-power seed layer and the second high-power seed layer comprise aluminum nitride (AlN) or scandium-doped aluminum nitride (ScAlN).
20. The piezoelectric layer and the second piezoelectric layer are made of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-titanate (PMN-PT), or LiNbO 3 16. The method of claim 15, comprising one or more of: (LNO).