In-substrate stress control of piezoelectric films using dynamic bias during piezoelectric device fabrication

Abstract

Examples disclosed herein relate to piezoelectric devices and methods for patterning piezoelectric layers for fabricating the piezoelectric devices. The methods include disposing a bottom electrode layer on a substrate, disposing a piezoelectric layer on the bottom electrode layer on a horizontal surface, varying an electrical bias to a pedestal during deposition of the piezoelectric layer, and forming a top electrode layer with a top electrode pattern on the piezoelectric layer. The substrate is supported by the pedestal. The piezoelectric device includes a substrate, a bottom electrode layer formed on the substrate, a piezoelectric layer formed on the bottom electrode layer on the horizontal surface, and a top electrode layer formed on the piezoelectric layer. The average stress of a plurality of stresses along the horizontal surface in the piezoelectric layer is about 50 MPa to about 300 MPa.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure generally relate to piezoelectric devices. More particularly, embodiments disclosed herein relate to piezoelectric devices and methods of forming piezoelectric layers for manufacturing piezoelectric devices. [Background technology]

[0002] Piezoelectric materials are materials that store electric charge when mechanical stress is applied and are frequently used in sensors and transducers for piezoelectric devices such as gyro sensors, inkjet printer heads, ultrasonic technology, and other microelectromechanical systems (MEMS) devices, including acoustic resonators for cell phones and other wireless electronics. Fabricating piezoelectric devices can be challenging due to the brittle nature of piezoelectric materials and stresses within the substrate. Stress ranges within the substrate can be as high as 100 MPa, depending on film thickness, stress gradients across the film in the vertical direction, and other factors. These high stress ranges affect the performance and yield of piezoelectric devices.

[0003] Therefore, what is needed in the art are improved methods for producing piezoelectric materials. Summary of the Invention

[0004] In one embodiment, a method for forming a piezoelectric element is disclosed. The method for forming a piezoelectric element includes disposing a bottom electrode layer on a substrate, the substrate being supported by a pedestal. A piezoelectric layer is disposed on the bottom electrode layer along a horizontal surface. An electrical bias to the pedestal is varied during deposition of the piezoelectric layer. A top electrode layer is formed on the piezoelectric layer in a top electrode pattern.

[0005] In another embodiment, a piezoelectric element is disclosed. The element includes a substrate, a lower electrode layer formed on the substrate, a piezoelectric layer formed on the lower electrode layer along a horizontal plane, and an upper electrode layer formed on the piezoelectric layer. A plurality of stresses along the horizontal plane in the piezoelectric layer have an average stress of about 50 MPa to about 300 MPa.

[0006] In yet another embodiment, a controller for a processing system is disclosed. The controller includes storing instructions that, when executed by a processor, cause the system to process a substrate in a processing chamber by disposing a bottom electrode layer on the substrate. The substrate is supported by a pedestal. A piezoelectric layer is disposed on the bottom electrode layer. An electrical bias to the pedestal is varied during deposition of the piezoelectric layer. An top electrode layer is formed on the piezoelectric layer in a top electrode pattern.

[0007] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that since the present disclosure may admit of other equally effective embodiments, the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered limiting in scope. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic top view of a piezoelectric element according to embodiments described herein. [Figure 2] 1 is a schematic cross-sectional view of a piezoelectric element according to an embodiment described herein. [Figure 3] 1 is a flow diagram of a method for forming a piezoelectric element according to embodiments described herein. [Figure 4A] 4 is a schematic side view of the substrate during the method of FIG. 3 for forming a piezoelectric element according to embodiments described herein. [Figure 4B] 4 is a schematic side view of the substrate during the method of FIG. 3 for forming a piezoelectric element according to embodiments described herein. [Figure 4C] 4 is a schematic side view of the substrate d during the method of FIG. 3 for forming a piezoelectric element according to embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0009] For ease of understanding, wherever possible, like reference numerals have been used to designate like elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0010] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to piezoelectric elements. More particularly, embodiments disclosed herein relate to piezoelectric elements and methods of fabricating piezoelectric layers for fabricating piezoelectric elements.

[0011] Patterning of piezoelectric material in piezoelectric devices can be difficult due to the brittle and hard characteristics of piezoelectric material. In piezoelectric devices, it is beneficial to pattern the piezoelectric material while controlling the stress range across the substrate. Improved patterning of piezoelectric material can be achieved by the methods disclosed herein. The methods disclosed herein allow for patterning of piezoelectric material with higher throughput.

[0012] Figure 1 is a schematic top view of a piezoelectric element 100. The piezoelectric element 100 shown in Figure 1 may be partially fabricated and may require other processing steps to form a functional element. Piezoelectric element 100 can be utilized in sensing applications (e.g., gyro sensors), ultrasonic technology, inkjet printing, or microelectromechanical systems (MEMS) devices, including acoustic resonators for cell phones and other wireless electronics.

[0013] Piezoelectric element 100 includes substrate 102 (shown in FIGS. 4A-4C), bottom electrode layer 104, piezoelectric layer 106, and top electrode layer 108. In some embodiments, piezoelectric element 100 can include a high-power seed layer disposed between bottom electrode layer 104 and piezoelectric layer 106. In another embodiment, piezoelectric element 100 can include an intermediate electrode layer, a second high-power seed layer, and a second piezoelectric layer. The intermediate electrode layer is disposed on piezoelectric layer 106, the second high-power seed layer is disposed on the intermediate electrode layer, and the second piezoelectric layer is disposed between the second high-power seed layer and top electrode layer 108. In another embodiment, additional electrode layers, high-power seed layers, and piezoelectric layers can be deposited to achieve desired thicknesses and functionality. In yet another embodiment, a primary seed layer can be disposed between the substrate and bottom electrode layer 104.

[0014] The substrate 102 can have a diameter ranging from about 100 mm to about 750 mm and can comprise silicon (Si), silicon carbide (SiC), SiC-coated graphite, or silicon oxide (SiO2). In one example, the substrate 102 has a diameter of about 1,000 cm 2 For example, about 2,000 cm 2 For example, about 4,000 cm 2 It has a surface area of ​​more than 10 ...

[0015] The lower electrode layer 104 is disposed on the upper surface of the substrate 102. The lower electrode layer 104 is configured to serve as the lower electrode of the piezoelectric element 100. Examples of materials suitable for the lower electrode layer 104 include platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, and LaSrMnO3. The lower electrode layer 104 can have a thickness of about 25 nm to about 200 nm, for example, about 50 nm to about 175 nm, for example, about 75 nm to about 150 nm, or about 125 nm.

[0016] The piezoelectric layer 106 is disposed on the bottom electrode layer 104. In certain embodiments, the piezoelectric layer 106 is formed of one or more layers including one or more of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), magnesium niobate-lead titanate (PMN-PT), or lithium niobate (LiNbO or LNO). The piezoelectric layer 106 can have a thickness of about 300 nm to about 2000 nm, e.g., about 750 nm to about 1500 nm, e.g., about 1000 nm. In some embodiments that can be combined with other embodiments described herein, the thickness of the piezoelectric layer 106 can vary between about 300 nm and about 2000 nm across the entire surface of the bottom electrode layer 104. In other embodiments that can be combined with other embodiments described herein, the thickness of the piezoelectric layer 106 is constant across the entire surface of the bottom electrode layer 104. The piezoelectric layer 106 is selectively etched via a laser etching process to form exposed portions 112 of the bottom electrode layer 104. The exposed portions 112 provide access to the bottom electrode layer 104.

[0017] The top electrode layer 108 is disposed on the surface of the piezoelectric layer 106. The top electrode layer 108 is configured to serve as the top electrode of the completed piezoelectric element. In certain examples, the top electrode layer 108 is formed of the same or a different material as the bottom electrode layer 104. Examples of suitable materials for the top electrode layer 108 include platinum (Pt), molybdenum (Mo), SrRuO3, LaNiO3, CaRuO3, LaSrMnO3, and the like. The top electrode layer 108 can have a thickness of about 25 nm to about 200 nm, for example, about 75 nm to about 150 nm, for example, about 100 nm.

[0018] As shown in FIG. 1 , the top electrode layer 108 may be patterned as desired on the surface of the piezoelectric layer 106. The top electrode layer 108 is formed with a top electrode pattern 110. The top electrode pattern 110 may be predetermined before manufacturing to meet the specifications of the piezoelectric element 100. The top electrode pattern 110 of the top electrode layer 108 is not limited to the pattern shown in FIG. 1 and may be adjusted as desired. For example, the top electrode pattern 110 may include a circular, rectangular, square, or irregular pattern.

[0019] 2 is a schematic cross-sectional view of piezoelectric element 100 taken along section line AA. A bottom electrode layer 104 is disposed on a surface of substrate 102. A piezoelectric layer 106 is disposed on the surface of bottom electrode layer 104 along a horizontal plane. A top electrode layer 108 is disposed on the surface of piezoelectric layer 106. In one embodiment, bottom electrode layer 104, piezoelectric layer 106, and top electrode layer 108 can be deposited using physical vapor deposition (PVD). In other embodiments, chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition processes can be used. The deposition process is performed in a processing chamber configured to perform PVD, CVD, ALD, or other deposition processes.

[0020] During deposition of the bottom electrode layer 104 and top electrode layer 108, an electrical bias is applied to a pedestal or substrate support within the processing chamber at a static value between about 400 W and about 3000 W. During deposition of the piezoelectric layer 106, a dynamic electrical bias is applied to the pedestal at various power levels between no bias (e.g., 0 W) and about 200 W, for example, between about 20 W and about 100 W. The pedestal supports the substrate 102 within the chamber.

[0021] Varying the bias (e.g., dynamic bias) results in an average stress in the piezoelectric layer 106 ranging from about 50 MPa to about 300 MPa. The average stress is the average stress of multiple stresses along the horizontal plane of the piezoelectric layer 106. The dynamic bias in the piezoelectric layer 106 results in a range of stress across the substrate 102 ranging from about ±0 MPa to about ±100 MPa, e.g., a maximum deviation from the average stress across the substrate of about 100 MPa and a minimum deviation from the average stress across the substrate of about 0 MPa. For example, in one embodiment, the dynamic bias results in an average stress in the piezoelectric layer 106 of about 200 MPa, and a range of stress across the substrate of about 100 MPa to about 300 MPa (i.e., ±100 MPa from the average stress value). In another embodiment, the dynamic bias in the piezoelectric layer 106 is about 100 MPa, and a range of stress across the substrate of about 50 MPa to about 150 MPa (i.e., ±50 MPa). The dynamic bias can be further adjusted to create average stress values ​​and ranges that suit a given function. Thus, the above examples are not intended to be limiting, as other mean stresses and stress ranges are contemplated by the present disclosure.

[0022] The dynamic bias controls the intra-substrate stress of the piezoelectric layer 106. A controlled stress range means that the piezoelectric layer 106 is flatter (e.g., more planar) within the piezoelectric element 100. Improved planarity affects the performance of the piezoelectric element 100 and improves the yield in manufacturing the piezoelectric element 100. Increasing or decreasing the dynamic bias during the formation of the piezoelectric element 100 can also affect the stress level of the piezoelectric layer 106. A large stress range within the piezoelectric layer 106 can lead to reduced performance.

[0023] The system can be adjusted to a predetermined mean stress, and then the dynamic bias can be increased or decreased based on measurements of the stress within the piezoelectric layer 106 to maintain the stress level and range close to the predetermined mean stress. The dynamic bias can also control the mean stress and stress range by controlling the material properties of the piezoelectric layer 106, such as the deposition rate and crystallinity. For example, improved control of crystallinity can increase the predictability of the piezoelectric layer 106's properties, and therefore adjusting the dynamic bias to promote favorable crystalline behavior can facilitate control of the stress within the substrate. Controlling the deposition rate further promotes uniform deposition, resulting in consistent film properties throughout the piezoelectric layer 106 and, consequently, the predetermined mean stress and stress range. In this manner, these piezoelectric devices 100 can be manufactured in high volume (HVP) production.

[0024] Figure 3 is a flow diagram of a method 300 for forming the piezoelectric element 100 shown in Figures 4A-4C. Figures 4A-4C are schematic side views of the substrate 102 in the method 300 for forming the piezoelectric element 100.

[0025] As shown in FIG. 4A, in operation 301, a bottom electrode layer 104 is disposed on a substrate 102. The substrate 102 is supported on a substrate support or pedestal. The bottom electrode layer 104 can be disposed via a PVD process, a CVD process, or an ALD process performed in a suitable processing chamber. In certain embodiments, the deposition process is performed at a temperature between about 25° C. and about 600° C., e.g., between about 400° C. and about 600° C., e.g., about 500° C. In certain embodiments, for deposition via PVD, the pedestal in the processing chamber is negatively biased during the deposition process by a pulsed or continuous power supply that supplies DC power to the pedestal at a static electrical bias power level between about 400 W and about 1000 W, e.g., between about 600 W and about 800 W.

[0026] As shown in FIG. 4B , in operation 302, a piezoelectric layer 106 is disposed on the bottom electrode layer 104. The piezoelectric layer 106 is disposed via a PVD process, a CVD process, or an ALD process performed in a suitable processing chamber. In a particular embodiment, a target in the processing chamber is negatively biased by a pulsed or continuous power supply that supplies RF power to a pedestal. The power supplied to the pedestal is a dynamic bias with a power level between about 0 W and about 200 W, for example, between about 20 W and about 100 W. During deposition of the piezoelectric layer 106, the power level is varied to control the stress in the piezoelectric layer 106.

[0027] Varying the bias (e.g., dynamic bias) results in an average stress in the piezoelectric layer 106 ranging from about 50 MPa to about 300 MPa. The dynamic bias is intentionally varied throughout the processing of the substrate to achieve a predetermined function. The dynamic bias in the piezoelectric layer 106 results in a range of stress across the substrate 102 ranging from about ±0 MPa to about ±200 MPa. In one embodiment, the dynamic bias results in an average stress in the piezoelectric layer 106 of about 200 MPa, and a range of stress across the substrate 102 of about 100 MPa to about 300 MPa (i.e., ±100 MPa from the average stress value). In another embodiment, the dynamic bias in the piezoelectric layer 106 is about 100 MPa, and a range of stress across the substrate 102 of about 50 MPa to about 150 MPa (i.e., ±50 MPa). The dynamic bias can be further adjusted to create an average stress value and stress range that is compatible with a predetermined function. Accordingly, the above examples are not intended to be limiting, as other average stresses and stress ranges are contemplated by this disclosure.

[0028] In operation 303, as shown in FIG. 4C , a top electrode layer 108 is formed on the piezoelectric layer 106. The top electrode layer 108 is formed with a top electrode pattern 110. The top electrode layer 108 can be formed at one or more predetermined locations on the piezoelectric surface 107. In one embodiment that can be combined with other embodiments described herein, the top electrode layer 108 is deposited on the piezoelectric layer 106, and then the top electrode pattern 110 is formed by an etching process. The top electrode layer 108 can be disposed via a PVD process, a CVD process, or an ALD process performed in an appropriate processing chamber. In another embodiment that can be combined with other embodiments described herein, the top electrode layer 108 is sputtered through a proximity mask to form the top electrode pattern 110. Multiple top electrode patterns 110 can be formed on the piezoelectric layer 106. The top electrode pattern 110 is not limited to the pattern shown in FIG. 1 .

[0029] 5 is a schematic cross-sectional view of a processing chamber 500. The processing chamber 500 is utilized in a method for depositing piezoelectric layers during the fabrication of the piezoelectric device 100.

[0030] The processing chamber 500 includes a piezoelectric element 100 disposed on a surface of a stage 502. The stage 502 is positioned within the processing chamber 500 such that a surface (e.g., a pedestal) of the stage 502 faces a showerhead 504. The processing chamber 500 is operable to deposit piezoelectric element layers (i.e., the top electrode layer 108, the piezoelectric layer 106, and the bottom electrode layer 104). The process chamber 500 includes a controller 508 and a power supply 520. The controller 508 is in communication with the stage 502, the showerhead 504, and the power supply 520.

[0031] The controller 508 is generally designed to facilitate control and automation of the methods described herein. Deposition of the piezoelectric element layers (i.e., the top electrode layer 108, the piezoelectric layer 106, and the bottom electrode layer 104) occurs in a process volume 506 of a processing chamber 500. The processing chamber 500 may be a PVD chamber, a CVD chamber, an ALD chamber, or other type of chamber for depositing films. The controller 508 is coupled to or can communicate with the processing chamber 500 and is configured to receive data or input as sensor readings from multiple sensors within the processing chamber 500. The controller 508 is further configured to store these sensor readings in a memory.

[0032] The sensor readings include other previous sensor readings from within the processing chamber. The sensor readings include values ​​calculated and stored after the controller 508 measures the sensor readings and runs them through a system model. The system model is a program configured to estimate deposition time, thickness, and electrical bias within the processing chamber 500 throughout the deposition process. Thus, the controller 508 is configured to both retrieve the stored sensor readings and store the sensor readings for future use. Maintaining previous sensor readings allows the controller 508 to adjust the system model over time to reflect a more accurate version of the processing chamber.

[0033] The controller 508 may include a CPU (i.e., a computer system) and may be in communication with the CPU. The CPU may be a hardware unit or combination of hardware units capable of executing software applications and processing data. The CPU may have memory and mass storage, input controls, and a display device. In some configurations, the CPU includes a digital signal processor (DSP), an application specific integrated circuit (ASIC), a graphics processing unit (GPU), and / or a combination of such units. The CPU is generally configured to execute one or more software applications and process stored data. Support circuits are coupled to the CPU for supporting the processor in a conventional manner.

[0034] The controller 508 is configured to control the deposition of the top electrode layer 108, the piezoelectric layer 106, and the bottom electrode layer 104, as well as any additional layers that may be deposited on the substrate 102. The controller 508 is further configured to communicate with a power supply 520 to control an electrical bias applied to the stage 502 during the deposition process. The controller 508 may include a non-transitory computer-readable medium for storing instructions for the deposition process of the piezoelectric element 100. The instructions include negatively biasing the stage 502 in the processing chamber with a pulsed or continuous power source (e.g., the power supply 520) during the deposition process when depositing the bottom electrode layer 104 via PVD, as in operation 301 of the method 300. The power supply 520 provides DC power to the stage 502 at a static electrical bias power level of about 400 W to about 1000 W, e.g., about 600 W to about 800 W. The instructions further include, when depositing the piezoelectric layer 106, as in operation 302, varying the electrical bias of the power source 520 applied during deposition of the piezoelectric layer 106. The stage 502 is negatively biased by a pulsed or continuous power source that supplies RF power to the stage 502. The power supplied by the power source 520 to the stage 502 is a dynamic bias at a power level between about 0 W and about 200 W, for example, between about 20 W and about 100 W.

[0035] The stage 502 includes a stage actuator 510 that allows the stage 502 to scan in the X, Y, and Z directions, as shown in the coordinate system illustrated in Figure 5. The stage 502 is coupled to the controller 508 to provide position information of the stage 502 to the controller 508. The stage 502 further communicates with the controller 508 so that the stage 502 can move in desired directions to etch the piezoelectric layer 106.

[0036] In yet another embodiment, which may be combined with other embodiments described herein, the piezoelectric element 100 may be subjected to further processing to further characterize the piezoelectric element 100 .

[0037] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of the present disclosure being determined by the claims that follow.

Claims

1. disposing a bottom electrode layer over a substrate, the substrate being supported by a pedestal; disposing a piezoelectric layer on the bottom electrode layer on a horizontal surface; varying the electrical bias to the pedestal during deposition of the piezoelectric layer; forming an upper electrode layer on the piezoelectric layer with an upper electrode pattern; 1. A method of forming a piezoelectric element, comprising:

2. 2. The method of claim 1, wherein the step of varying the electrical bias to the pedestal is performed between 0 W and 200 W.

3. The method of claim 1 , wherein an average stress of the plurality of stresses along the horizontal plane in the piezoelectric layer is between about 50 MPa and about 300 MPa.

4. 4. The method of claim 3, wherein the maximum deviation from the average stress across the substrate is about 100 MPa and the minimum deviation from the average stress across the substrate is about 0 MPa.

5. 10. The method of claim 1, further comprising applying a static electrical bias of between 400 W and 3000 W to the pedestal during deposition of the bottom electrode layer and the top electrode layer.

6. The piezoelectric layer is made of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-titanate (PMN-PT), or LiNbO 3 10. The method of claim 1, comprising one or more of: (LNO);

7. 10. The method of claim 1, wherein the bottom electrode layer, piezoelectric layer, and top electrode layer are deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

8. The upper electrode layer and the lower electrode layer are made of platinum (Pt), molybdenum (Mo), SrRuO 3 , LaNiO 3 , CaRuO 3 , or LaSrMnO 3 The method of claim 1 , comprising:

9. A substrate; a lower electrode layer formed on the substrate; a piezoelectric layer formed on the bottom electrode layer on a horizontal surface, wherein a plurality of stresses in the piezoelectric layer along the horizontal surface have an average stress of about 50 MPa to about 300 MPa; an upper electrode layer formed on the piezoelectric layer; A piezoelectric element comprising:

10. The piezoelectric layer is made of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-titanate (PMN-PT), or LiNbO 3 10. The piezoelectric element of claim 9, comprising one or more of: (LNO).

11. 10. The piezoelectric element according to claim 9, wherein the piezoelectric layer has a thickness of 300 nm to 2000 nm.

12. 10. The piezoelectric element of claim 9, wherein the thickness of the piezoelectric layer varies between 300 nm and 2000 nm across the surface of the bottom electrode layer.

13. The upper electrode layer and the lower electrode layer are made of platinum (Pt), molybdenum (Mo), SrRuO 3 , LaNiO 3 , CaRuO 3 , or LaSrMnO 3 The piezoelectric element of claim 9 , comprising:

14. 10. The piezoelectric element according to claim 9, wherein the lower electrode layer has a thickness of 25 nm to 200 nm.

15. 10. The piezoelectric element according to claim 9, wherein the upper electrode layer has a thickness of 25 nm to 200 nm.

16. 1. A controller for a processing system storing instructions that, when executed by a processor, cause the system to: processing the substrate in the processing chamber by disposing the lower electrode layer on the substrate supported by the pedestal; disposing a piezoelectric layer on the lower electrode layer along a horizontal plane; Varying the electrical bias to the pedestal during deposition of the piezoelectric layer; forming an upper electrode layer on the piezoelectric layer with an upper electrode pattern; controller.

17. 17. The controller of claim 16, wherein the electrical bias to the pedestal is varied between 0 W and 200 W.

18. 17. The controller of claim 16, wherein an average stress of the plurality of stresses along the horizontal plane in the piezoelectric layer is between about 50 MPa and about 300 MPa.

19. 20. The controller of claim 18, wherein a maximum deviation from the average stress across the substrate is about 100 MPa and a minimum deviation from the average stress across the substrate is about 0 MPa.

20. The piezoelectric layer is made of aluminum nitride (AlN), scandium-doped aluminum nitride (ScAlN), lead zirconate titanate (PZT), lead magnesium niobate-titanate (PMN-PT), or LiNbO 3 17. The controller of claim 16, comprising one or more of: (LNO).

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