Highly uniform SiC crystals, ingots, substrates, and methods for manufacturing the same, and semiconductor devices

Abstract

This application provides highly uniform SiC crystals, ingots, substrates, and semiconductor devices, and relates to the technical field of silicon carbide wafers. The SiC crystals are grown directly by the PVT method without subsequent processing. The SiC crystals include faceted and non-faceted regions, where the faceted regions are located on the peripheral edge of the SiC crystal, and the doping concentration variation rate of the faceted regions is at least 1.5 times that of the non-faceted regions, and / or the carrier concentration variation rate of the faceted regions is at least 5 times that of the non-faceted regions. The faceted regions are removed during subsequent crystal processing, resulting in a faceted-free ingot and subsequently processed wafers and substrates with low loss, ensuring higher yield, performance, and reliability for the device side.

Description

[Technical Field]

[0001] This application relates to the technical field of silicon carbide wafers, and in particular to the production of highly uniform SiC crystals, ingots, substrates and its manufacturing method, and Related to semiconductor devices.

[0002] This application is based on a Chinese patent application filed on October 9, 2023 with the China Patent Office, bearing application number 202311294326.5 and entitled "Highly uniform silicon carbide substrate and semiconductor device," and a Chinese patent application filed on November 3, 2023 with application number 202311464895.X and entitled "SiC crystal with facets only at the edge, wafer thereof, and semiconductor device." and an application filed with the China Patent Office on May 11, 2024, with application number 202410579039.7, entitled "Highly uniform SiC crystals, ingots, substrates, and manufacturing methods thereof, and semiconductor devices." Priority is claimed from Chinese patent application Ser. No. 09 / 109,599, filed on Dec. 1, 2003, the entire contents of which are incorporated herein by reference. [Background technology]

[0003] Silicon carbide semiconductors have attracted attention due to their excellent physical properties, such as a wide band gap, high breakdown field strength, and high thermal conductivity. Power devices manufactured based on silicon carbide single crystal substrates have excellent properties, such as high voltage resistance, high temperature resistance, and low loss, and are therefore widely applied in industrial fields such as new energy vehicles, solar power generation, and power grids. Over the years of technological and industrial development, significant progress has been made in the manufacturing technology of silicon carbide single crystals. However, several problems remain, such as: 1) quality issues, which affect the yield, performance, and reliability of silicon carbide devices; and 2) cost issues, which affect the application of silicon carbide in terminals. Material and device yield losses due to material quality are also a major reason for the current high cost and difficulty in application of silicon carbide.

[0004] Furthermore, quality issues in silicon carbide include two types: first, significant quality issues such as material quality and yield due to defect issues can often be seen in the crystalline material indicators; and second, reliability issues such as material yield and device performance due to quality consistency issues can often be seen in the crystalline material indicators, which often pose a significant risk to reliability when applied to subsequent devices.

[0005] Facets are an inherent attribute of SiC crystals produced by sublimation, and such facets are present in all SiC crystals and wafers produced by conventional physical vapor transport (PVT). The facet regions have higher doping concentrations than other regions, and as a result, the carrier concentration and resistivity of the facet regions are significantly different from those of other regions, making them prone to quality problems in terms of electrical performance and defect state.

[0006] In this field, facets are commonly referred to as "growth characteristic surfaces," "growth facets," "characteristic growth surfaces," etc., and the corresponding English term is "facet." In this application, facet does not mean a growth interface. Summary of the Invention [Problem to be solved by the invention]

[0007] Therefore, improving quality and reducing costs are the goals of the continuous development of silicon carbide crystalline materials. In particular, the silicon carbide industry is currently rapidly entering the stage of large-scale production and application, and the stability, consistency, and reliability of the performance of silicon carbide materials play an important role in industrial development. This application focuses on the problem of consistent electrical performance during the production of silicon carbide single crystals, and aims to solve the problem of inconsistent electrical performance due to the inherent properties during silicon carbide growth and the resulting risks to device performance and reliability. [Means for solving the problem]

[0008] In order to solve the above problems, in a first aspect of the present application, there is provided a SiC crystal in which facets exist only at the edges, said SiC crystal being obtained by direct growth using a PVT method without subsequent processing, said SiC crystal including a faceted region and a non-faceted region, said faceted region being located on the outer peripheral end surface of the SiC crystal, and properties within the entire area of ​​said faceted region satisfying any one or two of the following a to b: a, the variation rate of the doping concentration in the facet region is 1.5 times or more than the variation rate of the doping concentration in the non-facet region; b, The variation rate of the carrier concentration in the faceted region is more than five times that of the carrier concentration in the non-faceted region.

[0009] The outer peripheral end face is the edge position of the lateral growth of the crystal, or is also called the edge position of the crystal.

[0010] In some embodiments, the distance between the edge of the facet region away from the outer peripheral edge and the outer peripheral edge is 3% or less of the diameter of the SiC crystal. In some embodiments, the distance between the edge of the facet region away from the outer peripheral edge and the outer peripheral edge is 2% or less of the diameter of the SiC crystal. The edge of the facet region away from the outer peripheral edge is the end of the facet region closer to the center of the silicon carbide crystal.

[0011] In some embodiments, the maximum cross-sectional area of ​​the facet region is 10% or less of the diametric cross-sectional area of ​​the SiC crystal and / or the volume of the facet region is 2% or less of the total volume of the SiC crystal. For example, the facet region may be at the edge of an obliquely upward or downward corner of the SiC crystal.

[0012] In some embodiments, the maximum cross-sectional area of ​​the facet region is 5% or less of the diametric cross-sectional area of ​​the SiC crystal, and / or the volume of the facet region is 0.6% or less of the total volume of the SiC crystal. The overall shape of the facet region may be triangular, conical, spherical, ellipsoidal, or rhomboidal. The diametric cross-section of the facet region may be elliptical, crescent, circular, or the like, but the present application is not limited thereto.

[0013] In some embodiments, the TDV of the faceted regions is at least six times the TDV of the non-faceted regions, or the TDV of the faceted regions is at least ten times the TDV of the non-faceted regions.

[0014] In some embodiments, the rate of variation of the dopant concentration in the faceted regions is at least five times greater than the rate of variation of the dopant concentration in the non-faceted regions, and / or the rate of variation of the carrier concentration in the faceted regions is at least ten times greater than the rate of variation of the carrier concentration in the non-faceted regions.

[0015] In the present invention, in a SiC crystal having facets only at the edges, the facet plane region is fixed directly to the edge of the crystal during the growth process by the PVT method, thereby reducing the loss rate of the subsequent silicon carbide crystal and reducing production costs.

[0016] In a second aspect of the present application, there is provided a facetless silicon carbide ingot obtained by removing the facet region from a SiC crystal having facets only at the edges.

[0017] In a third aspect of the present application, there is provided a SiC wafer, the SiC wafer being obtained by removing facet regions using a SiC crystal having facets only at the edges to obtain a facetless silicon carbide ingot, which is further cut to obtain the facetless silicon carbide ingot, the SiC wafer being free from any one or more of facets, highly doped regions, and defect accumulating regions within the entire area of ​​the SiC wafer.

[0018] A highly doped region refers to a black spot resembling a "birthmark" that can be seen with the naked eye and has a higher doping concentration than a non-faceted region in a silicon carbide wafer, and a defect accumulating region refers to a black spot resembling a "birthmark" that can be seen with the naked eye and has a higher defect density than a non-faceted region in a silicon carbide wafer.

[0019] In some embodiments, the SiC wafer has a doping concentration variation within a facet of <10% and / or a carrier concentration variation within a facet of <5%.

[0020] In some embodiments, the SiC wafer has a within-facet doping concentration variation of <8% and / or a within-facet carrier concentration variation of <3%.

[0021] In some embodiments, the TDV density of the SiC wafer is 100 cm -2 In some embodiments, the TDV density of the silicon carbide wafer is less than 10 cm -2 is smaller than.

[0022] In some embodiments, the SiC wafer is a silicon carbide wafer of any thickness, for example, the SiC wafer is 200 μm or more thick, or the silicon carbide wafer is 300 μm or more thick, or the silicon carbide wafer is 400 μm or more thick.

[0023] In some embodiments, the SiC wafer may be N-doped or co-doped with any other element, for example, nitrogen gas may be co-doped with one or more of P, As, Ge, Sn, B, and Al, and the resulting silicon carbide wafer may be of a conductive type.

[0024] In some embodiments, the wafer size may be 4 inches, 6 inches, 8 inches, 10 inches, or 12 inches.

[0025] In some embodiments, the basal plane dislocations (abbreviated as BPDs) in the silicon carbide wafer have a total density variation of 50 cm -2 In some embodiments, the silicon carbide wafer BPD has a total density variation of less than 20 cm -2 In some embodiments, the silicon carbide wafer BPD has a total density variation of less than 10 cm -2 Among these, the variation in the total density of BPDs is "maximum value of BPD density in the facet of the silicon carbide wafer - minimum value of BPD density in the facet of the silicon carbide wafer."

[0026] In a fourth aspect of the present application, there is provided a highly uniform silicon carbide substrate of a conductivity type obtained by processing the SiC crystal, wherein properties within the entire area of ​​the silicon carbide substrate satisfy one or two of the following a to b: a, the doping concentration fluctuation rate is <10%; b, The carrier concentration fluctuation rate is <5%.

[0027] In some embodiments, the silicon carbide substrate is an n-type element Doping, The aforementioned n-type element doping doping Concentration is ≥ 1E18cm -3 The silicon carbide substrate does not include either one or two of highly doped regions or defect accumulating regions within its entire area, and the silicon carbide substrate is produced by a PVT method.

[0028] The growth feature plane is an inherent attribute of SiC crystal produced by the PVT method, and in the highly uniform silicon carbide substrate of the present application, the tendency of movement of the growth feature plane can be varied during growth by the PVT method, allowing it to move to the edge of the crystal and be fixed within 5 mm from the edge of the crystal. When the crystal is actually used, the edge is always cut, and therefore a silicon carbide substrate that does not include the growth feature plane can be obtained by processing the crystal, such as cutting, grinding, and polishing.

[0029] The presence of the growth-characterized surface in the original substrate causes defects to be concentrated in that region, and the element doping process induces elements to gather and increase in the growth-characterized surface as well, resulting in the appearance of non-uniform doping, a higher resistivity in the growth-characterized surface than in other regions, and poor carrier uniformity throughout the substrate, which limits the large-scale use of silicon carbide substrates as described above.

[0030] The highly uniform silicon carbide substrate of the present application has a no-growth feature surface, and the entire substrate exhibits uniform distribution in both the radial and axial directions, thereby fundamentally suppressing the generation and concentration of defects, and avoiding the aggregation of elements during the doping process, thereby achieving uniform element doping, thereby improving the doping uniformity, resistivity uniformity, and carrier uniformity of the substrate. Therefore, devices produced using this silicon carbide substrate not only have excellent performance, but also have good consistency in mass production, which is advantageous for industrialization and widespread use.

[0031] In some embodiments, the n-type element The main doping element in the doping is N, but other elements may be co-doped in addition to N. Examples of such elements include group V elements such as phosphorus and arsenic, group IV elements such as Ge and Sn, and group III elements such as B and Al.

[0032] In some embodiments, the variation in doping concentration may be <8%, or the variation in doping concentration may be <5%, or the variation in doping concentration may be <3%.

[0033] In some embodiments, the variation in carrier concentration is <3%, or the variation in carrier concentration is <2%, or the variation in carrier concentration is <1%.

[0034] In some embodiments, the doping concentration but 5E19cm -3 Below is If The carrier concentration fluctuation rate is <5%.

[0035] In some embodiments, the n-type element doping is N2 doping, the variation rate of the doping concentration is <3%, and the variation rate of the carrier concentration is <1%.

[0036] The rate of variation of the doping concentration is "maximum value of doping concentration in the facet of the silicon carbide substrate - minimum value of doping concentration in the facet of the silicon carbide substrate", and the rate of variation of the carrier concentration is "maximum value of carrier concentration in the facet of the silicon carbide substrate - minimum value of carrier concentration in the facet of the silicon carbide substrate".

[0037] The N-type element doping concentration is 1e18cm -3 This is larger than the above and belongs to the medium-high nitrogen doping range. Those skilled in the art will understand that the higher the doping concentration, the more likely it is that the doping will be non-uniform. However, in the present application, the growth feature plane is fixed to the crystal edge in the process of controlling the tendency of movement of the growth feature plane, thereby improving the doping uniformity during the doping process and making the resistivity of the substrate more uniform.

[0038] Carriers depend on the doping concentration and uniformity in the crystal, and the carrier concentration variation rate of the silicon carbide substrate of the present application of <5% can represent the carrier uniformity of the silicon carbide substrate, which is advantageous for improving the quality of the downstream device-side lithography process and further improving device performance.

[0039] In some embodiments, the TDV density of the silicon carbide substrate is 100 cm -2 In some embodiments, the TDV density of the silicon carbide substrate is less than 50 cm -2 In some embodiments, the TDV density of the silicon carbide substrate is less than 10 cm -2The total density variation (TDV) is defined as the density of edge dislocations (TEDs) or screw dislocations (TSDs) within a lattice of a specific area, e.g., n lattices with areas of 1mm x 1mm, 2mm x 2mm, 5mm x 5mm, and 10mm x 10mm, as d1, d2, d3, ... dn. TDV is the difference (dmax - dmin) between the maximum TED / TSD density and the minimum TED / TSD density. The elimination of growth features results in a uniform doping concentration within the facets of the silicon carbide substrate, improving TDV and eliminating problems with dislocations and stacking faults within the silicon carbide substrate.

[0040] In some embodiments, the variation in total density of the silicon carbide substrate TED is greater than 100 cm -2 In some embodiments, the variation in total density of the silicon carbide substrate TED is less than 50 cm -2 In some embodiments, the variation in total density of the silicon carbide substrate TED is less than 10 cm -2 is smaller than.

[0041] In the silicon carbide substrate of the present invention, the growth feature plane is eliminated and the distribution of TEDs and TSDs can be made more uniform, resulting in a low TDV value and a uniform distribution of dislocations across the entire substrate, eliminating the problem of low overall defect density but locally high density that existed in conventional substrates.

[0042] In some embodiments, the variation in total density of basal plane dislocations (abbreviated as BPDs) in the silicon carbide substrate is 50 cm -2 In some embodiments, the variation in total density of the silicon carbide substrate BPD is less than 20 cm -2 In some embodiments, the variation in total density of the silicon carbide substrate BPD is less than 10 cm -2 is smaller than.

[0043] When the substrate is used to manufacture a power electronic device, the low dopant concentration variation rate and the low carrier concentration variation rate can ensure that the device has excellent electrical performance and reliability during the device production process.

[0044] In some embodiments, the silicon carbide substrate may be 4 inches, 6 inches, 8 inches, 10 inches, or 12 inches in size.

[0045] In a fifth aspect of the present application, there is provided a semiconductor device including the SiC wafer or highly uniform silicon carbide substrate.

[0046] Fifth aspect of the present application So, The present invention provides a method for manufacturing the highly uniform silicon carbide substrate, wherein the silicon carbide substrate is obtained from a crystal that has undergone at least a cutting step. Facets are an inherent attribute of SiC crystals produced by sublimation, and such facet regions exist in both SiC crystals and wafers produced by conventional physical vapor transport. To fix the facets to the crystal edges and remove them during subsequent crystal processing, thereby ensuring that the entire ingot and subsequently processed wafers and substrates are free of facets, the present invention's processing method for SiC crystals located at the facet edges includes a stable crystal growth stage, and the growth process conditions for the stable crystal growth stage include the following steps:

[0047] S1: A discontinuous temperature gradient distribution is provided in the radial direction of the crystal growth surface, a limiting edge exists close to the crystal growth edge, the distance between the limiting edge and the crystal growth edge is 6 mm or less, a continuous and positive temperature gradient is set from the limiting edge to the crystal center, the temperature gradient within the range between the limiting edge and the crystal growth edge is ≧2°C / cm, and the temperature gradient value within the range between the limiting edge and the crystal growth edge is greater than the temperature gradient value from the limiting edge to the crystal center.

[0048] S2: Set the seed crystal so that the deviation angle in the crystal orientation parallel to the <11-20> or <1-100> or any other c-plane direction is >0°.

[0049] S3: The angle α of the crystal-grown graphite ring in the direction parallel to the crystal growth direction is set to be greater than 0°.

[0050] S4: The silicon carbide powder is sufficiently arranged between the inner wall of the crystal growth chamber and the crystal growth graphite ring, thereby ensuring a sufficient reaction atmosphere for the lateral growth of the SiC crystal and ensuring a chemical environment for continuous lateral growth of the SiC crystal, and the highly uniform silicon carbide substrate is obtained by processing the SiC crystal.

[0051] In some embodiments, the temperature gradient within the confinement side and the crystal growth edge described in step S1 is ≥ 5°C / cm; and / or The deviation angle of the seed crystal in the <11-20> crystal orientation in step S2 is >2°, and / or The angle of the crystal-grown graphite ring in the direction parallel to the crystal growth direction in step S3 is α≧8°.

[0052] In some embodiments, the distance between the limiting side and the crystal growth edge is 5 mm or less.

[0053] In some embodiments, in step S1, a continuous positive temperature gradient is set within a range of 5 mm from the crystal growth edge, the value of the continuous positive temperature gradient being ≦3° C. / cm, and the temperature gradient within a range of less than 5 mm from the crystal growth edge being ≧5° C. / cm. For example, as shown in FIG. 6 , the coordinate origin is set to the center of the wafer, and a discontinuous temperature gradient distribution is set in the radial direction of the crystal growth surface, the positive temperature gradient within a range of more than 5 mm from the crystal growth edge being a continuous smooth curve, and the temperature gradient within a range of less than 5 mm from the crystal growth edge is larger than the temperature gradient within a range of more than 5 mm from the crystal growth edge.

[0054] The radial temperature gradient is calculated as the ratio of the difference (T2-T1) between the temperature T1 at a point close to the wafer center and the temperature T2 at a point far from the wafer center to the distance d between the two points, with the wafer center as the origin and radiating outward in the radial direction. A positive (forward) temperature gradient is ΔT = (T2-T1) / d, and conversely, a negative temperature gradient is ΔT = (T1-T2) / d.

[0055] In the manufacturing method employed in the present application, step S1 is set so that the edge also continuously grows and expands laterally during the crystal growth process. The present application ensures sufficient driving force for lateral growth of the crystal edge and continuously ensures the ability of the crystal edge to expand by increasing the temperature gradient within a range of less than 6 mm from the crystal growth edge compared to a range of more than 6 mm from the crystal growth edge during the crystal growth process. The expansion growth drives the growth feature plane to move toward the crystal edge and fixes it within a range of 5 mm from the crystal edge, resulting in a highly uniform silicon carbide substrate. However, as will be understood by those skilled in the art, the silicon carbide substrate of the present application may be obtained by controlling the trend of the growth feature plane in other ways. Therefore, this application only describes the manufacturing method for the highly uniform silicon carbide substrate obtained in this application. Other methods for controlling the trend of the growth feature plane are beyond the scope of this study.

[0056] The radial temperature gradient of crystal growth in step S1 can be set using technical means commonly used in the industry, such as by adjusting parameters such as the temperature or pressure in the growth chamber or the thickness of the heat-insulating layer. Setting a discontinuous temperature gradient can be achieved by improving the structuring of the crystal growth chamber and optimizing the temperature distribution at the crystal growth interface, achieving a controllable temperature gradient. For example, by placing a material with lower thermal conductivity at the edge of the crystal growth chamber than at the center to reduce edge heat loss and thereby achieve a jump in the temperature distribution at the crystal growth interface. Conversely, a reverse temperature gradient distribution can be achieved by placing a material with higher thermal conductivity at the crystal growth edge or by reducing the thickness of the edge heat-insulating layer. The temperature distribution can also be adjusted by using a different thermal boundary structure or a novel material in the growth chamber, such as by applying a highly reflective TaC coating material to the graphite ring at the crystal growth edge to concentrate the heat radiation in the growth chamber at the crystal growth edge and achieve a jump in the temperature gradient. Using these technical means commonly used in the industry, solutions can be configured according to actual needs to achieve the goal of adjusting the temperature gradient in the crystal growth chamber.

[0057] In some embodiments, in the crystal growth stabilization step, the temperature in the growth chamber is increased to 2200°C or higher at a rate of 10 to 50°C / min, and the pressure in the growth chamber is reduced to 1 to 100 mbar, and then the settings in steps S1 to S4 are maintained for 50 hours or more to grow the crystal.

[0058] In some embodiments, in the crystal growth stabilization step, the temperature inside the growth chamber is increased to 2200°C or higher at a rate of 10 to 30°C / min, and the pressure is reduced to 5 to 50 mbar, and then the settings of steps S1 to S4 are maintained for 50 hours or more to grow the crystal.

[0059] In the present application, silicon carbide crystals are produced by the PVT method, and the crystal growth is performed using isostatically pressed graphite as the raw material for the growth chamber (crucible) and SiC powder as the raw material for crystal growth. In order to ensure excellent and stable electrical performance of silicon carbide, in some embodiments, silicon carbide having a certain purity is used to synthesize the powder, and the total impurity content of the silicon carbide powder is 1E19 cm -3 and in some embodiments, the content of total impurities in the silicon carbide powder is 1E17 cm or less. -3 The following is the result.

[0060] In the present application, during silicon carbide crystal growth, SiC powder is placed inside a graphite crucible, and a SiC seed crystal is placed at the top of the growth chamber. The crucible is then sealed, and the crucible is placed and wrapped in a heat insulating material made of soft or hard graphite felt, and then transferred to a crystal growth equipment chamber for crystal growth.

[0061] In the present application, as shown in Fig. 3, a graphite support member is provided on the top of the SiC crucible, and SiC powder is charged between the graphite support member and the wall of the SiC crucible as a material source for lateral growth, thereby ensuring sufficient radial expansion space for the lateral growth of the crystal. However, the present application is not limited to this, and other design methods may also be used.

[0062] In some embodiments, the method further comprises a crystal nucleation stage before the crystal stable growth stage, and the growth process conditions for the crystal nucleation stage comprise the following steps:

[0063] After sealing the crystal growth chamber, -3 The growth chamber is evacuated to below 100 Pa, and after the vacuum level has stabilized for a certain period of time, inert gas is introduced. The pressure in the growth chamber is gradually increased to 100-1000 mbar and then stabilized. At the same time, nitrogen gas is introduced into the chamber at 1 ml / min-100 ml / min.

[0064] In some embodiments, during the crystal nucleus formation stage, the pressure in the growth chamber is increased, and the temperature in the growth chamber is gradually increased from room temperature to 1600-2100°C and then kept constant. The constant temperature and pressure are maintained for 5-50 hours, after which the crystal stable growth stage is carried out.

[0065] In some embodiments, during the crystal nucleation stage, the temperature in the growth chamber is constant at 1800 to 2100°C, and the pressure in the growth chamber is constant at 300 to 800 mbar, and the constant temperature and pressure are maintained for 30 to 50 hours before the crystal stable growth stage is carried out.

[0066] In the crystal nucleus formation stage, the silicon carbide powder sublimes to form crystal nuclei. In the subsequent stable crystal growth stage, the silicon carbide powder sublimes sufficiently and is transferred to the seed crystal, where it grows stably, ultimately producing a silicon carbide crystal. Because the diameter of the seed crystal is at least 5 mm larger than the diameters of the target crystal and substrate, the produced SiC crystal has enough margin for edge processing, and once the edge is cut, a highly uniform silicon carbide crystal can be obtained. In addition, this method ensures smooth production of large-sized silicon carbide substrates and improves the quality of the produced silicon carbide substrates. [Effects of the Invention]

[0067] Compared with the prior art, the present application achieves at least one of the following beneficial effects:

[0068] (1) In this application, in a SiC crystal having facets only at the edge, the facet regions are fixed to the outer peripheral end surface of the SiC crystal during the growth process using the direct PVT method, and the facet regions are then removed during the subsequent crystal processing process, resulting in a low loss rate and a lack of facet regions in the entire ingot and in the subsequently processed wafers and substrates, thereby reducing the production cost of silicon carbide crystals and ensuring the production of silicon carbide crystals with few defects and high uniformity.

[0069] (2) In the present application, the silicon carbide wafer has high uniformity in doping uniformity, carrier uniformity, etc. Also, in the present application, the silicon carbide wafer has no facets that can be seen with the naked eye.

[0070] (3) In the present application, the silicon carbide substrate has no visible facets, and the variation rate of the doping concentration within the entire area range is less than 10%, and the variation rate of the carrier concentration is less than 5%, which indicates that the silicon carbide substrate has high uniformity, and that semiconductor devices manufactured using the silicon carbide substrate have higher yield, performance, and reliability.

[0071] (4) In the present application, the silicon carbide substrate has a TDV density of 100 cm 2 within the entire area. -2 The overall defect density is smaller than that of conventional substrates, but the problem of locally high density is eliminated. Furthermore, there are almost no dislocations or stacking faults, making it more suitable for widespread use and application.

[0072] (5) In the present application, the silicon carbide substrate has high uniformity in doping, carrier uniformity, etc. When the substrate is cut to manufacture semiconductor devices, the utilization rate of the effective area can be improved, and the manufactured semiconductor devices not only have better performance than other substrates of the same area, but also are more numerous, which reduces the production cost of the semiconductor devices. [Brief explanation of the drawings]

[0073] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description of the embodiments taken in conjunction with the following drawings.

[0074] [Figure 1] 1 shows one exemplary embodiment including a structural schematic diagram of a faceted silicon carbide substrate as seen by the naked eye. [Figure 2] 1 shows one illustrative example of a schematic diagram of the facet growth process of the present application. [Figure 3] 1 shows one exemplary embodiment of a schematic diagram of a silicon carbide crystal growth structure of the present application. [Figure 4] 10 is a graph comparing the carrier concentration of a silicon carbide substrate of Example 2 with the carrier concentration of a silicon carbide substrate of Comparative Example 1. [Figure 5] 1 illustrates one exemplary embodiment of a structural schematic diagram of a growth-feature-free silicon carbide substrate. [Figure 6] 1 shows one exemplary embodiment of a schematic diagram of a discontinuous temperature gradient provided radially on a crystal growth surface according to the present application. DETAILED DESCRIPTION OF THE INVENTION

[0075] In order to make the above objects, features and advantages of the present application more clearly understandable, the present application will be described in more detail below with reference to the drawings and specific embodiments. It should be noted that, unless inconsistent, the examples and features in the examples of the present application can be combined with each other.

[0076] In the following description, numerous specific details are set forth to facilitate a thorough understanding of the present application; however, the present application may be implemented in other ways different from those described herein, and therefore the scope of protection of the present application is not limited to the specific embodiments disclosed below.

[0077] In the silicon carbide crystal manufacturing process of Examples 1 to 6 described below, the growth feature plane can be fixed to the silicon carbide crystal edge, and as the crystal edge is cut, a silicon carbide substrate with a non-growth feature plane is obtained. Because the inherent structural attributes of the growth feature plane are eliminated, even if the number of defects in the silicon carbide substrate itself is reduced, no aggregation occurs. At the same time, aggregation of elements during doping, i.e., the presence of highly doped regions, can be avoided, and as a result, the doping uniformity and carrier uniformity of the silicon carbide substrate with a structure like the non-growth feature plane are both improved.

[0078] Example 1 This embodiment relates to a method for manufacturing a 6-inch high-uniformity silicon carbide substrate, which specifically includes the following steps:

[0079] (1) During the crystal nucleation stage After the silicon carbide powder and seed crystal were placed in the crucible, the growth chamber was sealed and the growth chamber was heated for 10 minutes using a mechanical pump and a vacuum pump. -3 After the vacuum level stabilized for a certain period of time, inert gas was introduced and the pressure in the growth chamber was gradually increased to 100 mbar, while nitrogen gas was introduced into the chamber at a rate of 10 ml / min. During the crystal nucleation stage, as the pressure in the growth chamber increased, the furnace temperature was gradually increased from room temperature to 1600°C by adjusting the power settings and maintained at this temperature for 10 hours.

[0080] (2) During the stable crystal growth stage After the crystal nucleation stage was completed, the temperature was increased to 2300°C at a rate of 20°C / min, and the pressure in the growth chamber was reduced to 3 mbar by adjusting the pressure controller and maintained for 60 h.

[0081] S1: A discontinuous temperature gradient distribution is provided in the radial direction of the crystal growth surface, and a continuous and positive temperature gradient is set within a range of 3 mm from the crystal growth edge and more than 4 mm from the crystal growth edge, with the continuous and positive temperature gradient value being 5°C / cm, and the temperature gradient within a range of less than 4 mm from the crystal growth edge being 10°C / cm, thereby sufficiently ensuring the driving force for lateral growth of the crystal edge and continuously ensuring the radial expansion growth ability of the crystal edge; S2: The deviation angle of the seed crystal in the <11-20> crystal orientation is set to 1.5°; S3: The angle α of the crystal-grown graphite ring in the direction parallel to the crystal growth direction is set to 10°, thereby ensuring sufficient radial expansion space for the lateral growth of the crystal; S4: The silicon carbide powder was placed sufficiently between the inner wall of the crystal growth chamber and the graphite ring for crystal growth, thereby ensuring a sufficient reaction atmosphere for the lateral growth of SiC crystals and a chemical environment that allows for continuous lateral growth of SiC crystals. The grown crystals were then cut, ground, polished, and other processes to obtain the desired silicon carbide substrates.

[0082] <Example 2> This embodiment relates to a method for manufacturing a 6-inch high-uniformity silicon carbide substrate, which specifically includes the following steps:

[0083] (1) During the crystal nucleation stage After the silicon carbide powder and seed crystal were placed in the crucible, the growth chamber was sealed and the growth chamber was heated for 10 minutes using a mechanical pump and a vacuum pump. -3 After the vacuum level stabilized for a certain period of time, inert gas was introduced and the pressure in the growth chamber was gradually increased to 400 mbar, while nitrogen gas was introduced into the chamber at 40 ml / min. During the crystal nucleation stage, as the pressure in the growth chamber increased, the furnace temperature was gradually increased from room temperature to 1900°C by adjusting the power settings and maintained at this temperature for 40 hours.

[0084] (2) During the stable crystal growth stage After the crystal nucleation stage was completed, the temperature was increased to 2500°C at a rate of 30°C / min, and the pressure in the growth chamber was reduced to 20 mbar by adjusting the pressure controller and maintained for 60 h.

[0085] S1: A discontinuous temperature gradient distribution is provided in the radial direction of the crystal growth surface, and a continuous and positive temperature gradient is set within a range of more than 5 mm from the crystal growth edge, with the boundary being 5 mm from the crystal growth edge. The continuous and positive temperature gradient value is 2°C / cm, and the temperature gradient within a range of less than 5 mm from the crystal growth edge is 8°C / cm, thereby sufficiently ensuring the driving force for lateral growth of the crystal edge and continuously ensuring the radial expansion growth ability of the crystal edge. S2: The deviation angle of the seed crystal in the <11-20> crystal orientation is set to 1°; S3: The angle α of the crystal-grown graphite ring in the direction parallel to the crystal growth direction is set to 8°, thereby ensuring sufficient radial expansion space for the lateral growth of the crystal; S4: The silicon carbide powder was placed sufficiently between the inner wall of the crystal growth chamber and the graphite ring for crystal growth, thereby ensuring a sufficient reaction atmosphere for the lateral growth of SiC crystals and a chemical environment that allows for continuous lateral growth of SiC crystals. The grown crystals were then cut, ground, polished, and other processes to obtain the desired silicon carbide substrates.

[0086] Example 3 This embodiment relates to a method for manufacturing a 6-inch high-uniformity silicon carbide substrate, which specifically includes the following steps:

[0087] (1) During the crystal nucleation stage After the silicon carbide powder and seed crystal were placed in the crucible, the growth chamber was sealed and the growth chamber was heated for 10 minutes using a mechanical pump and a vacuum pump. -3 After the vacuum level stabilized for a certain period of time, inert gas was introduced and the pressure in the growth chamber was gradually increased to 900 mbar, while nitrogen gas was introduced into the chamber at 60 ml / min. During the crystal nucleation stage, as the pressure in the growth chamber increased, the furnace temperature was gradually increased from room temperature to 2000°C by adjusting the power settings and maintained at this temperature for 40 hours.

[0088] (2) During the stable crystal growth stage After the crystal nucleation stage was completed, the temperature was increased to 2700°C at a rate of 40°C / min, and the pressure in the growth chamber was reduced to 40 mbar by adjusting the pressure controller and maintained for 60 h.

[0089] S1: A discontinuous temperature gradient distribution is provided in the radial direction of the crystal growth surface, and a continuous and positive temperature gradient is set within a range of 2 mm from the crystal growth edge and more than 3 mm from the crystal growth edge, with the continuous and positive temperature gradient value being 3°C / cm, and the temperature gradient within a range of less than 3 mm from the crystal growth edge being 12°C / cm, thereby sufficiently ensuring the driving force for lateral growth of the crystal edge and continuously ensuring the radial expansion growth ability of the crystal edge. S2: The deviation angle of the seed crystal in the <11-20> crystal orientation is set to 3°; S3: The angle α of the crystal-grown graphite ring in the direction parallel to the crystal growth direction is set to 10°, thereby ensuring sufficient radial expansion space for the lateral growth of the crystal; S4: The silicon carbide powder was placed sufficiently between the inner wall of the crystal growth chamber and the graphite ring for crystal growth, thereby ensuring a sufficient reaction atmosphere for the lateral growth of SiC crystals and a chemical environment that allows for continuous lateral growth of SiC crystals. The grown crystals were then cut, ground, polished, and other processes to obtain the desired silicon carbide substrates.

[0090] Example 4 This embodiment relates to a method for manufacturing a 6-inch high-uniformity silicon carbide substrate, which specifically includes the following steps:

[0091] (1) During the crystal nucleation stage After the silicon carbide powder and seed crystal were placed in the crucible, the growth chamber was sealed and the growth chamber was heated for 10 minutes using a mechanical pump and a vacuum pump. -3 After the vacuum level stabilized for a certain period of time, inert gas was introduced and the pressure in the growth chamber was gradually increased to 300 mbar, while nitrogen gas was introduced into the chamber at 40 ml / min. During the crystal nucleation stage, as the pressure in the growth chamber increased, the furnace temperature was gradually increased from room temperature to 1800°C by adjusting the power settings and maintained at this temperature for 30 hours.

[0092] (2) During the stable crystal growth stage After the crystal nucleation stage was completed, the temperature was increased to 2400°C at a rate of 30°C / min, and the pressure in the growth chamber was reduced to 10 mbar by adjusting the pressure controller and maintained for 70 h.

[0093] S1: A discontinuous temperature gradient distribution is provided in the radial direction of the crystal growth surface, and a continuous and positive temperature gradient is set within a range of 1 mm from the crystal growth edge and greater than 4.5 mm from the crystal growth edge, with the continuous and positive temperature gradient value being 2°C / cm, and the temperature gradient within a range of less than 4.5 mm from the crystal growth edge being 4°C / cm, thereby sufficiently ensuring the driving force for lateral growth of the crystal edge and continuously ensuring the radial expansion growth ability of the crystal edge. S2: The deviation angle of the seed crystal in the <11-20> crystal orientation is set to 0.5°; S3: The angle α of the crystal-grown graphite ring in the direction parallel to the crystal growth direction is set to 20°, thereby ensuring sufficient radial expansion space for the lateral growth of the crystal; S4: The silicon carbide powder was placed sufficiently between the inner wall of the crystal growth chamber and the graphite ring for crystal growth, thereby ensuring a sufficient reaction atmosphere for the lateral growth of SiC crystals and a chemical environment that allows for continuous lateral growth of SiC crystals. The grown crystals were then cut, ground, polished, and other processes to obtain the desired silicon carbide substrates.

[0094] <Example 5> The present example differs significantly from Example 2 in that in step S1, the temperature gradient within a range of less than 5 mm from the crystal growth edge is 6°C / cm, and an 8-inch silicon carbide substrate is manufactured in this example. The other steps are the same as those in Example 2.

[0095] Example 6 The present embodiment differs significantly from Example 2 in that in step S1, a continuous and positive temperature gradient is set within a range of more than 5 mm from the crystal growth edge, the value of the continuous and positive temperature gradient is 7°C / cm, and an 8-inch silicon carbide substrate is manufactured in this embodiment, while the other steps are the same as those in Example 2.

[0096] (Comparative Example 1) This comparative example differs from Example 2 in that in step S1, a continuous and positive temperature gradient is set from the center of the crystal to the edge, and the continuous and positive temperature gradient is 3°C / cm. The other steps are the same as in Example 2.

[0097] (Comparative Example 2) This comparative example differs from Example 2 in that in step S1, the temperature gradient in the range less than 5 mm from the crystal growth edge is 1° C. / cm, and the other steps are the same as Example 2.

[0098] Specifically, the parameters of the processing methods of Examples 1 to 6 are shown in Table 1.

[0099] [Table 1]

[0100] <Experimental Example 1> For SiC crystals with edge-only facets produced by the above method, the location of the facet regions in the crystal is shown in Table 2. The volume of the facet regions can be calculated using calculus or modeling methods.

[0101] [Table 2]

[0102] As shown in Table 2, in the present invention, SiC crystals with facets only on the edges are directly controlled during the PVT production process to move the facet region away from the outer peripheral end surface of the crystal, moving the facet to a region outside the target diameter of the crystal. This allows the facet region to be removed with a low loss rate during subsequent crystal processing, resulting in SiC crystals with few defects. In Comparative Examples 1 and 2, the facet region is located in an intermediate position, within the range of the target diameter of the crystal, resulting in low yield, performance, and reliability of the devices obtained in subsequent processing.

[0103] The SiC crystal obtained in the example, which has facets only on the edges, was processed, and the facet region was removed and directly cut to obtain SiC wafers. Comparative Example 1 and Comparative Example 2 were cut to form silicon carbide wafers. The SiC wafer performance test is shown in Table 3.

[0104] The rate of variation of the doping concentration is "maximum value of doping concentration in the facet - minimum value of doping concentration in the facet", and the rate of variation of the carrier concentration is "maximum value of carrier concentration in the facet - minimum value of carrier concentration in the facet".

[0105] [Table 3]

[0106] As shown in Table 3, it can be seen that the silicon carbide wafer obtained according to the present invention has high uniformity in doping uniformity, carrier uniformity, etc. Furthermore, the silicon carbide wafer of the present invention has no visible facets.

[0107] Based on Examples 1 to 3, the SiC crystals produced in Examples 1 to 3, each having facets only on the edges, were directly cut to obtain silicon carbide wafers including facets. The performance tests of the obtained silicon carbide wafers including facets were conducted, and the results are shown in Table 4.

[0108] [Table 4]

[0109] As shown in Table 4, the variation rate of the dopant concentration including the facet region is 1.5 times or more than the variation rate of the dopant concentration in the non-facet region, the variation rate of the carrier concentration including the facet region is 4 times or more than the variation rate of the carrier concentration in the non-facet region, and the TDV of the facet region is 6 times or more than the TDV of the non-facet region.

[0110] The present invention provides a SiC crystal with facets only at the edges that can be grown directly by the PVT method without subsequent processing. The facet regions are fixed to the peripheral end surfaces of the SiC crystal, and then removed during subsequent processing of the crystal, resulting in a low loss rate and a facet-free ingot and subsequently processed wafers and substrates. This reduces the production cost of silicon carbide crystals and ensures that silicon carbide wafers with few defects and high uniformity can be obtained.

[0111] <Experimental Example 2> In both the above examples and comparative examples, silicon carbide crystals were manufactured by the PVT crystal growth method, and both the examples and comparative examples used silicon carbide substrates obtained by the same edge cutting (5 mm cut), radial cutting, grinding and polishing processes. The results of performance detection of the obtained silicon carbide substrate samples are shown in Table 5.

[0112] [Table 5]

[0113] The present invention establishes a discontinuous temperature gradient distribution in the radial direction of the crystal growth surface, thereby fully ensuring the driving force for lateral growth at the crystal edge and continuously ensuring the radial expansion growth capability of the crystal edge. The crystals of the examples and comparative examples do not change in substrate quality even when subjected to the same conventional edge cutting, radial cutting, grinding, and polishing processes. Therefore, based on the data in Table 2, the manufacturing method of the present invention can control the tendency of growth feature planes to move and fix them at the crystal edge. This control of movement tendency is shown in Figure 2, where the growth feature planes at the crystal edge can be removed by cutting the crystal edge. Therefore, the substrates of Examples 1 to 6 do not have growth feature planes. Neither the conventional positive temperature gradient of Comparative Example 1 nor the 1°C / mm temperature gradient at the edge of Comparative Example 2 can move and fix the growth feature planes at the edge.

[0114] It can be seen that the silicon carbide substrates of Comparative Example 1 and Comparative Example 2 both contain a growth feature surface with the structure shown in FIG. 1 that is visible to the naked eye, and do not contain black spots like "birthmarks" within the entire area range of the silicon carbide substrate with a growth featureless surface. None of the silicon carbide substrates produced in Examples 1 to 6 contain a growth feature surface with the structure shown in FIG. 5 that is visible to the naked eye. From the above Examples and Comparative Examples and FIGS. 1 and 5, it can be seen that silicon carbide substrates with a growth featureless surface were produced using the production method of the present application, and when combined with other parameters disclosed in Table 5, the absence of a structure like a growth feature surface meant that the variation rate of the doping concentration within the facet of the silicon carbide substrate was <10%, the variation rate of the carrier concentration was <5%, and the TDV density was 200 cm -2 The silicon carbide substrates including the growth feature planes of Comparative Examples 1 and 2 had a doping concentration variation rate within the facet of more than 15%, a carrier concentration variation rate of more than 50%, and a TDV of 450 cm -2 , indicating that the performance of the silicon carbide substrate as a whole is inferior.

[0115] As shown in Figure 4, the abscissa represents test points in the diameter direction of the substrate, and the ordinate represents carrier concentration. The curve without black dots in Figure 4 is a graph showing the variation in carrier concentration in the diameter direction of the silicon carbide substrate without growth features of Example 2 of the present application, while the curve with black dots is a graph showing the variation in carrier concentration in the diameter direction of the conventional substrate of Comparative Example 1. As shown in Figure 4, the silicon carbide substrate with the conventional growth features has significantly high-concentration nitrogen-doped regions and high-carrier-concentration regions in the diameter direction within the growth feature region. The resistivity in these regions is significantly lower than that of other regions, resulting in a non-uniform resistivity distribution within the facet of the substrate. Furthermore, the highly nitrogen-doped regions tend to be areas with the highest crystal growth rates and are prone to defects such as edge dislocations. The high-concentration carrier regions can also convert and extend basal plane dislocations into stacking faults during epitaxial processing and device use, further affecting the yield, performance, and ultimate reliability of the device.

[0116] The present invention eliminates growth features, which significantly improves doping uniformity and carrier uniformity within the substrate, and eliminates the accumulation of defects within the substrate, such as growth feature inclusions, dislocations, and micropipes, which are typically present in substrates. This significantly improves substrate quality and yield, and the substrate's performance and reliability during subsequent device processing and use are significantly improved.

[0117] Because the elimination of growth features is completed during the crystal growth stage and subsequent substrate processing does not affect the electrical performance, the present application does not limit the substrate processing method, which is within the ordinary skill of those in the art. This growth method is simple and easy to implement, and can ensure stress and defect control in the crystal center region with a continuous and small temperature gradient. The innovative method allows the growth features to be fixed at the crystal edge and then removed during subsequent crystal processing, ensuring the absence of growth features in the entire ingot and subsequently processed substrates, achieving the goal of eliminating defect-accumulating regions and ensuring device yield and reliability.

[0118] However, the present invention also includes, but is not limited to, methods for manufacturing silicon carbide substrates that do not include growth feature planes. Those skilled in the art can also manufacture silicon carbide substrates using other methods that can control the growth feature planes. Therefore, the manufacturing methods disclosed in the present invention are merely examples and do not constitute limitations on the performance of the silicon carbide substrate itself. Those skilled in the art can also research new manufacturing methods for obtaining the silicon carbide substrate of the present invention by applying creative efforts to conventional technical means. Other manufacturing methods are not within the scope of the present invention, and therefore research on them will not be conducted.

[0119] The above description is merely a preferred embodiment of the present application, and does not limit the present application. Those skilled in the art can make various modifications and variations to the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A SiC crystal having facets only at its edges, The SiC crystal is obtained by direct growth using a PVT method without subsequent processing, the SiC crystal includes a facet region and a non-facet region, the facet region is located on the outer peripheral end surface of the SiC crystal, and properties within the entire area of ​​the facet region satisfy one or two of the following a to b: a. the variation rate of the doping concentration of the facet region is 1.5 times or more than the variation rate of the doping concentration of the non-facet region; b. A SiC crystal characterized in that the rate of variation of the carrier concentration in the facet region is at least five times the rate of variation of the carrier concentration in the non-facet region.

2. 2. The SiC crystal according to claim 1, wherein the distance between the edge of said facet region remote from the outer peripheral end face and said outer peripheral end face is 3% or less of the diameter of said SiC crystal.

3. the maximum cross-sectional area of ​​the facet region is 10% or less of the diametric cross-sectional area of ​​the crystal; and / or 2. The SiC crystal according to claim 1, wherein the volume of the facet region is 2% or less of the total volume of the crystal.

4. the maximum cross-sectional area of ​​the facet region is 5% or less of the diametric cross-sectional area of ​​the crystal; and / or 4. The SiC crystal according to claim 3, wherein the volume of the facet region is 0.6% or less of the total volume of the crystal.

5. 2. The SiC crystal according to claim 1, wherein the TDV of the facet region is at least six times the TDV of the non-facet region.

6. 6. The SiC crystal of claim 5, wherein the TDV of the facet region is at least 10 times the TDV of the non-facet region.

7. the rate of variation of the dopant concentration in the faceted region is at least five times the rate of variation of the dopant concentration in the non-faceted region; and / or 2. The SiC crystal according to claim 1, wherein the rate of variation of the carrier concentration in the facet region is at least 10 times the rate of variation of the carrier concentration in the non-facet region.

8. A non-faceted silicon carbide ingot, 8. A facetless silicon carbide ingot obtained by removing the facet regions from a SiC crystal having facets only at the edges according to claim 1.

9. A highly uniform silicon carbide substrate, The silicon carbide substrate is obtained by processing the SiC crystal according to any one of claims 1 to 7, is a conductive type, and has properties within the entire area of ​​the silicon carbide substrate that satisfy one or two of the following a to b: a, the doping concentration variation is <10%; b. A highly uniform silicon carbide substrate characterized in that the carrier concentration fluctuation rate is <5%.

10. The silicon carbide substrate is n-type doped, and the concentration of n-type element doping is ≧1E １８ cm －３ 10. The highly uniform silicon carbide substrate according to claim 9, wherein the silicon carbide substrate is free of any one or more of growth feature planes, highly doped regions, and defect concentrated regions within the entire area of ​​the silicon carbide substrate.

11. 10. The highly uniform silicon carbide substrate of claim 9, wherein the doping concentration variation is <8%.

12. 10. The highly uniform silicon carbide substrate of claim 9, wherein the variation rate of the carrier concentration is <3%.

13. The doping concentration is 5E １９ cm －３ 11. The highly uniform silicon carbide substrate of claim 10, wherein the carrier concentration is less than or equal to 100% and the variation rate of the carrier concentration is less than 5%.

14. The n-type element doping is N ２ 11. The highly uniform silicon carbide substrate of claim 10, wherein the doping is a variance of the doping concentration <3% and the variance of the carrier concentration is <1%.

15. The TDV density of the silicon carbide substrate is 100 cm －２ 10. The highly uniform silicon carbide substrate of claim 9, wherein the surface roughness is smaller than 100 nm.

16. The TDV density of the silicon carbide substrate is 10 cm －２ 16. The highly uniform silicon carbide substrate of claim 15, wherein the surface roughness is less than 0.05 μm.

17. 10. The highly uniform silicon carbide substrate according to claim 9, wherein the size of the silicon carbide substrate is 6 inches, 8 inches, 10 inches, or 12 inches.

18. A semiconductor device comprising: A semiconductor device comprising the highly uniform silicon carbide substrate of claim 9.

Images