Method, apparatus, integrated circuit, and circuit board for low parasitic power conversion

Abstract

Disclosed embodiments include a method, apparatus, integrated circuit, and circuit board for power conversion with low parasitics. The apparatus includes an integrated circuit for power conversion. The integrated circuit includes a plurality of power transistors and a plurality of metal regions connected to the power transistors. A first portion of the metal regions is connected to source regions of the power transistors. A second portion of the metal regions is connected to drain regions of the power transistors. The first and second portions have at least one of a substantially equal number of metal regions, a substantially equal resistance, or a balanced distribution of metal regions.

Description

[Technical Field]

[0001] Priority claims This disclosure claims priority to U.S. patent application Ser. No. 18 / 053,973, filed Nov. 9, 2022, entitled "METHODS, APPARATUSES, INTEGRATED CIRCUITS, AND CIRCUIT BOARDS FOR POWER CONVERSION WITH REDUCED PARASITICS" (Attorney Docket No. 15794.0047-00000), the entire contents of which are incorporated herein by reference for all purposes.

[0002] The present disclosure relates to power conversion, and more particularly to methods, apparatus, integrated circuits, and printed circuit boards for power conversion with low parasitic losses. [Background technology]

[0003] Many electronic products, particularly mobile computing and / or communication products and components (e.g., notebook computers, ultrabook computers, tablet devices, LCD and LED displays), require multiple voltage levels. For example, power amplifiers for radio frequency transmitters may require relatively high voltages (e.g., 12 volts (V) or higher), while logic circuits may require lower voltage levels (e.g., 1-2 V). Other circuits may require intermediate voltage levels (e.g., 5-10 V). Power converters are often used to generate lower or higher voltages from a common power source, such as a battery, to meet the power requirements of various components in electronic products. Summary of the Invention [Means for solving the problem]

[0004] Embodiments of the present disclosure may provide methods, apparatus, integrated circuits, and circuit boards for power conversion with low parasitics.

[0005] These embodiments include an apparatus for power conversion. The apparatus includes an integrated circuit for power conversion. The integrated circuit includes a plurality of power transistors and a plurality of metal regions connected to the power transistors. A first portion of the metal regions is connected to a source region of the power transistor. A second portion of the metal regions is connected to a drain region of the power transistor. The first and second portions have at least one of a substantially equal number of metal regions, a substantially equal resistance, or a balanced distribution of metal regions.

[0006] These embodiments also include a power transistor for power conversion, the power transistor comprising a plurality of active regions, a plurality of terminals, and a plurality of conductive paths, each terminal electrically connected to at least one of the active regions via at least one of the conductive paths, each conductive path comprising one or more horizontally oriented metal conductors and one or more vertically oriented metal conductors, wherein the sum of the lengths of the one or more vertically oriented metal conductors exceeds the sum of the lengths of the one or more horizontally oriented metal conductors in a majority of the conductive paths.

[0007] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram of an exemplary apparatus for power conversion according to an embodiment of the present disclosure. [Figure 2A] FIG. 1 illustrates a top view of an exemplary apparatus for power conversion according to an embodiment of the present disclosure. [Figure 2B] FIG. 2B is a diagram of an example integrated circuit for the power conversion of FIG. 2A in accordance with an embodiment of the present disclosure. [Figure 2C] FIG. 2C is a diagram of example input / output terminals of the example integrated circuit of FIG. 2B in accordance with an embodiment of the present disclosure. [Figure 2D]2 is another top view of the exemplary apparatus for power conversion of FIG. 1 in accordance with an embodiment of the present disclosure. [Figure 2E] 2 is a cross-sectional view of the exemplary apparatus for power conversion of FIG. 1 in accordance with an embodiment of the present disclosure. [Figure 2F] FIG. 2F is a cross-sectional view of an exemplary integrated circuit and circuit board for the power conversion of FIG. 2E in accordance with an embodiment of the present disclosure. [Figure 3A] FIG. 10 is a cross-sectional view of another exemplary circuit board and integrated circuit for power conversion according to an embodiment of the present disclosure. [Figure 3B] 1 is a cross-sectional view of an exemplary apparatus for power conversion according to an embodiment of the present disclosure. [Figure 4] FIG. 1 is a block diagram of an exemplary integrated circuit for power conversion, according to an embodiment of the present disclosure. [Figure 5A] 1 is a cross-sectional view of an exemplary integrated circuit for power conversion according to an embodiment of the present disclosure. [Figure 5B] FIG. 2 is a perspective view of metal regions of an exemplary integrated circuit for power conversion, according to an embodiment of the present disclosure. [Figure 6A] FIG. 2 is a top view of a redistribution layer (RDL) region and an active area of ​​an exemplary integrated circuit for power conversion, according to some embodiments. [Figure 6B] FIG. 2 is a top view of a RDL region, a gate region, and an active region of an exemplary integrated circuit for power conversion according to some embodiments. [Figure 7A] FIG. 2 is a top view of a Metal-4 (M4) area and an active area of ​​an exemplary integrated circuit for power conversion, according to some embodiments. [Figure 7B] FIG. 1 is a top view of four M4 regions and six active regions of an exemplary integrated circuit for power conversion, according to some embodiments. [Figure 7C] FIG. 1 is a top view of the M4 region, a via between metal layers 4 and 3 (V43 via), and active areas of an exemplary integrated circuit for power conversion according to some embodiments. [Figure 7D]FIG. 1B is a top view of five M4 regions, V43 vias, and six active areas of an exemplary integrated circuit for power conversion according to some embodiments. [Figure 8A] FIG. 2 is a top view of the Metal-3 (M3) area and active area of ​​an exemplary integrated circuit for power conversion, according to some embodiments. [Figure 8B] FIG. 1 is a top view of eight M3 regions and two active regions of an exemplary integrated circuit for power conversion according to some embodiments. [Figure 8C] FIG. 1 is a top view of four M4 regions and eight M3 regions of an exemplary integrated circuit for power conversion, according to some embodiments. [Figure 8D] FIG. 1B is a top view of a via between metal layers 3 and 2 (V32 via) and active areas of an exemplary integrated circuit for power conversion, according to some embodiments. [Figure 8E] FIG. 1B is a top view of eight M3 regions, V32 vias, and two active areas of an exemplary integrated circuit for power conversion according to some embodiments. [Figure 9A] FIG. 2 is a top view of the Metal-2 (M2) and active areas of an exemplary integrated circuit for power conversion, according to some embodiments. [Figure 9B] FIG. 1 is a top view of an M2 region and six active regions of an exemplary integrated circuit for power conversion according to some embodiments. [Figure 9C] FIG. 1 is a top view of the M3 and M2 regions of an exemplary integrated circuit for power conversion, in accordance with some embodiments. [Figure 10A] FIG. 2 is a top view of the Metal-1 (M1) area and active area of ​​an exemplary integrated circuit for power conversion, according to some embodiments. [Figure 10B] FIG. 2 is a top view of the M1 region and active area of ​​an exemplary integrated circuit for power conversion, according to some embodiments. [Figure 10C] FIG. 2 is a top view of an M1 region and partial active area of ​​an exemplary integrated circuit for power conversion according to some embodiments. [Figure 10D]FIG. 1 is a top view of the M1 region, a via between metal layers 2 and 1 (V21 via), and a partial active area of ​​an exemplary integrated circuit for power conversion according to some embodiments. [Figure 11] FIG. 1 illustrates a top view of two M2 regions, multiple gate regions, and partial active areas of an exemplary integrated circuit for power conversion in accordance with some embodiments. [Figure 12] 2 illustrates an example configuration of the example apparatus for power conversion of FIG. 1 according to an embodiment of the present disclosure. [Figure 13] FIG. 2 is a circuit diagram of an exemplary apparatus for power conversion of FIG. 1 in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following disclosure provides many different exemplary embodiments or examples for implementing various features of the presented subject matter. Brief specific examples of components and configurations are described below to illustrate the present disclosure. It should be understood that these are merely examples and are not intended to be limiting. Furthermore, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations described.

[0010] The terms used herein generally have their ordinary meanings in the art and in the particular context in which each term is used. The use of examples herein, including examples of any term described herein, is illustrative only and does not limit the scope and meaning of the disclosure or any exemplified term in any way. Likewise, the disclosure is not limited to the various embodiments provided herein.

[0011] The terms "first," "second," etc. may be used herein to describe various elements, but these elements are not limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of its associated listed items.

[0012] Spatial terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to facilitate the description of the relationship between one illustrated element or feature and another. These spatial terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the drawings. Other orientations of the device (such as rotated 90 degrees or other orientations) are contemplated, and the spatial descriptors used herein should be interpreted accordingly.

[0013] In this disclosure, the term “coupled” may also be referred to as “electrically coupled,” and the term “connected” may also be referred to as “electrically connected.” “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

[0014] A power converter is capable of receiving, sourcing, or operating at large currents in one or more of its current paths. At large currents, the power supply paths and operation are susceptible to parasitic losses that adversely affect performance. Parasitic losses are I 2and R, where "I" is the current and "R" is the resistance. The larger the current, the more significant the power loss. For example, the power delivery path and large current of a particular buck converter can reduce the respective power conversion efficiency due to parasitic losses. Additional constraints can also exacerbate unwanted parasitic losses. For example, due to limited die space, signals may be launched onto a printed circuit board (PCB) and routed as needed.

[0015] Disclosed embodiments may include designs that reduce the inductor requirements for a buck converter. For example, embodiments may place a charge pump converter between the input power and the buck converter. This arrangement reduces the inductor requirements for the buck converter, allowing embodiments to use chip inductors for the buck converter, even when the input voltage is relatively high (e.g., 12 volts (V)). For example, the charge pump converter may step down the input voltage before supplying it to the buck converter. By allowing the buck converter to operate using a step-down voltage, the requirements for its associated inductor are reduced, allowing the use of small chip inductors instead of larger inductors that require additional space.

[0016] The disclosed embodiments may include additional benefits. As one example, the disclosed embodiments utilize inductors to move the converter's power node to the edge, thereby freeing up peripheral space on the PCB. This power routing mechanism can reduce the number of layers on the PCB or module for routing all signals.

[0017] As another example, disclosed embodiments may position the output terminals of a buck converter to enable the use of coupled inductors. Instead of routing power radially and locating the output terminals at diametrically opposed locations to reduce parasitic effects, disclosed embodiments may position the output terminals of the buck converter adjacently along the same edge of the converter. For example, by locating four voltage output terminals at the four corners of the circuit layout, a radial design may limit the feasibility of linking the output terminals to increase output amperage delivery. Disclosed embodiments address this issue by locating the output terminals side-by-side and routing the current vertically. Closely locating the output terminals may facilitate linking two or more output terminals to provide additional current to a load. Also, locating the output nodes of a buck converter side-by-side on the same side of the device may advantageously enable the use of coupled inductors. For example, by locating multiple voltage outputs from a buck converter on the same die, two or more outputs may be linked to the same coupled inductor. This configuration would not be possible if the inductor linking arrangement were distributed radially. Additionally, the use of coupled inductors reduces overall inductor size requirements, further favoring space savings.

[0018] While embodiments of the present disclosure may address these problems and provide these benefits, the problems and features described are exemplary and are not intended to limit the scope of the claims or the present disclosure. Indeed, embodiments of the disclosure may address problems and provide benefits not expressly recited.

[0019] FIG. 1 is a diagram of an exemplary apparatus 100 for power conversion, according to an embodiment of the disclosure. As shown in FIG. 1 , apparatus 100 may include an integrated circuit 110, a circuit board 120, and inductors 131, 132, 133, and 134. Integrated circuit 110 may include power conversion circuitry and may be connected to circuit board 120 for power conversion. Circuit board 120 may include circuitry (not shown) for launching signals from integrated circuit 110. Inductors 131, 132, 133, and 134 may be connected to circuit board 120 and electrically connected to integrated circuit 110 to form four buck converters, shown as BUCK1, 2, 3, and 4 in FIG. 1 . Each of the four buck converters may receive an input power V IN The output power V OUT-1 , V OUT-2 , V OUT-3 , and V OUT-4 It may be converted into:

[0020] Inductors 131, 132, 133, and 134 may be chip inductors, which feature small packages and can be used in a variety of applications, including power conversion and high-frequency circuits. Chip inductors may be inductors in a chip form factor for use in integrated circuits in electronic devices. Chip inductors can be used in power converters, RF transceivers, computers, and other electronic devices. Exemplary chip inductors include ferrite cores with wire windings or multiple layers of wire. Chip inductors provide voltage conversion benefits and can be used to form filter circuits and resonant circuits. Compared to traditional discrete inductors, chip inductors can be more compact and lightweight.

[0021] As shown in FIG. 1, an integrated circuit 110 receives an input voltage V IN The charge pump converter may include a step-down converter for stepping down an input voltage V INand the four buck converters BUCK1, 2, 3, and 4. The charge pump converter may be configured to charge the input voltage V IN (e.g., 12 V) can be stepped down. The stepped down voltage reduces the requirements for inductors 131, 132, 133, and 134. This allows in some embodiments inductors 131, 132, 133, and 134 to be implemented with chip inductors instead of larger inductors that require additional space.

[0022] During power conversion, current may flow from integrated circuit 110 to inductors 131, 132, 133, and 134 through multiple conductive lines (not shown in FIG. 1 ) on circuit board 120. The conductive lines may extend along a direction perpendicular to the surface of circuit board 120, as described below. Thus, the current may be vertical to the surface of circuit board 120 and, correspondingly, vertical to the circuits on circuit board 120, such as the circuits for emitting signals. This results in low parasitics (such as parasitic capacitors and inductors) from these circuits on circuit board 120. By converting power with low parasitics, device 100 may provide efficient power conversion.

[0023] In some embodiments, integrated circuit 110 of device 100 may include a charge pump converter (FIG. 1) for two or more charge pumps (not shown). Integrated circuit 110 may also include a buck converter circuit for at least two buck converters (e.g., at least two of buck converters BUCK1, 2, 3, and 4 (FIG. 1)). At least two of inductors 131, 132, 133, and 134 may include chip inductors. At least two buck converters (e.g., BUCK1 and 2 (FIG. 1)) may be individually connected to at least two chip inductors (e.g., inductors 131 and 132 (FIG. 1)) through respective conductive lines (e.g., conductive lines 121a and 121b (FIG. 2F)).

[0024] 2A is a top view of the exemplary apparatus 100 for power conversion of FIG. 1, according to an embodiment of the disclosure. As shown in FIG. 2A, the apparatus 100 may include an integrated circuit 110, a circuit board 120, and inductors 131, 132, 133, and 134, connected as described above with reference to FIG. 1. Inductors 131, 132, 133, and 134 may each be 330 nanohenries (nH). In some embodiments, inductors 131, 132, 133, and 134 may each be 100 nH, 200 nH, 470 nH, or other values.

[0025] The integrated circuit 110 may be packaged, for example, in a ball grid array (BGA) package and may include a plurality of conductive balls for input / output signals. Among these conductive balls, the integrated circuit 110 may have a first plurality of conductive balls LX1 (FIG. 2B) that output a current to the inductor 131, a second plurality of conductive balls LX2 (FIG. 2B) that output a current to the inductor 132, a third plurality of conductive balls LX3 (FIG. 2B) that output a current to the inductor 133, and a fourth plurality of conductive balls LX4 (FIG. 2B) that output a current to the inductor 134. In other words, the conductive balls LX1, LX2, LX3, and LX4 may be output terminals of the integrated circuit 110 that output a current to the inductors 131, 132, 133, and 134 through conductive lines of the circuit board 120.

[0026] 2A , regions LX1, LX2, LX3, and LX4 may indicate that conductive balls LX1, LX2, LX3, and LX4 of the integrated circuit 110 may be present in these regions. In other words, the output terminals of the integrated circuit 110 (e.g., conductive balls LX1, LX2, LX3, and LX4) may be located directly below the inductors 131, 132, 133, and 134. Therefore, at least a portion of the integrated circuit 110 (including conductive balls LX1, LX2, LX3, and LX4 and internal circuits connected thereto) may be located directly below the inductors 131, 132, 133, and 134.

[0027] 2A, output terminals for outputting current (e.g., conductor balls LX1, LX2, LX3, and LX4) may be present in the right half of the integrated circuit 110. The integrated circuit 110 also includes a plurality of conductor balls V IN The conductive ball V may be provided. IN are input terminals of the integrated circuit 110 and may be located on the left half of the integrated circuit 110 in FIG. 2A. In some embodiments, output terminals for outputting current may be located on the left half, top half, or bottom half of the integrated circuit 110. Conductor balls may be located on the right half, bottom half, or top half of the integrated circuit 110.

[0028] In some embodiments, the conductive lines may be located on a common edge of the circuit board. For example, as shown in FIG. 2A , output terminals for outputting current (e.g., conductor balls LX1, LX2, LX3, and LX4) may be arranged along multiple lines of a ball grid array. When integrated circuit 110 is mounted on circuit board 120, the output terminals for outputting current may be mounted on the edge of circuit board 120 to facilitate coupling to inductors 131, 132, 133, and 134. In these embodiments, the conductive lines may be located on the edge of circuit board 120.

[0029] 2B is a diagram of an example integrated circuit 110 for power conversion of FIG. 2A, according to an embodiment of the disclosure. As shown in FIG. 2B, the integrated circuit 110 includes a plurality of conductor balls V IN , a plurality of conductive balls CB1, a plurality of conductive balls VX, a plurality of conductive balls P2, a plurality of conductive balls GND, a plurality of conductive balls P1, a plurality of conductive balls CB2, conductive balls LX1, LX2, LX3, and LX4, and a plurality of conductive balls I / O. In FIG. 2B, conductive balls without reference labels may be used for the same function as conductive balls labeled with the same pattern. These conductive balls are input / output terminals of the integrated circuit 110 and may be connected to peripheral circuits for power conversion, as shown in FIG. 13.

[0030] In FIG. 2B, the conductive balls LX1, LX2, LX3, and LX4, as well as VX corresponding to the four buck converters, are also shown as dashed line blocks BUCK1, 2, 3, and 4. The conductive balls LX1 and VX in the dashed line block BUCK1 can be used for the buck converter BUCK1. The conductive balls LX2 and VX in the dashed line block BUCK2 can be used for the buck converter BUCK2. The conductive balls LX3 and VX in the dashed line block BUCK3 can be used for the buck converter BUCK3. The conductive balls LX4 and VX in the dashed line block BUCK4 can be used for the buck converter BUCK4.

[0031] 2B, output terminals (including conductor balls LX1, LX2, LX3, and LX4) for outputting current may be located in portions within dashed line blocks BUCK1, 2, 3, and 4. These portions of integrated circuit 110 may be located directly below inductors 131, 132, 133, and 134 (FIG. 2A or FIG. 2D).

[0032] 2B, the output terminals (including conductive balls LX1, LX2, LX3, and LX4) for outputting current may be adjacently arranged along the same edge of the integrated circuit 110. This may facilitate connecting two or more of the output terminals to supply additional current to a load. Also, arranging the output terminals (including conductive balls LX1, LX2, LX3, and LX4) adjacently on the same side of the integrated circuit 110 and / or the device 100 may advantageously enable the use of coupled inductors for various configurations, as will be described below with reference to FIG.

[0033] 2C is a diagram of exemplary input / output terminals of the exemplary integrated circuit 110 for power conversion of FIG. 2B, according to an embodiment of the disclosure. As shown in FIG. 2C, the input / output terminals of the integrated circuit 110 are connected to conductor balls V IN , conductor ball CB1, conductor ball VX, conductor ball P2, conductor ball GND, conductor ball P1, conductor ball CB2, conductor balls LX1, LX2, LX3, and LX4, and conductor ball I / O. In FIG. 2C, conductor balls without reference labels may be used for the same purpose as conductor balls labeled with the same pattern.

[0034] FIG. 2D is another top view of the exemplary apparatus 100 for power conversion of FIG. 1 in accordance with an embodiment of the disclosure. As shown in FIG. 2D , the apparatus 100 may include an integrated circuit 110, a circuit board 120, and inductors 131, 132, 133, and 134, connected as described above with reference to FIG. 1 . The inductors 131, 132, 133, and 134 may share an inductor core 135 and thus be connected together as a coupled inductor. The inductors 131, 132, 133, and 134 may be connected in various configurations, as described below with reference to FIG. 12 . A coupled inductor has two or more windings on a common core. Coupled inductors function in DC-DC converters by transferring energy from one winding to another through a common core. By connecting two or more inductors, the power converter can efficiently provide a desired output voltage and / or current.

[0035] As shown in FIG. 2D, at least a portion of integrated circuit 110 may be directly underneath inductors 131, 132, 133, and 134.

[0036] 2E is a cross-sectional view taken along line CC' of the exemplary apparatus 100 of FIG. 1, according to an embodiment of the disclosure. As shown in FIG. 2E, the apparatus 100 for power conversion may include an integrated circuit 110, a circuit board 120, and an inductor 130. The inductor 130 may include inductors 131, 132, 133, and 134.

[0037] The integrated circuit 110 may be part of a power converter and may be mounted on a circuit board 120. The integrated circuit 110 is connected to multiple conductive lines (FIG. 2F) on the circuit board 120, and multiple longitudinal currents I VTC may be sent to the inductor 130. As shown in FIG. 2E, the longitudinal current I VTC may be, for example, vertical to the surface 121 of the circuit board 120. In one example, the vertical current I VTC may be 4A, 8A, or 16A.

[0038] Circuit board 120 may include surfaces 121 and 122, metal layers M1, M2, M3, and M4, and a plurality of conductive lines between metal layers M1 and M2 and between metal layers M3 and M4. Surfaces 121 and 122 are opposite surfaces of circuit board 120. The conductive lines between metal layers M1 and M2 (FIG. 2F) may extend along a direction perpendicular to surface 121 of circuit board 120. Inductor 130 may be mounted on surface 121 of circuit board 120 and electrically connected to integrated circuit 110 through the conductive lines between metal layers M1 and M2. As shown in FIG. 2E, at least a portion of integrated circuit 110 may be directly below inductor 130.

[0039] As mentioned above, the longitudinal current I VTC may be, for example, vertical with respect to the surface 121 of the circuit board 120. The device 100 may receive, generate, and operate at large currents. Powering and operating at large currents is susceptible to parasitic losses that reduce the power conversion efficiency of the buck converters BUCK1, 2, 3, and 4. Also, because the size of the integrated circuit 110 is smaller than the inductor, the signal may be dumped onto the circuit board 120 and routed as needed. This may exacerbate parasitic effects on the device 100. The vertical current I VTC This configuration can reduce the adverse effects of such parasitics. By reducing the parasitic effects, the device 100 can convert power efficiently. In addition, in some embodiments, the longitudinal current I between the integrated circuit 110 and the inductor 130 VTC The use of the conductive balls LX1, LX2, LX3, and LX4 may also facilitate adjacent placement of the output terminals (including the conductive balls LX1, LX2, LX3, and LX4). The adjacent placement of the output terminals may allow for the use of coupled inductors for various configurations of the device 100 for power conversion. It may also allow for the use of chip inductors, which may reduce the size of the device 100.

[0040] 2F is a cross-sectional view of the exemplary integrated circuit 110 and circuit board 120 of FIG. 2E, according to an embodiment of the disclosure. As shown in FIG. 2F, the circuit board 120 may include a plurality of conductive lines 121a, 121b, 121c, and 121d extending from the metal layer M2 to the metal layer M1. Conductor balls LX1, LX2, LX3, and LX4 (FIG. 2B or 2C), i.e., output terminals of the integrated circuit 110, are directly connected to the conductive lines 121a, 121b, 121c, and 121d, and a longitudinal current I VTC may be output to the inductor 130 (FIG. 2E). As shown in FIG. 2F, the conductive lines 121a, 121b, 121c, and 121d may extend directly from the conductive balls LX1, LX2, LX3, and LX4 to the inductor 130 (FIG. 2E) along a direction perpendicular to the surface 121.

[0041] 2E and 2F, the integrated circuit 110 may be embedded within a circuit board 120. The circuit board 120 has layers D1, D2, and D3. Layer D2 may be between layers D1 and D3. The integrated circuit 110 may be mounted on layer D2.

[0042] 2F, circuit board 120 may have metal layers M1 and M2. Conductive lines 121a, 121b, 121c, and 121d may be connected between metal layers M1 and M2. Integrated circuit 110 may be connected to conductive lines 121a, 121b, 121c, and 121d on metal layer M2.

[0043] 2F, circuit board 120 may include a first plurality of terminals 121a-M1, 121b-M1, 121c-M1, and 121d-M1 on surface 121. Terminals 121a-M1, 121b-M1, 121c-M1, and 121d-M1 may be connected to first ends of conductive lines 121a, 121b, 121c, and 121d, and may be connected to inductor 130 (FIG. 2E). Circuit board 120 may also include a second plurality of terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 connected to the other ends of conductive lines 121a, 121b, 121c, and 121d on metal layer M2. Terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 may be connected to integrated circuit 110 for power conversion. As shown in FIG. 2F, terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 may be directly below terminals 121a-M1, 121b-M1, 121c-M1, and 121d-M1.

[0044] 2F, conductive lines 121a, 121b, 121c, and 121d may extend directly from terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 to terminals 121a-M1, 121b-M1, 121c-M1, and 121d-M1 along a direction perpendicular to surface 121. Terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 may be internal to circuit board 120 on metal layer M2.

[0045] As described above, the circuit board 120 has layers D1, D2, and D3. Layer D2 may be between layers D1 and D3. Terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 may be on the layer D2 side.

[0046] 2F, conductive lines 121a, 121b, 121c, and 121d may be connected between metal layers M1 and M2. Terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 may be present in metal layer M2. Conductive lines 121a, 121b, 121c, and 121d may conduct longitudinal current I from terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 to terminals 121a-M1, 121b-M1, 121c-M1, and 121d-M1. VTC The longitudinal current I VTC may flow along a direction perpendicular to the surface 121 of the circuit board 120 .

[0047] 3A is a cross-sectional view of another exemplary circuit board 140 and integrated circuit 110 for power conversion, according to embodiments of the disclosure. As shown in FIG. 3A, circuit board 140 may include surfaces 141 and 142, metal layers M1 and M2, and a plurality of conductive lines 141a, 141b, 141c, and 141d. Integrated circuit 110 may be mounted on surface 142. Conductive lines 141a, 141b, 141c, and 141d may have similar functionality to conductive lines 121a, 121b, 121c, and 121d of FIG. 2F. Conductive lines 141a, 141b, 141c, and 141d may be connected between integrated circuit 110 mounted on surface 142 and an inductor (e.g., inductor 130 (FIG. 2E)) mounted on surface 141.

[0048] 3A, circuit board 140 may include a first plurality of terminals 141a-M1, 141b-M1, 141c-M1, and 141d-M1 on surface 141. Terminals 141a-M1, 141b-M1, 141c-M1, and 141d-M1 may be present in metal layer M1 and connected to first ends of conductive lines 141a, 141b, 141c, and 141d. Terminals 141a-M1, 141b-M1, 141c-M1, and 141d-M1 may also be connected to an inductor on surface 141, such as inductor 130 (FIG. 2E). Circuit board 120 may also include a second plurality of terminals 141a-M2, 141b-M2, 141c-M2, and 141d-M2 in metal layer M2. Terminals 141a-M2, 141b-M2, 141c-M2, and 141d-M2 may be connected to the other ends of conductive lines 141a, 141b, 141c, and 141d. Terminals 141a-M2, 141b-M2, 141c-M2, and 141d-M2 may be on surface 142 and connected to integrated circuit 110. As shown in FIG. 3A, terminals 141a-M2, 141b-M2, 141c-M2, and 141d-M2 may be located directly below terminals 141a-M1, 141b-M1, 141c-M1, and 141d-M1.

[0049] Conductive lines 141a, 141b, 141c, and 141d conduct longitudinal current I from terminals 141a-M2, 141b-M2, 141c-M2, and 141d-M2 on surface 142 to terminals 141a-M1, 141b-M1, 141c-M1, and 141d-M1 on surface 141. VTC The longitudinal current I VTC may flow along a direction perpendicular to surfaces 141 and 142 to an inductor, such as inductor 130 (FIG. 2E).

[0050] 3B is a cross-sectional view of an exemplary apparatus 200 for power conversion, according to an embodiment of the present disclosure. As shown in FIG. 3B, apparatus 200 may include integrated circuit 110 (FIG. 3A), circuit board 140 (FIG. 3A), molded component 220, and molded power inductor 230. Integrated circuit 110 may be mounted on circuit board 140 and operate as described above with reference to FIG. 3A. Conductive traces 141 of circuit board 140 may include one or more of conductive traces 141a, 141b, 141c, and 141d (FIG. 3A) and may be configured to carry longitudinal current from integrated circuit 110 to molded power inductor 230. Molded component 220 may include molded capacitors and / or molded resistors, which are used as the capacitors and resistors in FIG. 13.

[0051] 4 is a block diagram of an example integrated circuit 110 for power conversion, according to an embodiment of the disclosure. As shown in FIG. 4, the integrated circuit 110 may include a conversion circuit 112 and a controller 114. The controller 114 may include circuitry configured to control multiple switches in the conversion circuit 112 for power conversion in various configurations, as described below with reference to FIG. 12.

[0052] 5A is a cross-sectional view of an exemplary integrated circuit 110 for power conversion, according to an embodiment of the disclosure. As shown in FIG. 5A, the integrated circuit 110 may include a substrate, an active region (AR) in an AR layer, multiple (six) Metal-1 (M1) regions in an M1 layer, three Metal-2 (M2) regions 201, 202, and 203 in an M2 layer, six Metal-3 (M3) regions in an M3 layer, three Metal-4 (M4) regions 401, 402, and 403 in an M4 layer, six vias (V1 vias) between the six M1 regions and the active region, six vias (V21 vias) between the M2 and M1 regions, six vias (V32 vias) between the M3 and M2 regions, and six vias (V43 vias) between the M4 and M3 regions. The AR regions include multiple power transistors.

[0053] The integrated circuit 110 receives an input power V IN (Fig. 1) OUT-1 , V OUT-2 , V OUT-3 , and V OUT-4 , the controller 114 of the integrated circuit 110 calculates the lateral current i between the transistors. AR-LAT and a longitudinal current i from the transistor to, for example, terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2 (FIG. 2F) of the circuit board 120 (FIG. 2F). VTC As shown in FIG. 5A, the transistor may be configured to operate by a longitudinal current i VTC may flow along a direction perpendicular to the substrate of the integrated circuit 110. VTC causes a longitudinal current I to flow through the conductive lines 121a, 121b, 121c, and 121d (FIG. 2F) via the terminals 121a-M2, 121b-M2, 121c-M2, and 121d-M2. VTC (Figure 2F)

[0054] As shown in Figure 5A, the power transistors in the active region reside in the AR layer. The M4, M3, M2, and M1 regions are stacked and connected together through the V43, V32, V21, and V1 vias, which connect to the source and drain regions of the power transistors in the active region. The stacked M4, M3, M2, and M1 regions and the V43, V32, V21, and V1 vias form a vertical current i in the integrated circuit 110. VTC are vertically oriented metal conductors configured to provide multiple conductive paths for currents to flow between the power transistors in the AR layer and the M4 regions 401, 402, and 403 in the M4 layer. As shown in FIG. 5A, six vertical currents i VTC-1 ~i VTC-6 flows along the Z axis.

[0055] The M4 layer is above the AR layer and is considered an upper layer in the integrated circuit 110 when compared to the M3, M2, M1, and AR layers. In some embodiments, the M3 layer is above the AR layer and is considered an upper layer in the integrated circuit 110 when compared to the M2, M1, and AR layers. In some embodiments, the integrated circuit 110 may also include an RDL region in the RDL layer above the M4 layer. The RDL region is connected to the M4 region 402 through a via (VR4 via) between the RDL and M4 layer and extends along the Y-axis to redistribute current. The integrated circuit 110 may also include multiple terminals (e.g., VX, LX1, LX2, LX3, and LX4 in FIG. 2C) connected to the RDL (FIG. 5A).

[0056] Also, as shown in FIG. 5A, most of the M4, M3, M2, and M1 regions are filled with the lateral current i LAT For example, the three horizontal currents i in the M2 layer are M2-LAT-1 ~i M2-LAT-3 and two transverse currents in the M4 layer i M4-LAT-1 and i M4-LAT-2 flows along the X-axis. In addition, two transverse currents i M3-LAT-1 and i M3-LAT-2 flows along the Y-axis. The transverse current i M2-LAT X-axis direction and transverse current i M3-LAT The Y-axis direction is the vertical current i VTC (longitudinal current i VTC-1 ~i VTC-6 It is perpendicular to the Z axis direction of the

[0057] Thus, the integrated circuit 110 may include a plurality of conductive paths electrically connected between terminals connected to the RDL and the power transistors in the AR layer. Each terminal may be electrically connected to at least one of the power transistors via at least one of the conductive paths. Each conductive path includes one or more horizontally oriented metal conductors and one or more vertically oriented metal conductors. In most of the conductive paths of the integrated circuit 110, the sum of the lengths of the one or more vertically oriented metal conductors exceeds the sum of the lengths of the one or more horizontally oriented metal conductors.

[0058] As shown in FIG. 5A , the M4 regions 401, 402, and 403 are thicker than the M3 region. Therefore, the M4 regions 401, 402, and 403 have lower resistance than the M3 region. The M3 region is thicker than the M2 regions 201, 202, and 203. Therefore, the M3 region has lower resistance than the M2 regions 201, 202, and 203. The M2 regions 201, 202, and 203 are thicker than the M1 region. That is, the metal regions in the upper layer have lower resistance than the metal regions in the lower layer. The M4 regions 401, 402, and 403, the six M3 regions, the M2 regions 201, 202, and 203, and the six M1 regions may be laterally oriented metal conductors in the integrated circuit 110. That is, in the integrated circuit 110, the resistance of each laterally oriented metal conductor in the M2 layer is lower than the resistance of each laterally oriented metal conductor in the M1 layer. The resistance of each of the horizontally oriented metal conductors in the M3 layer is lower than the resistance of each of the horizontally oriented metal conductors in the M2 layer. The resistance of each of the horizontally oriented metal conductors in the M4 layer is lower than the resistance of each of the horizontally oriented metal conductors in the M3 layer.

[0059] In some embodiments, the integrated circuit 110 may include M4, M3, M2, and M1 regions as laterally oriented metal conductors for conductive paths. That is, the laterally oriented metal conductors of the integrated circuit 110 may include an M1 metal conductor in an M1 layer above the power transistor and an M2 metal conductor in an M2 layer above the M1 layer. The laterally oriented metal conductors may also include an M3 metal conductor in an M3 layer above the M2 layer and an M4 metal conductor in an M4 layer above the M3 layer. The width of the M1 metal conductor is smaller than the width of the M2 metal conductor. The width of the M2 metal conductor is smaller than the width of the M3 metal conductor. The width of the M3 metal conductor is smaller than the width of the M4 metal conductor.

[0060] As a result, if both conductive paths through the upper and lower regions are available, lateral currents will be more likely to occur and flow through the upper metal region than through the lower region. For example, longitudinal currents i VTC-1 ~i VTC-6 The total amount of the transverse current i is assumed to be 0.5 milliamperes (mA). M4-LAT-1 , i M4-LAT-2 , i M3-LAT-1 , i M3-LAT-2 , and i M2-LAT-1 ~i M2-LAT-3 The total amount of the vertical current i is assumed to be 0.1mA. VTC The total amount (0.5mA) of the horizontal current i M4-LAT , i M3-LAT , and i M2-LAT is greater than the total amount (0.1mA).

[0061] The integrated circuit 110 also includes conductive balls LX1, LX2, LX3, and LX4 (FIG. 2A) as output terminals connected to the conductive paths (the stacked M4, M3, M2, and M1 regions in FIG. 5A). The conductive balls LX1, LX2, LX3, and LX4 of the integrated circuit 110 conduct the longitudinal current i VTC (For example, the longitudinal current i in Figure 5A VTC-3 and i VTC-4 ) to inductors 131, 132, 133, and 134 (FIG. 2A).

[0062] For example, the M4 regions 401, 402, and 403 may have a thickness of 35 micrometers (μm) and a length along the Z-axis direction. M4 ) is 35 μm, that is, W M4 The six M3 regions may have a thickness of 17 μm. The M3 regions may have a width (W M3 ) is 17 μm, that is, W M3 The M2 regions 201, 202, and 203 may have a thickness of 8 μm. The M2 regions 201, 202, and 203 may have a width (W M2 ) is 8 μm, that is, W M2 The M1 region may have a thickness of 0.5 μm. The M1 region may have a width (W M1 ) is 0.5 μm, that is, W M1 =0.5 μm.

[0063] In Figure 5A, the M1 region is connected to source regions S2, S3, and S4 and drain regions D1, D2, and D3 of the AR region of the power transistor. The source region S2 and the drain region D2 form one of the power transistors. The source region S3 and the drain region D3 form one of the power transistors. The active region includes the source region S1 (not shown) together with the drain region D1, thereby forming one of the power transistors. The active region includes the source region S4 and the drain region D4 (not shown) together with the power transistors.

[0064] As shown in FIG. 5A , three M4 regions 401, 402, and 403 exist in the M4 layer, which is above the M3, M2, M1, and AR layers of the integrated circuit 110. Three M2 regions 201, 202, and 203 exist in the M2 layer, which is below the M4 layer and above the AR layer. The M4 regions 401, 402, and 403 (35 μm) are thicker and wider than the M2 regions 201, 202, and 203 (8 μm). Therefore, the M4 regions 401, 402, and 403 have lower resistance than the M2 regions 201, 202, and 203, and are configured to pass more current than the M2 regions 201, 202, and 203. That is, the lateral current i flowing through the M4 region 401 is M4-LAT-1 is the transverse current i flowing through the M2 region 201 M2-LAT-1 The transverse current i flowing through the M4 region 403 is larger than M4-LAT-2 is the transverse current i flowing through the M2 region 203 M2-LAT-3 As described above, the M4 regions 401, 402, and 403 and the M2 regions 201, 202, and 203 are laterally oriented metal conductors. That is, the current flowing through each laterally oriented M4 metal conductor in the M4 layer may exceed the current flowing through each laterally oriented M2 conductor in the M2 layer. Also, the current flowing through each laterally oriented M4 metal conductor in the M4 layer may exceed the current flowing through each laterally oriented M3 conductor in the M3 layer. Also, the current flowing through each laterally oriented M2 metal conductor in the M2 layer may exceed the current flowing through each laterally oriented M1 conductor in the M1 layer.

[0065] In some embodiments, two lateral currents i flowing in the M4 layer M4-LAT-1 and i M4-LAT-2 The total amount of the two transverse currents i M2-LAT-1 and i M2-LAT-3 The transverse current i flowing through the M2 region 202 is larger than the total amount of M2-LAT-2 is considered to be small. From the AR region to the M4 region 402, the longitudinal current i VTC-3 and i VTC-4 The two direct conductive paths from the drain region D2 to the M4 region 402 and from the source region S3 to the M4 region 402 are formed from the AR region (S3 or D2) to the M2-LAT-2202 to M4 region 402.

[0066] As shown in FIG. 5A, a conductive path P23-M2 exists between the source region S3 of the third transistor and the terminal connected to the RDL. The conductive path P23-M2 runs from the source region S3 of the third transistor through the M2 region 202 in the M2 layer to the terminal (not shown) connected to the RDL. The conductive path P23-M2 includes a first plurality of vertically oriented metal conductors (including stacked portions of V1, M1, V21, and M2), horizontally oriented metal conductors on the M2 region 202, and a second plurality of vertically oriented metal conductors (including stacked portions of M2, V32, M3, V43, M4, and VR4). The sum of the lengths of the first and second plurality of vertically oriented metal conductors exceeds the length of the horizontally oriented metal conductor.

[0067] As shown in FIG. 5A, the integrated circuit 110 includes a first plurality of metal regions connected to a source region of a power transistor. The integrated circuit 110 also includes a second plurality of metal regions connected to a drain region of the power transistor. The first and second plurality of metal regions have at least one of a substantially equal number of metal regions, a substantially equal resistance, or a balanced distribution of metal regions. That is, the number of M4, M3, M2, and M1 regions connected to the source region of the power transistor is substantially equal to the number of M4, M3, M2, and M1 regions connected to the drain region of the power transistor. The first plurality of stacked metal regions forming the first conductive path from the source region to the first M4 region have a substantially equal resistance to the second plurality of stacked metal regions forming the second conductive path from the drain region to the second M4 region. The first and second M4 regions may be the same M4 region or different M4 regions.

[0068] In some embodiments, integrated circuit 110 includes multiple active areas, each similar to the active area of ​​Figure 5A. One or more RDL, M4, M3, and M2 regions may intersect one or more of the active areas.

[0069] 5B is a perspective view of a metal region of an integrated circuit 110 for power conversion, according to an embodiment of the present disclosure. As shown in FIG. 5B, the integrated circuit 110 includes a substrate including two M4 regions, two M3 regions, two M2 regions, two M1 regions, and an active region. The active region includes multiple power transistors (not shown). The integrated circuit 110 has a crossed orientation of metal wires. The two M4 regions have widths W M4 = 35 μm and extends along the X-axis direction. The two M3 regions have a width of W M3 = 17 μm and extends along the Y-axis direction. The two M2 regions have a width W M2 = 8 μm and extends along the X-axis direction. The two M1 regions have a width W M1 =0.5 μm and extends along the Y-axis.

[0070] In some embodiments, an exemplary integrated circuit for power conversion may have a plurality of metal regions. The plurality of metal regions may include a plurality of first metal regions in a first layer. The first metal regions may have a first width. The plurality of metal regions may also include a plurality of second metal regions in a second layer. The second metal regions may have a second width. The second layer may be above the first layer. The second width is greater than the first width.

[0071] For example, the integrated circuit 110 of Figures 5A and 5B may include multiple M4, M3, M2, and M1 regions. That is, the metal region of the integrated circuit 110 includes an M2 region in the M2 layer. The M2 region has a width W M2 The metal region of the integrated circuit 110 has an M3 region in the M3 layer. The M3 region has a width W M3 = 17 μm. The M3 layer is above the M2 layer. The width of the M3 region (17 μm) is larger than the width of the M2 region (8 μm). The width of the M3 region (17 μm) is approximately twice the width of the M2 region (8 μm).

[0072] In some embodiments, the plurality of metal regions of the exemplary integrated circuit for power conversion may further include a plurality of third metal regions in a third layer. The third metal regions have a third width. The third layer is above the second layer. The third width is greater than the second width.

[0073] For example, the metal region of the integrated circuit 110 of Figures 5A and 5B includes an M4 region in the M4 layer. M4 = 35 μm. The M4 layer is located above the M3 layer. The width of the M4 region (35 μm) is larger than the width of the M3 region (17 μm). The width of the M4 region (35 μm) is approximately twice the width of the M3 region (17 μm).

[0074] In some embodiments, the plurality of metal regions of the exemplary integrated circuit for power conversion may further include a plurality of fourth metal regions in a fourth layer. The fourth layer is below the first layer and has a fourth width. A first portion of the fourth metal region is connected to a source region of the power transistor. A second portion of the fourth metal region is connected to a drain region of the power transistor. The fourth width is significantly smaller than the first width.

[0075] For example, the metal region of the integrated circuit 110 of Figures 5A and 5B also includes an M1 region in an M1 layer that is below an M2 layer and has a width W M1 = 0.5 μm. The width of the M1 region (0.5 μm) is significantly smaller than the width of the M2 region (8 μm). As shown in Figure 5A, three of the six M1 regions are connected to the source region of the power transistor. The other three of the six M1 regions are connected to the drain region of the power transistor.

[0076] In some embodiments, an exemplary integrated circuit for power conversion may have M4, M3, and M2 regions on layers M4, M3, and M2. The width of the M3 region may be 90% of the width of the M4 region. The width of the M2 region may be 90% of the width of the M3 region.

[0077] In some embodiments, an exemplary integrated circuit for power conversion may have M4, M3, and M2 regions on layers M4, M3, and M2. The width of the M3 region may be 80% of the width of the M4 region. The width of the M2 region may be 80% of the width of the M3 region.

[0078] In some embodiments, an exemplary integrated circuit for power conversion may have M4, M3, and M2 regions on layers M4, M3, and M2. The width of the M3 region may be 70% of the width of the M4 region. The width of the M2 region may be 70% of the width of the M3 region.

[0079] In some embodiments, an exemplary integrated circuit for power conversion may have M4, M3, and M2 regions on layers M4, M3, and M2. The width of the M3 region may be 60% of the width of the M4 region. The width of the M2 region may be 60% of the width of the M3 region.

[0080] In some embodiments, an exemplary integrated circuit for power conversion may have M4, M3, and M2 regions on layers M4, M3, and M2. The width of the M3 region may be 50% of the width of the M4 region. The width of the M2 region may be 50% of the width of the M3 region.

[0081] In some embodiments, an exemplary integrated circuit for power conversion may have M4, M3, and M2 regions on layers M4, M3, and M2. The width of the M3 region may be 40% of the width of the M4 region. The width of the M2 region may be 40% of the width of the M3 region.

[0082] In some embodiments, an exemplary integrated circuit for power conversion may have M4, M3, and M2 regions on layers M4, M3, and M2. The width of the M3 region may be 30% of the width of the M4 region. The width of the M2 region may be 30% of the width of the M3 region.

[0083] In some embodiments, an exemplary integrated circuit for power conversion may have M4, M3, and M2 regions on layers M4, M3, and M2. The width of the M3 region may be 20% of the width of the M4 region. The width of the M2 region may be 20% of the width of the M3 region.

[0084] In some embodiments, an exemplary integrated circuit for power conversion may have M4, M3, and M2 regions on layers M4, M3, and M2. The width of the M3 region may be 10% of the width of the M4 region. The width of the M2 region may be 10% of the width of the M3 region.

[0085] In some embodiments, an exemplary integrated circuit for power conversion may have M4, M3, and M2 regions on layers M4, M3, and M2. The width of the M3 region may be 90% to 10% of the width of the M4 region. The width of the M2 region may be 90% to 10% of the width of the M3 region.

[0086] In some embodiments, an exemplary integrated circuit for power conversion may be mounted on a circuit board having a plurality of conductive lines extending along a first direction perpendicular to a surface of the circuit board. The exemplary integrated circuit may include a plurality of metal regions. The plurality of metal regions of the exemplary integrated circuit may include a plurality of first metal regions in a first layer of the exemplary integrated circuit extending along a second direction. The plurality of metal regions of the exemplary integrated circuit may also include a plurality of second metal regions in a second layer of the exemplary integrated circuit extending along a third direction. The second layer is above the first layer. The third direction is perpendicular to the second direction.

[0087] For example, integrated circuit 110 is mounted on circuit board 120 of FIG. 2F or circuit board 140 of FIG. 3A. Circuit board 120 (FIG. 2F) includes conductive lines 121a, 121b, 121c, and 121d extending along the Z-axis direction perpendicular to the surface of circuit board 120. Circuit board 140 (FIG. 3A) includes conductive lines 141a, 141b, 141c, and 141d extending along the Z-axis direction perpendicular to the surface of circuit board 140. Integrated circuit 110 (FIG. 2F or FIG. 3A) may include multiple M4, M3, M2, and M1 regions (FIG. 5A). That is, integrated circuit 110 may include M2 ​​regions 201, 202, and 203 (FIG. 5A) extending along the X-axis direction on the M2 layer of integrated circuit 110. The integrated circuit 110 may also include six M3 regions (FIG. 5A) in an M3 layer of the integrated circuit 110 that extend along a Y-axis direction (FIG. 5B). The M3 layer is above the M2 layer. The Y-axis direction is perpendicular to the X-axis direction.

[0088] In some embodiments, the exemplary integrated circuit for power conversion further includes a plurality of third metal regions in a third layer extending along the second direction. The third layer is above the second layer. For example, integrated circuit 110 (FIG. 5A) may also include M4 regions 401, 402, and 403 (FIG. 5A) in an M4 layer of integrated circuit 110 extending along the X-axis direction. The M4 layer is above the M3 layer.

[0089] In some embodiments, an exemplary integrated circuit for power conversion may include a plurality of power transistors. The power transistors have a plurality of gate regions extending along a third direction. The exemplary integrated circuit may further include a plurality of fourth metal regions in a fourth layer extending along the third direction. The fourth layer is above the third layer. The fourth metal regions extend along the same third direction as the gate regions. For example, integrated circuit 110 (FIG. 5A) may include a plurality of power transistors. The power transistors include a plurality of gate regions, such as gate regions G2 and G3 in FIG. 5A. Gate regions G2 and G3 may extend along the Y-axis direction. Integrated circuit 110 (FIG. 5A) may further include a plurality of RDL regions (FIGS. 5A and 6A) in an RDL layer extending along the Y-axis direction. The RDL layer is above the M4 layer. The RDL metal regions extend along the same Y-axis direction as the gate regions.

[0090] 6A illustrates a top view of RDL regions and active regions of an integrated circuit 110 for power conversion, according to some embodiments. As shown in FIG. 6A, the integrated circuit 110 may include three RDL regions in the RDL layer and multiple active regions in the AR layer. The three RDL regions may extend along the Y-axis direction. The three RDL regions may be formed above all of the active regions and may be configured to redistribute vertical current from any of the active regions (i.e., any of the power transistors) to the appropriate output terminals of the integrated circuit 110.

[0091] 6B is a top view of a portion of the RDL and gate regions over the active area of ​​the integrated circuit 100 of FIG. 6A, according to some embodiments. As shown in FIGS. 6A and 6B, the RDL regions of the integrated circuit 110 may extend along the Y-axis (FIG. 6A). The integrated circuit 110 may include multiple gate regions above the active area. The gate regions may extend along the Y-axis direction. That is, the RDL and gate regions may extend along the same Y-axis direction in the integrated circuit 110.

[0092] In some embodiments, an exemplary integrated circuit for power conversion includes multiple RDL regions that extend along the same direction as multiple gate regions on multiple active regions in the exemplary integrated circuit. For example, as shown in FIG. 6A , three RDL regions in integrated circuit 110 may extend along the Y-axis direction. Furthermore, integrated circuit 110 may include multiple gate regions above each active region, similar to the gate regions on the active regions shown in FIG. 6B . Furthermore, the gate regions above each active region may extend along the Y-axis direction. Thus, integrated circuit 110 may include three RDL regions that extend along the same Y-axis direction as the multiple gate regions on the active regions.

[0093] 7A is a top view of an M4 region and an active region of an integrated circuit 110 for power conversion, according to some embodiments. As shown in FIG. 7A, the integrated circuit 110 may include multiple M4 regions and multiple active regions. The M4 regions may extend along the X-axis direction. As shown in FIG. 7A, the multiple M4 regions of the integrated circuit 110 may be formed above all of the active regions and may be configured to receive vertical current from any of the active regions (i.e., any of the power transistors) or to send vertical current to any of the active regions.

[0094] 7B is a top view of four M4 regions and six active regions of an exemplary integrated circuit for power conversion, according to some embodiments. As shown in FIG. 7B, the four M4 regions may be formed above the six active regions. The M4 regions have a width W M4 In one example, the width W M4 is 35 μm, that is, W M4=35 μm. In some embodiments, the M4 region of integrated circuit 110 may be any size feasible for the technology node, provided that it is wider and / or thicker than the M3, M2, and M1 regions below it. In some embodiments, the M4 region of integrated circuit 110 may be any size feasible for the technology node, provided that it is less resistive than the M3, M2, and M1 regions below it.

[0095] 7C is a top view of the M4 region, V43 vias between the M4 and M3 layers, and active areas of an integrated circuit 110 for power conversion, according to some embodiments. As shown in FIG. 7C, the integrated circuit 110 may include V43 vias formed in a balanced distribution over multiple active areas (i.e., power transistors) of the integrated circuit 110.

[0096] 7D is a top view of five M4 regions, V43 vias, and six active areas of an integrated circuit 110 for power conversion, according to some embodiments. As shown in FIG. 7D, 60 V43 vias may be formed in a balanced distribution under the five M4 regions and over the six active areas (i.e., power transistors) of the integrated circuit 110.

[0097] 8A is a top view of an M3 region and an active region of an integrated circuit 110 for power conversion, according to some embodiments. As shown in FIG. 8A, the integrated circuit 110 may include multiple M3 regions and multiple active regions. The M3 regions may extend along the Y-axis direction. As shown in FIG. 8A, the multiple M3 regions of the integrated circuit 110 may be formed above all of the active regions and may be configured to receive vertical current from any of the active regions (i.e., any of the power transistors) or to send vertical current to any of the active regions.

[0098] 8B is a top view of eight M3 regions and two active regions of an integrated circuit 110 for power conversion, according to some embodiments. As shown in FIG. 8B, the eight M3 regions may be formed above the two active regions. The M3 regions have a width W M3 In one example, the width W M4 is 17 μm, that is, W M3 = 17 μm.

[0099] 8C is a top view of four M4 regions and eight M3 regions of an integrated circuit 100 for power conversion, according to some embodiments. As shown in FIG. 8C, the four M4 regions may extend along the X-axis direction. The eight M3 regions may extend along the Y-axis direction. That is, the M3 regions may extend along a direction perpendicular to the direction in which the M4 regions may extend. As shown in FIG. 8C, the M4 regions have a width W M4 In one example, the width W M4 is 35 μm, that is, W M4 The M3 region may have a width W M3 The width W M4 is 17 μm, i.e., W M3 The width of the M3 region may be about 50% of the width of the M4 region. The width of the M4 region may be about twice the width of the M3 region, i.e., W M4 =2×W M3 may be.

[0100] In some embodiments, the M3 region of integrated circuit 110 may have any size feasible for the technology node, so long as it is thinner and / or less thick than the M4 region above it and wider and / or thicker than the M2 and M1 regions (FIG. 5A or 5B) below it. In some embodiments, the M3 region of integrated circuit 110 may have any size feasible for the technology node, so long as it is more resistive than the M4 region above it and less resistive than the M2 and M1 regions (FIG. 5A or 5B) below it.

[0101] 8D is a top view of V32 vias and active areas between the M3 and M2 layers of an integrated circuit 110 for power conversion, according to some embodiments. As shown in FIG. 8D, the integrated circuit 110 may include V32 vias formed in a balanced distribution over multiple active areas (i.e., power transistors) of the integrated circuit 110.

[0102] 8E is a top view of eight M3 regions, V32 vias, and two active areas of an exemplary integrated circuit for power conversion, according to some embodiments. As shown in FIG. 8E, 24 V32 vias may be formed in a balanced distribution under the eight M3 regions and above each active area (i.e., power transistor) of the integrated circuit 110. Four additional V32 vias may be formed at the four corners of the active areas.

[0103] Also, in some embodiments, an exemplary integrated circuit for power conversion includes a plurality of first vias connected between a first metal region and a second metal region and a plurality of second vias connected between the second metal region and a third metal region, the first vias having a balanced distribution over the power transistor, and the second vias having a balanced distribution over the power transistor.

[0104] For example, as shown in Figures 7C and 7D, integrated circuit 110 may include multiple V43 vias connected between the M4 region and the M3 region (Figure 5A). The multiple V43 vias may have a balanced distribution over the multiple active regions (i.e., power transistors) of integrated circuit 110. Also, as shown in Figures 8D and 8E, integrated circuit 110 may include multiple V32 vias connected between the M3 region and the M2 region (Figure 5A). The multiple V32 vias may have a balanced distribution over the multiple active regions (i.e., power transistors) of integrated circuit 110.

[0105] FIG. 9A is a top view of the M2 region and active region of an integrated circuit 110 for power conversion, according to some embodiments.

[0106] As shown in Figure 9A, the integrated circuit 110 may include multiple M2 regions and multiple active regions. The M2 regions may extend along the X-axis direction. As shown in Figure 9A, the multiple M2 regions of the integrated circuit 110 may be formed above all of the active regions and may be configured to receive vertical current from any of the active regions (i.e., any of the power transistors) or to send vertical current to any of the active regions.

[0107] 9B is a top view of sixteen M2 regions and six active regions of an integrated circuit 110 for power conversion, according to some embodiments. As shown in FIG. 9B, the M2 regions may be formed above the six active regions. The M2 regions have a width W M2 In one example, the width W M2 is 8 μm, that is, W M2 =8 μm. In some embodiments, the M2 region of integrated circuit 110 may be any size feasible for the technology node, so long as it is wider and / or thicker than the M1 region below it. In some embodiments, the M2 region of integrated circuit 110 may be any size feasible for the technology node, so long as it is more resistive than the M4 and M3 regions above it.

[0108] FIG. 9C is a top view of the M3 and M2 regions of an exemplary integrated circuit for power conversion, according to some embodiments.

[0109] As shown in FIG. 9C, the eight M3 regions may extend along the Y-axis direction. The sixteen M2 regions may extend along the X-axis direction. That is, the M2 regions may extend along a direction perpendicular to the direction in which the M3 regions may extend. As shown in FIG. 9C, the M3 regions may have a width W M3 The width W M4 is, for example, 17 μm, i.e., W M3 The M2 region may have a width W M2 The width W M2 is 8 μm, i.e., WM2 The width of the M2 region may be about 50% of the width of the M3 region. The width of the M3 region may be about twice the width of the M2 region, i.e., W M3 =2×W M2 may be.

[0110] In some embodiments, the M2 region of integrated circuit 110 may have any size feasible for the technology node, so long as it is thinner and / or less thick than the M3 region above it and wider and / or thicker than the M1 region (FIG. 5A or 5B) below it. In some embodiments, the M2 region of integrated circuit 110 may have any size feasible for the technology node, so long as it is more resistive than the M4 and M3 regions above it.

[0111] 10A illustrates a top view of an M1 region and an active region of an integrated circuit 110 for power conversion, according to some embodiments. As shown in FIG. 10A, the integrated circuit 110 may include multiple M1 regions and multiple active regions. The M1 regions may extend along a y-axis direction. As shown in FIG. 10A, the multiple M1 regions of the integrated circuit 110 may be formed above all of the active regions and may be configured to receive vertical current from source and drain regions of power transistors in the active regions and to send vertical current to the source and drain regions of the power transistors.

[0112] 10B is a top view of an M1 region and an active region of an integrated circuit 110 for power conversion, according to some embodiments. As shown in FIG. 10B, the integrated circuit 110 may include multiple M1 regions formed above each active region. The M1 regions have a width W M1 The width W M1 is, for example, 0.5 μm, i.e., W M1 The M2 region above the M1 region may have a width W M2 The width W M2 is 8 μm, i.e., W M2The width of the M1 region may be 6.25% of the width of the M2 region, i.e., W M1 =0.0625×W M2 The width of the M1 region may be significantly smaller than the width of the M2 region above the M1 region.

[0113] In some embodiments, the width of the M1 region may be 5-20% of the width of the M2 region, and the width of the M1 region may be significantly smaller than the width of the M2 region above the M1 region.

[0114] 10C is a top view of an M1 region and a partial active area of ​​an integrated circuit for power conversion 110, according to some embodiments. As shown in FIG. 10C, in the active area, multiple M1 regions may extend along the Y-axis direction.

[0115] FIG. 10D is a top view of an M1 region, V21 vias between the M2 and M1 layers, and a partial active area of ​​an integrated circuit 110 for power conversion, according to some embodiments. As shown in FIG. 10D, the integrated circuit 110 may include V21 vias formed with a balanced distribution over a partial active area (i.e., power transistors) of the integrated circuit 110. While FIG. 10D only shows a partial active area, the other portions of the active area are the same as shown. That is, the integrated circuit 110 may include V21 vias formed with a balanced distribution over the active area (i.e., power transistors) of the integrated circuit 110. The integrated circuit 110 may include V21 vias formed with a balanced distribution over all of the active areas of the integrated circuit 110.

[0116] FIG. 11 illustrates a top view of two M2 regions, multiple gate regions, and partial active regions of an integrated circuit 110 for power conversion, according to some embodiments. As shown in FIG. 11, the integrated circuit 110 may include multiple gate regions formed above the partial active regions. The gate region may extend along the Y-axis direction. The two M2 regions may extend along the X-axis direction. As shown in FIG. 11, two ends of the gate region may be connected to two M2 regions, respectively. Both M2 regions may be configured to transmit current to or from the gate region, which may enable fast and efficient current transmission. The two M2 regions in FIG. 11 may be two above and two below the eight M2 regions above the active region in FIG. 9B. The other six of the eight M2 regions above the active region may be connected to the source or drain regions of the power transistor.

[0117] In some embodiments, the integrated circuit 110 may include multiple power transistors for power conversion. One or more of the power transistors may each include multiple active regions, multiple terminals, and multiple conductive paths. Each terminal may be electrically connected to at least one of the active regions via at least one of the conductive paths. Each conductive path may include one or more horizontally oriented metal conductors and one or more vertically oriented metal conductors. In a majority of the conductive paths, the sum of the lengths of the one or more vertically oriented metal conductors may exceed the sum of the lengths of the one or more horizontally oriented metal conductors.

[0118] For example, the power transistor of integrated circuit 110 may have six active regions (FIG. 9B). Each of the six active regions may include multiple transistors, each with a gate region, a source region, and a drain region (FIG. 11). As shown in FIG. 11, all of the gate regions may be connected together by an M2 region. All of the source regions may also be connected together. All of the drain regions may also be connected together. That is, the parallel connection of multiple transistors in the active regions may form an equivalent transistor with increased power handling capabilities. Furthermore, the parallel connection of equivalent transistors in the six active regions may form a power transistor with high power handling capabilities.

[0119] The power transistor may also include multiple terminals connected to the M4 region (FIG. 7B). The power transistor may also include multiple conductive paths, such as the conductive path P23-M2 (FIG. 5A). Each terminal may be electrically connected to at least one of the six active regions via at least one of the conductive paths. Each conductive path may include one or more horizontally oriented metal conductors (e.g., the conductive path P23-M2 on the M2 region 202 in FIG. 5A) and one or more vertically oriented metal conductors (e.g., the V1, M1, V21, V32, M3, V43, and M4 regions along the conductive path P23-M2 in FIG. 5A). In most of the conductive paths, the sum of the lengths of the one or more vertically oriented metal conductors may exceed the sum of the lengths of the one or more horizontally oriented metal conductors.

[0120] In some embodiments, the laterally oriented metal conductor may include a first metal conductor in a first metal layer above the active region and a second metal conductor in a second metal layer above the first metal layer. The width of the first metal conductor may be smaller than the width of the second metal conductor. For example, the laterally oriented metal conductor of a power transistor may include M2 ​​regions 201, 202, and 203 ( FIG. 5A ) in an M2 layer above the active region. The laterally oriented metal conductor of a power transistor may also include M4 regions 401, 402, and 403 in an M4 layer above the M2 layer. The widths of the M2 regions 201, 202, and 203 may be 8 μm. The widths of the M4 regions 401, 402, and 403 may be 35 μm. The widths of the M2 regions 201, 202, and 203 (8 μm) are smaller than the widths of the M4 regions 401, 402, and 403 (35 μm).

[0121] In some embodiments, in a power transistor, the current flowing through each laterally oriented metal conductor in the second metal layer exceeds the current flowing through each laterally oriented metal conductor in the first metal layer. For example, the current flowing through each laterally oriented M4 region in the M4 layer may be 0.3 mA. The current flowing through each laterally oriented M2 region in the M2 layer may be 0.1 mA. The current flowing through each M4 region (0.3 mA) exceeds the current flowing through each M2 region (0.1 mA).

[0122] In some embodiments, in a power transistor, the resistance of each laterally oriented metal conductor in the second metal layer is lower than the resistance of each laterally oriented metal conductor in the first metal layer. For example, M4 regions 401, 402, and 403 (FIG. 5A) in the M4 layer are thicker than M2 regions 201, 202, and 203 (FIG. 5A) in the M4 layer. Therefore, the resistance of each of the M4 regions 401, 402, and 403 is lower than the resistance of each of the M2 regions 201, 202, and 203.

[0123] FIG. 12 illustrates an example configuration of the apparatus 100 for power conversion of FIG. 1 , according to an embodiment of the disclosure. As shown in FIG. 12 , the apparatus 100 may have configurations 1, 2, 3, 4, and 5 for outputting power. The controller 114 (FIG. 4 ) may be configured to determine one of the configurations 1, 2, 3, 4, and 5 and connect the inductors 131, 132, 133, and 134 based on the determined configuration. As shown in FIG. 2D , the inductors 131, 132, 133, and 134 may share an inductor core 135 or may be connected together based on the determined configuration.

[0124] In configuration 1, the controller 114 controls the inductors 131, 132, 133, and 134 to generate an output power V OUT-1 , V OUT-2 , V OUT-3 , and V OUT-4 In configuration 2, the controller 114 may be configured to determine that inductors 132 and 133 are connected together and output power V OUT-2 and V OUT-3 The controller 114 may be configured to determine that the inductors 131 and 134 can output a current of 8 A based on the output power V OUT-1 and V OUT-4 In configuration 3, the controller 114 may be configured to determine that the inductors 131 and 132 are connected together and the output power V OUT-1 and V OUT-2 The controller 114 may be configured to determine that a current of 8 A can be output based on the inductors 133 and 134 connected together and the output power V OUT-3 and V OUT-4 The power supply may be configured to determine that a current of 8 A can be output based on the above.

[0125] In configuration 4, the controller 114 controls the inductors 131, 132, and 133 to be connected together and to generate an output power VOUT-1 , V OUT-2 , and V OUT-3 The controller 114 may be configured to determine that the inductor 134 can output a current of 12 A based on the output power V OUT-4 In configuration 5, the controller 114 may be configured to determine that the inductors 131, 132, 133, and 134 are connected together and output a current of 4 A. OUT-1 , V OUT-2 , V OUT-3 , and V OUT-4 The power supply may be configured to determine that a current of 16 A can be output based on the above.

[0126] When controller 114 determines one of configurations 1, 2, 3, 4, and 5, inductors 131, 132, 133, and 134 may be connected as described above and configured to emit multiple voltage outputs, such as converted voltages of 4 A, 8 A, 12 A, and 16 A currents, as shown with reference to FIG. 12.

[0127] 13 is a circuit diagram of an exemplary apparatus 100 for power conversion of FIG. 1 , according to some embodiments. As shown in FIG. 13 , apparatus 100 may include integrated circuit 110, inductors 131, 132, 133, and 134, and a number of peripheral circuits (such as capacitors and resistors) connected to or between integrated circuit 110 and inductors 131, 132, 133, and 134. The peripheral circuits may be implemented on circuit board 120 ( FIG. 1 ). Apparatus 100 may convert input power V based on configurations 1, 2, 3, 4, and 5 ( FIG. 12 ). IN The signal processing unit may be configured to convert the signal into a signal.

[0128] The foregoing embodiments have been described herein with reference to numerous specific details that may vary from implementation to implementation. Certain adaptations and modifications of these described embodiments are possible. Other embodiments may become apparent to those skilled in the art from consideration of the specification and practice of the subject matter disclosed herein. Additionally, the sequence of steps depicted in the figures is for illustrative purposes only and is not intended to limit the invention to any particular sequence of steps. Thus, those skilled in the art will appreciate that the steps may be performed in different orders to achieve the same method.

[0129] It will be understood that certain features herein that are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features herein that are, for brevity, described in the context of a single embodiment may also be provided separately, in any suitable subcombination, or as suitable in any other described embodiment herein. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, if the embodiment will function without those elements.

[0130] The above embodiments can be further described using the following clauses. 1. An apparatus for power conversion, comprising: an integrated circuit for power conversion, a plurality of power transistors; a plurality of metal regions connected to a plurality of power transistors; Equipped with a first portion of the metal region connected to source regions of the plurality of power transistors; a second portion of the metal region connected to the drain regions of the plurality of power transistors; An apparatus comprising an integrated circuit, wherein the first and second portions have at least one of a substantially equal number of metal areas, a substantially equal resistance, or a balanced distribution of metal areas.

[0131] 2. The device of clause 1, wherein the integrated circuit is mounted on a circuit board having a surface and a plurality of conductive lines, the conductive lines extending along a direction perpendicular to the surface, and the integrated circuit is connected to the conductive lines.

[0132] 3. The device described in clause 2, wherein the integrated circuit is connected to an inductor mounted on the surface of the circuit board through at least one of the conductive lines, and at least a portion of the integrated circuit is directly below the inductor.

[0133] 4. Multiple metal areas a plurality of first metal regions in a first layer, the first metal regions having a first width; a plurality of second metal regions in a second layer above the first layer, the second metal regions having a second width; Equipped with 4. The apparatus of any of clauses 1-3, wherein the second width is greater than the first width.

[0134] 5. The apparatus of clause 4, wherein the second width is twice the first width.

[0135] 6. The plurality of metal regions are a plurality of third metal regions in a third layer above the second layer, the third metal regions further comprising a third width; 5. The apparatus of clause 4, wherein the third width is greater than the second width.

[0136] 7. The apparatus of clause 6, wherein the third width is twice the second width.

[0137] 8. The plurality of metal regions further comprises a plurality of fourth metal regions in a fourth layer below the first layer, the fourth metal regions having a fourth width; a first portion of the fourth metal region connected to source regions of the plurality of power transistors; a second portion of the fourth metal region connected to the drain regions of the plurality of power transistors; 7. The apparatus of clause 6, wherein the fourth width is significantly smaller than the first width.

[0138] 9. The above direction is a first direction; Multiple metal regions a plurality of first metal regions extending along a second direction in the first layer; a plurality of second metal regions extending along a third direction in a second layer above the first layer; Equipped with 9. The apparatus of any of clauses 1-8, wherein the third direction is perpendicular to the second direction.

[0139] 10. The apparatus of clause 9, wherein the plurality of metal regions further comprises a plurality of third metal regions extending along the second direction in a third layer above the second layer.

[0140] 11. A plurality of power transistors include a plurality of gate regions extending along a third direction; 11. The apparatus of clause 10, wherein two ends of the gate regions of the plurality of power transistors are connected to a portion of the first metal region.

[0141] 12. The integrated circuit further comprises a plurality of fourth metal regions extending along a third direction in a fourth layer above the third layer; 12. The apparatus of clause 11, wherein the fourth metal region extends along the same third direction as the gate region.

[0142] 13. An integrated circuit is a plurality of first vias connected between the first metal region and the second metal region; a plurality of second vias connected between the second metal region and the third metal region; Furthermore, the first vias have a balanced distribution over the plurality of power transistors; 12. The apparatus of claim 11, wherein the second vias have a balanced distribution over the plurality of power transistors.

[0143] 14. The apparatus of clause 3, wherein the inductor is coupled to a buck converter circuit in the integrated circuit through a conductive line.

[0144] 15. The apparatus of clause 3, wherein the inductor is coupled to the integrated circuit through a plurality of conductive lines.

[0145] 16. The apparatus of clause 3, wherein the inductor is a coupled inductor.

[0146] 17. The device of clause 3, wherein the inductor is a chip inductor.

[0147] 18. The integrated circuit includes a charge pump circuit and a buck converter circuit; 4. The apparatus of claim 3, wherein the buck converter circuit is coupled to the inductor through at least one of the conductive lines.

[0148] 19. An integrated circuit includes a charge pump circuit for two or more charge pumps and a buck converter circuit for at least two buck converters; the inductor includes at least two chip inductors; 4. The apparatus of clause 3, wherein at least two buck converters are individually coupled to each of the at least two chip inductors through respective conductive lines.

[0149] 20. The device described in clause 2, wherein the conductive lines are disposed on a common edge of the circuit board.

[0150] 21. The integrated circuit has a plurality of output terminals for outputting current; The output terminals are directly connected to the conductive lines, 3. The apparatus of claim 2, wherein the conductive lines extend directly from the output terminals to the inductor along a direction perpendicular to the surface.

[0151] 22. The apparatus of clause 21, wherein the output terminal is within a portion of the integrated circuit directly below the inductor.

[0152] 23. The device according to clause 2, wherein the integrated circuit is embedded within the circuit board.

[0153] 24. A circuit board comprising first, second, and third layers; The second layer is between the first and third layers, 24. The apparatus of claim 23, wherein the integrated circuit is implemented on the second layer.

[0154] 25. A circuit board comprising first and second metal layers; a conductive line connected between the first metal layer and the second metal layer; 24. The apparatus of clause 23, wherein the integrated circuit is connected to conductive lines in the second metal layer.

[0155] 26. The surface is a first surface; the circuit board further comprising a second surface; 3. The apparatus of claim 2, wherein the integrated circuit is mounted on the second surface.

[0156] 27. The apparatus of clause 3, wherein the inductor comprises multiple coupled inductors sharing a common inductor core.

[0157] 28. An integrated circuit includes a control circuit; A control circuit determines the output configuration of the coupled inductor; 28. The apparatus of clause 27, wherein the coupled inductor emits multiple voltage outputs.

[0158] 29. An integrated circuit includes a control circuit; 28. The apparatus of clause 27, wherein the control circuit outputs a longitudinal current from the integrated circuit to the inductor, the longitudinal current flowing along a direction perpendicular to the integrated circuit.

[0159] 30. A power transistor for power conversion, comprising: a plurality of active regions; A plurality of terminals; Multiple conductive paths Equipped with each terminal electrically connected to at least one of the active areas via at least one of the conductive paths; Each conductive path comprises one or more horizontally oriented metal conductors and one or more vertically oriented metal conductors; A power transistor in which the sum of the lengths of one or more vertically oriented metal conductors exceeds the sum of the lengths of one or more horizontally oriented metal conductors along a majority of the conduction path.

[0160] 31. A horizontally oriented metal conductor is a first metal conductor in a first metal layer above the active region; a second metal conductor in a second metal layer above the first metal layer; Equipped with 31. The power transistor of claim 30, wherein a width of the first metal conductor is less than a width of the second metal conductor.

[0161] 32. The power transistor of clause 31, wherein the current flowing through each laterally oriented metal conductor in the second metal layer exceeds the current flowing through each laterally oriented metal conductor in the first metal layer.

[0162] 33. The power transistor of clause 31, wherein the resistance of each laterally oriented metal conductor in the second metal layer is less than the resistance of each laterally oriented metal conductor in the first metal layer.

[0163] The foregoing outlines features of several embodiments so that those skilled in the art may more fully appreciate aspects of the present disclosure. Those skilled in the art will readily appreciate that this disclosure may be used as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. 1. An apparatus for power conversion, comprising: an integrated circuit for power conversion, a plurality of power transistors; a plurality of metal regions connected to the plurality of power transistors; Equipped with a first portion of the metal region connected to source regions of the plurality of power transistors; a second portion of the metal region connected to drain regions of the plurality of power transistors; The apparatus comprising the integrated circuit, wherein the first and second portions have at least one of a substantially equal number of metal areas, a substantially equal resistance, or a balanced distribution of metal areas.

2. 10. The device of claim 1, wherein the integrated circuit is mounted on a circuit board having a surface and a plurality of conductive lines, the conductive lines extending along a direction perpendicular to the surface, and the integrated circuit is connected to the conductive lines.

3. 3. The apparatus of claim 2, wherein the integrated circuit is connected through at least one of the conductive lines to an inductor mounted on the surface of the circuit board, with at least a portion of the integrated circuit directly underneath the inductor.

4. the plurality of metal regions: a plurality of first metal regions in a first layer, the first metal regions having a first width; a plurality of second metal regions in a second layer above the first layer, the second metal regions having a second width; Equipped with The apparatus of any one of claims 1 to 3, wherein the second width is greater than the first width.

5. The apparatus of claim 4 , wherein the second width is twice the first width.

6. the plurality of metal regions are a plurality of third metal regions in a third layer above the second layer, the third metal regions having a third width; The apparatus of claim 4 or 5, wherein the third width is greater than the second width.

7. The apparatus of claim 6 , wherein the third width is twice the second width.

8. the plurality of metal regions further comprising a plurality of fourth metal regions in a fourth layer below the first layer, the fourth metal regions having a fourth width; a first portion of the fourth metal region connected to source regions of the plurality of power transistors; a second portion of the fourth metal region connected to drain regions of the plurality of power transistors; 8. The device of claim 6 or 7, wherein the fourth width is significantly smaller than the first width.

9. the plurality of metal regions: a plurality of first metal regions extending along a first direction in the first layer; a plurality of second metal regions extending along a second direction in a second layer above the first layer; Equipped with The apparatus of any preceding claim, wherein the second direction is perpendicular to the first direction.

10. 10. The apparatus of claim 9, wherein the plurality of metal regions further comprises a plurality of third metal regions extending along the first direction in a third layer above the second layer.

11. the plurality of power transistors each having a plurality of gate regions extending along the second direction; 11. The apparatus of claim 10, wherein two ends of the gate regions of the plurality of power transistors are connected to a portion of the first metal region.

12. the integrated circuit further comprises a plurality of fourth metal regions extending along the second direction in a fourth layer above the third layer; 12. The device of claim 11, wherein the fourth metal region extends along the same second direction as the gate region.

13. The integrated circuit comprises: a plurality of first vias connected between the first metal region and the second metal region; a plurality of second vias connected between the second metal region and the third metal region; Furthermore, the first vias have a balanced distribution over the plurality of power transistors; The apparatus of claim 11 , wherein the second vias have a balanced distribution over the plurality of power transistors.

14. The apparatus of claim 2 , wherein the conductive lines are disposed on a common edge of the circuit board.

15. 15. The device of claim 2 or 14, wherein the integrated circuit is embedded within the circuit board.

16. the circuit board comprising first, second, and third layers; the second layer is between the first layer and the third layer; 16. The apparatus of claim 15, wherein the integrated circuit is implemented in the second layer.

17. the circuit board comprises first and second metal layers; the conductive line is connected between the first metal layer and the second metal layer; 16. The apparatus of claim 15, wherein the integrated circuit is connected to the conductive lines in the second metal layer.

18. the surface is a first surface; the circuit board further comprising a second surface; The apparatus of claim 2 , wherein the integrated circuit is mounted on the second surface.

19. 4. The apparatus of claim 3, wherein the inductor is coupled to a buck converter circuit within the integrated circuit through the conductive line.

20. The apparatus of claim 3 , wherein the inductor is coupled to the integrated circuit through a plurality of the conductive lines.

21. The apparatus of claim 3 , wherein the inductor is a coupled inductor.

22. The device of claim 3 , wherein the inductor is a chip inductor.

23. the integrated circuit comprises a charge pump circuit and a buck converter circuit; 4. The apparatus of claim 3, wherein the buck converter circuit is coupled to the inductor through at least one of the conductive lines.

24. the integrated circuit comprises a charge pump circuit for two or more charge pumps and a buck converter circuit for at least two buck converters; the inductor comprises at least two chip inductors; 4. The apparatus of claim 3, wherein the at least two buck converters are individually coupled to each of the at least two chip inductors through respective conductive lines.

25. the integrated circuit has a plurality of output terminals for outputting current; the output terminal is directly connected to the conductive line; 4. The device of claim 3, wherein the conductive line extends directly from the output terminal to the inductor along the direction perpendicular to the surface.

26. 26. The apparatus of claim 25, wherein the output terminal is in a portion of an integrated circuit directly below the inductor.

27. The apparatus of claim 3 , wherein the inductor comprises multiple coupled inductors sharing a common inductor core.

28. the integrated circuit comprises a control circuit; the control circuit determines an output configuration of the coupled inductor; 30. The apparatus of claim 27, wherein the coupled inductor emits multiple voltage outputs.

29. the integrated circuit comprises a control circuit; 28. The apparatus of claim 27, wherein the control circuit outputs a longitudinal current from the integrated circuit to the inductor that flows along a direction perpendicular to a surface of the integrated circuit.

30. 1. A power transistor for power conversion, comprising: a plurality of active regions; A plurality of terminals; Multiple conductive paths Equipped with each terminal electrically connected to at least one of the active regions through at least one of the conductive paths; Each conductive path comprises one or more horizontally oriented metal conductors and one or more vertically oriented metal conductors; The power transistor, wherein the sum of the lengths of the one or more vertically oriented metal conductors exceeds the sum of the lengths of the one or more horizontally oriented metal conductors in most of the conductive path.

31. The laterally oriented metal conductor is a first metal conductor in a first metal layer above the active region; a second metal conductor in a second metal layer above the first metal layer; Equipped with 31. The power transistor of claim 30, wherein the width of the first metal conductor is less than the width of the second metal conductor.

32. 32. The power transistor of claim 31, wherein the current flowing through each laterally oriented metal conductor in the second metal layer exceeds the current flowing through each laterally oriented metal conductor in the first metal layer.

33. 33. The power transistor of claim 31 or 32, wherein the resistance of each laterally oriented metal conductor in the second metal layer is less than the resistance of each laterally oriented metal conductor in the first metal layer.

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