Storage unit, 3D memory and manufacturing method thereof, electronic device

Abstract

A memory unit, a 3D memory and its manufacturing method, and an electronic device, which relate to the semiconductor technical field, include a first transistor and a second transistor disposed on a substrate (1), the first transistor including a first gate electrode (11), a first electrode (33), a second electrode (34), and a first semiconductor layer (6) disposed on the substrate, the second transistor including a third electrode (51), a fourth electrode (52) disposed on the substrate (1), a second gate electrode (12) extending along a direction perpendicular to the substrate (1), and a second semiconductor layer (9) surrounding a sidewall of the second gate electrode (12), the second semiconductor layer (9) including a second source contact region (91) and a second drain contact region (92) disposed at an interval, and a channel between the second source contact region (91) and the second drain contact region (92) being a horizontal channel.

Description

[Technical Field]

[0001] TECHNICAL FIELD The embodiments of the present disclosure relate to the field of semiconductor technology, but are not limited thereto, and in particular to a storage unit, a 3D memory and its manufacturing method, and an electronic device.

[0002] This application claims priority to a Chinese patent application filed with the China Patent Office on October 18, 2022, bearing application number 202211269945.4 and entitled "Storage unit, 3D memory and manufacturing method thereof, and electronic device," the contents of which are hereby incorporated by reference. [Background technology]

[0003] Conventionally, the storage unit structure of a typical dynamic random access memory (DRAM) is a 1T1C type, in which the source electrode of one transistor is connected to one capacitor. This structure uses a capacitor to store data, but the capacitor consumes electricity during reading and leaks current, so the charge in the capacitor needs to be constantly refreshed, resulting in relatively high power consumption. In addition, the capacitor manufacturing process occupies a large area, making it difficult to reduce its size.

[0004] The 2Transistor 0Capacitor (2T0C) memory unit uses two transistors as a unit structure, stores charge using a gate capacitor, and stores information by changing the transconductance of the transistor. Summary of the Invention

[0005] The following is a summary of the subject matter described herein, which does not limit the scope of protection of the claims.

[0006] An embodiment of the present disclosure provides a memory unit, the memory unit comprising a first transistor and a second transistor disposed on a substrate; the first transistor includes a first gate electrode, a first electrode, a second electrode, and a first semiconductor layer disposed on the substrate, the first gate electrode extending along a direction parallel to the substrate; the second transistor includes a third electrode and a fourth electrode disposed on the substrate, a second gate electrode extending along a direction perpendicular to the substrate, and a second semiconductor layer surrounding sidewalls of the second gate electrode, the first gate electrode being connected to the second semiconductor layer, the second semiconductor layer including a second source contact region and a second drain contact region spaced apart, the third electrode contacting the second source contact region of the second semiconductor layer, the fourth electrode contacting the second drain contact region of the second semiconductor layer, a channel between the second source contact region and the second drain contact region being a horizontal channel. In one exemplary embodiment, in a plane perpendicular to the substrate, an orthogonal projection of the first gate electrode and an orthogonal projection of the third electrode overlap each other, and an orthogonal projection of the third electrode and an orthogonal projection of the fourth electrode overlap each other, and the first gate electrode of the first transistor and the third electrode of the second transistor are an integrated structure.

[0007] In one exemplary embodiment, the first gate electrode is connected to a second source contact region of the second semiconductor layer.

[0008] In one exemplary embodiment, in a plane perpendicular to the substrate, there is an overlap between the orthogonal projection of the first electrode and the orthogonal projection of the first gate electrode.

[0009] In one exemplary embodiment, the second drain contact region of the second semiconductor layer and the second source contact region of the second semiconductor layer are located on sidewalls of the second semiconductor layer and are opposite and spaced apart.

[0010] In one exemplary embodiment, the second electrode surrounds and is connected to the first semiconductor layer, a cross section of the second electrode has a ring-shaped opening in a plane perpendicular to the substrate, and the first semiconductor layer is located within the opening of the second electrode.

[0011] In one exemplary embodiment, the first electrode is disposed on a side of the second electrode away from the second gate electrode.

[0012] In one exemplary embodiment, the first semiconductor layer includes a sidewall and two ends, the first semiconductor layer includes a first source contact region and a first drain contact region, the first source contact region is located on the sidewall of the first semiconductor layer and surrounds the first semiconductor layer, and the first drain contact region is located on the sidewall of the first semiconductor layer and surrounds the first semiconductor layer, or is located at the end of the two ends that is away from the second gate electrode.

[0013] In one exemplary embodiment, the first electrode extends along a third direction, the first gate electrode extends along a second direction, the third electrode extends along the second direction, and the fourth electrode extends along a third direction, wherein the second direction and the third direction intersect and are parallel to the substrate.

[0014] In one exemplary embodiment, in a plane parallel to the substrate, there is no overlap between the orthogonal projection of the first electrode and the orthogonal projection of the second electrode, and there is no overlap between the orthogonal projection of the third electrode and the orthogonal projection of the fourth electrode.

[0015] In one exemplary embodiment, in a cross section perpendicular to the substrate, the first electrode, the second electrode, and the third electrode are located on a first side of the second gate electrode, the fourth electrode is located on a second side of the second gate electrode, and the first side and the second side are opposite each other.

[0016] In one exemplary embodiment, the distance between the surface of the first electrode closer to the substrate and the substrate is smaller than the distance between the surface of the third electrode closer to the substrate and the substrate, and the distance between the surface of the first electrode away from the substrate and the substrate is greater than the distance between the surface of the third electrode away from the substrate and the substrate.

[0017] In one exemplary embodiment, the third electrode and fourth electrode layers are different regions of the same conductive layer and are spaced apart, and the same conductive layer is substantially parallel to the substrate.

[0018] In one exemplary embodiment, the second transistor further includes a second gate insulating layer disposed between the second gate electrode and the second semiconductor layer and surrounding a sidewall of the second gate electrode, and along a direction perpendicular to the substrate, a length of the second semiconductor layer is equal to or less than a length of the second gate insulating layer, is equal to or greater than a length of the third electrode, and is equal to or greater than a length of the fourth electrode.

[0019] In one exemplary embodiment, the material of the first and second semiconductor layers comprises a metal oxide semiconductor material.

[0020] In one exemplary embodiment, the metal in the metal oxide semiconductor material comprises at least one of indium, tin, zinc, aluminum, and gallium.

[0021] An embodiment of the present disclosure provides a storage unit, comprising a read transistor and a write transistor disposed on a substrate; the read transistor includes a first gate electrode, a first semiconductor layer, a first source electrode, and a first drain electrode, the first semiconductor layer surrounding the first gate electrode, and the first gate electrode extending along a direction parallel to the substrate; the write transistor includes a second gate electrode, a second semiconductor layer, a second source electrode, and a second drain electrode, the second semiconductor layer surrounding the second gate electrode, the second gate electrode extending along a direction perpendicular to the substrate, and the second source electrode of the write transistor connected to the first gate electrode of the read transistor; The channel of the second semiconductor layer of the write transistor is a horizontal channel.

[0022] In one exemplary embodiment, the read transistors and write transistors are distributed in the substrate at intervals along a direction parallel to the substrate.

[0023] In one exemplary embodiment, the second gate electrode extends along a direction perpendicular to the substrate and has a sidewall, the second semiconductor layer surrounds the sidewall, and the second semiconductor layer includes a second source contact region; The first gate electrode extends along a direction parallel to the substrate and has a sidewall and two ends, the first semiconductor layer surrounds at least the sidewall, and one of the two ends extends to a second source contact region of the second semiconductor layer and contacts the second semiconductor layer.

[0024] In one exemplary embodiment, a sidewall of the second semiconductor layer further includes a second drain contact region, the second source contact region and the second drain contact region are located in different regions of the sidewall of the second semiconductor layer, and there is an overlapping region between the second source contact region and the second drain contact region when orthogonally projected on a plane perpendicular to the substrate, so that a channel between the second source contact region and the second drain contact region is parallel to the substrate; The sidewalls of the first semiconductor layer have a first source contact region and a first drain contact region, and a channel between the first source contact region and the first drain contact region is parallel to the substrate.

[0025] In an embodiment of the present disclosure, a 3D memory is provided, comprising a plurality of layers of storage units stacked along a direction perpendicular to a substrate; the storage unit in each layer comprises a read transistor and a write transistor; the read transistor includes a first gate electrode, a first semiconductor layer, a first source electrode, and a first drain electrode, and the first gate electrode extends along a direction parallel to the substrate; the write transistor includes a second gate electrode, a second semiconductor layer, a second source electrode, and a second drain electrode, and the second gate electrode extends along a direction perpendicular to the substrate; A second source electrode of the write transistor is connected to a first gate electrode of the read transistor, the first semiconductor layer surrounds the first gate electrode, the second semiconductor layer surrounds the second gate electrode, and a channel of the second semiconductor layer of the write transistor is a horizontal channel.

[0026] In one exemplary embodiment, the read transistors and write transistors in the same layer are distributed in the substrate at intervals along a direction parallel to the substrate.

[0027] In one exemplary embodiment, the first gate electrode of the read transistor and the second source electrode of the write transistor are an integral structure.

[0028] In one exemplary embodiment, the first gate electrode extends along a second direction parallel to the substrate; the first semiconductor layer includes a first source contact region and a first drain contact region, and the second semiconductor layer includes a second source contact region and a second drain contact region; The memory units of each layer further include a first bit line and a second bit line extending along a third direction parallel to the substrate, the third direction intersecting with the second direction, the first bit line being connected to a first drain contact region of the first semiconductor layer, and the second bit line being connected to a second drain contact region of the second semiconductor layer; The memory units of each layer further include a first word line and a second word line extending along a direction perpendicular to the substrate; The first word lines are respectively connected to first source contact regions of first semiconductor layers of the memory units in different layers, and the second word lines are respectively connected to second gate electrodes of the memory units in different layers.

[0029] In one exemplary embodiment, the first word line surrounds the sidewalls of each first semiconductor layer of the storage units of different layers, and is connected to the first source contact region of the sidewall of each first semiconductor layer.

[0030] In one exemplary embodiment, the first gate electrode has a sidewall, a first end and a second end, the first end being connected to a second source contact region of the second semiconductor layer, and the first bit line being connected to the second end.

[0031] An embodiment of the present disclosure provides a method for manufacturing a 3D memory, the 3D memory comprising: a plurality of layers of memory units stacked along a direction perpendicular to a substrate, a first word line, and a second word line; the memory units of each layer comprise a read transistor and a write transistor; the read transistor comprises a first gate electrode, a first semiconductor layer, a first source electrode, and a first drain electrode; and the write transistor comprises a second gate electrode, a second semiconductor layer, a second source electrode, and a second drain electrode; the manufacturing method includes: Providing a substrate; Sequentially depositing and patterning an insulating thin film and a metal thin film alternately on the substrate to form a stack structure including alternating insulating layers and metal layers, the metal layers including a first sub-portion and a second sub-portion to be connected, and a first drain electrode of the read transistor; etching the stack structure to form a via through the stack structure, etching the first sub-portion to form a first passage, and etching the second sub-portion to form a second passage, the first passage, the second passage, and the via penetrating; depositing a semiconductor thin film, a gate insulating thin film, and a metal thin film in sequence on a sidewall of a passage consisting of the first passage, the second passage, and the via, completely filling the passage; and etching the gate insulating thin film and the metal thin film in the via to form a first semiconductor layer located in the first passage, a second source electrode, a first gate electrode, and a second drain electrode located in the second passage; depositing a semiconductor thin film on a sidewall of the via to form a second semiconductor layer of the write transistor, the second semiconductor layer including a second source contact region and a second drain contact region spaced apart, the second source electrode contacting the second source contact region, the second drain electrode contacting the second drain contact region, and a channel between the second source contact region and the second drain contact region being a horizontal channel; depositing a thin metal film in the via to completely fill the via to form the second word line, and a second gate electrode of the write transistor in a different layer is part of the second word line; patterning to form the first word line extending along a direction perpendicular to the substrate, wherein a first source electrode of the read transistor in a different layer is part of the first word line.

[0032] An embodiment of the present disclosure provides an electronic device, comprising the storage unit according to any of the above embodiments.

[0033] Other features and advantages of the present disclosure will be set forth in the following description, and in part will be obvious from the description, or may be learned by the practice of the present disclosure. The objects and advantages of the present disclosure may be realized and obtained by the structure particularly pointed out in the description and drawings.

[0034] Other aspects will be understood after reading and understanding the drawings and detailed description. [Brief explanation of the drawings]

[0035] The drawings are intended to provide a further understanding of the technical solution of the present disclosure, are a part of the specification, and are intended to interpret the technical solution of the present disclosure together with the embodiments of the present disclosure, but are not intended to limit the technical solution. [Figure 1A] FIG. 2 is a schematic diagram of a storage unit according to one example embodiment. [Figure 1B] 1B is a cross-sectional view of the storage unit shown in FIG. 1A in the direction AA. [Figure 2] FIG. 2 is an equivalent circuit diagram of a storage unit according to one exemplary embodiment. [Figure 3] FIG. 10 is a schematic diagram after forming a third insulating thin film according to one example embodiment. [Figure 4] FIG. 10 is a schematic diagram after groove formation according to one exemplary embodiment. [Figure 5] FIG. 10 is a schematic diagram of the trench after filling according to one exemplary embodiment. [Figure 6] FIG. 10 is a schematic diagram after via formation according to one exemplary embodiment. [Figure 7A] FIG. 10 is a schematic diagram after passage formation according to one exemplary embodiment. [Figure 7B] FIG. 2 is a schematic diagram of a first metal layer according to one example embodiment. [Figure 8A] FIG. 2 is a schematic diagram after forming a first semiconductor layer and a first gate insulating layer according to one example embodiment. [Figure 8B] FIG. 8B is a schematic diagram of a local portion of FIG. 8A. [Figure 8C] FIG. 8C is a cross-sectional view taken along the direction BB in FIG. 8B. [Figure 9A] FIG. 2 is a schematic diagram after forming a second metal layer according to one exemplary embodiment. [Figure 9B] FIG. 9B is a schematic diagram of a local portion of FIG. 9A. [Figure 9C] FIG. 9C is a cross-sectional view taken along the direction BB in FIG. 9B. [Figure 10A] FIG. 10 is a schematic diagram after removal of the second metal layer in the via according to one example embodiment. [Figure 10B] FIG. 10B is a schematic diagram of a local portion of FIG. 10A. [Figure 10C]10C is a cross-sectional view taken along the direction BB in FIG. 10B. [Figure 11A] FIG. 2 is a schematic diagram after gate electrode formation according to one example embodiment. [Figure 11B] FIG. 11B is a schematic diagram of a local portion of FIG. 11A. [Figure 11C] FIG. 11C is a cross-sectional view taken along the direction BB in FIG. 11B. [Figure 12] FIG. 4 is a schematic diagram of a slot 44 after formation according to one exemplary embodiment. [Figure 13A] FIG. 3 is a schematic diagram after formation of a fourth metal layer 34' according to one example embodiment. [Figure 13B] FIG. 13B is a schematic diagram of a local portion of FIG. 13A. [Figure 14A] FIG. 10 is a schematic diagram after slotting according to one example embodiment. [Figure 14B] FIG. 14B is a schematic diagram of a local portion of FIG. 14A. [Figure 14C] FIG. 14C is a cross-sectional view taken along the direction BB in FIG. 14B. [Figure 15] FIG. 10 is a schematic diagram after forming a fifth insulating layer according to one example embodiment. [Figure 16] 1 is a cross-sectional schematic diagram of a storage unit according to one example embodiment. [Figure 17A] 1 is a schematic cross-sectional view of a 3D memory according to one example embodiment taken along a direction parallel to the substrate. FIG. [Figure 17B] 1 is a schematic cross-sectional view of a 3D memory according to an example embodiment taken along a direction perpendicular to the substrate. FIG. [Figure 18] 1 is a flow chart of a method for manufacturing a 3D memory according to one example embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0036] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. When there is no conflict, the embodiments and features of the embodiments of the present disclosure can be combined with each other.

[0037] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs.

[0038] Therefore, the embodiments of the present disclosure are not limited to the above sizes, and the shapes and sizes of the components in the drawings do not reflect actual proportions. In addition, the drawings are schematic illustrations of ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0039] The use of ordinal numbers such as "first," "second," and "third" in this disclosure is intended to avoid confusion of elements and does not denote any order, quantity, or importance.

[0040] In this disclosure, for convenience, the positions of components are described with reference to the drawings using terms indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer." However, this is for the purpose of explaining and simplifying the present specification, and is not intended to indicate or suggest that the described devices or elements have a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit the present disclosure. The positional relationships of components are appropriately changed depending on the direction in which each component is described. Therefore, the terms described in the disclosure are not limited and may be appropriately changed in some cases.

[0041] In the present disclosure, unless otherwise clearly specified and limited, the terms "attach," "couple," and "connect" should be understood broadly. For example, they may be fixedly connected, detachably connected, or integrally connected. They may be mechanically connected or electrically connected. They may be directly connected, indirectly connected via a linker, or internally connected between two elements. Those skilled in the art can understand the meaning of the above terms in the present disclosure according to the specific circumstances.

[0042] In this disclosure, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode. In this disclosure, a channel region refers to a region through which current mainly flows.

[0043] In the present disclosure, an electrode may be a source electrode or a drain electrode, and one of the two electrodes of the same transistor is a source electrode and the other is a drain electrode.

[0044] In this disclosure, "electrical connection" includes cases where components are connected via an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected components. Examples of the "element having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0045] In this disclosure, "parallel" refers to nearly parallel or almost parallel, and for example, refers to a state in which the angle formed by two straight lines is between -10° and 10°, and thus includes a state in which the angle is between -5° and 5°. "Perpendicular" refers to nearly perpendicular, and for example, refers to a state in which the angle formed by two straight lines is between 80° and 100°, and therefore includes a state in which the angle is between 85° and 95°.

[0046] In the embodiments of the present disclosure, "A and B are an integrated structure" may refer to the absence of a clear dividing interface, such as a clear fault or gap, in the microstructure. Generally, forming a connected film layer by patterning in one film layer is an integrated structure. For example, A and B are formed into a single film layer using the same material, and the connected structures are simultaneously formed through the same patterning process.

[0047] In this embodiment, a novel structure of 2T0C memory unit is provided, which contributes to the design of high density memory units in space and industrialization in process, and provides a 3D memory.

[0048] FIG. 1A is a three-dimensional structural schematic diagram of a memory unit according to an exemplary embodiment, in which a word line and a bit line are both included. FIG. 1B is a cross-sectional view of the memory unit shown in FIG. 1A along the AA direction. As shown in FIG. 1A, this embodiment provides a memory unit, which may include a first transistor and a second transistor disposed on a substrate 1. The first transistor may include a first gate electrode 11, a first semiconductor layer 6, a first electrode 33, and a second electrode 34 disposed on the substrate 1. The second transistor may include a third electrode 51 and a fourth electrode 52 disposed on the substrate 1, a second gate electrode 12 extending along a first direction Z (a direction perpendicular to the substrate 1), and a second semiconductor layer 9 surrounding a sidewall of the second gate electrode 12. The first gate electrode 11 is connected to the second semiconductor layer 9. The second semiconductor layer 9 includes a second source contact region 91 and a second drain contact region 92 spaced apart, the third electrode 51 contacts the second source contact region 91, the fourth electrode 52 contacts the second drain contact region 92, and a channel between the second source contact region 91 and the second drain contact region 92 is a horizontal channel.

[0049] According to the novel 2T0C design proposal of the present application, the gate electrode of the second transistor has a vertical structure and the channel is a horizontal channel, which is not stacked on the first transistor, which can reduce the size of the storage unit in the direction perpendicular to the substrate and contribute to the fabrication of a 3D stack of 2T0C storage units with a compact structure, simplifying the process and reducing costs. Not stacked may also be understood as being distributed at intervals on the substrate, for example, being distributed at intervals in the direction parallel to the substrate.

[0050] According to the solution of this embodiment, the second semiconductor layer 9 of the second transistor surrounds the second gate electrode 12, and due to the provision of the source contact region 91 and the drain contact region 92 in the second semiconductor layer 9, the channel direction between the third electrode 51 and the fourth electrode 52 of the second transistor generally extends along a direction parallel to the substrate 1. For example, in one embodiment, there is an overlap between the third electrode 51 and the fourth electrode 52 when orthogonally projected parallel to the first direction. The memory structural design is novel, thereby achieving a compact structure between the first and second transistors. Furthermore, when fabricating a 3D stacked memory unit, the gate electrodes of the second transistors in each stack are connected as word lines, and the vertically extending word lines simplify the 2T0C structural process and save space.

[0051] The horizontal channel described in the present embodiment may be understood as a type of non-vertical channel, and may be an embodiment in which the longitudinal direction of the channel or the direction of carrier propagation is in a plane parallel to the substrate.

[0052] In some embodiments, the horizontal channel may be a planar channel rather than a vertical channel, where the carriers in the channel extend in a direction generally parallel to the substrate rather than perpendicular to the substrate.

[0053] The channel extending in the plane may be a straight channel, a ring-shaped channel, or an arc-shaped channel, depending on the shape of the semiconductor layer between the source electrode and the drain electrode.

[0054] In some embodiments, the channels of the second transistor and the first transistor may be horizontal channels as described above.

[0055] The second transistor of the present application has a gate electrode extending along the vertical direction and a horizontal channel, so that when fabricating a vertically stacked 3D structure, a via extending along the vertical direction is formed in a single step, a channel film layer of each memory unit is formed in a single step on the sidewall of the via, a gate electrode insulating layer of each memory unit is formed in a single step, and then a gate electrode or word line is filled in the via, and different regions of the word line are used as gate electrodes of transistors in different layers.

[0056] The first transistor has a first gate electrode 11 extending horizontally and a horizontal channel, which isolates adjacent first transistors of a plurality of transistors stacked vertically, realizing a compact storage unit consisting of the first and second transistors and effectively reducing the size of the device.

[0057] The parallelism between the channel and the substrate 1 may be approximately parallel, and in practical applications, this is determined by the relative positions between the effective source and drain electrodes. For example, in a longitudinal cross section of the source and drain electrodes, the outer contour of at least one of the upper and lower surfaces of the electrodes lies on a plane, and the plane is approximately parallel to the main surface of the substrate.

[0058] In one exemplary embodiment, the second semiconductor layer 9 extends on the sidewalls of the second gate electrode 12 to form a ring-shaped semiconductor layer extending along a direction perpendicular to the substrate 1. In one exemplary embodiment, for one transistor, the second semiconductor layer 9 surrounds each region of the sidewalls of the gate electrode. Exemplarily, the second semiconductor layer 9 is ring-shaped, and in the cross section at each position of the second gate electrode 12, the second semiconductor layer 9 is ring-shaped, and the size of the ring matches the outer contour shape of the cross section of the second gate electrode 12. Alternatively, the second semiconductor layer 9 may be partially surrounding. For example, there may be gaps in the semiconductor layer 9 in the direction perpendicular to the substrate 1. In one exemplary embodiment, the first direction Z may intersect with the substrate 1. In this specification, "intersecting with the substrate 1" refers to intersecting with the upper surface of the substrate 1 (i.e., the surface on which the first transistor and the second transistor are disposed), "parallel to the substrate 1" refers to being parallel to the upper surface of the substrate 1, and "perpendicular to the substrate 1" refers to being perpendicular to the upper surface of the substrate 1. In this case, multiple memory units may be stacked vertically. However, the embodiments of the present disclosure are not limited thereto, and the first direction Z may be parallel to the substrate 1. Although the subsequent embodiments will be described as an example in which the first direction Z intersects with the substrate 1, the following description can be applied to a solution in which the first direction Z is parallel to the substrate 1, and perpendicular to the substrate 1 can be replaced with parallel to the first direction Z, and parallel to the substrate 1 can be replaced with perpendicular to the first direction Z.

[0059] In one exemplary embodiment, the second transistor may further include a second gate insulating layer 10 disposed between the second gate electrode 12 and the second semiconductor layer 9 and surrounding a sidewall of the second gate electrode 12, and the second semiconductor layer 9 is isolated from the second gate electrode 12 via the second gate insulating layer 10. The third electrode 51 and the fourth electrode 52 are insulated from the second gate electrode 12 via the second gate insulating layer 10.

[0060] In one exemplary embodiment, in a plane perpendicular to the substrate 1, there may be an overlapping portion between the orthogonal projection of the first gate electrode 11 and the orthogonal projection of the third electrode 51.

[0061] In one exemplary embodiment, in a plane perpendicular to the substrate 1, there may be an overlapping portion between the orthogonal projection of the first gate electrode 11 and the orthogonal projection of the third electrode 51, and there may be an overlapping portion between the orthogonal projection of the third electrode 51 and the orthogonal projection of the fourth electrode 52, and the first gate electrode 11 of the first transistor is connected to the third electrode 51 of the second transistor.

[0062] In one exemplary embodiment, the first gate electrode 11 and the third electrode 51 may be an integrated structure, i.e., the first gate electrode 11 and the third electrode 51 are formed simultaneously using the same material and the same manufacturing process. However, embodiments of the present disclosure are not limited thereto, and the first gate electrode 11 and the third electrode 51 may be a non-integrated structure, or the first gate electrode 11 and the third electrode 51 may be separate electrodes.

[0063] Illustratively, the first gate electrode 11 and the third electrode 51 are one and the same electrode extending along the same direction, and the electrodes are referred to as the first gate electrode 11 and the third electrode 51. For example, the first gate electrode 11 extends in a direction parallel to the substrate 1, and an end portion thereof extends to the source contact region of the second semiconductor layer and is connected to the source contact region.

[0064] In one exemplary embodiment, in a plane perpendicular to the substrate 1, there may be an overlap between the orthogonal projection of the first electrode 33 and the orthogonal projection of the first gate electrode 11.

[0065] In one exemplary embodiment, the second drain contact region 92 of the second semiconductor layer 9 and the second source contact region 91 of the second semiconductor layer 9 are located on the sidewalls of the second semiconductor layer 9 and are opposite and spaced apart.

[0066] In one exemplary embodiment, the first transistor may further include a first gate insulating layer 7 surrounding the first gate electrode 11 and a first semiconductor layer 6 surrounding the first gate insulating layer 7. The first electrode 33 is connected to the first semiconductor layer 6. The first semiconductor layer 6 forms an accommodating cavity, the first gate electrode 11 is disposed in the accommodating cavity, and the first gate insulating layer 7 separates the first semiconductor layer 6 and the first gate electrode 11.

[0067] The accommodating cavity formed by the first semiconductor layer 6 may be a cavity with only one opening, or may be a cavity with two openings, and the cross section of the cavity is annular.

[0068] In one exemplary embodiment, the second electrode 34 surrounds and is connected to the first semiconductor layer 6, and in a plane perpendicular to the substrate 1, the cross section of the second electrode 34 has a ring-shaped opening, and the first semiconductor layer 6 is located within the opening of the second electrode 34.

[0069] In one exemplary embodiment, the first electrode 33 may be located on the side of the second electrode 34 away from the second gate electrode 12, and may be located on the side of the first gate electrode 11 away from the second gate electrode 12.

[0070] In one exemplary embodiment, the first semiconductor layer 6 may include a sidewall and two ends, and the first semiconductor layer 6 includes a first source contact region 61 and a first drain contact region 62, the first source contact region 61 being located on the sidewall of the first semiconductor layer 6 and surrounding the first semiconductor layer 6, and the first drain contact region 62 being located on the sidewall of the first semiconductor layer 6 and surrounding the first semiconductor layer 6, or being located at the end of the two ends that is away from the second gate electrode 12.

[0071] In one exemplary embodiment, in a cross section perpendicular to the substrate 1, the first electrode 33, the second electrode 34, and the third electrode 51 may be located on a first side of the second gate electrode 12, and the fourth electrode 52 may be located on a second side of the second gate electrode 12, and the first side and the second side are opposite each other.

[0072] In one exemplary embodiment, the first electrodes 33 may extend along a third direction Y.

[0073] In one exemplary embodiment, the length of the second electrodes 34 along the third direction Y may be smaller than the length of the first electrodes 33 along the third direction Y. In this embodiment, when forming a memory unit array, the second electrodes 34 of different memory units may be separated. However, the embodiment of the present disclosure is not limited thereto, and the length of the second electrodes 34 along the third direction Y may be equal to or greater than the length of the first electrodes 33 along the third direction Y.

[0074] In one exemplary embodiment, the second electrode 34 may extend along a first direction Z.

[0075] In one exemplary embodiment, in a plane perpendicular to the substrate 1, there may be an overlap between the orthogonal projection of the first electrode 33 and the orthogonal projection of the first gate electrode 11.

[0076] In one exemplary embodiment, in a plane parallel to the substrate 1, there may be no overlap between the orthogonal projection of the first electrode 33 and the orthogonal projection of the second electrode 34, and there may be no overlap between the orthogonal projection of the third electrode 51 and the orthogonal projection of the fourth electrode 52.

[0077] In one exemplary embodiment, a first distance between the surface of the third electrode 51 closer to the substrate 1 and the substrate 1 along a direction perpendicular to the substrate 1 may be the same as a second distance between the surface of the fourth electrode 52 closer to the substrate 1 and the substrate 1. However, embodiments of the present disclosure are not limited thereto, and the first distance and the second distance may be different.

[0078] In one exemplary embodiment, the first thickness of the third electrode 51 may be the same as the second thickness of the fourth electrode 52 along the direction perpendicular to the substrate 1. However, embodiments of the present disclosure are not limited thereto, and the first thickness and the second thickness may be different.

[0079] In one exemplary embodiment, the distance between the surface of the third electrode 51 closest to the substrate 1 and the substrate 1 may be equal to the distance between the surface of the fourth electrode 52 closest to the substrate 1 and the substrate 1, and the distance between the surface of the third electrode 51 away from the substrate 1 and the substrate 1 may be equal to the distance between the surface of the fourth electrode 52 away from the substrate 1 and the substrate 1.

[0080] In one exemplary embodiment, the film layers of the third electrode 51 and the fourth electrode 52 may be different regions of the same conductive film layer and may be spaced apart, and the same conductive film layer is approximately parallel to the substrate 1.

[0081] In one exemplary embodiment, in a plane parallel to the substrate 1, the orthogonal projection of the second gate electrode 12 may be located outside the orthogonal projection of the third electrode 51, and the orthogonal projection of the second gate electrode 12 may be located outside the orthogonal projection of the fourth electrode 52.

[0082] In one exemplary embodiment, the first direction Z may be perpendicular to the substrate 1 .

[0083] 1B , in a cross section perpendicular to the substrate 1, the third electrode 51 is located on a first side of the second gate electrode 12, and the fourth electrode 52 is located on a second side of the second gate electrode 12, and the first side and the second side are opposite each other. However, embodiments of the present disclosure are not limited thereto, and the third electrode 51 and the fourth electrode 52 may be located in other positions.

[0084] In one exemplary embodiment, the third electrode 51 may extend along a second direction X, and the fourth electrode 52 may extend along a third direction Y, the second direction X may be parallel to the substrate 1, the third direction Y may be parallel to the substrate 1, and the second direction X and the third direction Y may intersect. However, embodiments of the present disclosure are not limited thereto, and the third electrode 51 and the fourth electrode 52 may have other shapes.

[0085] In one exemplary embodiment, the second direction X and the third direction Y may be perpendicular, but embodiments of the present disclosure are not limited thereto and other angles may be formed between the second direction X and the third direction Y.

[0086] In one exemplary embodiment, the cross section of the first electrode 33 in the direction perpendicular to the substrate 1 may be rectangular, but the embodiments of the present disclosure are not limited thereto, and the cross section of the first electrode 33 may be other shapes, for example, circular, hexagonal, etc.

[0087] In one exemplary embodiment, the cross sections of the third electrode 51 and the fourth electrode 52 in the direction perpendicular to the substrate 1 may be rectangular, but the embodiments of the present disclosure are not limited thereto, and the cross sections of the third electrode 51 and the fourth electrode 52 may be other shapes, for example, circular, hexagonal, etc.

[0088] In one exemplary embodiment, the third electrode 51 and the fourth electrode 52 may be connected to positions other than those shown in Figure 1A. For example, the third electrode 51 is connected to a first side of the ring-shaped pillar made of the second semiconductor layer 9, and the fourth electrode 52 is connected to a second side of the ring-shaped pillar made of the second semiconductor layer 9, and the first side and the second side are adjacent to each other.

[0089] In one exemplary embodiment, the third electrode 51 and the fourth electrode 52 may be formed simultaneously in a single manufacturing process, but the embodiments of the present disclosure are not limited thereto and may be manufactured by different processes.

[0090] In one exemplary embodiment, the distance between the surface of the first electrode 33 closer to the substrate 1 and the substrate 1 may be smaller than the distance between the surface of the third electrode 51 closer to the substrate 1 and the substrate 1, and the distance between the surface of the first electrode 33 away from the substrate 1 and the substrate 1 may be larger than the distance between the surface of the third electrode 51 away from the substrate 1 and the substrate 1. Along a direction perpendicular to the substrate 1, the thickness of the first electrode 33 may be larger than the thickness of the third electrode 51.

[0091] In one exemplary embodiment, the distance between the surface of the second electrode 34 facing away from the substrate 1 and the substrate 1 may be the same as the distance between the surface of the second gate electrode 12 facing away from the substrate 1 and the substrate 1.

[0092] 1B, the first semiconductor layer 6 and the second semiconductor layer 9 may or may not be physically connected. In FIG. 1B, the edge of the first semiconductor layer 6 contacts the sidewall of the second semiconductor layer 9. However, in some embodiments, if isolation is required, the edge of the first semiconductor layer 6 does not contact the sidewall of the second semiconductor layer 9, but can be isolated by an insulating layer between them when fabricating the membrane layers.

[0093] In a 2T0C structure, the first transistor is a read transistor and the second transistor is a write transistor. Generally, the read transistor needs to be turned on and the write transistor needs to be turned off. In this case, contact between the edge of the first semiconductor layer 6 and the sidewall of the second semiconductor layer 9 does not significantly affect the operation of the first transistor.

[0094] In some embodiments, the edges of the first semiconductor layer 6 and the sidewalls of the second semiconductor layer 9 can be isolated in a spatial structure to avoid other effects due to contact between them.

[0095] 1A , the length of the second semiconductor layer 9 along the direction perpendicular to the substrate 1 may be equal to the length of the second gate electrode 12. However, embodiments of the present disclosure are not limited thereto, and in one exemplary embodiment, the length of the second semiconductor layer 9 along the direction perpendicular to the substrate 1 may be equal to or less than the length of the second gate electrode 12 and equal to or less than the length of the second gate insulating layer 10, and may be equal to or greater than the length of the third electrode 51 and equal to or greater than the length of the fourth electrode 52. According to the solution of this embodiment, the channel length can be shortened, thereby reducing leakage current.

[0096] In one exemplary embodiment, along a direction perpendicular to the substrate 1, the length of the second semiconductor layer 9 may be equal to the length of the second gate insulating layer 10, and the length of the second gate insulating layer 10 may be equal to the length of the second gate electrode 12.

[0097] In one exemplary embodiment, along a direction perpendicular to the substrate 1, the length of the second gate insulating layer 10 may be smaller than the length of the second gate electrode 12 and may be greater than or equal to the length of the second semiconductor layer 9.

[0098] In one exemplary embodiment, the first semiconductor layer 6 and the second semiconductor layer 9 may be metal oxide semiconductor layers or silicon-containing semiconductor layers.

[0099] In one exemplary embodiment, the metal in the metal oxide semiconductor layer may include, but is not limited to, at least one of indium, tin, zinc, aluminum, and gallium.

[0100] In one exemplary embodiment, the metal oxide semiconductor layer may include at least one of indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, and tin aluminum zinc oxide, but is not limited thereto.

[0101] As shown in FIG. 1B , in this embodiment, the size of the channel between the third electrode 51 and the fourth electrode 52 can be controlled by the length of the overlapping portion between the orthogonal projection of the third electrode 51 and the orthogonal projection of the fourth electrode 52 in a plane perpendicular to the substrate 1. In FIG. 1B , the length of the overlapping portion between the orthogonal projection of the third electrode 51 and the orthogonal projection of the fourth electrode 52 is d. The channel size can be controlled by controlling the thickness of the third electrode 51 and the fourth electrode 52 in a direction perpendicular to the substrate 1. Compared to a transistor in which the source electrode surrounds the gate electrode, a transistor in which the drain electrode surrounds the gate electrode controls the channel size by changing the size of the via where the gate electrode is located (which requires a mask change) or by increasing the distance between the source electrode and the drain electrode (which increases the volume of the transistor). This embodiment allows for more convenient control of the channel size, requires fewer process changes, and has a smaller impact on the transistor size.

[0102] As shown in FIGS. 1A and 1B, an embodiment of the present disclosure provides a memory unit, comprising a read transistor and a write transistor disposed on a substrate; The read transistor may be a first transistor, and the read transistor includes a first gate electrode 11, a first semiconductor layer 6, a first source electrode (which may be a second electrode 34), and a first drain electrode (which may be a first electrode 33), and the first semiconductor layer 6 surrounds the first gate electrode 11; The write transistor may be a second transistor, and the write transistor includes a second gate electrode 12, a second semiconductor layer 9, a second source electrode (which may be a third electrode 51), and a second drain electrode (which may be a fourth electrode 52), wherein the second semiconductor layer 9 surrounds the second gate electrode 12, and the second source electrode of the write transistor is connected to the first gate electrode 11 of the read transistor; The channel of the second semiconductor layer 9 of the write transistor is a horizontal channel.

[0103] In one exemplary embodiment, the second gate electrode 12 extends along a direction perpendicular to the substrate 1 and has a sidewall, the second semiconductor layer 9 surrounds the sidewall, and the second semiconductor layer 9 includes a second source contact region 91; The first gate electrode 11 extends along a direction parallel to the substrate 1 and has a sidewall and two ends, the first semiconductor layer 6 surrounds at least the sidewall, and one of the two ends extends to the second source contact region 91 of the second semiconductor layer 9 and contacts the second semiconductor layer 9.

[0104] In one exemplary embodiment, a sidewall of the second semiconductor layer 9 further includes a second drain contact region 92, the second source contact region 91 and the second drain contact region 92 are located in different regions of the sidewall of the second semiconductor layer 9, and there is an overlapping region in the orthogonal projection of the second source contact region 91 and the second drain contact region 92 in a plane perpendicular to the substrate 1, so that a channel between the second source contact region 91 and the second drain contact region 92 is parallel to the substrate 1; The sidewalls of the first semiconductor layer 6 may have a first source contact region 61 and a first drain contact region 62, and a channel between the first source contact region 61 and the first drain contact region 62 is parallel to the substrate.

[0105] 2 is an equivalent circuit schematic diagram of a memory unit according to an embodiment of the present disclosure. As shown in FIG. 2, in one exemplary embodiment, the first transistor may be a read transistor and the second transistor may be a write transistor. The first electrode 33 may be connected to a read bit line, and the second electrode 34 may be connected to a read word line. The second gate electrode 12 may be connected to a write word line, and the fourth electrode 52 may be connected to a write bit line.

[0106] When a voltage is applied to the write word line (i.e., the second gate electrode 12), the channel turns on, connecting the third electrode 51 and the fourth electrode 52. The read and write processes are as follows: 1) When writing a "1," a read voltage is applied to the write bit line (i.e., the fourth electrode 52), injecting charge into the memory node (the memory node between the first gate electrode 11 and the third electrode 51, indicated by the arrow in FIG. 2), and the first transistor turns on. When reading a "1," a read voltage is applied to the read word line (i.e., the second electrode 34) in the read transistor, storing a certain charge in the memory node. This allows current to pass between the read bit line and the read word line, or between the first electrode 33 and the second electrode 34 in the drawing. This is then magnified and identified by the peripheral circuitry, completing the "1" read process. (2) When writing "0", the write bit line (i.e., the fourth electrode 52) extracts charge due to a voltage lower than the threshold voltage, and the first transistor does not turn on. When reading "0", the read transistor applies a read voltage to the read word line (i.e., the second electrode 34). Since there is no charge on the storage node, no current or a small current passes between the read bit line (i.e., the first electrode 33) and the read word line (i.e., the second electrode 34), which is then amplified and identified by the peripheral circuit, completing the "0" read process.

[0107] The technical solution of this embodiment will be described below using the manufacturing process of the display substrate of this embodiment. The "patterning process" described in this embodiment includes processes such as film layer deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant technology. The "photolithography process" described in this embodiment includes film layer coating, mask exposure, and development, and is a mature manufacturing process in the relevant technology. The deposition may be a known process such as sputtering, evaporation, or chemical vapor deposition, the coating may be a known coating process, and the etching may be a known method, but is not limited thereto. In this description, a "thin film" refers to a thin film layer fabricated by a deposition or coating process based on a certain material. If the "thin film" does not require a patterning process or photolithography process in the entire manufacturing process, the "thin film" can also be referred to as a "layer." If the "thin film" requires a patterning process or photolithography process in the entire manufacturing process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. After the patterning or photolithography process, a "layer" contains at least one "pattern."

[0108] In one exemplary embodiment, the manufacturing process of the storage unit may include the following steps.

[0109] 1) As shown in FIG. 3, a first insulating thin film, a first metal thin film, and a second insulating thin film are sequentially deposited on a substrate 1 to form a first insulating layer 2, a first metal layer 3, and a second insulating layer 4.

[0110] In one exemplary embodiment, the substrate 1 may be made of glass, silicon, or a flexible material. The flexible material may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. In an exemplary embodiment, the substrate 1 may have a single-layer structure or a multi-layer laminate structure. The laminate structure substrate may include a flexible material / inorganic material / flexible material, and the inorganic material may be one or more of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). The substrate 1 may be a semiconductor substrate, and may include, for example, at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0111] In one exemplary embodiment, the first insulating thin film and the second insulating thin film may be low-K medium layers, i.e., medium layers with a dielectric constant K<3.9. For example, they may be one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC). The first insulating thin film and the second insulating thin film may be made of the same material or different materials.

[0112] In one exemplary embodiment, the first metal thin film may include, but is not limited to, at least one of tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta).

[0113] 4 , the first insulating layer 2, the first metal layer 3, and the second insulating layer 4 are patterned by a patterning process to form a first groove P1 and a second groove P2. The first groove P1 penetrates the first insulating layer 2, the first metal layer 3, and the second insulating layer 4, and the second groove P2 penetrates the first insulating layer 2, the first metal layer 3, and the second insulating layer 4. The first metal layer 3 may include a first sub-portion 31 extending along the second direction X, a second sub-portion 32 extending along the third direction Y, and a first electrode 33 extending along the third direction Y, and the first sub-portion 31 connects the second sub-portion 32 and the first electrode 33.

[0114] In one exemplary embodiment, in a plane parallel to the substrate 1, the first insulating layer 2, the first metal layer 3 and the second insulating layer 4 may have an H-shaped cross section.

[0115] In one exemplary embodiment, the first groove P1 and the second groove P2 may have the same size and shape, but embodiments of the present disclosure are not limited thereto, and the first groove P1 and the second groove P2 may have different sizes and shapes.

[0116] In this embodiment, the pattern of the first metal layer 3 is merely an example, and other patterns may be used. For example, the current second sub-section 32 may be divided into two sections along the extension direction of the first sub-section 31, and only one of the sections may be reserved as the second sub-section 32.

[0117] 3) As shown in FIG. 5, a third insulating thin film is deposited on the substrate 1 on which the pattern has been formed to form a third insulating layer 5, and the third insulating layer 5 fills the first groove P1 and the second groove P2.

[0118] In one exemplary embodiment, the third insulating thin film may be a low-K medium layer, i.e., a medium layer with a dielectric constant K<3.9. For example, it may be one or more of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC). The third insulating thin film, the first insulating thin film, and the second insulating thin film may be made of the same material or different materials. The fourth insulating thin film is similar and will not be described again.

[0119] 6, in the substrate 1 on which the pattern is formed, a via 41 is formed penetrating the first insulating layer 2, the first metal layer 3, and the second insulating layer 4, and in a plane parallel to the substrate 1, an orthogonal projection of the via 41 and an orthogonal projection of the first sub-portion 31 may have an overlapping portion, and an orthogonal projection of the via 41 and an orthogonal projection of the second sub-portion 32 may have an overlapping portion. Although the cross section of the via 41 in the plane parallel to the substrate 1 shown in FIG. 6 is rectangular, the embodiment of the present disclosure is not limited thereto, and the cross section of the via 41 in the plane parallel to the substrate 1 may have another shape, such as a circle, a pentagon, a hexagon, etc.

[0120] 5) As shown in FIGS. 7A and 7B, the first sub-portion 31, the second sub-portion 32, and the connection portion between the first electrode 33 and the first sub-portion 31 in the first metal layer 3 are selectively etched, so that only the first electrode 33 remains in the first metal layer 3, and a third groove P3 is formed in the first electrode 33 toward the first sub-portion 31 (the first sub-portion 31 has already been etched). At this time, a first passage 42 consisting of the region where the selectively etched first sub-portion 31 is located, a second passage 43 consisting of the region where the second sub-portion 32 is located, and the via 41 are formed, and the first passage 42 and the via 41 penetrate each other, and the second passage 43 and the via 41 penetrate each other.

[0121] 6) As shown in Figures 8A, 8B, and 8C, a first semiconductor thin film and a first gate electrode oxide thin film are sequentially deposited on the sidewalls of the passages (i.e., via 41, first passage 42, and second passage 43) formed in step 5 to form a first semiconductor layer 6 and a first gate insulating layer 7. Figure 8C is a cross-sectional view along the B-B direction of Figure 8B, showing only the first semiconductor layer 6 and the first gate insulating layer 7. At this time, the first semiconductor layer 6 and the first gate insulating layer 7 serve as passage walls of the passages, and the first semiconductor layer 6 surrounds the first gate insulating layer 7.

[0122] In one exemplary embodiment, the first gate electrode oxide thin film may be a high-K medium material, which may include, but is not limited to, at least one of silicon oxide, aluminum oxide, and hafnium oxide.

[0123] In one exemplary embodiment, the first semiconductor thin film is a channel layer, which may be a silicon-containing film layer or a metal oxide semiconductor. The metal oxide semiconductor may comprise at least one of IGZO, indium tin oxide (ITO), and indium zinc oxide (IZO). When used as a semiconductor layer, IGZO has the advantages of low leakage current and short refresh time. The second semiconductor thin film is similar and will not be described again.

[0124] In one exemplary embodiment, the first semiconductor thin film and the first gate electrode oxide thin film can be deposited by atomic layer deposition (ALD).

[0125] 6) As shown in Figures 9A, 9B, and 9C, a second metal thin film is deposited in the passages (i.e., via 41, first passage 42, and second passage 43) to form a second metal layer 8, which completely fills the passages. Figure 9C is a cross-sectional view along the B-B direction of Figure 9B, showing only the first semiconductor layer 6, the first gate insulating layer 7, and the second metal layer 8. At this time, the first gate insulating layer 7 surrounds the second metal layer 8.

[0126] In one exemplary embodiment, the second metal thin film may include, but is not limited to, at least one of tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta), and the second metal thin film may be the same as or different from the first metal thin film.

[0127] 7) As shown in Figures 10A, 10B, and 10C, selectively photolithograph and etch the second metal layer 8 and the first gate insulating layer 7 in the via 41, while preserving the second metal layer 8 and the first gate insulating layer 7 in other locations in the via (the second metal layer 8 in the first via 42 and the second via 43 parallel to the substrate 1). Figure 10C is a cross-sectional view along the B-B direction in Figure 10B, showing only the first semiconductor layer 6, the first gate insulating layer 7, and the second metal layer 8. The second metal layer 8 located in the first via 42 is the third electrode 51 of the second transistor, and the second metal layer 8 located in the second via 43 is the fourth electrode 52 of the second transistor, and the third electrode 51 and the fourth electrode 52 are isolated from each other.

[0128] 11A, 11B, and 11C, a second semiconductor thin film, a second gate electrode oxide thin film, and a third metal thin film are sequentially deposited on the sidewalls of the via 41 obtained by the etching, to form a second semiconductor layer 9, a second gate insulating layer 10, and a second gate electrode 12, respectively, and the second gate insulating layer 10 surrounds the second gate electrode 12, the second semiconductor layer 9 surrounds the second gate insulating layer 10, and the second gate electrode 12 completely fills the area surrounded by the second gate insulating layer 10. Figure 11C is a cross-sectional view along the B-B direction in Figure 11B, and shows only the first semiconductor layer 6, the first gate insulating layer 7, the second semiconductor layer 9, the second gate insulating layer 10, the second metal layer 8 (third electrode 51, fourth electrode 52), and the second gate electrode 12.

[0129] In one exemplary embodiment, the second gate electrode oxide thin film may be a high-K medium material, which may include, but is not limited to, at least one of silicon oxide, aluminum oxide, and hafnium oxide. The materials of the second gate electrode oxide thin film and the first gate electrode oxide thin film may be the same or different.

[0130] In one exemplary embodiment, the second semiconductor thin film and the first semiconductor thin film may use the same material.

[0131] In one exemplary embodiment, the third metal thin film may include, but is not limited to, at least one of tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), and tantalum (Ta). The third metal thin film may be the same as or different from the first and second metal thin films. The fourth metal thin film is similar and will not be described again.

[0132] 12 is etched in the substrate 1 on which the pattern has been formed, but the first semiconductor layer 6 and the portion included in the first semiconductor layer 6 are not etched. The slot structure 44 penetrates each film layer in the substrate 1, and in a plane perpendicular to the substrate 1, the orthogonal projection of the slot structure 44 is located outside the orthogonal projection of the first electrode 33, the orthogonal projection of the via 41, and the orthogonal projection of the fourth electrode 52.

[0133] 10) As shown in FIGS. 13A and 13B, a fourth metal thin film is deposited in the slot structure 44 to form a fourth metal layer 34' filling the slot structure 44.

[0134] 11) As shown in Figure 14A, in the substrate 1 on which the pattern has been formed, a fourth groove P4 and a fifth groove P5 are formed through the fourth metal layer 34', and a second electrode 34 is formed. As shown in Figure 14B, similar to the first groove P1 and the second groove P2, the fourth groove P4 and the fifth groove P5 are respectively located on both sides of the fourth metal layer 34', and the length of the second electrode 34 along the third direction Y is shorter than the length of the first electrode 33 along the third direction Y, and the second electrode 34 surrounds the first semiconductor layer 6. Figure 14C is a cross-sectional view along the B-B direction of Figure 14B, and as can be seen from the drawing, the fabrication of the main structures of the first and second transistors is basically completed.

[0135] 12) As shown in FIG. 15, a fourth insulating thin film is deposited on the substrate 1 on which the pattern has been formed to form a fourth insulating layer 55, which fills the fourth groove P4 and the fifth groove P5.

[0136] In the memory unit manufactured by the above manufacturing process, the second passage 43 may include the first gate insulating layer 7 surrounding the fourth electrode 52 and the first semiconductor layer 6 surrounding the first gate insulating layer 7. However, the embodiment of the present disclosure is not limited thereto, and the second passage 43 may not include the first gate insulating layer 7 surrounding the fourth electrode 52 and the first semiconductor layer 6 surrounding the first gate insulating layer 7 (excluding the region intersecting with the via 41). That is, the first gate insulating layer 7 and the first semiconductor layer 6 may be removed from the second passage 43. For process convenience, the first gate insulating layer 7 and the first semiconductor layer 6 may be retained in the second passage 43.

[0137] In one exemplary embodiment, if only one storage unit is to be manufactured, steps 11) and 12) above may be omitted.

[0138] The above manufacturing process is merely an example, and the embodiments of the present disclosure are not limited thereto and may be manufactured in other ways. For example, a first metal thin film may be deposited and then patterned using a patterning process to form an H-shaped first metal layer 3. A second insulating thin film may then be deposited to form a second insulating layer 4, and the formation of the first groove P1 and the second groove P2, or the deposition of a third insulating thin film, may not be necessary.

[0139] FIG. 16 is a schematic cross-sectional view of a memory unit according to another illustrative embodiment. As shown in FIG. 16, in this embodiment, the memory unit includes a first transistor and a second transistor. The first transistor may include a first electrode 33, a second electrode 34, a first gate electrode 11, a first gate insulating layer 7 surrounding the first gate electrode 11, and a first semiconductor layer 6 surrounding the first gate insulating layer 7. The second transistor may include a third electrode 51, a fourth electrode 54, a second gate electrode 12, a second semiconductor layer 9 extending along a first direction Z, and a second gate insulating layer 10 isolating the second semiconductor layer 9 from the second gate electrode 12. In a direction perpendicular to the substrate 1, the thickness of the fourth electrode 52 may be greater than the thickness of the third electrode 51.

[0140] An embodiment of the present disclosure further provides an electronic device, comprising the storage unit according to any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, a portable power source, etc. The storage device may include, but is not limited to, a computer memory, etc.

[0141] 17A is a schematic plan view of a 3D memory according to an embodiment of the present disclosure, and FIG. 17B is a schematic cross-sectional view of the 3D memory according to an embodiment of the present disclosure. As shown in FIG. 17A and FIG. 17B, this embodiment provides a 3D memory, which may include multiple layers of memory units stacked along a direction perpendicular to a substrate 1, The storage unit of each layer may include a read transistor and a write transistor, the read transistor may be a first transistor and the write transistor may be a second transistor; the read transistor includes a first gate electrode 11, a first semiconductor layer 6, a first source electrode (which may be the second electrode 34), and a first drain electrode (which may be the first electrode 33), and the first gate electrode 11 may extend along a direction parallel to the substrate 1; the write transistor includes a second gate electrode 12, a second semiconductor layer 9, a second source electrode (which may be the third electrode 51), and a second drain electrode (which may be the fourth electrode 52), and the second gate electrode 12 may extend along a direction perpendicular to the substrate 1; The second source electrode of the write transistor is connected to the first gate electrode 11 of the read transistor, the first semiconductor layer 6 surrounds the first gate electrode 11, the second semiconductor layer 9 surrounds the second gate electrode 12, and the channel of the second semiconductor layer 9 of the write transistor is a horizontal channel.

[0142] In the 3D memory according to this embodiment, the second semiconductor layer of the write transistor surrounds the second gate electrode, and due to the provision of the source contact region and the drain contact region in the second semiconductor layer, the channel direction between the source electrode and the drain electrode generally extends in a direction parallel to the substrate, the second transistor and the first transistor are not stacked, and the structure between the first transistor and the second transistor is compact, which can reduce the size of the memory unit in the direction perpendicular to the substrate and contribute to the fabrication of a 3D stack of 2T0C memory units with a compact structure, simplifying the process and reducing costs.

[0143] In one exemplary embodiment, the read transistors and write transistors in the same layer are distributed in the substrate 1 at intervals along a direction parallel to the substrate 1 .

[0144] In one exemplary embodiment, the first gate electrode 11 of the read transistor and the second source electrode of the write transistor may be an integrated structure, but are not limited to this and may also be two separate electrodes.

[0145] In one exemplary embodiment, the first gate electrode 11 may extend along a second direction parallel to the substrate 1; The first semiconductor layer 6 may include a first source contact region 61 and a first drain contact region 62, and the second semiconductor layer 9 may include a second source contact region 91 and a second drain contact region 92; The memory unit of each layer may further include a first bit line 330 and a second bit line 520 extending along a third direction parallel to the substrate 1, the third direction intersecting with the second direction, the first bit line 330 being connected to a first drain contact region 62 of the first semiconductor layer 6, and the second bit line 520 being connected to a second drain contact region 92 of the second semiconductor layer 9; The memory units of each layer may further include a first word line 340 and a second word line 120 extending along a direction perpendicular to the substrate 1, The first word lines 340 are connected to the first source contact regions 61 of the first semiconductor layers 6 of the memory units in different layers, and the second word lines 120 are connected to the second gate electrodes 12 of the memory units in different layers. The second gate electrodes 12 of the memory units in different layers may be part of the second word lines 120.

[0146] According to the solution of this embodiment, the second gate electrodes of the write transistors of each stack are connected as word lines, and the word lines extending in the vertical direction simplify the structure process of 2T0C and save space.

[0147] In one exemplary embodiment, the first word line 340 surrounds the sidewalls of each first semiconductor layer 6 of the memory units of different layers and is connected to the first source contact region 61 on the sidewall of each first semiconductor layer 6.

[0148] In one exemplary embodiment, the first gate electrode 11 may have a sidewall, a first end and a second end, the first end being connected to a second source contact region 91 of the second semiconductor layer 9, and the first bit line 330 being connected to the second end.

[0149] In one exemplary embodiment, the second semiconductor layers 9 of the write transistors of different layers may be an integrated structure.

[0150] In one exemplary embodiment, write transistors in different layers may share one annular second semiconductor layer 9 extending along a direction perpendicular to the substrate 1 .

[0151] In one exemplary embodiment, the write transistor may further include a second gate insulating layer 10 surrounding the second gate electrode 12 , and the second semiconductor 9 surrounding the second gate insulating layer 10 .

[0152] In one exemplary embodiment, write transistors in different layers may share one annular second gate insulating layer 10 extending along a direction perpendicular to the substrate 1 .

[0153] In one exemplary embodiment, the projections of the first gate electrodes 11 of different layers on the substrate 1 may be located in the same region, the projections of the first source electrodes of different layers on the substrate 1 may be located in the same region, the projections of the first drain electrodes of different layers on the substrate 1 may be located in the same region, the projections of the second gate electrodes 12 of different layers on the substrate 1 may be located in the same region, the projections of the second source electrodes of different layers on the substrate 1 may be located in the same region, and the projections of the second drain electrodes of different layers on the substrate 1 may be located in the same region.

[0154] Regarding the structure of the read transistor and the write transistor in the above 3D memory, reference can be made to the structure of the first transistor and the second crystal in the above embodiments, and the description will not be repeated here.

[0155] As shown in FIG. 18 , an embodiment of the present disclosure provides a method for manufacturing a 3D memory, the 3D memory including multiple layers of memory units, first word lines, and second word lines stacked along a direction perpendicular to a substrate, the memory units of each layer including a read transistor and a write transistor, the read transistor including a first gate electrode, a first semiconductor layer, a first source electrode, and a first drain electrode, and the write transistor including a second gate electrode, a second semiconductor layer, a second source electrode, and a second drain electrode, and the manufacturing method may include the following steps 1801 to 1806:

[0156] In step 1801, a substrate is provided, and insulating thin films and metal thin films are alternately deposited and patterned on the substrate to form a stack structure including alternating insulating layers and metal layers, and the metal layers include a first sub-portion and a second sub-portion to be connected, and a first drain electrode of the read transistor.

[0157] In step 1802, the stack structure is etched to form a via through the stack structure, the first sub-portion is etched to form a first passage, and the second sub-portion is etched to form a second passage, the first passage, the second passage, and the via penetrating through.

[0158] In step 1803, a semiconductor thin film, a gate insulating thin film, and a metal thin film are sequentially deposited on the sidewalls of the passage consisting of the first passage, the second passage, and the via, completely filling the passage, and the gate insulating thin film and the metal thin film in the via are etched to form a first semiconductor layer located in the first passage, a second source electrode, a first gate electrode, and a second drain electrode located in the second passage.

[0159] Step 1804 deposits a semiconductor thin film on the sidewalls of the via to form a second semiconductor layer of the write transistor, the second semiconductor layer including spaced-apart second source and drain contact regions, the second source electrode contacting the second source contact region, the second drain electrode contacting the second drain contact region, and a channel between the second source and second drain contact regions being a horizontal channel.

[0160] Step 1805 deposits a thin metal film in the via to completely fill the via and form the second word line, and a second gate electrode of the write transistor in a different layer is part of the second word line.

[0161] Step 1806 patterns to form the first word line extending along a direction perpendicular to the substrate, and the first source electrode of the read transistor in a different layer is part of the first word line.

[0162] In the 3D memory fabricated by the 3D memory fabrication method according to the embodiment of the present disclosure, the gate electrode of the second transistor has a vertical structure and the channel is a horizontal channel that is not stacked on the first transistor, which reduces the size of the memory unit in the direction perpendicular to the substrate and contributes to the fabrication of a compact 3D stack of 2T0C memory units, simplifying the process and reducing costs. Furthermore, in the 3D memory according to this embodiment, the channel size can be changed by adjusting the thickness of the source electrode or drain electrode, which is a simple process and has little impact on the size of the transistor. The fabrication method according to the embodiment of the present disclosure can be implemented using currently mature manufacturing equipment, requires only small changes to conventional processes, is highly compatible with conventional manufacturing processes, is simple to implement, easy to implement, has high production efficiency, low production costs, and a high yield rate.

[0163] The above are the embodiments disclosed in the present disclosure, but the above contents are merely embodiments used to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Those skilled in the art can make any modifications and changes to the embodiments and details without departing from the spirit and scope disclosed in the present disclosure, and the patent protection scope of the present disclosure is subject to the scope of the attached claims.

Claims

1. a storage unit comprising a first transistor and a second transistor disposed on a substrate; the first transistor includes a first gate electrode, a first electrode, a second electrode, and a first semiconductor layer disposed on the substrate, the first gate electrode extending along a direction parallel to the substrate; the second transistor includes a third electrode and a fourth electrode disposed on the substrate, a second gate electrode extending along a direction perpendicular to the substrate, and a second semiconductor layer surrounding sidewalls of the second gate electrode, the first gate electrode being connected to the second semiconductor layer, the second semiconductor layer including a second source contact region and a second drain contact region disposed at a distance from each other, the third electrode contacting the second source contact region of the second semiconductor layer, the fourth electrode contacting the second drain contact region of the second semiconductor layer, and a channel between the second source contact region and the second drain contact region being a horizontal channel;

2. 2. The memory unit according to claim 1, wherein the first transistor and the second transistor are distributed on the substrate at intervals along a direction parallel to the substrate.

3. 2. The memory unit of claim 1, wherein in a plane perpendicular to the substrate, there is an overlapping portion between the orthogonal projection of the first gate electrode and the orthogonal projection of the third electrode, there is an overlapping portion between the orthogonal projection of the third electrode and the orthogonal projection of the fourth electrode, and the first gate electrode of the first transistor and the third electrode of the second transistor are an integrated structure.

4. The storage unit of claim 1 , wherein the first gate electrode is connected to a second source contact region of the second semiconductor layer.

5. The storage unit according to claim 1 , wherein an overlapping portion exists between the orthogonal projection of the first electrode and the orthogonal projection of the first gate electrode in a plane perpendicular to the substrate.

6. The memory unit of claim 4 , wherein the second drain contact region of the second semiconductor layer and the second source contact region of the second semiconductor layer are located on sidewalls of the second semiconductor layer and are opposite and spaced apart.

7. 7. The memory unit of claim 6, wherein the second electrode surrounds the first semiconductor layer and is connected to the first semiconductor layer, and in a plane perpendicular to the substrate, the cross section of the second electrode has a ring-shaped opening, and the first semiconductor layer is located within the opening of the second electrode.

8. The memory unit according to claim 7 , wherein the first electrode is disposed on a side of the second electrode that is away from the second gate electrode.

9. 8. The memory unit of claim 7, wherein the first semiconductor layer includes a sidewall and two ends, the first semiconductor layer includes a first source contact region and a first drain contact region, the first source contact region is located on the sidewall of the first semiconductor layer and surrounds the first semiconductor layer, and the first drain contact region is located on the sidewall of the first semiconductor layer and surrounds the first semiconductor layer, or is located at the end of the two ends that is away from the second gate electrode.

10. 6. The memory unit of claim 5, wherein the first electrode extends along a third direction, the first gate electrode extends along a second direction, the third electrode extends along the second direction, and the fourth electrode extends along a third direction, and the second direction and the third direction intersect and are parallel to the substrate.

11. The memory unit of claim 7, wherein in a plane parallel to the substrate, there is no overlap between the orthogonal projection of the first electrode and the orthogonal projection of the second electrode, and there is no overlap between the orthogonal projection of the third electrode and the orthogonal projection of the fourth electrode.

12. 8. The memory unit of claim 7, wherein in a cross section perpendicular to the substrate, the first electrode, the second electrode, and the third electrode are located on a first side of the second gate electrode, the fourth electrode is located on a second side of the second gate electrode, and the first side and the second side are opposite sides.

13. A memory unit described in any one of claims 5 to 12, wherein the distance between the surface of the first electrode closer to the substrate and the substrate is smaller than the distance between the surface of the third electrode closer to the substrate and the substrate, and the distance between the surface of the first electrode away from the substrate and the substrate is greater than the distance between the surface of the third electrode away from the substrate and the substrate.

14. A memory unit as described in any one of claims 2 to 12, wherein the film layers of the third electrode and the fourth electrode are different regions of the same conductive film layer and are spaced apart, and the same conductive film layer is approximately parallel to the substrate.

15. The second transistor further includes a second gate insulating layer disposed between the second gate electrode and the second semiconductor layer and surrounding a sidewall of the second gate electrode, and along a direction perpendicular to the substrate, the length of the second semiconductor layer is less than or equal to the length of the second gate insulating layer, is greater than or equal to the length of the third electrode, and is greater than or equal to the length of the fourth electrode. The memory unit of any one of claims 2 to 12.

16. 13. The storage unit of claim 6, wherein the material of the first and second semiconductor layers comprises a metal oxide semiconductor material.

17. 17. The storage unit of claim 16, wherein the metal in the metal oxide semiconductor material comprises at least one of indium, tin, zinc, aluminum, and gallium.

18. a storage unit comprising a read transistor and a write transistor disposed on a substrate; the read transistor includes a first gate electrode, a first semiconductor layer, a first source electrode, and a first drain electrode, the first semiconductor layer surrounding the first gate electrode, and the first gate electrode extending along a direction parallel to the substrate; the write transistor includes a second gate electrode, a second semiconductor layer, a second source electrode, and a second drain electrode, the second semiconductor layer surrounding the second gate electrode, the second gate electrode extending along a direction perpendicular to the substrate, and the second source electrode of the write transistor connected to the first gate electrode of the read transistor; The channel of the second semiconductor layer of the write transistor is a horizontal channel.

19. 20. The memory unit according to claim 18, wherein the read transistors and write transistors are distributed at intervals on the substrate along a direction parallel to the substrate.

20. the second gate electrode extends along a direction perpendicular to the substrate and has a sidewall, the second semiconductor layer surrounds the sidewall, and the second semiconductor layer includes a second source contact region; 19. The memory unit of claim 18, wherein the first gate electrode extends along a direction parallel to the substrate and has a sidewall and two ends, the first semiconductor layer surrounds at least the sidewall, and one of the two ends extends to a second source contact region of the second semiconductor layer and contacts the second semiconductor layer.

21. a sidewall of the second semiconductor layer further comprising a second drain contact region, the second source contact region and the second drain contact region being located in different regions of the sidewall of the second semiconductor layer, and the second source contact region and the second drain contact region being orthogonally projected in a plane perpendicular to the substrate have overlapping regions, so that a channel between the second source contact region and the second drain contact region is parallel to the substrate; 21. The storage unit of claim 20, wherein a sidewall of the first semiconductor layer has a first source contact region and a first drain contact region, and a channel between the first source contact region and the first drain contact region is parallel to the substrate.

22. A 3D memory comprising multiple layers of storage units stacked along a direction perpendicular to a substrate; the storage unit in each layer comprises a read transistor and a write transistor; the read transistor includes a first gate electrode, a first semiconductor layer, a first source electrode, and a first drain electrode, and the first gate electrode extends along a direction parallel to the substrate; the write transistor includes a second gate electrode, a second semiconductor layer, a second source electrode, and a second drain electrode, and the second gate electrode extends along a direction perpendicular to the substrate; a second source electrode of the write transistor is connected to a first gate electrode of the read transistor, the first semiconductor layer surrounds the first gate electrode, the second semiconductor layer surrounds the second gate electrode, and a channel of the second semiconductor layer of the write transistor is a horizontal channel.

23. The 3D memory of claim 22 , wherein the read transistors and write transistors in the same layer are distributed in the substrate at intervals along a direction parallel to the substrate.

24. 23. The 3D memory of claim 22, wherein the first gate electrode of the read transistor and the second source electrode of the write transistor are an integrated structure.

25. the first gate electrode extends along a second direction parallel to the substrate; the first semiconductor layer includes a first source contact region and a first drain contact region, and the second semiconductor layer includes a second source contact region and a second drain contact region; The memory units of each layer further include a first bit line and a second bit line extending along a third direction parallel to the substrate, the third direction intersecting with the second direction, the first bit line being connected to a first drain contact region of the first semiconductor layer, and the second bit line being connected to a second drain contact region of the second semiconductor layer; The memory units of each layer further include a first word line and a second word line extending along a direction perpendicular to the substrate; 23. The 3D memory of claim 22, wherein the first word lines are connected to first source contact regions of first semiconductor layers of the storage units in different layers, and the second word lines are connected to second gate electrodes of the storage units in different layers.

26. 26. The 3D memory of claim 25, wherein the first word lines surround sidewalls of each first semiconductor layer of the storage units in different layers and are connected to first source contact regions on sidewalls of each first semiconductor layer.

27. 26. The 3D memory of claim 25, wherein the first gate electrode has a sidewall, a first end, and a second end, the first end connected to a second source contact region of the second semiconductor layer, and the first bit line connected to the second end.

28. A method for manufacturing a 3D memory, the 3D memory comprising: a plurality of layers of memory units stacked along a direction perpendicular to a substrate; a first word line; and a second word line; the memory units of each layer comprise a read transistor and a write transistor; the read transistor comprises a first gate electrode, a first semiconductor layer, a first source electrode, and a first drain electrode; and the write transistor comprises a second gate electrode, a second semiconductor layer, a second source electrode, and a second drain electrode; the manufacturing method includes: Providing a substrate; sequentially depositing and patterning an insulating thin film and a metal thin film alternately on the substrate to form a stack structure including alternating insulating layers and metal layers, the metal layers including a first sub-portion and a second sub-portion to be connected, and a first drain electrode of the read transistor; etching the stack structure to form a via through the stack structure, etching the first sub-portion to form a first passage, and etching the second sub-portion to form a second passage, the first passage, the second passage, and the via penetrating; depositing a semiconductor thin film, a gate insulating thin film, and a metal thin film in sequence on a sidewall of a passage consisting of the first passage, the second passage, and the via, completely filling the passage, and etching the gate insulating thin film and the metal thin film in the via to form a first semiconductor layer located in the first passage, a second source electrode, a first gate electrode, and a second drain electrode located in the second passage; depositing a semiconductor thin film on a sidewall of the via to form a second semiconductor layer of the write transistor, the second semiconductor layer including a second source contact region and a second drain contact region spaced apart, the second source electrode contacting the second source contact region, the second drain electrode contacting the second drain contact region, and a channel between the second source contact region and the second drain contact region being a horizontal channel; depositing a thin metal film in the via to completely fill the via to form the second word line, and a second gate electrode of the write transistor in a different layer is part of the second word line; patterning the substrate to form the first word line extending along a direction perpendicular to the substrate, and a first source electrode of the read transistor in a different layer being part of the first word line.

29. An electronic device comprising a storage unit according to any one of claims 1 to 17, or a storage unit according to any one of claims 18 to 21, or a 3D memory according to any one of claims 22 to 27.

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