MEMORY CELL ARRAY HAVING ROW GAP BETWEEN ERASE GATE LINE AND DUMMY FLOATING GATE - Patent application

Abstract

1. A memory cell array having rows and columns of memory cells, each of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region, wherein a strap region is disposed between a first plurality of columns and a second plurality of columns, and for a row of memory cells, a dummy floating gate is disposed in the strap region, and an erase gate line electrically connects together the erase gates of the memory cells in a row and in the first plurality of columns, the erase gate line being aligned with the dummy floating gate with a row-wise gap between the erase gate line and the dummy floating gate.

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. patent application Ser. No. 18 / 104,228, filed Jan. 31, 2023, entitled "Memory Cell Array With Row Direction Gap Between Erase Gate Lines and Dummy Floating Gates."

[0002] FIELD OF THE INVENTION The present invention relates to non-volatile memory devices, and more particularly to improving the stability of memory cell current during read operations. [Background technology]

[0003] Nonvolatile memory devices are well known in the art. See, for example, U.S. Patent No. 7,868,375, which discloses a four-gate memory cell configuration. Specifically, FIG. 1 of the present application illustrates a split-gate memory cell 10 having spaced-apart source and drain regions 14 / 16 formed in a silicon semiconductor substrate 12. A channel region 18 in the semiconductor substrate is defined between the source region 14 and the drain region 16. A floating gate 20 is disposed above and insulated from a first portion of the channel region 18 (and is also partially above and insulated from the source region 14) (and controls the conductivity of the first portion of the channel region 18). A control gate 22 is disposed above and insulated from the floating gate 20. A select gate 24 is disposed above and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18). The select gate 24 is laterally adjacent to the floating gate 20 and may include an upper portion extending above and above the control gate 22. The erase gate 26 is disposed above and insulated from the source region 14, laterally adjacent to the floating gate 20, and has an upper portion extending above and above the floating gate 20 forming a notch 27 facing the edge of the floating gate 20. The notch 27 and the edge of the floating gate 20 may be insulated from each other by a tunnel oxide layer 28. The memory cells 10 may be arranged in pairs as shown in FIG. 1, with two memory cells 10 sharing a common source region 14.

[0004] Various combinations of voltages are applied to the control gate 22, select gate 24, erase gate 26, and / or source and drain regions 14 / 16 to program the memory cell 10 (i.e., inject electrons into the floating gate 20), erase the memory cell 10 (i.e., remove electrons from the floating gate 20 through the tunnel oxide 28), and read the memory cell 10 (i.e., measure or detect the conductivity of the channel region 18 to determine the programming state of the floating gate 20).

[0005] The memory cell 10 can be operated in a digital manner, with the memory cell 10 being set to one of only two possible states: a programmed state and an erased state. The memory cell 10 is erased by applying a high positive voltage to the erase gate 26 and, optionally, a negative voltage on the control gate 22, inducing electron tunneling from the floating gate 20 to the erase gate 26 through the tunnel oxide layer 28 (leaving the floating gate 20 in a more positively charged state—the erased state). The memory cell 10 can be programmed by applying positive voltages on the control gate 22, the erase gate 26, the select gate 24, and the source region 14, and passing a current through the drain region 16. Electrons then flow along the channel region 18 from the drain region 16 toward the source region 14, and some electrons are accelerated and heated, causing them to be injected onto the floating gate 20 by hot electron injection (leaving the floating gate in a negatively charged state—the programmed state). The memory cell 10 can be read by applying a positive voltage to the select gate 24 (turning on the portion of the channel region under the select gate 24) and a positive voltage on the drain region 16 (and optionally on the erase gate 26 and / or control gate 22) and sensing current flow through the channel region 18. If the floating gate 20 is positively charged (erased), the memory cell 10 is turned on and current flows from the source region 14 to the drain region 16 (i.e., the memory cell 10 is sensed to be in its erased "1" state based on the sensed current). If the floating gate 20 is negatively charged (programmed), the channel region 18 under the floating gate 20 is turned off, thereby blocking any current flow (i.e., the memory cell 10 is sensed to be in its programmed "0" state based on the absence of current flow).

[0006] The following table provides non-limiting examples of erase, program, and read voltages. Table 1 [Table 1]

[0007] The memory cells 10 can be manipulated in an analog fashion, alternating between the memory state (i.e., the amount of charge, such as the number of electrons on the floating gate 20) of the memory cell, which can vary continuously anywhere from a fully erased state (minimal electrons on the floating gate) to a fully programmed state (maximum number of electrons on the floating gate), or only part of this range. This means that the cell storage is analog, allowing for very precise and individual adjustment of each memory cell 10 in the memory cell array. Alternatively, the memory can operate as an MLC (multilevel cell), where it is configured to be programmed to one of many discrete values ​​(such as 16 or 64 different values). In the case of analog or MLC programming, the programming voltage is applied for only a limited time, or as a series of pulses, until the desired programming state is achieved. In the case of multiple programming pulses, intervening read operations between the programming pulses can be used to determine whether the desired programming state has been achieved (in which case programming stops) or not (in which case programming continues).

[0008] The memory cells 10 may be arranged in an array (i.e., arranged in rows and columns). As shown in FIG. 1, each pair of memory cells 10 shares a common source region 14 and a common erase gate 26. As shown in the array layout of FIG. 2, multiple pairs of memory cells 10 shown in FIG. 1 may be arranged end-to-end in a column, with two adjacent pairs of memory cells sharing a common drain region 16. The source regions 14 of a row of memory cell pairs may be formed as a continuous source line 14a of diffusion in the semiconductor substrate 12, electrically connecting all of the source regions 14 of the row of memory cell pairs. The control gates 22 of a row of memory cells 10 may be formed as a continuous control gate line 22a of a conductive material, such as polysilicon, electrically connecting all of the control gates 22 of the row of memory cells. The select gates 24 of a row of memory cells 10 may be formed as a continuous select gate line 24a (also called a word line) of a conductive material, such as polysilicon, electrically connecting all of the select gates 24 of the row of memory cells. The erase gates 26 of a row of memory cells 10 may be formed as a continuous erase gate line 26a of a conductive material, such as polysilicon, that electrically connects all of the erase gates 26 of the row of memory cells. The floating gate 20 may be formed of a conductive material, such as polysilicon.

[0009] It is necessary to periodically connect to the various lines of the array. Summary of the Invention

[0010] The above-mentioned problems and needs are addressed by a memory cell array including a plurality of memory cells arranged in rows and columns, each of the plurality of memory cells including: spaced apart source and drain regions formed in a semiconductor substrate and having a channel region extending therebetween; a floating gate disposed above and insulated from a first portion of the channel region; a select gate disposed above and insulated from a second portion of the channel region; and an erase gate disposed above and insulated from the source regions. A strap region is disposed between the first plurality of columns of memory cells and the second plurality of columns of memory cells. For one of the rows of memory cells, a dummy floating gate is disposed in the strap region above and insulated from the substrate between two of the memory cells in the row of memory cells, and a first erase gate line electrically connects together the erase gates of the memory cells in the row of memory cells and in the first plurality of columns of memory cells, the first erase gate line being aligned with the dummy floating gate with a first row-wise gap between the first erase gate line and the dummy floating gate.

[0011] The memory cell array includes a plurality of memory cells arranged in rows and columns, each of the plurality of memory cells including spaced apart source and drain regions formed in a semiconductor substrate and having a channel region extending therebetween, a floating gate disposed above and insulated from a first portion of the channel region, a select gate disposed above and insulated from a second portion of the channel region, and an erase gate disposed above and insulated from the source region, and a strap region disposed between the first plurality of columns of memory cells and the second plurality of columns of memory cells. For the first row of memory cells and the second row of memory cells, a first dummy floating gate is disposed in the strap region above and insulated from the substrate between two of the memory cells in the first row of memory cells, a second dummy floating gate is disposed in the strap region above and insulated from the substrate between two of the memory cells in the second row of memory cells, and a first erase gate line electrically connects together the erase gates of the memory cells in the first and second rows of memory cells and in the first plurality of columns of memory cells, the first erase gate line being aligned with the first dummy floating gate with a first row gap between the first erase gate line and the first dummy floating gate and being aligned with the second dummy floating gate with a second row gap between the first erase gate line and the second dummy floating gate.

[0012] Other objects and features of the present disclosure will become apparent from a review of the specification, claims, and accompanying drawings.

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[0020] [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a cross-sectional side view of a pair of conventional memory cells. [Figure 2] FIG. 1 is a layout diagram illustrating a conventional layout of various lines of an array of memory cells. [Figure 3] FIG. 1 is a layout diagram illustrating the layout of various line and strap regions of an array of memory cells. [Figure 4] FIG. 1 is a partial layout diagram illustrating one layout of various line and strap regions of an array of memory cells. [Figure 5] FIG. 10 is a partial layout diagram illustrating row-wise overlap between one of a plurality of erase gate lines and one of a plurality of dummy floating gates. [Figure 6] FIG. 10 is a partial layout diagram illustrating a row gap between one of a plurality of erase gate lines and one of a plurality of dummy floating gates. [Figure 7] FIG. 10 is a layout diagram illustrating the layout of various lines and strap regions of an array of memory cells with row-wise gaps between the erase gate lines and dummy memory cells. [Figure 8] FIG. 10 is a cross-sectional side view of another example memory cell. [Figure 9] 9 is a layout diagram illustrating the layout of various line and strap regions of the array of memory cells of FIG. 8 with gaps in the row direction between the erase gate lines and the dummy memory cells. DETAILED DESCRIPTION OF THE INVENTION

[0022] Periodic strap regions can be incorporated into the memory cell array to provide space and access for connecting to various lines of the memory array. Figure 3 illustrates a memory array of memory cells 10 similar to those of Figure 1, with like element numbers referring to like elements. The memory array of Figure 3 includes a first strap region 30, a second strap region 32, and a third strap region 34. Each strap region is the region between two of the columns 36 of memory cells 10. In the example of Figure 3, three columns 36 of memory cells 10 are shown disposed between each strap region, although the number of columns 36 of memory cells 10 between each strap region can vary.

[0023] The strap regions 30, 32, and 34 provide areas between columns of memory cells 36 where vertical contacts may be formed, extending downward from higher-level metal layers that make electrical contact with various lines of the memory array (where signal lines may be formed). For example, in the first strap region 30, a vertical contact 38 extends downward from the upper metal layer to make electrical contact with a select gate line (word line) 24a, and a vertical contact 40 extends downward from the upper metal layer to make electrical contact with a source line 14a. In the example of FIG. 3, each source line 14a electrically connects together the source regions 14 of two rows of memory cells (and extends across the strap regions 30, 32, and 34). Each erase gate line 26a electrically connects together the erase gates of memory cells in two adjacent rows of memory cells. To provide access to the source lines 14a, portions of the erase gate lines 26a in the center of the first strap region 30 are removed (e.g., by etching) to allow the vertical contacts 40 to make electrical contact with the source lines 14a without electrically contacting the erase gate lines 26a (i.e., the vertical contacts are electrically connected to the source lines and are disposed within the first strap region 30 and between the erase gate lines 26a). In the second strap region 32, the vertical contacts 40 extend downward from the upper metal layer and make electrical contact with the source lines 14a. To provide access to the source lines 14a, portions of the erase gate lines 26a in the center of the second strap region 32 are removed (e.g., by etching) to allow the vertical contacts 40 to make electrical contact with the source lines 14a without electrically contacting the erase gate lines 26a (i.e., the vertical contacts are electrically connected to the source lines and are disposed within the first strap region 30 and between the erase gate lines 26a). In the third strap region 34, a vertical contact 44 extends downward from the upper metal layer to make electrical contact with the tub portion 22b (i.e., the widened portion) of the control gate line 22a, and a vertical contact 40 extends downward from the upper metal layer to make electrical contact with the source line 14a.To provide access to the source lines 14a, portions of the erase gate lines 26a in the center of the third strap region 34 are removed (e.g., by etching) so that vertical contacts 40 can make electrical contact with the source lines 14a without electrically contacting the erase gate lines 26a (i.e., the vertical contacts are electrically connected to the source lines and are disposed within the first strap region 30 and between the erase gate lines 26a). Because the diffusions in the semiconductor substrate 12 (which form the source lines 14a) are less conductive than the metal lines to which they are connected, vertical contacts 40 for the source lines 14a can be included in all three strap regions 30, 32, 34.

[0024] To facilitate fabrication and maintain the polysilicon density in the strap regions 30, 32, 34 relative to the column of memory cells, dummy floating gates 20a may be formed in the strap regions 30, 32, 34 as shown in FIG. 3. The dummy floating gates 20a may be formed in the portions of the strap regions 30, 32, 34 where the control gate line 22a overlaps the underlying diffusion in the semiconductor substrate 12, and may be of the same conductive material (e.g., polysilicon) as the floating gates 20 and of the same general configuration (i.e., disposed above and insulated from the substrate) as the floating gates 20. For any given strap region and row of memory cells, there may be a dummy floating gate 20a disposed in the strap region and between two of the memory cells 10 in that row of memory cells. Forming the dummy floating gates 20a as part of the process of forming the floating gates 20 streamlines fabrication and improves reliability and yield by approximating the density of the conductive material in the strap regions 30, 32, 34 to that of the column of memory cells.

[0025] The inventors have discovered that the proximity of the erase gate line 26a to the dummy floating gate 20a can cause capacitive coupling between the erase gate line 26a and the dummy floating gate 20a, which can disrupt the programming state of adjacent memory cells. For example, as shown in Figure 4, memory cell 10n having floating gate 20n is adjacent to strap region 30 having dummy floating gate 20a, which in turn is adjacent to memory cell 10m having floating gate 20m. The erase gate line 26a extends partially into strap region 30 such that at both ends of the dummy floating gate 20a, the erase gate line 26a partially overlaps the dummy gate 20a in the row direction (referred to herein as row overlap, RDO), as shown in Figures 4-5. As used herein, row overlap RDO refers to how each erase gate line 26a is aligned with its respective dummy floating gate 20a, and is the distance between two vertical lines (extending in the column direction), one aligned with the edge of a dummy floating gate 20a and the other aligned with the edge of an adjacent erase gate line 26a, indicating the overlap of these two features in the row direction (even though these elements are separated from each other in the column direction, so that there is no actual physical overlap). Row overlap RDO can result in excessive capacitive coupling between the dummy floating gate 20a and the erase gate line 26a, so that erasing or programming memory cell 10n can disturb the programmed state of memory cell 10m. For example, erasing the floating gate 20n of memory cell 10n may at least partially erase the dummy floating gate 20a, which in turn may at least partially erase the floating gate 20m of memory cell 10m and / or may cause data retention leakage for both the floating gate 20n and the floating gate 20m. Additionally, programming the floating gate 20n may partially program the dummy floating gate 20a, which in turn may cause the partially programmed dummy floating gate 20a to disturb the programmed state of the floating gate 20m of memory cell 10m.

[0026] The inventors have discovered that reconfiguring the alignment of the erase gate lines 26a near each dummy floating gate 20a strap region to replace the row-wise overlap RDO between the dummy floating gate 20a and the erase gate line 26a with a row-wise gap RDG between the dummy floating gate 20a and the respective erase gate line 26a can result in a significant reduction in unintentional changes in the programmed state of the dummy floating gate 22a, and therefore a significant reduction in programmed-state disturbances to nearby memory cell floating gates 20. As used herein, row-wise gap RDG relates to how each erase gate line 26a is aligned with its respective dummy floating gate 20a, and is the distance between two vertical lines (extending in the column direction), one aligned with an edge of the dummy floating gate 20a and the other aligned with an edge of each adjacent erase gate line 26a, as shown in Figures 6 and 7, and denotes the gap between these two features in the row direction. 6 and 7, for any given dummy floating gate 20a in one of the rows of memory cells 10, there is a first row-wise gap RDG relative to a first erase gate line 26a (e.g., to the left or right side of the dummy erase gate 20a) and a second row-wise gap RDG relative to a second erase gate line 26a (e.g., to the other of the left or right side of the dummy erase gate 20a). The first and second row-wise gaps on either side of the dummy floating gate 20a may be, but need not be, the same size. If the edge is not a straight line, a vertical line intersects the farthest point where each dummy floating gate 20a extends in the row direction toward its adjacent memory cell column and where each erase gate line 26a extends in the row direction toward the center of the strap region. The alignment of the erase gate line 26a with the dummy floating gate 20a with a row gap RDG means that this alignment does not have a row overlap RDO (i.e., the row gap RDG and the row overlap RDO are mutually exclusive).

[0027] Since it was discovered that the larger the tunnel oxide, the larger the row gap should be, it was further determined that the minimum value of the row gap RDG to achieve improved performance can be related to the thickness of the tunnel oxide layer 28. Specifically, the thickness of the tunnel oxide layer 28 can be selected taking into account the erase operation voltage applied to the gate being erased, and therefore represents the potential capacitive coupling between the erase gate line 26a and the dummy floating gate 20a.

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[0028] Having a row gap RDG that is at least twice the thickness of the tunnel oxide layer 28 can be realized in nonvolatile memory cell configurations that deviate from that of Figure 1. Specifically, Figure 8 illustrates a memory cell similar to that of Figure 1, but with the control gate omitted. Figure 9 illustrates an array of memory cells of Figure 8 with a row gap RDG between the erase gate line 26a and the dummy memory cells 20a.

[0029] It will be understood that the present invention is not limited to the above-described embodiments illustrated herein, but encompasses all modifications falling within the scope of any claims. For example, references to the present invention herein are not intended to limit the scope of the claims or the terminology thereof, but instead merely refer to one or more features that may be covered by one or more of the claims. The examples of materials, processes, and values ​​described above are merely illustrative and should not be construed as limiting the scope of the claims. Moreover, as will be apparent from the claims and the specification, not all method steps may need to be performed in the exact order illustrated or claimed unless otherwise specified.

Claims

1. A memory cell array, a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell of the plurality of memory cells including: spaced apart source and drain regions formed in a semiconductor substrate and having a channel region extending therebetween; a floating gate disposed above and insulated from a first portion of the channel region; a select gate disposed above and insulated from a second portion of the channel region; and an erase gate disposed above and insulated from the source region; a strap region disposed between the first plurality of columns of memory cells and the second plurality of columns of memory cells; For one row of the plurality of rows of memory cells: a dummy floating gate disposed in the strap region above and insulated from the substrate and between two of the memory cells in the row of memory cells; a first erase gate line electrically connecting together the erase gates of the memory cells in the row of memory cells and in the first plurality of columns of memory cells, the first erase gate line aligned with the dummy floating gate with a first row-wise gap between the first erase gate line and the dummy floating gate.

2. 2. The memory cell array of claim 1, further comprising a second erase gate line electrically connecting together the erase gates of the memory cells in the one row of memory cells and in the second plurality of columns of memory cells, the second erase gate line aligned with the dummy floating gate with a second row-wise gap between the second erase gate line and the dummy floating gate.

3. a source line electrically connecting together the source regions of the memory cells in the one row of memory cells and in the first and second columns of memory cells, the source line extending across the strap region; 3. The memory cell array of claim 2, further comprising: a vertical contact electrically connected to the source line and disposed in the strap region and between the first erase gate line and the second erase gate line.

4. a select gate line electrically connecting together the select gates of the memory cells in the row of memory cells and in the first and second columns of memory cells, the select gate line extending across the strap region; 2. The memory cell array of claim 1, further comprising: a vertical contact electrically connected to the select gate line and disposed within the strap region.

5. 2. The memory cell array of claim 1, wherein said each memory cell of said plurality of memory cells further comprises a control gate disposed above and insulated from said floating gate.

6. control gate lines electrically connecting together the control gates of the memory cells in the row of memory cells and in the first and second columns of memory cells, the control gate lines extending across the strap regions; 6. The memory cell array of claim 5, further comprising: a vertical contact electrically connected to the control gate line and disposed within the strap region.

7. the erase gates of the memory cells in the row of memory cells and in the first plurality of columns of memory cells are insulated from their respective floating gates by a tunnel oxide layer having a thickness; The memory cell array of claim 1 , wherein the first row gap is at least twice the thickness of the tunnel oxide layer.

8. the erase gates of the memory cells in the row of memory cells and in the second plurality of columns of memory cells are insulated from their respective floating gates by a tunnel oxide layer having a thickness; The memory cell array of claim 2 , wherein the second row gap is at least twice the thickness of the tunnel oxide layer.

9. A memory cell array, a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each memory cell of the plurality of memory cells including: spaced apart source and drain regions formed in a semiconductor substrate and having a channel region extending therebetween; a floating gate disposed above and insulated from a first portion of the channel region; a select gate disposed above and insulated from a second portion of the channel region; and an erase gate disposed above and insulated from the source region; a strap region disposed between the first plurality of columns of memory cells and the second plurality of columns of memory cells; For the first row of memory cells and the second row of memory cells: a first dummy floating gate disposed in the strap region above and insulated from the substrate and between two memory cells of the plurality of memory cells in the first row of memory cells; a second dummy floating gate disposed in the strap region above and insulated from the substrate and between two of the plurality of memory cells in the second row of memory cells; a first erase gate line electrically connecting together the erase gates of the memory cells in the first and second rows of memory cells and in the first plurality of columns of memory cells; the first erase gate line is aligned with the first dummy floating gate with a first row gap between the first erase gate line and the first dummy floating gate, and is aligned with the second dummy floating gate with a second row gap between the first erase gate line and the second dummy floating gate.

10. 10. The memory cell array of claim 9, further comprising: a second erase gate line electrically connecting together the erase gates of the memory cells in the first and second rows of memory cells and in the second plurality of columns of memory cells, the second erase gate line aligned with the first dummy floating gate with a third row gap between the second erase gate line and the first dummy floating gate and aligned with the second dummy floating gate with a fourth row gap between the second erase gate line and the second dummy floating gate.

11. source lines electrically connecting together the source regions of the memory cells in the first and second rows of memory cells and in the first and second columns of memory cells, the source lines extending across the strap regions; 11. The memory cell array of claim 10, further comprising: a vertical contact electrically connected to the source line and disposed in the strap region and between the first erase gate line and the second erase gate line.

12. a first select gate line electrically connecting together the select gates of the memory cells in the first row of memory cells and in the first and second columns of memory cells, the first select gate line extending across the strap region; a first vertical contact electrically connected to the first select gate line and disposed within the strap region; a second select gate line electrically connecting together the select gates of the memory cells in the second row of memory cells and in the first and second columns of memory cells, the second select gate line extending across the strap region; 10. The memory cell array of claim 9, further comprising: a second vertical contact electrically connected to the second select gate line and disposed within the strap region.

13. 10. The memory cell array of claim 9, wherein said each memory cell of said plurality of memory cells further comprises a control gate disposed above and insulated from said floating gate.

14. first control gate lines electrically connecting together the control gates of the memory cells in the first row of memory cells and in the first and second columns of memory cells, the first control gate lines extending across the strap regions; a first vertical contact electrically connected to the first control gate line and disposed within the strap region; a second control gate line electrically connecting together the control gates of the memory cells in the second row of memory cells and in the first and second columns of memory cells, the second control gate line extending across the strap region; 14. The memory cell array of claim 13, further comprising: a second vertical contact electrically connected to the second control gate line and disposed within the strap region.

15. the erase gates of the memory cells in the first and second rows of memory cells and in the first plurality of columns of memory cells are insulated from their respective floating gates by a tunnel oxide layer having a thickness; 10. The memory cell array of claim 9, wherein the first row gap is at least twice the thickness of the tunnel oxide layer and the second row gap is at least twice the thickness of the tunnel oxide layer.

16. the erase gates of the memory cells in the first and second rows of memory cells and in the second plurality of columns of memory cells are insulated from their respective floating gates by a tunnel oxide layer having a thickness; 11. The memory cell array of claim 10, wherein the third row gap is at least twice the thickness of the tunnel oxide layer and the fourth row gap is at least twice the thickness of the tunnel oxide layer.

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