Method and system for operating a PNP bidirectional double-base bipolar junction transistor

Abstract

One example is a method of operating a PNP double-sided double-base bipolar junction transistor (DSDB BJT), the method including conducting a first load current from an upper terminal of a power module to an upper base of the transistor, through the transistor, and from the lower base to a lower terminal of the power module, and then, in response to assertion of a first shutoff signal, opening a lower main FET and diverting a first shutoff current through a lower collector-emitter of the transistor to the lower terminal, thereby shutting off the first load current from the lower base to the lower terminal, and blocking current from the upper terminal to the lower terminal by the transistor.

Description

[Technical Field]

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 382,924, entitled "Methods and Systems of Operating a PNP Bi-Directional Double-Base Bipolar Junction Transistor (B-TRAN)," filed November 9, 2022, which is incorporated herein by reference as if reproduced in full below. [Background technology]

[0002] A double-sided double-base (DSDB) bipolar junction transistor (BJT) (hereinafter, DSDB-BJT) is a junction transistor constructed with a base and collector-emitter on a first side of a bulk region and a separate, isolated base and collector-emitter on a second side of the bulk region opposite the first side. When properly configured by an external driver, current can selectively flow through the collector-emitter of a DSDB-BJT in either direction; therefore, a DSDB-BJT device is considered a bidirectional device. Based on its bidirectionality, whether the collector-emitter is considered a collector or an emitter depends on the polarity of the applied external voltage and, therefore, the direction of current flow through the DSDB-BJT.

[0003] DSDB-BJT devices can be constructed as NPN devices that are normally off, i.e., normally non-conducting, from the top collector-emitter to the bottom collector-emitter (or vice versa). DSDB-BJT devices can also be constructed as PNP devices that are normally on, i.e., normally conducting, from the top collector-emitter to the bottom collector-emitter (or vice versa). Summary of the Invention

[0004] At least one example is a method of operating a power module having a bidirectional double-base bipolar junction transistor, the method comprising: conducting a first load current from an upper terminal of the power module to an upper base of the transistor, through the transistor, and from a lower base to a lower terminal of the power module; and then, in response to assertion of a first shutoff signal, opening a lower main FET and diverting a first shutoff current through a lower collector-emitter of the transistor to the lower terminal, thereby shutting off the first load current from the lower base to the lower terminal, and blocking current flow from the upper terminal to the lower terminal by the transistor.

[0005] In the example method, during the conducting, the method may further include injecting charge carriers into the top collector-emitter, and the method may further include stopping the injection of charge carriers into the top collector-emitter in response to the assertion of the first blocking signal. Stopping the injection of charge carriers may further include stopping the injection of charge carriers a non-zero predetermined time before blocking the first load current by opening the lower main FET.

[0006] In the example method, interrupting the first load current may further include interrupting the first load current using the lower main FET having a breakdown voltage of 100 volts or less, and blocking current may further include blocking at an applied voltage across the upper and lower terminals of 600 volts or more.

[0007] In the example method, diverting the first shutoff current may further include coupling the lower collector-emitter to the lower terminal, which may further include coupling the lower collector-emitter to the lower terminal with a voltage source or a current source.

[0008] The example method may further include, after blocking current from the upper terminal to the lower terminal, conducting a second load current from the lower terminal of the power module to the lower base of the transistor, through the transistor, and from the upper base to the upper terminal, and then, in response to assertion of a second blocking signal, blocking the second load current from the upper base to the upper terminal by opening an upper main FET and diverting a second shutoff current through an upper collector-emitter to the upper terminal, and blocking current from the lower terminal to the upper terminal with the transistor. Blocking the second load current may further include blocking the second load current using the upper main FET having a breakdown voltage of 100 volts or less, and blocking current from the lower terminal to the upper terminal may further include blocking at an applied voltage across the lower terminal and the upper terminal of 600 volts or more.

[0009] A further example is a switch assembly including: an upper terminal, a lower terminal, and an upper control input; a transistor defining an upper base, an upper collector-emitter, a lower base, and a lower collector-emitter; an upper main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper base, and a gate; a lower main FET defining a first lead coupled to the lower base, a second lead coupled to the lower terminal, and a gate; and a controller coupled to the upper control input, the gate of the upper main FET, and the gate of the lower main FET. For a first applied voltage across the upper terminal and the lower terminal, the controller may be configured to assert the gate of the upper main FET to cause the upper main FET to conduct, configuring the transistor for conduction from the upper base to the lower base, and assert the gate of the lower main FET to cause the lower main FET to conduct, thereby causing a first load current to flow from the upper terminal to the lower terminal; detect a deassertion of the upper control input; and, in response to the deassertion of the upper control input, deassert the gate of the lower main FET to block the first load current from the lower base.

[0010] In this example switch assembly, the breakdown voltage of the transistor may be 600 volts or greater, and the breakdown voltage of the lower main FET may be 100 volts or less.

[0011] In this example switch assembly, the breakdown voltage of the transistor may be approximately 1200 volts, and the breakdown voltage of the lower main FET may be 80 volts or less.

[0012] The example switch assembly may further include an upper CE source and an upper CE FET, the upper CE source configured to selectively inject charge carriers into the upper collector-emitter through the upper CE FET, wherein when the controller configures the transistor for conduction from the upper base to the lower base, the controller is further configured to make the upper CE FET conductive to inject charge carriers into the upper collector-emitter, and when the controller detects the upper control input being deasserted, the controller is further configured to make the upper CE FET non-conductive to stop injection of charge carriers into the upper collector-emitter. When the controller makes the upper CE FET non-conductive, the controller may be configured to make the upper CE FET non-conductive a non-zero predetermined time period before deasserting the gate of the lower main FET. When the controller detects the deassertion of the upper control input, the controller may be further configured to electrically float the upper collector-emitter.

[0013] The example switch assembly may further include a lower CE FET defining a first lead coupled to the lower collector-emitter, a second lead coupled to the lower terminal, and a gate coupled to the controller, wherein the controller is further configured to assert the gate of the lower CE FET to divert a shut-off current to the lower terminal when the controller detects the upper control input being deasserted. The switch assembly may further include a lower CE source configured to selectively extract charge carriers from the lower collector-emitter through the lower CE FET, wherein the controller may be further configured to cause the lower CE FET to conduct to extract charge carriers from the lower collector-emitter when the controller detects the upper control input being deasserted.

[0014] The example switch assembly may further include a lower control input coupled to the controller, wherein the controller may be configured to: for a second applied voltage across the upper and lower terminals, having an opposite polarity to the first applied voltage, assert the gate of the lower main FET to cause the lower main FET to conduct, configuring the transistor for conduction from the upper base to the lower base, and assert the gate of the upper main FET to cause the upper main FET to conduct, thereby causing a second load current to flow from the lower terminal to the upper terminal; detect a deassertion of the lower control input; and, in response to the deassertion of the lower control input, deassert the gate of the upper main FET to block the second load current from the upper base. The switch assembly may further include a lower CE source and a lower CE FET, the lower CE source configured to selectively inject charge carriers into the lower collector-emitter through the lower CE FET, and when the controller configures the transistor for conduction from the lower base to the upper base, the controller may be further configured to make the lower CE FET conductive to inject charge carriers into the lower collector-emitter, and when the controller detects the lower control input being deasserted, the controller may be further configured to make the lower CE FET non-conductive to stop injection of charge carriers into the lower collector-emitter.

[0015] Another example is a second example method of operating a bidirectional double-base bipolar junction transistor, the method including: causing the transistor to conduct from the upper base to the lower base by supplying a current to the upper collector-emitter of the transistor and electrically floating the lower collector-emitter of the transistor; and then causing the transistor to become non-conductive by electrically floating the upper collector-emitter, electrically floating the lower base, and directing a shutoff current through the lower collector-emitter of the transistor.

[0016] In this second example method, electrically floating the lower base may further include rendering a lower main electrically controlled switch having a first lead coupled to the lower base non-conductive.

[0017] In the second example method, causing the transistor to conduct may further include closing an upper main electrically controlled switch coupled between an upper terminal and the upper base, and closing a lower main electrically controlled switch coupled between a lower terminal and the lower base.

[0018] Rendering the transistor non-conductive may further include opening the upper main electrically controlled switch, conducting the shut-off current to the upper base through a diode associated with the upper main electrically controlled switch, and diverting the shut-off current from the lower base to the lower collector-emitter by opening the lower main electrically controlled switch. [Brief explanation of the drawings]

[0019] For a detailed description of example embodiments, reference will now be made to the accompanying drawings. [Figure 1] FIG. 1 shows a partial block diagram, partially electrical schematic, of a power module using NPN DSDB-BJTs. [Figure 2]FIG. 1 shows a partial block diagram, partially electrical schematic, of a power module using PNP DSDB-BJTs. [Figure 3] FIG. 1 shows a partial electrical schematic, partial block diagram of a power module using a PNP DSDB-BJT in accordance with at least some embodiments. [Figure 4] 1 illustrates a cross-sectional elevation view of a PNP DSDB-BJT according to at least some embodiments. [Figure 5A] 5A-5G illustrate, in simplified form, an NPN DSDB-BJT with example external electrical connections to illustrate several operating states of the NPN DSDB-BJT, according to at least some embodiments. [Figure 5B] 5A-5G illustrate, in simplified form, an NPN DSDB-BJT with example external electrical connections to illustrate several operating states of the NPN DSDB-BJT, according to at least some embodiments. [Figure 5C] 5A-5G illustrate, in simplified form, an NPN DSDB-BJT with example external electrical connections to illustrate several operating states of the NPN DSDB-BJT, according to at least some embodiments. [Figure 5D] 5A-5G illustrate, in simplified form, an NPN DSDB-BJT with example external electrical connections to illustrate several operating states of the NPN DSDB-BJT, according to at least some embodiments. [Figure 5E] 5A-5G illustrate, in simplified form, an NPN DSDB-BJT with example external electrical connections to illustrate several operating states of the NPN DSDB-BJT, according to at least some embodiments. [Figure 5F] 5A-5G illustrate, in simplified form, an NPN DSDB-BJT with example external electrical connections to illustrate several operating states of the NPN DSDB-BJT, according to at least some embodiments. [Figure 5G]5A-5G illustrate, in simplified form, an NPN DSDB-BJT with example external electrical connections to illustrate several operating states of the NPN DSDB-BJT, according to at least some embodiments. [Figure 6] FIG. 1 shows a partial electrical schematic, partial block diagram of a switch assembly according to at least some embodiments. [Figure 7] 1 illustrates a partial electrical schematic diagram of an example switch assembly according to at least some embodiments. [Figure 8] 1 illustrates a method in accordance with at least some embodiments. [Figure 9] 1 illustrates a method in accordance with at least some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0020] definition Various terms are used to refer to particular system components. Different companies may refer to components by different names, and this document does not intend to distinguish between components that differ in name but not function. In the following description and claims, the terms "including" and "having" are used open-endedly and, therefore, should be interpreted to mean "including, but not limited to." Also, the term "couple" is intended to mean either an indirect connection or a direct connection. Thus, when a first device couples to a second device, the connection may be by a direct connection or by an indirect connection via other devices and connections.

[0021] "About" with reference to a stated parameter means the stated parameter, plus / minus ten percent (+ / -10%) of the stated parameter.

[0022] "Assert" means to produce or maintain a first predetermined state of a Boolean signal. A Boolean signal may be asserted high, i.e., at a higher voltage, or low, i.e., at a lower voltage, at the discretion of the circuit designer. Similarly, "deassert" means to produce or maintain a second predetermined state of a Boolean signal, opposite to the asserted state.

[0023] "FET" means a field effect transistor, such as a junction gate FET (JFET) or a metal oxide silicon FET (MOSFET).

[0024] "Closing," with reference to an electrically controlled switch (e.g., a FET), means making the electrically controlled switch conductive. For example, closing a FET used as an electrically controlled switch may mean driving the FET into a fully conductive state.

[0025] "Opening," with reference to an electrically controlled switch (eg, a FET), means causing the electrically controlled switch to be non-conductive.

[0026] "Double-sided double-base bipolar junction transistor" means a junction transistor having a base and collector-emitter on a first face or side of a bulk region and a base and collector-emitter on a second face or side of the bulk region, the base and collector-emitter on the first side being distinct from the base and collector-emitter on the second side.

[0027] The "collector-emitter region" of a PNP bidirectional device means a region of P-type doping that forms a junction with the bulk substrate and / or base region of N-type doping. + The portions of the collector-emitter region (which transition to a different doping type) are not considered to be of a different doping type.

[0028] "Collector-emitter" means an electrical pin or terminal that is directly coupled to a collector-emitter region. The presence of intervening wirebonds and bondpads does not exclude a collector-emitter from being directly coupled to a collector-emitter region.

[0029] "Top collector-emitter" means the collector-emitter of a double-sided double-base bipolar junction transistor on a first side of the bulk region of the transistor, and should not be read to mean the position of that collector-emitter relative to gravity.

[0030] "Lower collector-emitter" means the collector-emitter of a double-sided double-base bipolar junction transistor on a second side of the bulk region of the transistor opposite the first side, and should not be read to mean the position of that collector-emitter relative to gravity.

[0031] The "base region" of a PNP bidirectional device means a region of N-type doping contiguous with a bulk N-type doped substrate. + The portion of the base region (where the doping transitions to the doping transition) is not considered to be of a different doping type.

[0032] "Base" means an electrical pin or terminal directly coupled to the base region. The presence of intervening wire bonds and bond pads does not exclude the base from being directly coupled to the base region.

[0033] "Upper base" means the base of a double-sided double-base bipolar junction transistor on a first side of the bulk region of the transistor, and should not be read to mean the position of that base relative to gravity.

[0034] "Lower base" means the base of a double-sided double-base bipolar junction transistor on a second side of the bulk region of the transistor opposite the first side, and should not be read to refer to the position of the base relative to gravity.

[0035] The terms "input" and "output," when used as nouns, refer to connections (e.g., electrical, software) and should not be read as verbs requiring an action. For example, a timer circuit may define a clock output. The example timer circuit may generate or drive a clock signal on the clock output. In a system implemented directly in hardware (e.g., on a semiconductor substrate), these "inputs" and "outputs" define electrical connections. In a system implemented in software, these "inputs" and "outputs" define parameters, respectively, that are read or written by instructions that perform a function.

[0036] "Controller" means, alone or in combination, a discrete circuit component, an application specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computing (RISC) with control software, a digital signal processor (DSP), a processor with control software, a programmable logic device (PLD), a field programmable gate array (FPGA), or a programmable system on a chip (PSOC) configured to read an input and drive an output in response to that input.

[0037] The following description is directed to various embodiments of the present invention. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed or otherwise used as limiting the scope of the present disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad applicability, and the description of any embodiment is intended merely to exemplify that embodiment, and is not intended to imply that the scope of the present disclosure, including the claims, is limited to that embodiment.

[0038] Various examples are directed to methods and systems for operating PNP double-sided double-base (DSDB) bipolar junction transistors (BJTs) (hereinafter simply DSDB-BJTs). This specification first references related art methods and systems for operating NPN DSDB-BJTs. Co-pending and commonly assigned U.S. patent application Ser. No. 17 / 537,726, filed November 30, 2021, describes a power module using DSDB-BJT devices, in which the primary current through the DSDB-BJT device is from the top collector-emitter to the bottom collector-emitter and vice versa. FIG. 1 shows a partial electrical schematic, partial block diagram, of a power module using DSDB-BJTs in an NPN configuration. Specifically, shown in FIG. 1 is a DSDB-BJT 100 defining an upper collector-emitter 112, an upper base 114, a lower collector-emitter 120, and a lower base 122. As indicated by the circuit symbol, the DSDB-BJT 100 is of an NPN structure. An NPN DSDB-BJT is a normally-off device, i.e., a device that is normally non-conducting. A driver circuit is associated with the DSDB-BJT 100 to configure the DSDB-BJT 100 to selectively conduct in either direction. Specifically, an upper driver 130 may be associated with the upper collector-emitter 112 and upper base 114, and a lower driver 132 may be associated with the lower collector-emitter 120 and lower base. The upper driver 130 selectively floats the upper base 114 and shorts the upper base 114 to the upper terminal 140 during conduction from the upper terminal 140 to the lower terminal 142, thereby reducing the V CEON Similarly, the lower driver 132 is designed and configured to inject charge carriers into the upper base 114 to lower the V of the DSDB-BJT 100, causing the lower base 122 to float and short the lower base 122 to the lower terminal 142 during conduction from the lower terminal 142 to the upper terminal 140. CEON The lower base 122 is designed and configured to inject charge carriers into the lower base 122 so as to reduce the

[0039] 1, the NPN DSDB-BJT 100 is configured for cascode operation, allowing current to flow in either direction. Specifically, the DSDB-BJT 100 includes a lower electrically controlled switch (hereinafter simply referred to as switch 144) coupled between the lower collector-emitter 120 and the lower terminal 142. The switch 144 is selected and implemented to block load current from the upper terminal 140 to the lower terminal 142 via the collector-emitters 112 and 120 when an externally applied voltage is positive on the upper terminal 140 side. Similarly, the DSDB-BJT 100 includes an upper electrically controlled switch (hereinafter simply referred to as switch 146) coupled between the upper terminal 140 and the upper collector-emitter 112. Switch 146 is selected and implemented to block load current from lower terminal 142 through collector-emitters 120 and 112 to upper terminal 140 when an externally applied voltage is positive at lower terminal 142. Thus, in the configuration of FIG. 1 using DSDB-BJT 100, load current flows through collector-emitters 112 and 120 as controlled by the voltage and current applied to upper base 114 and lower base 122.

[0040] The aforementioned co-pending application by the same applicant indicates that a similar power module can be implemented using a PNP-structure DSDB-BJT. FIG. 2 shows a partial block diagram, partially an electrical schematic, of a power module using a PNP-structure DSDB-BJT. Specifically, shown in FIG. 2 is a DSDB-BJT 200. As indicated by the circuit symbol, the DSDB-BJT 200 is of a PNP structure. The DSDB-BJT 200 defines an upper collector-emitter 112, an upper base 114, a lower collector-emitter 120, and a lower base 122. Because PNP transistors are normally-on devices, i.e., devices that are normally conductive, the upper driver 130 and the lower driver 132 would be designed and configured to configure the DSDB-BJT 200 to be non-conductive during periods when the power module is blocking current. Again, as mentioned above, even in the case of a power module implementing a PNP configuration of DSDB-BJT 200, the DSDB-BJT may still be configured for cascode operation with current interruption performed by switch 144 or 146 depending on the direction of the current.

[0041] 1 and 2 simultaneously, the inventors herein believe that a person skilled in the art tasked with implementing a power module using a PNP-configured DSDB-BJT would implement the design of FIG. 2 in which the collector-emitter is used as the primary load current path through the DSDB-BJT device. In other words, a person skilled in the art would implement a design in which the load current flows through the collector-emitter by applying a significantly smaller, controlled voltage and current to bases 114 and 122 as a function of the polarity of the externally applied voltage.

[0042] However, it has been found that the PNP structure DSDB-BJT shown in Figure 2 has a forward voltage drop V CEON In the case of the DSDB-BJT100 shown in Figure 1, the forward voltage drop V CEONcan be lowered by minority carrier injection into the bulk or base region. Biasing the base on the same side of the device as the collector-emitter is acting as the collector reduces V CEON In contrast to a three-terminal PNP transistor, where the base is on the opposite side of the collector, the base on the same side of the BTRAN is referred to as the c-base.

[0043] The inventors herein have discovered that the forward voltage drop V of a PNP DSDB-BJT can be reduced by providing and / or injecting minority carriers through the collector-emitter on the electrically positive side of the device, so that the primary load current through the PNP device is carried through the base rather than the collector-emitter. CEON A reduction in the

[0044] FIG. 3 shows a partial electrical schematic, partial block diagram of a power module using a DSDB-BJT in a PNP configuration according to various embodiments. Specifically, shown in FIG. 3 is a DSDB-BJT 300 defining an upper collector-emitter 302, an upper base 304, a lower collector-emitter 306, and a lower base 308. As shown in the circuit symbol, the DSDB-BJT 300 is of a PNP configuration, but with a continuous base region extending from region 304 to region 308. In related art NPN or PNP devices, the base region is sandwiched between the collector and emitter. A driver circuit is associated with the DSDB-BJT 300 to control conduction of the DSDB-BJT 300. Specifically, an upper driver 310 may be associated with the upper collector-emitter 302 and the upper base 304, and a lower driver 312 may be associated with the lower collector-emitter 306 and the lower base 308. The upper driver 310 is designed and configured to selectively float the upper collector-emitter 302, float the upper base 304, short the upper collector-emitter 302 to an upper terminal 314, and inject minority carriers into a drift region between the upper base 304 and the lower base 308. Similarly, the lower driver 312 is designed and configured to selectively float the lower collector-emitter 306, float the lower base 308, and short the lower collector-emitter 306 to a lower terminal 316, and inject minority carriers into a drift region between the lower base 308 and the upper base 304. The injection of minority carriers into the drift region controls the V CEON significantly reduces

[0045] In the example of Figure 3, the DSDB-BJT 300 is configured for cascode operation, allowing current to flow in either direction. Specifically, the DSDB-BJT 300 includes a lower electrically controlled switch (hereinafter simply referred to as the lower main switch 318) coupled between the lower base 308 and the lower terminal 316. The lower main switch 318 is selected and implemented to interrupt a load current from the upper terminal 314 to the lower terminal 316 via the bases 304 and 308 when an externally applied voltage is positive at the upper terminal 314. Similarly, the DSDB-BJT 300 includes an upper electrically controlled switch (hereinafter simply referred to as the upper main switch 320) coupled between the upper terminal 314 and the upper base 304. The upper main switch 320 is selected and implemented to interrupt a load current from the lower terminal 316 to the upper terminal 314 via the bases 308 and 304 when an externally applied voltage is positive at the lower terminal 316. 3 using a PNP structure DSDB-BJT 300, the main load current flows through the bases 304 and 308 as controlled by the voltage and current applied to the top collector-emitter 302 and bottom collector-emitter 306, as opposed to the configuration of FIG. 2. This specification now refers in more detail to the example DSDB-BJT 300.

[0046] FIG. 4 shows a cross-sectional elevation view of an example of a PNP-structure DSDB-BJT. Specifically, FIG. 4 shows a DSDB-BJT 300 having an upper surface or upper side 400 and a lower surface or lower side 402. The designations "upper" and "lower" are arbitrary and are used merely for convenience of explanation. The upper side 400 faces in the opposite direction from the lower side 402. In other words, an outward pointing vector perpendicular to the upper side 400 (not specifically shown) points in the opposite direction relative to an outward pointing vector perpendicular to the lower side 402 (not specifically shown).

[0047] The top side 400 includes a plurality of collector-emitter regions 404 that form junctions with a drift region or bulk substrate 406. The top side 400 further defines a plurality of base regions 408 disposed between the collector-emitter regions 404. The collector-emitter regions 404 are coupled together to form the upper collector-emitter 302. The base regions 408 are coupled together to form the upper base 304. Similarly, the bottom side 402 includes a plurality of lower collector-emitter regions 410 that form junctions with the bulk substrate 406. The bottom side 402 further defines a plurality of lower base regions 412 disposed between the lower collector-emitter regions 410. The lower collector-emitter regions 410 are coupled together to form the lower collector-emitter 306. The lower base regions 412 are coupled together to form the lower base 308.

[0048] In this example DSDB-BJT 300, the collector-emitter regions 404 and 410 are P-type, and the base regions 408 and 412 are N-type. In this example system, shallow P+ regions provide ohmic contact from the collector-emitter regions 404 and 410 to one or more metallization layers (not specifically numbered) and thus to the respective collector-emitters 302 and 306. Also in this example system, shallow N+ contact doping provides ohmic contact from the base regions 408 and 412 to one or more metallization layers (not specifically numbered) and thus to the respective bases 304 and 308. In this example, optional dielectric-filled trench 414 provides lateral isolation between the base and collector-emitter regions.

[0049] In this example case, the various structures and doping associated with top side 400 are mirror images of the various structures and doping associated with bottom side 402. However, in some cases, the various structures and doping associated with top side 400 are constructed at a different time than the various structures and doping of bottom side 402, and therefore, slight differences in structure and doping between the two sides due to manufacturing tolerances may exist, but such do not adversely affect the operation of the device as a bidirectional double-base bipolar junction transistor.

[0050] According to example embodiments and in the claims, the status of a region as a base region or a collector-emitter region is defined based on the doping type and junction formation. Thus, the status of a terminal or connection as a base or collector-emitter is based on the underlying region to which that terminal is coupled. Specifically, the collector-emitter region of the PNP DSDB-BJT 300 refers to a region of P-type doping that forms a junction with an N-type doped bulk substrate and / or base region. Still referring to FIG. 4 and considering the top collector-emitter region 404, the example top collector-emitter region 404, which is P-type, forms a junction with an N-type bulk substrate 406. In the case of the DSDB-BJT 300, the bulk region 406 has a continuous N-type doping (i.e., N-type doping in the bulk substrate 406). - From the N in the base region 408, the N used to form the ohmic contacts + The carrier concentration varies but has the same doping type (e.g., P to P) + The portions of the collector-emitter region (which transition to a different doping type) are not considered to be of a different doping type.

[0051] Similarly, the base region of the DSDB-BJT 300 refers to a region of N-type doping that is continuous with the bulk substrate of N-type doping. Still referring to FIG. 4 and considering the upper base region 408, the example upper base region 408, which is N-type, is continuous with the bulk substrate of N-type doping. Again, for the DSDB-BJT 300, the bulk substrate 406 is effectively the base region due to the continuous N-type doping. The carrier concentrations vary but have the same doping type (e.g., transitioning from N- to N, then P to N). + The portion of the base region (where the doping transitions to the doping transition) is not considered to be of a different doping type.

[0052] Thus, the status of a terminal or connection as a base or collector-emitter is not defined by the path of the main load current and / or the location where a control voltage or current is applied; rather, the status of a terminal or connection as a base or collector-emitter is defined by the doping type within the transistor device. Electrically tracing from the upper base 304 to the lower base 308, only N-type regions exist, and variations in carrier concentration do not change the fact that all the regions from the upper base 304 to the lower base 308 are N-type. However, from the upper collector-emitter 302 to the lower collector-emitter 306, a PN junction exists, i.e., the P-type upper collector-emitter region 404 forms a junction with the N-type bulk substrate 406, and the N-type bulk substrate forms a junction with the P-type lower collector-emitter region 410.

[0053] 5A-5G show, in simplified form, cross-sectional views of a PNP-structured DSDB-BJT with example external electrical connections to illustrate several operating states. Specifically, FIGS. 5A-5G show seven example states of a DSDB-BJT 300 configured so that the main load current is carried across or through the base region: (from left to right) passive off (FIG. 5A), active off (FIG. 5B), diode on (FIG. 5C), passive on (FIG. 5D), active on (FIG. 5E), pre-turn off (FIG. 5F), and bidirectional blocking (FIG. 5G). Each will be discussed in turn.

[0054] Referring first to Figure 5A, Figure 5A illustrates an example of an upper terminal 314 and a lower terminal 316. Between the upper terminal 314 and the lower terminal is a DSDB-BJT 300, shown in simplified form, defining an upper collector-emitter 302, an upper base 304, a lower collector-emitter 306, and a lower base 308. In the examples of Figures 5A-5G, assume that an externally applied voltage has a more positive polarity relative to the upper terminal 314 than the lower terminal 316. In the passive-off configuration example of Figure 5A, the DSDB-BJT 300 has the upper collector-emitter 302 electrically floating, the upper base 304 coupled to the upper terminal 314, the lower collector-emitter 306 coupled to the lower terminal 316, and the lower base 308 electrically floating. In the configuration of Figure 5A, in some cases, the DSDB-BJT 300 can have a breakdown voltage of 600 volts or more, and in some cases, approximately 1200 volts. Therefore, no appreciable current flows through the DSDB-BJT 300 due to the reverse-biased PN junction formed between the lower collector-emitter 306 and the upper base 304. Because the electrical configuration of Figure 5A can be implemented with purely passive components (e.g., diodes and resistors), and therefore the driver circuitry does not need to have operating power to implement the configuration of Figure 5A, the example state of Figure 5A is referred to as "passive off."

[0055] FIG. 5B illustrates an example active-off configuration of the DSDB-BJT 300. Specifically, the top collector-emitter 302 is electrically floating, the top base 304 is coupled to the top terminal 314, the bottom collector-emitter 306 is coupled to the bottom terminal 316 via a voltage source 500, and the bottom base 308 is electrically floating. The voltage source 500 provides a negative bias to the bottom collector-emitter 306. As described in more detail below, the voltage source 500 can accelerate the transition of the DSDB-BJT 300 to a non-conducting state when transitioning from one of the conducting states (also described below) to a non-conducting state. In the configuration of FIG. 5B, in some cases, the DSDB-BJT 300 can have a breakdown voltage of 600 volts or more, and in some cases, a breakdown voltage of approximately 1200 volts. Thus, in the active-off configuration, no appreciable current flows through the DSDB-BJT 300 due to the reverse-biased PN junction formed between the lower collector-emitter 306 and the upper base 304. The example state of FIG. 5B is referred to as "active-off" because, in the electrical configuration of FIG. 5B, the associated driver circuitry uses operating power to implement the configuration (e.g., to power the voltage source 500).

[0056] FIG. 5C illustrates an example diode-on configuration for the DSDB-BJT 300. Specifically, the top collector-emitter is coupled to the top terminal 314, the top base 304 is electrically floating, the bottom collector-emitter 306 is electrically floating, and the bottom base 308 is coupled to the bottom terminal 316. In the diode-on configuration, the PN junction formed between the top collector-emitter 302 and the bulk substrate is forward biased, allowing current to flow from the top terminal 314 to the bottom terminal 316. The voltage drop across the DSDB-BJT 300 in the configuration of FIG. 5C is approximately the forward diode voltage drop, approximately 0.7 volts. The diode-on configuration of FIG. 5C is presented for consistency with the discussion of the diode-on configuration (not shown) of an NPN-structure DSDB-BJT; in practice, this diode-on configuration may be used only in limited circumstances or not at all.

[0057] 5D shows an example passive-on configuration of the DSDB-BJT 300. Specifically, the top collector-emitter 302 is left electrically floating, the top base 304 is coupled to the top terminal 314, the bottom collector-emitter 306 is left electrically floating, and the bottom base 308 is coupled to the bottom terminal 316. The voltage drop across the DSDB-BJT 300 in the configuration of FIG. 5D is based on the substrate resistance (e.g., approximately 2 ohms for a 260 μm thick substrate). This conductive state is similar to the forward voltage drop V CEON The example state of FIG. 5D is referred to as "passive-on" because it does not involve the injection of charge carriers in an attempt to lower the potential.

[0058] 5E shows an example active-on configuration of the DSDB-BJT 300. Specifically, the top collector-emitter 302 is coupled to the top terminal 314 via a voltage source 502, the top base 304 is coupled to the top terminal 314, the bottom collector-emitter 306 is electrically floating, and the bottom base 308 is coupled to the bottom terminal 316. The voltage source 502 provides a positive bias to the top collector-emitter 302 with respect to the top base 304, and the voltage source 502 may provide any suitable bias voltage (e.g., 0.2 V-2 V). The voltage source 502 injects charge carriers across the PN junction into the bulk substrate, which results in a base-to-base forward voltage drop V for a main current of 30 amperes (A) through the base. CEON to about 0.2 V compared to about 10-20 V without charge carrier injection.

[0059] 5F illustrates an example pre-turn-off configuration for the DSDB-BJT 300. Specifically, the top collector-emitter 302 is coupled to the top terminal 314, the top base 304 is coupled to the top terminal 314, the bottom collector-emitter 306 is coupled to the bottom terminal 316, and the bottom base 308 is coupled to the bottom terminal 316. An equivalent configuration can be achieved by omitting the coupling of the top collector-emitter 302 to the top terminal 314. In the pre-turn-off configuration of FIG. 5F, the resistance of the DSDB-BJT 300 between the terminals 314 and 316 increases while excess minority carriers are pushed out of the base region. The highest resistance occurs when the base region returns to its intrinsic doping density (e.g., when the minority carrier density is about 1E17 / cm 3 (high minority carrier injection in the on-state) to approximately 5E13 / cm 3 When the resistivity decreases to 0.2 mΩ cm (substrate intrinsic doping), 2 to 2 Ω·cm 2 (This can increase to 0.2 mΩ·cm.) This change in minority carrier density increases the voltage drop between the upper terminal 314 and the lower terminal 316. 2 With a 30 A load at an Rsp of 100 Ω, the pre-turn-off configuration of FIG. 5F exhibits a voltage drop of approximately 60 V from the top terminal 314 to the bottom terminal 316.

[0060] In the bidirectional blocking example of FIG. 5G, for the DSDB-BJT 300, the top collector-emitter 302 is coupled to the top terminal 314, the top base 304 is left electrically floating, the bottom collector-emitter 306 is coupled to the bottom terminal, and the bottom base 308 is left electrically floating. Therefore, no appreciable current flows through the DSDB-BJT 300. In the configuration of FIG. 5G, the breakdown voltage of the DSDB BJT 300 depends on the reverse PN junction breakdown voltage in either polarity. The reverse PN junction breakdown voltage is V CEON It is determined by the junction profile, taking into account the trade-off between the 3 For a 300 μm thick N-type substrate of doping, the breakdown voltage between the P-type and N-type regions can exceed 1200 V.

[0061] In many situations, the DSDB-BJT 300 will be configured to transition directly from either the passive-off configuration of FIG. 5A or the active-off configuration of FIG. 5B to the active-on configuration of FIG. 5E without implementing any intermediate configurations or states. That is, the diode-on configuration of FIG. 5C and the passive-on configuration of FIG. 5D are optional configurations that may nevertheless find use in some situations. With respect to the transition from conducting to non-conducting, in many situations the DSDB-BJT 300 will be transitioned directly from the active-on configuration of FIG. 5E to the active-off configuration of FIG. 5B, the passive-off configuration of FIG. 5A, or the bidirectional blocking configuration of FIG. 5G without implementing any intermediate configurations or states. That is, the diode-on configuration of FIG. 5C, the passive-on configuration of FIG. 5D, and the pre-turn-off configuration of FIG. 5F are optional intermediate configurations in the transition from conducting to non-conducting, that nevertheless find use in some situations.

[0062] 5A-5G are for situations where the externally applied voltage has a positive polarity at the top terminal 314. However, the example DSDB-BJT 300 is a symmetrical device, and now that we understand how to control current flow in the DSDB-BJT in the polarity examples shown, controlling current flow in the opposite direction follows directly.

[0063] FIG. 6 illustrates a partial electrical schematic, partial block diagram of an example power module or switch assembly. Specifically, the example switch assembly 600 includes a PNP DSDB-BJT 300 and a driver 602. The DSDB-BJT 300 is illustrated with an example circuit symbol having two emitters and two bases. The circuit symbol shows an upper collector-emitter 302, an upper base 304, a lower collector-emitter 306, and a lower base 308. The example driver 602 defines an upper collector-emitter terminal 608 coupled to the upper collector-emitter 302, an upper conduction terminal 610 coupled to the upper base 304, a lower collector-emitter terminal 612 coupled to the lower collector-emitter 306, and a lower conduction terminal 614 coupled to the lower base 308. The upper base 304 is coupled to an upper terminal 314 of the switch assembly 600 via an upper conduction terminal 610. The lower base 308 is coupled to a lower terminal 316 of the switch assembly 600 via a lower conduction terminal 614.

[0064] The example driver 602 includes a controller 616, an electrical isolator 618, and an isolation transformer 620. To place the DSDB-BJT 300 in various conducting and non-conducting modes, the example driver 602 includes a plurality of electrically controlled switches and charge carrier sources. Specifically, the example driver 602 includes a switch 622 having a first lead coupled to the upper terminal 314, a second lead coupled to the upper collector-emitter 302, and a control input coupled to the controller 616. While the example switch 622 is shown as a single-pole, single-throw switch, in practice, the switch 622 could be a FET, and the control input would be the gate of the FET. Thus, when the switch 622 is made conducting by asserting its control input, the upper collector-emitter 302 is coupled to the upper terminal 314.

[0065] The driver 602 further includes a charge carrier source 624, illustrated as a battery. The charge carrier source 624 has a negative lead coupled to the upper terminal 314. Another electrically controlled switch 626 (hereafter simply switch 626) has a first lead coupled to the positive terminal of the charge carrier source 624, a second lead coupled to the upper collector-emitter 302, and a control input coupled to the controller 616. While the example switch 626 is also shown as a single-pole, single-throw switch, in practice the switch 626 could be a field-effect transistor (FET) with the gate of the FET as the control input. Thus, when the switch 626 is conducting, the charge carrier source 624 is coupled between the upper terminal 314 and the upper collector-emitter 302. The driver 602 further includes another charge carrier source 628, illustrated as a battery. The charge carrier source 628 has a positive lead coupled to the upper terminal 314. Another electrically controlled switch 630 (hereafter simply switch 630) has a first lead coupled to the negative terminal of a charge carrier source 628, a second lead coupled to the top collector-emitter 302, and a control input coupled to the controller 616. While the example switch 630 is also shown as a single-pole, single-throw switch, in practice switch 630 could be a FET with the gate of the FET as the control input. Thus, when switch 630 is conducting, charge carrier source 628 is coupled between the top terminal 314 and the top collector-emitter 302.

[0066] The driver 602 further includes an upper main switch 320 having a first lead coupled to the upper terminal 314, a second lead defining an upper conduction terminal 610 coupled to the upper base 304, and a control input coupled to the controller 616. As mentioned above, although the example upper main switch 320 is shown as a single-pole, single-throw switch, in practice the upper main switch 320 may be a FET with the gate of the FET as the control input. Thus, when the upper main switch 320 is made conductive, such as by asserting its control input, the upper terminal 314 is coupled to the upper base 304.

[0067] Referring now to the bottom of DSDB-BJT 300, example driver 602 further includes a switch 632 having a first lead coupled to bottom terminal 316, a second lead coupled to bottom collector-emitter 306, and a control input coupled to controller 616. While example switch 632 is shown as a single-pole, single-throw switch, in practice switch 632 may be a FET, with the control input being the gate of the FET. Thus, when switch 632 is made conductive by asserting its control input, bottom collector-emitter 306 is coupled to bottom terminal 316.

[0068] The driver 602 further includes a charge carrier source 634, illustrated as a battery. The charge carrier source 634 has a negative lead coupled to the lower terminal 316. Another electrically controlled switch 636 (hereinafter simply switch 636) has a first lead coupled to the positive terminal of the charge carrier source 634, a second lead coupled to the lower collector-emitter 306, and a control input coupled to the controller 616. While the example switch 636 is shown as a single-pole, single-throw switch, in practice the switch 636 could be a field-effect transistor (FET) with the gate of the FET as the control input. Thus, when the switch 636 is conducting, the charge carrier source 634 is coupled between the lower terminal 316 and the lower collector-emitter 306. The example driver 602 further includes another charge carrier source 638, illustrated as a battery. The charge carrier source 638 has a positive lead coupled to the lower terminal 316. Another electrically controlled switch 640 (hereafter simply switch 640) has a first lead coupled to the negative terminal of charge carrier source 638, a second lead coupled to bottom collector-emitter 306, and a control input coupled to controller 616. While example switch 640 is shown as a single-pole, single-throw switch, in practice switch 640 could be a FET with the gate of the FET as the control input. Thus, when switch 640 is conducting, charge carrier source 638 is coupled between bottom terminal 316 and bottom collector-emitter 306.

[0069] The example driver 602 further includes a lower main switch 318 having a first lead coupled to the lower terminal 316, a second lead defining a lower conduction terminal 614 coupled to the lower base 308, and a control input coupled to the controller 616. As previously mentioned, although the example lower main switch 318 is shown as a single-pole, single-throw switch, in practice the lower main switch 318 may be a FET with the gate of the FET as the control input. Thus, when the lower main switch 318 is conducting, such as by asserting its control input, the lower terminal 316 is coupled to the lower base 308.

[0070] Controller 616 defines control inputs 642 and 644 and control outputs 646, 648, 650, 652, 654, 656, 657, and 658 coupled to the control inputs of switches 320, 630, 626, 622, 632, 636, 640, and 318, respectively. When control input 642 is asserted, controller 616 is designed and constructed to configure DSDB-BJT 300 for conduction from upper terminal 314 to lower terminal 316. Conversely, when control input 642 is deasserted, controller 616 is designed and constructed to configure DSDB-BJT 300 to prevent current flow from upper terminal 314 to lower terminal 316. Similarly, when control input 644 is asserted, controller 616 is designed and constructed to configure DSDB-BJT 300 for conduction from bottom terminal 316 to top terminal 314. Conversely, when control input 644 is deasserted, controller 616 is designed and constructed to configure DSDB-BJT 300 to block current flow from bottom terminal 316 to top terminal 314. When control inputs 642 and 644 are both asserted, controller 616 configures DSDB-BJT 300 for current flow in both directions (e.g., AC breaker service), and when control inputs 642 and 644 are both deasserted, controller 616 blocks current flow in both directions.

[0071] The configuration in which the DSDB-BJT 300 is rendered non-conductive depends on the polarity of the applied voltage. Accordingly, the example controller 616 may further define a polarity input 660 that receives a Boolean indication of the applied polarity. In the example driver 602, a comparator 662 has a first input coupled to the upper terminal 314 (connection indicated by bubble “A”) and a second input coupled to the lower terminal 316. The comparator 662 defines a comparison output coupled to the polarity input 660. While FIG. 6 shows the first and second inputs directly coupled to their respective conduction terminals, in practice, the voltage across the DSDB-BJT 300 when non-conductive can be large (e.g., 1200 V), and therefore each of the first and second inputs may be coupled to a respective conduction terminal via a respective voltage divider circuit. In still further cases, the applied polarity may be determined by systems and devices external to the switch assembly 600 and a Boolean signal is sent across the electrical isolator 618 to the polarity input 660 .

[0072] Transitioning DSDB-BJT 300 from non-conducting to conducting and then back to non-conducting can be a multi-step process. To implement the multi-step process, controller 616 can be individual circuit components, an application specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computing (RISC), a digital signal processor (DSP), a processor with control software, a programmable logic device (PLD), or a field programmable gate array (FPGA), a programmable system on a chip (PSOC), and / or a combination configured to read control inputs 642 and 644, read polarity input 660, and drive control outputs to effect the mode transition of DSDB-BJT 300.

[0073] In the example system, the switch assembly 600 is electrically floating. To receive control inputs 642 and 644 in the electrical domain of the switch assembly 600, the example driver 602 implements an electrical isolator 618. The example electrical isolator 618 may take any suitable form, such as an optical coupler or a capacitive isolation device. Regardless of the exact nature of the electrical isolator 618, external control signals (e.g., Boolean signals) may be coupled to control inputs 664 and 666 of the electrical isolator 618. The electrical isolator 618 then passes those control signals to the electrical domain of the switch assembly 600. In this example, the external control signals are passed to the control inputs 642 and 644 of the controller 616.

[0074] Reference is now made to the isolation transformer 620. Various devices within the switch assembly 600 may use operating power. For example, the controller 616 may use the bus voltage and power to enable various operating modes of the DSDB-BJT 300. Additionally, charge carrier sources within the system may actually be implemented as separate voltage sources in the form of switching power converters or as separate current sources also implemented using switching power converters. The switching power converters implementing the charge carrier sources may use the bus voltage and power. The isolation transformer 620 is provided to provide operating power within the electrical domain of the switch assembly 600. An external system (not specifically shown) may provide an AC signal (e.g., 15V AC) between primary leads 668 and 670 of the isolation transformer 620. The isolation transformer 620 generates an AC voltage on secondary leads 672 and 674. The AC voltage on the secondary side of isolation transformer 620 is provided to an AC-DC power converter 676, which rectifies the AC voltage and converts it into a bus voltage V BUS(e.g., 3.3V, 5V, 12V). The power provided by the AC-DC power converter 676 may be used by various components of the switch assembly 600. In other cases, there may be multiple isolation transformers (e.g., one on each side of the DSDB-BJT). Even more, a single isolation transformer with multiple secondary windings may be used. Next, example configurations for making the DSDB-BJT 300 conducting and / or non-conducting in the context of the switch assembly 600 are described.

[0075] As an example, consider a situation in which the applied voltage has a positive polarity on the upper terminal 314. Further, assume that the control input 664 provided to the electrical isolator 618 is deasserted, thereby deasserting the control signal provided to the control input 642 of the controller 616. Based on the deasserted control input 642, the controller 616 is designed and configured to place the DSDB-BJT 300 in a non-conducting configuration, taking into account the applied polarity (e.g., as read by the controller 616 through the polarity input 660). Thus, in this example configuration, the upper main switch 320 is conductive, the lower main switch 318 is non-conductive, and either 1) the switch 632 is conductive (passive off), or 2) the switch 640 is conductive (active off). In some examples, the upper main switch 320 is made conductive by the controller 616 asserting the control output 646. However, in other cases, as described in more detail below, the upper main switch 320 is implemented as a FET with an internal body diode. Thus, conductivity of the upper main switch 320 may initially be based at least on an applied voltage forward biasing the body diode of the FET implementing the upper main switch 320. A similar configuration and / or operation may exist for the lower main switch 318 when configured to block reverse polarity current flow.

[0076] Still considering the example configuration with positive polarity at the upper terminal 314, next assume that the control signal provided to the control input 664 of the galvanic isolator 618 is asserted, which in turn asserts the control signal provided to the control input 642 of the controller 616. Based on this assertion, in the example switch assembly 600, the controller 616 can be designed and constructed to directly place the DSDB-BJT 300 in the active-on configuration ( FIG. 5E ). To do so, the controller 616 can assert control output 646 (if not already asserted) to cause the upper main switch 320 to conduct, assert control output 650 to cause switch 626 to conduct, assert control output 658 to cause the lower main switch 318 to conduct, and deassert or leave the remaining control outputs deasserted. In yet another case, to place the DSDB BJT 300 in a conducting state, the controller 616 can be designed and constructed to turn on the switch 626 a predetermined period (e.g., about 0.1 μs-5 μs) before turning on the lower main switch 318. Turning on the switch 626 before turning on the lower main switch 318 can charge the capacitance between the collector-emitter 302 and the base 304, allowing the DSDB BJT 300 to become fully conducting more quickly when the lower main switch 318 is turned on.

[0077] Optionally, again with positive polarity at the upper terminal 314, the controller 616 can be designed and constructed to cause the DSDB-BJT 300 to pass through intermediate conduction configurations before reaching the active-on configuration. For example, the controller 616 can momentarily place the DSDB-BJT 300 in a passive-on configuration (FIG. 5D) by asserting control output 646 to cause the upper main switch 320 to conduct, asserting control output 658 to cause the lower main switch 318 to conduct, and deasserting or leaving the remaining control outputs deasserted. When used, the passive-on configuration can last for a predetermined period of time (e.g., about 0.1 μs-5 μs). As another example of an intermediate conduction state, the controller 616 can place the DSDB-BJT 300 in a diode-on configuration ( FIG. 5C ) by fleetingly asserting control output 652 to turn on switch 622, asserting control output 658 to turn on the lower main switch 318, and deasserting or leaving the remaining control outputs deasserted. When used, the diode-on configuration may last for a predetermined period of time (e.g., approximately 0.1 μs–5 μs). In practice, the upper main switch 320 may have an internal body diode or a discrete parallel diode coupled to it, such that the diode-on configuration may not be possible when the upper terminal 314 has a positive polarity because the body diode or discrete parallel diode would be forward biased. A similar diode-on configuration inoperability may exist when the lower terminal 316 has a positive polarity if the lower main switch 318 has a body diode or discrete parallel diode. That said, after the intermediate conduction configuration, the controller 616 places the DSDB-BJT 300 in the active-on configuration.

[0078] In the active-on configuration, with a positive polarity at the top terminal 314, the charge carrier source 624 injects charge carriers into the top collector-emitter 302. Injecting charge carriers into the top collector-emitter 302 increases the number of charge carriers in the drift region of the DSDB-BJT 300, which in turn increases the V measured between the bases 304 and 308. CEON In one example, the charge carrier source 624 injecting charge carriers reduces V between the bases 304 and 308 for a current of about 30 A-100 A through the bases 304 and 308. CEON to about 0.2 V. The charge carrier source 624 can be at any suitable voltage between 0.5 V and 5.0 V, inclusive, and in some cases between 0.6 V and 1.5 V.

[0079] Still referring to FIG. 6 , and still considering positive polarity on the upper terminal 314, consider further that the control input 664 provided to the electrical isolator 618 transitions from asserted to deasserted, and thus the control signal provided to the control input 642 of the controller 616 transitions from asserted to deasserted. Based on this transition, the controller 616 is designed and constructed to again place the DSDB-BJT 300 in a non-conducting configuration. In an example case, the controller 616 can directly implement the aforementioned passive-off or active-off configuration from the conducting state of the DSDB-BJT 300. In other cases, the controller 616 may turn off the switch 626 a predetermined time (e.g., about 0.1 μs-5 μs) before opening the lower main FET 318, which reduces minority carriers in the drift region, thereby lowering the peak and / or shortening the duration of the commutation current. Also, with regard to the timing of changing the states of the upper main switch 320 and the lower main switch 318, when the DSDB-BJT 300 transitions to a non-conducting state with the assumed polarity, the lower main switch 318 may be made non-conducting, but the upper main switch 320 may remain in a conducting state for a predetermined period of time (e.g., approximately 450 nanoseconds or less) as the current through the switch assembly 600 drops, which may shorten the reverse recovery time of the body diode associated with the upper main switch 320.

[0080] Optionally, the controller 616 may be designed and constructed to cause the DSDB-BJT 300 to pass through intermediate conducting configurations before reaching the non-conducting configuration. For example, the controller 616 may fleetingly place the DSDB-BJT 300 in a diode-on configuration (FIG. 5C), a passive-on configuration (FIG. 5D), or a pre-turn-off configuration (FIG. 5F). When used, the intermediate configurations between active-on and active-off may last for a predetermined period of time (e.g., about 0.1 μs-5 μs).

[0081] 6 was with positive polarity on the top terminal 314. However, again, the example DSDB-BJT 300 and associated driver are symmetrical, and now it is straightforward to understand how to configure the DSDB-BJT 300 into various conducting and non-conducting states, and control of current flow in the opposite direction.

[0082] The switch assembly of FIG. 6 illustrates an example DSDB-BJT 300 configured for cascode operation. In such a configuration, blocking of current flow through the device (e.g., during a transition from conducting to non-conducting) is primarily performed by the upper main switch 320 and the lower main switch 318. For example, with a positive polarity on the upper terminal 314, current flow through the switch assembly 600 is first blocked by the lower main switch 318, and then further blocked by the DSDB-BJT 300. Conversely, with a positive polarity on the lower terminal 316, current flow through the switch assembly 600 is first blocked by the upper main switch 320, and then further blocked by the DSDB-BJT 300. Therefore, because blocking is performed by the DSDB-BJT 300, it follows that the breakdown voltages of the upper main switch 320 and the lower main switch 318 can be significantly lower than the breakdown voltage of the DSDB-BJT 300. For example, the breakdown voltage of the DSDB-BJT 300 may be 600V or more, in some cases about 1200V, while the upper main switch 320 and the lower main switch 318 may each have a breakdown voltage of 100V or less, in some cases 80V or less.

[0083] In the transition from a conducting state to a non-conducting state through the bases 304 and 308, a relatively small amount of current, i.e., a shutoff current, can momentarily flow through the collector-emitter opposite to the positive polarity. For example, if there is a positive polarity on the upper terminal 314 and current flows from the upper base 304 and out the lower base 308 through the DSDB-BJT 300, interrupting the current with the lower main switch 318 causes the shutoff current to momentarily flow through the lower collector-emitter 306. In other words, when the load current through the DSDB-BJT 300 is interrupted by the lower main switch 318, the lower PN junction becomes reverse biased, and therefore the shutoff current is commutated through the lower collector-emitter 306 for a short period of time (note that, for the sake of the assumption, the lower collector-emitter 306 is left electrically floating during conduction). Thus, the passive-off configuration ( FIG. 5A ) and the active-off configuration ( FIG. 5B ) provide a current path for the shutoff current to the bottom terminal 316. In the active-off configuration ( FIG. 5B ), the charge carrier source 638 (corresponding to the voltage source 500 in FIG. 5B ) can accelerate the transition of the DSDB-BJT 300 to a non-conducting state by extracting charge carriers from the bulk region and more quickly reverse-biasing the PN junction formed between the bottom collector-emitter 306 and the bulk region. Now that we understand the commutation of current through the bottom collector-emitter 306 when there is a positive voltage at the top terminal 314, an equivalent description of the commutation of current through the top collector-emitter 302 when there is a positive voltage at the bottom terminal 316 follows directly.

[0084] Figure 7 shows a partial electrical diagram of an example switch assembly. Specifically, Figure 7 shows an example DSDB-BJT 300 and a portion of an example driver 602. Driver 602 may also include an isolation transformer, an AC-DC power converter, an electrical isolator, a controller, and a comparator, although these components are omitted from the simplified representation of Figure 7. For illustrative purposes, the top side of Figure 7 shows switches 320, 622, 626, and 630 and example charge carrier sources 624 and 628. The bottom side shows switches 318, 632, 636, and 640 and example charge carrier sources 634 and 638.

[0085] As alluded to above, many of these switches are implemented as FETs. In the example switch assembly of FIG. 7, the upper main switch 320 is shown as a FET having a source coupled to the upper terminal 314, a drain coupled to the upper base 304, a gate defining a control input, and a body diode coupled between the source and drain. When an applied voltage has a positive polarity on the upper terminal 314, the body diode becomes forward biased, causing the upper main switch 320 to conduct (without any action by the controller 616 (FIG. 6)). During the conducting state of the DSDB-BJT 300, the controller 616 drives the gate to cause the FET to conduct, reducing the overall voltage drop. In the example case, the FET used to implement the upper main switch 320 can have a breakdown voltage of 100 V or less, in some cases about 80 V, while the DSDB-BJT 300 can have a breakdown voltage of 600 V or more, in some cases about 1200 V.

[0086] The example switch 622 is shown as a pair of back-to-back FETs. Specifically, the switch 622 is shown as a first FET with its source coupled to the top terminal 314 and a second FET with its source coupled to the top collector-emitter 302, with the drains of the FETs tied together. The gates of the FETs may be individually coupled to the controller 616 ( FIG. 6 ), or the gates may be tied together and driven by the controller 616 as a single unit. Each of the FETs has a body diode, and in the configuration shown, the cathodes of the body diodes are tied together. Having back-to-back FETs allows for bidirectional current blocking and bidirectional current flow, regardless of the presence of the body diodes. With positive polarity on the top terminal 314, the switch 622 can be conductive during an optional diode-on configuration ( FIG. 5C ) or an optional pre-turn-off configuration ( FIG. 5F ). However, during the active-on configuration ( FIG. 5E ), switch 622 may be non-conductive (e.g., to allow other devices to inject charge carriers into the top collector-emitter 302). Thus, with a positive polarity on the top terminal 314, when the gate is deasserted, the back-to-back FETs block current flow even though the body diode of the first FET is forward-biased. Even with a positive polarity on the bottom terminal 316, switch 622 can be conductive upon transition to the passive-off configuration (although passive-off using switch 622 does power driver 602). For example, the shut-off current in the passive-off configuration may be carried by switch 622.

[0087] Similarly, switch 626 is shown as a pair of back-to-back FETs. Specifically, switch 626 is shown as FET 700, whose source is coupled to charge carrier source 624, and FET 702, whose source is coupled to top collector-emitter 302, with the drains of FETs 700 and 702 tied together. The gates of FETs 700 and 702 may be individually coupled to controller 616 ( FIG. 6 ), or the gates may be tied together and driven by controller 616 as a single unit. FETs 700 and 702 each have a body diode, and in the illustrated configuration, the cathodes of these body diodes are tied together. Having back-to-back FETs allows for bidirectional current blocking and bidirectional current flow, regardless of the presence of the body diodes. With positive polarity on top terminal 314, an active-on configuration can be achieved by charge carrier source 624 injecting charge carriers into top collector-emitter 302 through FETs 700 and 702. In another mode, current flow from the charge carrier source 624 to the top collector-emitter 302 may be blocked by the FET 702 even though the body diode of the FET 700 may be forward biased by the charge carrier source 624 .

[0088] Still considering the switch 626 and resistors 704 and 706 (and corresponding resistors 708 and 710 for the lower switch 636), body diodes may be used to enable a power-up safe mode. That is, resistors 704 and 706 ensure that a race condition during power-up of the switch assembly 600 does not cause inadvertent conduction through the DSDB-BJT 300. Specifically, the switch assembly 600 may have its upper terminal 314 and lower terminal 316 tied together within the overall system. Before the AC-DC power converter 676 ( FIG. 6 ) is powered up and / or before the controller 616 has had a chance to bootstrap into an operational state, a voltage may appear across the upper terminal 314 and lower terminal 316 with either polarity. As an example, consider a power-up condition in which a positive polarity appears at the lower terminal 316 before the controller 616 is operational. In such a situation, the body diode of the FET implementing the lower main switch 318 will conduct. Furthermore, the body diode of FET 702 of switch 626 becomes forward biased, causing shutoff and / or leakage current to flow from the upper collector-emitter 302 to the upper terminal 314, thus achieving the passive-off configuration ( FIG. 5A ). A similar configuration occurs when a positive polarity appears at the upper terminal 314, causing leakage current to flow through the body diode of FET 712, resistor 708, and resistor 710. Thus, even without control by controller 616, DSDB-BJT 300 enters a non-conduction-safe mode regardless of the polarity of the voltage applied between the upper terminal 314 and the lower terminal 316.

[0089] According to this example system, the active-on configuration (FIG. 5E) can be selectively implemented at different voltages over time. Specifically, the example switch assembly 600 further includes a charge carrier source 718, illustratively shown as a battery, with its negative lead coupled to the top terminal 314. A switch, illustratively shown as a FET 720, has its source coupled to the positive lead of the charge carrier source 718, its drain coupled to the top collector-emitter 302, and its control input or gate coupled to the controller 616 (FIG. 6). With positive polarity on the top terminal 314, the active-on configuration can initially be implemented by the FET 720 and the charge carrier source 718. Thus, in the active-on configuration, the charge carrier source 718 can initially inject charge carriers into the top collector-emitter 302 at a first rate. The controller 616 can be designed and constructed to slow down the charge carrier injection rate by, after a predetermined period of time, making the FET 720 non-conductive and substantially simultaneously making the switch 626 conductive, thus using the charge carrier source 624 to inject charge carriers into the top collector-emitter 302 at a slower rate. CEON When driven low, the lowered V CEON can be maintained using charge carrier source 624. Now that we understand the use of charge carrier sources 624 and 718 in implementing an active-on configuration when there is positive polarity on top terminal 314, an equivalent description of implementing an active-on configuration using charge carrier sources 638 and 716 (together with switch 714) when there is positive polarity on bottom terminal 316 follows directly.

[0090] Still referring to FIG. 7 , particularly the top side, switch 630 is shown as a single FET having a source coupled to the top collector-emitter 302, a drain coupled to the negative lead of charge carrier source 628, a gate defining a control input coupled to controller 616 ( FIG. 6 ), and a body diode coupled between the source and drain. When the FET itself is non-conducting, a voltage associated with charge carrier source 628 can keep the FET's body diode reverse-biased; thus, a back-to-back FET may not be required for switch 630. A diode 722 is disposed between the FET's source and top collector-emitter 302 to prevent current flow from the top terminal 314 to the top collector-emitter 302 in power loss and / or start-up situations. Specifically, diode 722 has its anode coupled to the top collector-emitter 302 and its cathode coupled to the cathode of the body diode of switch 630. As mentioned above, switch 630 and charge carrier source 628 can be used to implement an active-off configuration when there is a positive polarity on the bottom terminal 316. When there is a positive polarity on the top terminal 314, a similar function is performed by switch 640, charge carrier source 624, and diode 724.

[0091] 7 further illustrates the lower main switch 318 as a FET having a source coupled to the lower terminal 316, a drain coupled to the lower base 308, a gate defining a control input, and a body diode coupled between the source and drain. When a positive polarity is present on the lower terminal 316, the body diode is forward biased, thus causing the lower main switch 318 to conduct (without any action by the controller 616 (FIG. 6)). During the conducting state of the DSDB-BJT 300, the controller 616 drives the gate to cause the FET to conduct, reducing the overall voltage drop. In an example case, the FET used to implement the lower main switch 318 may have a breakdown voltage of 100V or less, in some cases about 80V, while the DSDB-BJT 300 may have a breakdown voltage of 600V or more, in some cases about 1200V.

[0092] Like switch 622, switch 632 may be implemented as back-to-back FETs, and likewise, switch 636 may be implemented as back-to-back FETs. The description of the operation of switches 632 and 636, taking into account the polarity of applied voltages, overlaps with the description of switches 622 and 626 and will not be repeated here to avoid unnecessarily lengthening the description.

[0093] When the various switches are implemented as FETs with body diodes as shown in FIG. 7, state transitions can be more easily and quickly performed by the controller 616 (FIG. 6). As an example, consider the driver 602 having the DSDB-BJT 300 in an active-on configuration with positive polarity on the upper terminal 314. In this situation, the upper main switch 320 is conducting, switch 626 or FET 720 is conducting, the lower main switch 318 is conducting, and the remaining switches are non-conducting. Now, consider the driver 602 receiving a command (e.g., deassertion of control input 642 (FIG. 6)) to make the DSDB-BJT 300 non-conducting. When the switches are implemented as FETs as shown, configuring the driver 602 to implement active-off mode can involve the controller 616 (FIG. 6) deasserting all gates of all FETs. The upper main switch 320 remains conducting based on its body diode being forward biased and conducting. The lower main switch 318 interrupts current flow, and its body diode becomes reverse-biased. The interruption of current flow diverts the shutoff current to flow through the body diode of FET 712 of switch 636 and resistors 708 and 710. At some point in the example situation, controller 616 may turn on switch 640 to implement an active-off configuration, although the timing is not critical. In other words, controller 616 may be designed and constructed to implement a passive-off configuration for only a moment before implementing an active-off configuration, subject to nothing other than reduced timing constraints. A similar argument applies to the case of interrupting current with a positive voltage on the lower terminal 316.

[0094] The various charge carrier sources shown in Figures 6 and 7 are illustratively shown as batteries. However, in practice, these charge carrier sources may be individual DC-DC converters, or a single DC-DC converter with controlled voltage outputs may be implemented for charge carrier sources on the same side with corresponding polarities (e.g., charge carrier sources 624 and 718). In other cases, the DC-DC converters may be implemented as current-controlled sources rather than voltage sources.

[0095] 8 illustrates a method according to at least some embodiments. Specifically, the method includes starting (block 800) and conducting a first load current from an upper terminal of a power module to an upper base of a transistor, through the transistor, and from the lower base to a lower terminal of the power module (block 802). Then, in response to assertion of a first shutoff signal, shutting off the first load current from the lower base to the lower terminal by opening the lower main FET and diverting a first shutoff current through the lower collector-emitter of the transistor to the lower terminal (block 804), and blocking current from the upper terminal to the lower terminal by the transistor (block 806). The method then ends (block 808).

[0096] 9 illustrates a method according to at least some embodiments. Specifically, the method starts (block 900) by providing a current to the upper collector-emitter of a transistor and electrically floating the lower collector-emitter of the transistor, thereby causing the transistor to conduct from the upper base to the lower base (block 902), and then by electrically floating the upper collector-emitter, electrically floating the lower base, and directing a shutoff current through the lower collector-emitter of the transistor (block 904). The method then ends (block 906).

[0097] The upper and lower main switches each have a corresponding voltage drop when fully on, but when implemented as power FETs, the forward voltage drop is small (e.g., 0.01 V to 0.1 V) and negligible in many cases compared to the forward voltage drop of the associated DSDB-BJT (e.g., 0.2 V to 0.6 V). It should also be noted that while the shutoff current through the collector-emitter opposite the positive polarity during the transition from on to off may have a peak current approximately equal to the load current, the collector-emitter regions and connections may not be designed to handle the full load current for extended periods of time; the inventors herein have found through simulations that, given the transient characteristics of the shutoff current (e.g., 1 μs to 3 μs), even a shutoff current with a peak equal to the load current does not adversely affect device operation.

[0098] Although many of the electrical connections in the drawings are shown as direct couplings with no intervening devices, they are not explicitly stated as such in the description above. Nevertheless, this paragraph serves as a prerequisite for referring to electrical connections in the claims as "directly coupled" with respect to electrical connections with no intervening devices shown in the drawings. Also, this paragraph does not preclude a base that is electrically connected to a collector-emitter through a transistor from being referred to as "directly coupled."

[0099] The above description is intended to be illustrative of the principles and various embodiments of this invention. Numerous modifications and variations will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such modifications and variations.

Claims

1. 1. A method of operating a power module having a bidirectional double-base bipolar junction transistor, comprising: conducting a first load current from an upper terminal of the power module to an upper base of the transistor, through the transistor, and from a lower base to a lower terminal of the power module; and then, in response to assertion of a first shut-down signal, interrupting the first load current from the lower base to the lower terminal by opening a lower main FET and diverting a first shutoff current through the lower collector-emitter of the transistor to the lower terminal; and blocking current flow from the upper terminal to the lower terminal by the transistor; How to have that.

2. During the conducting, the method further includes injecting charge carriers into the upper collector-emitter; The method further includes halting the injection of charge carriers into the upper collector-emitter in response to the assertion of the first blocking signal. The method of claim 1.

3. 3. The method of claim 2, wherein stopping the injection of charge carriers further comprises stopping the injection of charge carriers a non-zero predetermined time before interrupting the first load current by opening the lower main FET.

4. interrupting the first load current further comprises interrupting the first load current using the lower main FET having a breakdown voltage of 100 volts or less; Blocking the current further comprises blocking when the applied voltage across the upper terminal and the lower terminal is 600 volts or greater. The method of claim 1.

5. 2. The method of claim 1, wherein diverting the first shutoff current further comprises coupling the lower collector-emitter to the lower terminal.

6. 6. The method of claim 5, wherein coupling the lower collector-emitter to the lower terminal further comprises coupling the lower collector-emitter to the lower terminal with a voltage source or a current source.

7. After blocking the current from the upper terminal to the lower terminal, conducting a second load current from the lower terminal of the power module to the lower base of the transistor, through the transistor, and from the upper base to the upper terminal; and then, in response to assertion of a second shut-down signal, interrupting the second load current from the upper base to the upper terminal by opening an upper main FET and diverting a second shutoff current through the upper collector-emitter to the upper terminal; and blocking current flow from the lower terminal to the upper terminal by the transistor; The method of claim 1 further comprising:

8. interrupting the second load current further comprises interrupting the second load current using the upper main FET having a breakdown voltage of 100 volts or less; and blocking current from the lower terminal to the upper terminal further comprises blocking when an applied voltage across the lower terminal and the upper terminal is 600 volts or greater. The method of claim 7.

9. 1. A switch assembly comprising: an upper terminal, a lower terminal, and an upper control input; a transistor defining an upper base, an upper collector-emitter, a lower base, and a lower collector-emitter; an upper main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper base, and a gate; a lower main FET defining a first lead coupled to the lower base, a second lead coupled to the lower terminal, and a gate; a controller coupled to the upper control input, the gate of the upper main FET, and the gate of the lower main FET, wherein for a first applied voltage across the upper and lower terminals, the controller: asserting the gate of the upper main FET to cause the upper main FET to conduct, configuring the transistor for conduction from the upper base to the lower base, and asserting the gate of the lower main FET to cause the lower main FET to conduct, thereby causing a first load current to flow from the upper terminal to the lower terminal; detecting a deassertion of the upper control input; and in response to the deassertion of the upper control input, deasserting the gate of the lower main FET to cut off the first load current from the lower base; a controller configured to A switch assembly having

10. 10. The switch assembly of claim 9, wherein the breakdown voltage of said transistor is greater than or equal to 600 volts and the breakdown voltage of said lower main FET is less than or equal to 100 volts.

11. 10. The switch assembly of claim 9, wherein the breakdown voltage of said transistor is about 1200 volts and the breakdown voltage of said lower main FET is 80 volts or less.

12. The switch assembly further comprises: an upper CE source and an upper CE FET, the upper CE source configured to selectively inject charge carriers into the upper collector-emitter through the upper CE FET; and when the controller configures the transistor for conduction from the upper base to the lower base, the controller is further configured to cause the upper CE FET to conduct to inject charge carriers into the upper collector-emitter; When the controller detects the deassertion of the upper control input, the controller is further configured to render the upper CE FET non-conductive to stop injection of charge carriers into the upper collector-emitter. The switch assembly of claim 9.

13. 13. The switch assembly of claim 12, wherein when the controller makes the upper CE FET non-conductive, the controller is configured to make the upper CE FET non-conductive a non-zero predetermined time period before deasserting the gate of the lower main FET.

14. 13. The switch assembly of claim 12, wherein the controller is further configured to electrically float the upper collector-emitter when the controller detects the deassertion of the upper control input.

15. The switch assembly further comprises: a lower CE FET defining a first lead coupled to the lower collector-emitter, a second lead coupled to the lower terminal, and a gate coupled to the controller; and When the controller detects the deassertion of the upper control input, the controller is further configured to assert the gate of the lower CE FET to divert shut-off current to the lower terminal. The switch assembly of claim 9.

16. The switch assembly further comprises: a lower CE source configured to selectively extract charge carriers from the lower collector-emitter through the lower CE FET; and When the controller detects the deassertion of the upper control input, the controller is further configured to cause the lower CE FET to conduct and extract charge carriers from the lower collector-emitter.

16. The switch assembly of claim 15.

17. The switch assembly further comprises: a lower control input coupled to the controller; and For a second applied voltage across the upper terminal and the lower terminal, the second applied voltage having an opposite polarity to the first applied voltage, the controller: asserting the gate of the lower main FET to cause the lower main FET to conduct, configuring the transistor for conduction from the upper base to the lower base, and asserting the gate of the upper main FET to cause the upper main FET to conduct, thereby causing a second load current to flow from the lower terminal to the upper terminal; detecting a deassertion of the lower control input; and in response to the deassertion of the lower control input, deasserting the gate of the upper main FET to cut off the second load current from the upper base; It is configured as follows: The switch assembly of claim 9.

18. The switch assembly further comprises: a lower CE source and a lower CE FET, the lower CE source configured to selectively inject charge carriers into the lower collector-emitter through the lower CE FET; and when the controller configures the transistor for conduction from the lower base to the upper base, the controller is further configured to cause the lower CE FET to conduct to inject charge carriers into the lower collector-emitter; When the controller detects the deassertion of the lower control input, the controller is further configured to render the lower CE FET non-conductive to stop injection of charge carriers into the lower collector-emitter.

18. The switch assembly of claim 17.

19. A method of operating a bidirectional double-base bipolar junction transistor, conducting the transistor from the upper base to the lower base by supplying current to the upper collector-emitter of the transistor and electrically floating the lower collector-emitter of the transistor; and rendering the transistor non-conductive by electrically floating the upper collector-emitter, electrically floating the lower base, and conducting a shutoff current through the lower collector-emitter of the transistor; How to have that.

20. 20. The method of claim 19, wherein electrically floating the lower base further comprises rendering a lower main electrically controlled switch having a first lead coupled to the lower base non-conductive.

21. Making the transistor conductive further comprises: closing an upper main electrically controlled switch coupled between an upper terminal and the upper base; closing a lower main electrically controlled switch coupled between the lower terminal and the lower base; 20. The method of claim 19, comprising:

22. Rendering the transistor non-conductive further comprises: opening the upper main electrical control switch; conducting the shutoff current to the upper base through a diode associated with the upper main electrically controlled switch; Diverting the shutoff current from the lower base to the lower collector-emitter by opening the lower main electrically controlled switch; 22. The method of claim 21, comprising:

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