Reusable templates for semiconductor design and manufacturing

Abstract

The substrate includes locations for coupling one or more chiplets to the substrate, the locations having dimensions bounding the dimensions of the chiplets coupleable to the substrate in the locations, and the locations additionally include an interface region having connections for one or more die-to-die interfaces of the one or more chiplets and a power region including a power interface having connections for one or more chiplets.

Description

[Background technology]

[0001] Various chiplets can be bonded to a substrate and to each other to form a semiconductor assembly. Different chiplets often have different dimensions, along with different dimensions for connections on the substrate for the different chiplets. Traditionally, substrates for semiconductor assemblies are designed for specific combinations of chiplets, resulting in customized design and manufacture of substrates for each combination of chiplets used. [Brief explanation of the drawings]

[0002] [Figure 1] FIG. 1 illustrates an exemplary reusable template according to certain embodiments disclosed herein. [Figure 2] 1A-1C illustrate template-based semiconductor assembly designs according to some embodiments. [Figure 3] 3 shows another design of a semiconductor assembly based on the same template of FIG. 2. [Figure 4] 3A and 3B show yet another design of a semiconductor assembly based on the same template of FIG. 2. [Figure 5] 3 shows another variation of the design of a semiconductor assembly based on the same template as in FIG. 2. [Figure 6] 1 is a cross-sectional view of a semiconductor assembly designed according to a template, in accordance with an embodiment of the present disclosure. [Figure 7] FIG. 2 illustrates a graphical representation of an exemplary template for a substrate of a semiconductor assembly, according to an embodiment of the present disclosure. [Figure 8] FIG. 10 illustrates an overhead graphical representation of another exemplary template for a substrate of a semiconductor assembly, in accordance with an embodiment of the present disclosure. [Figure 9]1 is a cross-sectional view of an exemplary integrated circuit device including a substrate formed based on a template selected from a set of templates, according to some embodiments. [Figure 10] FIG. 1 illustrates an exemplary computing device, according to some embodiments. [Figure 11] FIG. 1 is a cross-sectional view of an exemplary integrated circuit device including a substrate formed based on a reusable template that specifies one or more external connections for a second chiplet, according to some embodiments. [Figure 12] 1 is a flowchart of an exemplary method for manufacturing a semiconductor assembly device designed using a reusable substrate template, according to some embodiments. [Figure 13] 1 is a flowchart of an exemplary method for generating a template for forming a substrate, according to some embodiments. [Figure 14] 1 is a flowchart illustrating an exemplary method for manufacturing a semiconductor assembly from a template-based layout file described herein. DETAILED DESCRIPTION OF THE INVENTION

[0003] Different chiplets that are bonded together to form a semiconductor assembly have different dimensions (e.g., length and width). When designing a semiconductor assembly, the combination of chiplets and their positions relative to one another are used to determine the size and location of the interface between each chiplet and the substrate. This involves designing a unique substrate for each configuration of chiplets in a different semiconductor assembly. Such individualized design of the substrate for each semiconductor assembly increases the amount of time to manufacture different semiconductor assemblies by incorporating additional time to create specific substrate designs for the different dimensions of the chiplets and the different relative positions of the chiplets in the different semiconductor assemblies. Furthermore, such individualized design of the semiconductor assembly-specific substrate prevents the substrate from being reused for different semiconductor assemblies, increasing manufacturing costs and manufacturing time for the different semiconductor assemblies.

[0004] While efforts have been made to provide electrical specifications that are applicable across a range of chiplets, previous efforts have not addressed the different dimensions for the interfaces of different chiplets. This lack of standardization for chiplet sizing results in designing unique package substrates for different combinations of chiplets and different locations of the chiplets relative to one another on the package substrate. Furthermore, while maintaining multiple locations on a substrate with identical dimensions provides some flexibility for the chiplets that can be bonded to the substrate, maintaining common dimensions for each location prevents dimensional variation for different chiplets bonded to the substrate.

[0005] To enable reuse of substrate designs having multiple chiplets with different dimensions, this specification describes various embodiments of templates for substrates. As used herein, the term “template” generally refers to one or more data structures (e.g., one or more files) that specify the layout of a substrate, including the locations of connectors on the substrate and routing information for connections between the connectors, such as conductive traces that couple a connector at one location on the substrate to a connector at another location on the substrate. In various embodiments, other design information for the substrate is included in the template. In various embodiments, a substrate formed from the template includes locations for several chiplets to be bonded to the substrate. Such a template can be used as a basis in the design process for a particular semiconductor package that includes the substrate and various other components. For example, a single template can be used to design and manufacture different semiconductor assemblies that include different chiplets with different dimensions bonded to specific locations on the substrate. This allows different chiplets with different dimensions to be bonded to specific locations on the substrate, providing greater flexibility in semiconductor assembly design. Additionally, manufacturing a substrate from a template allows for the reuse of a common substrate for chiplets with different dimensions, rather than manufacturing specific substrates to accommodate the specific dimensions of the different chiplets.

[0006] In some embodiments, a template has a first location for coupling a first chiplet to a substrate and a second location for coupling one or more additional chiplets to the substrate. The second location includes an interface region on the substrate and a power region including a power interface. The power interface includes connections for one or more additional chiplets. This allows a substrate formed using a particular template to include multiple additional chiplets having dimensions that do not exceed the dimensions of the second location. In this way, the template enables reuse of a substrate layout across multiple designs and provides increased flexibility for coupling additional chiplets having different sizes to substrates fabricated from the template.

[0007] In some embodiments, the substrate includes locations for coupling one or more chiplets to the substrate, the locations having dimensions that limit the dimensions of additional chiplets that can be coupled to the substrate at the locations. The locations include an interface region including connections for one or more die-to-die interfaces of the one or more chiplets and a power region including a power interface with connections for the one or more chiplets. In some embodiments, the substrate includes an additional location for coupling a first chiplet to the substrate, the additional location including connections for coupling the first chiplet to the substrate. In some embodiments, the substrate includes connections between the interface region at the location and the interface region at the additional location.

[0008] In some embodiments, a chiplet has dimensions that do not exceed the dimensions of the location. In some embodiments, the width of a chiplet does not exceed the width of the location. In some embodiments, the length of a chiplet does not exceed the length of the location. In some embodiments, the combined width of multiple chiplets does not exceed the width of the location. In some embodiments, the combined length of multiple chiplets does not exceed the length of the location.

[0009] In some embodiments, the location includes a sideband region, and the substrate includes a connection between the sideband region and a second sideband region at a different location for a sideband interface between the chiplet at the location and another chiplet at a different location, the sideband interface extending across the die-to-die interface. In some embodiments, the location includes an external connection including a connection that couples the chiplet to one or more components external to the semiconductor assembly including the substrate, and the substrate includes a connection path from the connection in the external connection region to the external connection.

[0010] This specification further describes a semiconductor assembly including a substrate. The substrate includes locations for coupling one or more chiplets to the substrate, the locations having dimensions that limit the dimensions of additional chiplets that can be coupled to the substrate at the locations. The locations include an interface region including connections for one or more die-to-die interfaces of the one or more chiplets and a power region including a power interface with connections for the one or more chiplets. The semiconductor assembly also includes at least one chiplet coupled to at least a subset of the connections in the interface region and to a subset of the connections in the power region, the at least one chiplet having dimensions that do not exceed the dimensions of the location.

[0011] In various embodiments, the substrate further includes an additional location for coupling the first chiplet to the substrate, the additional location including a connection for coupling the first chiplet to the substrate, hi some embodiments, the semiconductor assembly includes the first chiplet coupled to the additional location.

[0012] In some embodiments, the at least one chiplet comprises multiple chiplets, the combined width of which does not exceed the width of the location. In various embodiments, the at least one chiplet comprises multiple chiplets, the combined length of which does not exceed the length of the location. In some embodiments, a subset of the connections in the power domain of the location are not coupled to the chiplet. In various embodiments, a subset of the connections in the interface domain of the second location are not coupled to the chiplet.

[0013] In some embodiments, the location includes a sideband region, and the substrate includes a connection between the sideband region and a second sideband region in a different location for a sideband interface between the chiplet in the location and another chiplet in a different location, the sideband interface extending the die-to-die interface, and the chiplet is coupled to one or more connections in the sideband region. In various embodiments, the location includes an external connection including a connection that couples the chiplet to one or more components external to the semiconductor assembly including the substrate, and the substrate includes a connection path from the connection in the external connection region to the external connection.

[0014] In another embodiment, a method for manufacturing a semiconductor assembly includes obtaining a first location for bonding a first chiplet to a substrate and obtaining a second location for bonding one or more additional chiplets to the substrate. The second location includes an interface area on the substrate for connections for one or more die-to-die interfaces between the first chiplet and the one or more additional chiplets, a power area on the substrate in the second location for a power interface including connections for the one or more additional chiplets, and dimensions for the power interface. The method further includes generating a layout file for the substrate based on the selected template.

[0015] In some embodiments, the input from the user further identifies a dedicated interface region within the first location and a dedicated interface region within the interface region of the second location for a second die-to-die interface having one or more characteristics.

[0016] The following disclosure provides many different embodiments or examples for implementing different features of the provided invention. To simplify the disclosure, specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature formed above or on a second feature includes embodiments in which the first and second features are formed in direct contact, as well as embodiments in which an additional feature is formed between the first and second features such that the first and second features are in direct contact. Furthermore, spatially relative terms such as "beneath," "below," "lower," "above," "upper," "back," "front," "top," "bottom," etc. are used herein to facilitate descriptions that describe the relationship of one element or feature to another element(s) or feature(s), as shown in the figures. Similarly, terms such as "front" and "back" or "top" and "rear" are used herein to more easily identify various components and to identify those components as, for example, opposite sides of another component. Spatially relative terms are intended to encompass different orientations of the device during use or processing in addition to the orientation depicted in the figures.

[0017] FIG. 1 is an overhead view of a graphical representation of a template 100 for a substrate of a semiconductor assembly. In embodiments, the graphical representation of the template (such as those shown in FIGS. 1-8) may be rendered on a display in a graphical user interface of an EDA tool or other application. For simplicity, each graphical representation of the layout is referred to herein as the template itself. Template 100 includes a first location 110 on a substrate where a first chiplet is to be bonded to the substrate. Similarly, template 100 includes a second location 120 on the substrate where one or more additional chiplets are to be bonded to the substrate. As described further herein, an additional chiplet having dimensions not exceeding those of second location 120 can be bonded to the substrate at second location 120, allowing different additional chiplets having different dimensions to be bonded to a substrate fabricated based on template 100.

[0018] In various embodiments, the template 100 includes data describing the dimensions of the substrate (e.g., the length and width of the substrate) and different locations within the substrate. The first location 110 has a length and width specified by the template 100. For example, the template 100 includes coordinates of the first location 110 relative to a reference point on the substrate, such as the coordinates of a corner of the first location 110 relative to a particular corner of the substrate. However, in other embodiments, the template 100 identifies the first location 110 within the substrate using any suitable reference point or description of the dimensions of the first location. Similarly, the second location 120 has a length and width specified by the template 100. For example, the template 100 includes coordinates of the second location 120 relative to a reference point on the substrate, such as the coordinates of a corner of the second location 120 relative to a particular corner of the substrate. In other embodiments, the template 100 specifies the coordinates of the second location 120 relative to the location of the first location 110 on the substrate. However, in other embodiments, the template 100 uses any suitable reference point or dimensional description of the first location 110 to identify the second location 120 within the substrate.

[0019] A first location 110 at which a first chiplet is coupled to a substrate in template 100 includes an interface region 117 that designates a location on the substrate for connections for one or more die-to-die interfaces. The die-to-die interfaces included in the first chiplet couple the first chiplet to one or more additional chiplets that are also coupled to the substrate, and the substrate includes electrical connections between the interface region 117 in the first location 110 for the first chiplet and one or more interface regions 127 in a second location 120 on the substrate where the one or more additional chiplets are coupled to the substrate as designated by template 100. Thus, connections in the interface region 117 in the first location 110 on the substrate are coupled to one or more connections in the interface region 127 of the second location 120 to enable communication between the one or more chiplets at the second location 120 and the first chiplet at the first location 110. Template 100 specifies locations on the substrate where interface region 117 specifies locations on the substrate for coupling the die-to-die interface of the first chiplet to the substrate, and where the die-to-die interfaces of one or more additional chiplets are coupled to the substrate at interface region 127 in second location 120. In various embodiments, the connections on the substrate for coupling the die-to-die interface of the first chiplet and the additional chiplets are solder bumps. Interface region 117 and interface region 127 specify, in various embodiments, the density of the solder bumps, the number and placement of the solder bumps, and / or the spacing between the solder bumps.

[0020] The first location 110 on the substrate designated for the first chiplet also includes a power area 115 that includes connections between the first chiplet and power and ground planes (not shown here). Thus, the power area 115 specifies the location within the substrate of connections for providing power to the first chiplet through the substrate. In various embodiments, the connections for providing power to the first chiplet are solder bumps. In some embodiments, the power area 115 at the first location 110 includes connections between the first chiplet and other signals. For example, a first set of connections within the power area 115 couples the first chiplet to power and ground planes, and a second set of connections within the power area 115 connects the first chiplet to other signals or other components. In various embodiments, the power area 115 specifies the density of solder bumps or the spacing between solder bumps. In other embodiments, different connections are used in the power area 115. Exemplary connections include conductive pillars, pins, pads, one or more silicon bridges, one or more silicon interposers, and integrated fan-out (InFO) connections.

[0021] Second location 120 on substrate also includes power area 125. Power area 125 designates a location on the substrate for coupling the power interface of one or more additional chiplets to power through the substrate. In various embodiments, the connections that provide power to the one or more additional chiplets are solder bumps, and the substrate includes solder bumps at the second location designated by power area 125. Power area 125 designates the density of the solder bumps or the spacing between the solder bumps in various embodiments. Other connectors are used to provide power, ground, or signals to the chiplets in different embodiments. Exemplary connections include conductive pillars, pins, pads, one or more silicon bridges, one or more silicon interposers, and InFO connections.

[0022] Template 100 specifies one or more dimensions of both interface region 127 and power region 125. Different templates 100 can include varying dimensions for both or either locations. The term "dimension" here refers to any combination of length, width, height, spacing between connections, density of connections, size of connections, type of connections, etc. For illustrative purposes, FIG. 2 shows second location 120 for coupling one or more additional chiplets to a substrate, having length 140 and width 130. Other templates 100 can have different widths for power region 125, different lengths for power region 125, or different widths and lengths for power region 125, with the different dimensions resulting in corresponding differences in the length and width of second location 120. In various embodiments, the dimensions of the interface region 127 for the one or more additional chiplets are consistent across different templates 100, allowing the interface region 127 for coupling the one or more additional chiplets to the first chiplet to have consistent dimensions across multiple templates 100, while one or more dimensions of the power region 125 for the one or more additional chiplets vary across different templates 100.

[0023] The dimensions of second location 120 allow chiplets having different dimensions to be coupled to the substrate in second location 120. In the example shown by FIG. 1 , an additional chiplet having a width not greater than width 130 and a length not greater than length 140 can be coupled to the substrate in second location 120 and coupled to power and ground via connections in power region 125, while being coupled to the first chiplet via connections in interface region 127. Thus, the dimensions of second location 120 specified by template 100 specify a range of dimensions for the additional chiplet that can be present in a substrate formed using template 100. This allows chiplets of various sizes to be coupled to a substrate designed according to template 100, and allows the substrate to be reused in various combinations of the first chiplet and different additional chiplets having dimensions not exceeding the dimensions of second location 120 for coupling one or more additional chiplets to the substrate. In contrast, conventionally designed substrates are custom-designed for a particular combination of chiplets, preventing chiplets other than those for which the conventional substrate was designed from being coupled to the substrate. This custom construction of the substrate increases the production time of the semiconductor assembly by introducing time to design the substrate for a particular combination of chiplets and time to manufacture the designed conventional substrate.

[0024] In various embodiments, template 100 is generated by an EDA system based on a design specified by a chip designer. The chip designer can use, for example, a graphical user interface of the EDA system to specify design parameters for template 100, including the dimensions of the substrate, the dimensions of each region, the coupling between connections within the regions, the type and density of such connections, etc. Once such parameters are specified, the EDA system obtains coordinates or other information identifying the position of a first location 110 on the substrate and, based on the graphical design (or other input provided by the chip designer), obtains coordinates or other information identifying the position of a second location 120 on the substrate. The information identifying the position of first location 110, in some embodiments, includes the dimensions (e.g., length and width) of first location 110 and at least a reference coordinate of first location 110 within the substrate. Similarly, the information identifying the position of second location 120, in some embodiments, includes the dimensions (e.g., length and width) of second location 120 and at least a reference coordinate of second location 120 within the substrate. The EDA system generates a template from the positions of the first locations 110 and the second locations 120 on the substrate and uses the template to generate a layout file that includes coordinates on the substrate of the first locations 110, coordinates of connections within the first locations 110, coordinates on the substrate of the second locations 120, and coordinates of the connections within the second locations 120, as well as conductive paths that connect the connections to one another. The layout file is stored and later used to manufacture a substrate that is the basis for a semiconductor device designed by a user. In some embodiments, the layout file can be loaded into the EDA system by a chip designer and used as the basis for designing a semiconductor device having various chiplets.

[0025] The template layout file generated by the EDA system includes the coordinates on the substrate of first location 110. The layout file includes coordinates of connections in interface region 117 and interface region 127 of second location 120 that couple the die-to-die interface of the first chiplet to the die-to-die interface of the additional chiplet via one or more traces, metallization layers, redistribution layers (RDL), etc. (not shown). Similarly, the layout file includes coordinates of power interface connections in power region 115. The power interface connections couple power and ground planes (not shown) to the first chiplet. For example, the connections in first location 110 are solder bumps, and therefore the layout file identifies locations on the substrate where the solder bumps will be placed when the substrate is formed. In various embodiments, the coordinates on the substrate of first location 110 and the connections in first location 110 are specified relative to a reference position on the substrate. Other examples of connections include conductive pillars, pins, pads, one or more silicon bridges, one or more silicon interposers, and InFO connections. Thus, the layout file specifies the position on the substrate to which the first chiplet is to be coupled, and specifies locations on the substrate for connections between the substrate and the pins or other connectors of the first chiplet.

[0026] The layout file of template 100 also includes coordinates of second location 120 and coordinates of placement of connections of the die-to-die interface within interface region 127 of second location 120 on the substrate. The layout file also specifies coordinates on the substrate for coupling the die-to-die interface of one or more additional chiplets to the substrate for communication (via one or more traces, RDL layers, metallization layers, etc.) with the die-to-die interface of the first chiplet. Similarly, the layout file includes coordinates for placement of connections for the power interface within power region 125 of the second location on the substrate. The layout file also specifies coordinates of connections coupling the additional chiplets to power and / or ground planes. For example, the connections in second location 120 are solder bumps, and thus the layout file identifies locations on the substrate where the solder bumps will be placed when the substrate is formed during manufacturing. In various embodiments, second location 120 and the coordinates on the substrate of the connections in second location 120 are specified relative to a reference position on the substrate.

[0027] In some embodiments, the layout file is a Graphic Design System Stream Format (GDSII) file that specifies the positions of the first location 110 and the second location 120 relative to a reference location on the substrate, and the locations for the connections and conductive traces that couple the different connections through the substrate. In other embodiments, the layout file is a Caltech Intermediate Form (CIF) file, an Open Artwork System Interchange Standard (OASIS) file, or an Electronic Design Interchange Format (EDIF) file. In other embodiments, the layout file is an alternative manufacturing specification for the substrate that includes information specifying the positions of the first location 110 and the second location 120 on the substrate and the coordinates within the first location 110 and the second location 120 for the connections for coupling the first chiplet and the additional chiplet to the substrate, respectively.

[0028] In various embodiments, the substrate is formed according to a layout file generated from the template-based design. When forming the substrate, connections for one or more die-to-die interfaces are positioned at coordinates specified by the layout file. Thus, connections for coupling to the die-to-die interfaces of the first chiplet and one or more additional chiplets are formed on the substrate at coordinates of interface region 117 within first location 110 on the substrate for the first chiplet, as specified by the layout file. Similarly, connections are formed on the substrate at coordinates within one or more interface regions 127 at second location 120 on the chiplet to couple to one or more additional chiplets based on the layout file. In various embodiments, the layout file specifies the density of the connections or the spacing between the connections. The connections are solder bumps in various embodiments, although other types of connections are used in other embodiments.

[0029] Similarly, connections for coupling power or ground planes to one or more additional chiplets are formed on the substrate according to the layout file. Thus, connections are formed on the substrate at locations within power region 125 of second location 120 on the substrate to couple one or more additional chiplets to the substrate based on coordinates specified by the layout file. In various embodiments, the template layout file specifies the density of the connections or the spacing between the connections. In various embodiments, the connections are solder bumps, although other types of connections are used in other embodiments. Other exemplary types of connections include conductive pillars, pins, pads, one or more silicon bridges, one or more silicon interposers, and InFO connections. The layout file generated from the design based on the template specifies one or more dimensions, such as the length and width of power region 125, in which coordinates of connections for coupling power to one or more additional chiplets through the substrate are located, allowing additional chiplets having dimensions no greater than the dimensions of second location 120 on the substrate to be coupled to connections on the substrate for die-to-die interfacing with the first chiplet and to be coupled to connections on the substrate to receive power within second location 120 on the substrate. Similarly, connections on the substate for coupling to the die-to-die interface of the first chiplet are formed at the first location 110 where the first chiplet is coupled to the substrate, and include connections in an interface region 117 of the first location 110 for coupling to the die-to-die interface of the first chiplet and connections in a power region 115 for coupling power to the first chiplet.

[0030] In some embodiments, the template 100 is included in a set of templates. In some embodiments, different sets of templates 100 are maintained for different first chiplets, allowing the different sets of templates 100 to account for different dimensions of the different first chiplets. One set of templates for a particular I / O controller chiplet may be stored, for example, along with one set of templates for a particular memory chiplet. Furthermore, in some embodiments, different sets of templates 100 are maintained for different first locations 110 where the first chiplet will be coupled to the substrate. For example, one set of templates may include a particular I / O controller chiplet vertically, and another set of templates may include the same particular I / O controller chiplet horizontally. Thus, in some embodiments, a set of templates 100 is retrieved (for design purposes) after a first chiplet is selected. From that point on, a designer can select one of the set templates based on other criteria, such as parameters of second locations within the templates and other chiplets the designer intends to include in the design. In other embodiments, the set of templates 100 is not extracted based on the first chiplet, but rather based on other criteria, such as substrate dimensions, the number of chiplets to be coupled to the substrate, one or more particular types of chiplets to be coupled to the substrate, or other suitable criteria.

[0031] In various embodiments, different templates 100 of the set have different dimensions for second locations 120 on the substrate, where the second locations 120 specify locations where one or more additional chiplets can be bonded to the substrate. In some embodiments, each template 100 of the set has one or more dimensions for the second locations 120 that differ from the other templates 100 of the set. For example, a first template of the set has dimensions for the second locations 120 that differ from corresponding dimensions for the second locations 120 specified by a second template of the set.

[0032] Further, in some embodiments, different templates in the set have one dimension of the second location 120 that is common across the templates in the set, and another dimension of the second location 120 varies across the different templates in the set. For example, each template in the set has a common width of the second location 120, but different lengths of the second location 120. In embodiments in which a set of templates is maintained, one of the templates 100 is selected via the EDA system, and the EDA system generates a layout file from the selected template 100 for fabricating a substrate. The templates may be stored in a repository, a database, an online storage location, a file system, or, in different embodiments, may be included as a library for the EDA system software. Selection of one of the templates may be made by the EDA system based on a user's selection of a template, based on a history of template access (e.g., reloading a last-used template), based on receipt of identification information for a particular chiplet from a user, based on a user specification of one or more design parameters, etc.

[0033] For further illustration, Figures 2, 3, 4, and 5 show different semiconductor assembly designs based on the same template. Figure 2 shows a semiconductor design based on template 100, as further described above in connection with Figure 1. The layout of Figure 2 shows a first chiplet 205 coupled to connections in interface region 117 of first location 110 and coupled to connections in power region 115 of first location 110. The connections in interface region 117 of the first location couple the die-to-die interface of first chiplet 205 to the substrate, while the connections in power region 115 couple the first chiplet to power and ground planes via substrate 200 fabricated based on template 100.

[0034] The layout of FIG. 2 also shows two additional chiplets: second chiplet 210A and third chiplet 210B. Second chiplet 210A is coupled to a subset of connections in second location 120, and third chiplet 210B is coupled to a different subset of connections. Second chiplet 210A includes a die-to-die interface that is coupled to connections on the substrate in interface region 127, allowing second chiplet 210A to communicate with first chiplet 205 via connections between interface region 127 and interface region 117. Second chiplet 210A is also coupled to power and ground planes via connections in power region 125. Similarly, third chiplet 210B includes a die-to-die interface that is coupled to connections in interface region 127, allowing communication with first chiplet 205 (and in some embodiments, second chiplet 210A) via connections between interface region 127 and interface region 117. Also, the third chiplet 210B is coupled to the power and ground planes via connections in the power region 125. As shown in Figure 2, some connections in the power region 125 of the second location 120 are not coupled to any of the chiplets. That is, chiplets having dimensions smaller than corresponding dimensions in the second location 120 will be coupled to the substrate 200 in the second location 120.

[0035] 2, the length 215 of the second chiplet 210A and the length 215 of the third chiplet 210B are less than the length 140 of the second location 120. Similarly, the width 220 of the second chiplet 210A and the width 220 of the third chiplet 210B are less than the width 130 of the second location 120. In various embodiments, the combined dimension of each of the additional chiplets 210A, 210B does not exceed the corresponding dimension of the second location 120. For example, as shown in FIG. 2, the sum of the width 220 of the second chiplet 210A and the width 220 of the third chiplet 210A does not exceed the width 130 of the second location 120.

[0036] For further explanation, FIG. 3 shows another exemplary semiconductor design having a layout based on template 100 for substrate 200. The semiconductor assembly shown in FIG. 3 includes a first chiplet 205 coupled to connections in interface region 117 to connections in power region 115, similar to that of FIG. 2. The exemplary semiconductor assembly shown in FIG. 3 includes chiplet 210B coupled to a subset of connections in second location 120 on substrate 200 and an alternate chiplet 305 coupled to another subset of connections in second location 120. Chiplet 305 is referred to as “alternate” to chiplet 210A of FIG. 2. The alternate chiplet 305 includes a die-to-die interface coupled to connections in interface region 127, allowing the alternate chiplet 305 to communicate with the first chiplet 205 via the connections in interface region 127.

[0037] Alternate chiplet 305 has a length 310 equal to the length of second location 120 on substrate 200 for coupling one or more additional chiplets and a width 315 that is less than width 130 of second location 120. As further described above in connection with FIG. 2 , chiplet 210B has a width 220 that is less than width 130 of second location 120 on substrate 200 for coupling one or more additional chiplets and a length 215 that is less than length 140 of second location 120 on substrate 200 for coupling one or more additional chiplets. Thus, the set of connections at second location 120 is not coupled to either alternate additional chiplet 305 or chiplet 210B. As shown in Figures 2 and 3, the dimensions of the second locations 120 on the substrate 200 for bonding one or more additional chiplets specified by the template allow additional chiplets having different dimensions to be bonded to the substrate within the second locations 120 on the substrate 200 for bonding one or more additional chiplets, enhancing the ability to use the substrate 200 for different configurations or designs of semiconductor assemblies.

[0038] To further illustrate, Figure 4 shows a semiconductor assembly design based on the same template 100 as in Figures 2 and 3. The semiconductor assembly shown in Figure 4 includes a first chiplet 205 coupled to connections in interface region 117 of first location 110 and connections in power region 115 of first location 110. The connections in interface region 117 of the first location couple the die-to-die interface of first chiplet 205 to the substrate, while the connections in power region 115 couple the first chiplet to power and ground through substrate 200.

[0039] In the exemplary semiconductor assembly illustrated by FIG. 4 , a second chiplet 405 is coupled to a subset of the connections in a second location 120 on the substrate 200. The second chiplet 405 includes die-to-die interfaces that are coupled to the connections in the interface region 127. The connections in the interface region 127 are coupled to the connections in the interface region 117 via traces, metallization layers, RDLs, etc. Thus, the second chiplet 405 is coupled to the first chiplet 205. The second chiplet 405 is also coupled to connections in the power region 125 that couple the second chiplet 405 to power and ground planes. The second chiplet 405 has a length 410 that is less than the length 140 of the second location 120 on the substrate 200 and a width 415 that is equal to the width 130 of the second location 120. Thus, a set of connections in the second location 120 on the substrate 200 are not coupled to the second chiplet 405 (or to any chiplet). That is, when fabricated, some connections at the second location are not coupled to any chiplet and, in some examples, are exposed. In the example shown by FIG. 4, the set of connections in the second location 120 that are not coupled to the second chiplet 405 are included in the power region 125, while in some embodiments, the connections in the interface region 127 of the second location 120 are not connected to any chiplet.

[0040] FIG. 5 also illustrates a layout of a semiconductor assembly based on the same template 100 as in FIGS. 2-4. Additionally, the first chiplet 305 in the exemplary assembly of FIG. 5 is the same as that in FIG. 4 and is connected to the substrate 200 in a similar manner. A second chiplet 505 is coupled to a subset of the connections in a second location 120 on the substrate 200. The second chiplet 505 has a length 510 equal to the length 140 of the second location 120 and a width 515 that is smaller than the width 130 of the second location 120. Thus, the set of connections in the second location 120 is not coupled to any chiplet. More specifically, the set of connections that are not coupled to any chiplet includes connections in both the power region 125 and the interface region 127 of the second location 120.

[0041] As shown in Figures 2-5, any number of chiplets having a range of dimensions can be coupled to second locations 120 of a substrate fabricated from template 100. This allows template 100 to be reused for different combinations of first chiplets at first locations 110 and one or more second chiplets coupled to second locations 120. Such flexibility in coupling second chiplets having different dimensions to second locations 120 reduces the manufacturing time of semiconductor assemblies by enabling the reuse of the substrate across different combinations of chiplets. Furthermore, second locations 120 of a substrate increase the flexibility of semiconductor assembly design by allowing different second chiplets having different dimensions to be coupled to the substrate within second locations 120.

[0042] For further explanation, FIG. 6 illustrates a cross-sectional view of a semiconductor assembly designed according to a template in accordance with an embodiment of the present disclosure. The exemplary semiconductor assembly of FIG. 6 includes a first chiplet 605 and a second chiplet 610 coupled to a substrate 600 designed using template 100. The first chiplet 605 in the semiconductor assembly illustrated in FIG. 6 is coupled to a connection 615 in the power region 115 of the first location 110 and a connection 615 in the interface region 117 of the first location 110, as further described above in connection with FIGS. 1-5. Similarly, the second chiplet 610 is coupled to a connection 615 in the power region 125 of the second location 120 and a connection 615 in the interface region 127 of the second location 120, as further described above in connection with FIGS. 1-5.

[0043] In the example illustrated by FIG. 6 , the second chiplet 610 is coupled to a subset of the connections 615 in the second location 120, and an additional subset of the connections 615 in the second location 120 remains uncoupled to the second chiplet 610 (or any chiplet). In some embodiments, the additional subset of the connections 615 remains exposed in the semiconductor assembly. In other embodiments, such as the embodiment illustrated in FIG. 6 , the additional subset of the connections 615 is coupled to a layer of material 620. In some examples, the material is silicon or another dielectric material. In various embodiments, the layer of material 620 does not include any active components. Coupling the layer of material 620 to the connections 615 in the second location 120 that are not coupled to the second chiplet 610 allows the semiconductor assembly to have a more uniform distribution of weight and height, improving the balance of the semiconductor assembly.

[0044] 7 shows a graphical representation of an example template 700 for a substrate of a semiconductor assembly. The template 700 includes a first location 110 where a first chiplet (not shown here) is to be coupled to the substrate. The reader will also recognize that in some embodiments, the template may specify multiple different chiplets within the first location 110.

[0045] Template 700 differs from template 100 described above in that interface region 117 of template 700 includes a dedicated interface region 705, and connections on the substrate located within dedicated interface region 705 are configured to exchange signals between a first chiplet and one or more second chiplets in second locations 120 using a second die-to-die interface that is different from the die-to-die interfaces supported by other connections in interface region 117. Stated another way, the “dedicated interface region” includes connections of the chiplet to a “sideband” coupling between the chiplets at the first and second locations, where the sideband coupling is in addition to another die-to-die coupling between the two locations. For example, the second die-to-die interface may be a die-to-die interface provided by the manufacturer of the first chiplet that provides a particular communication format or speed for communicating with the second chiplet. In some embodiments, the distance between connections on the substrate within dedicated interface region 705 or the pitch of the connections on the substrate differs from the distance between connections or the pitch of the connections outside of dedicated interface region 705. In this manner, the dedicated interface regions 705 enable the template 700 to designate locations on the substrate to use different die-to-die interfaces for a second chiplet at a second location to communicate with a first chiplet at a first location. While Figure 7 shows template 700 designating locations of die-to-die interfaces and dedicated die-to-die interfaces, in other embodiments, the template 700 includes any number of different dedicated interface regions 705 within the interface region 117 to identify locations on the substrate for connections using any number of different types of die-to-die interfaces.

[0046] Similarly, template 700 includes a dedicated interface area 710 within interface region 127 of second location 120. Connections on the substrate in dedicated interface region 710 are coupled to connections on the substrate in dedicated interface region 705 to exchange signals between the first and second chiplets using the second die-to-die interface. In this manner, dedicated interface region 710 allows template 700 to designate locations on the substrate to use a different die-to-die interface than supported by connections in other areas of interface region 127 to communicate with chiplets in first location 110. In the example of FIG. 7 , dedicated interface region 715 of second location 120 includes connections for coupling the second chiplet to the substrate so that the second chiplet receives power through the substrate. Dedicated interface region 715 may include connections of a different number, density, type, or pitch and / or may be coupled to power and ground planes with different characteristics than those of the other connections in power region 125. That is, the power region 125 of the template can include a variety of different power and ground connections. While Figure 7 shows template 700 specifying the locations of the die-to-die interface and the second die-to-die interface, in other embodiments, template 700 includes any number of dedicated interface regions 710 within interface region 127 to identify locations on the substrate for connections using any number of different types of die-to-die interfaces.

[0047] In some embodiments, the die-to-die interface supported by connections in interface region 117 outside of dedicated interface region 710 and outside of dedicated interface region 715 is based on a standard. The standard defines the functionality provided by the die-to-die interface. The connections in interface region 117 outside of dedicated interface region 710 and outside of dedicated interface region 715 provide a physical connection for a first chiplet and a second chiplet to communicate with each other based on the standard. Exemplary standards for configuring the die-to-die interface include Universal Chiplet Interconnect Express (UCIe), Open Domain-Specific Architecture (ODSA), Common Hardware for Interfaces, Processors, and Systems (CHIPS) Alliance, or other standards that define communication between chiplets. The second die-to-die interface supported by connections in dedicated interface region 710 and inside dedicated interface region 715 provides functionality different from the functionality provided by the standard. For example, the second die-to-die interface has one or more different communication protocols than the standard-based die-to-die interface or provides additional functionality than the standard-based die-to-die interface. In some embodiments, the second die-to-die interface is determined by the manufacturer of the first chiplet. Thus, the template 700 shown in FIG. 7 allows a second chiplet using a die-to-die interface provided by a standard to be coupled to a substrate for communication with the first chiplet. Additionally or alternatively, the template allows a second chiplet using the second die-to-die interface to be coupled to a substrate for communication with the first chiplet.This allows a substrate formed based on template 700 to support different interfaces for communication between a first chiplet and one or more second chiplets.

[0048] 8 shows a graphical overhead view of another exemplary template 800 for a substrate of a semiconductor assembly. Template 800 includes a first location 110 where a first chiplet (not shown here) is to be coupled to the substrate. The reader will also recognize that in some embodiments, the template may specify multiple different chiplets within first location 110.

[0049] 8 differs from the template 100 described above in that the interface region 117 of the template 800 includes a standardized interface region 805 and a sideband region 815. The standardized interface region 805 includes connections for use with a die-to-die interface for exchanging data between a first chiplet (not shown) in the first location 110 and a second chiplet (not shown) in the second location 120. The connections in the standardized interface region 805 at the first location 110 are coupled to connections in the standardized interface region 810 at the second location 120. As will be further described below in connection with FIG. 11 , the connections in the standardized interface region 805 at the first location 110 are coupled to connections in the standardized interface region 810 at the second location 120 via one or more conductive paths included in a substrate formed based on the template 800.

[0050] In various embodiments, the die-to-die interface between the first and second chiplets supports a particular set of communication functions or protocols for exchanging data between the first and second chiplets. For example, the die-to-die interface is configured based on a standard, and connections within the standardized interface area 805 at the first location 110 and the standardized interface area 810 at the second location 120 provide physical connections for the first and second chiplets to communicate with each other based on the standard. Exemplary standards for configuring the die-to-die interface include UCIe, ODSA, CHIPS Alliance, or other standards that define communication between chiplets. In other examples, the manufacturer of the first chiplet defines communication between the first and second chiplets via the die-to-die interface corresponding to the standardized interface area 805 at the first location 110 and the standardized interface area 810 at the second location 120. Thus, template 800 specifies locations on the substrate where connections will be placed for the first and second chiplets to communicate using the standardized interface.

[0051] In some embodiments, the first and second chiplets communicate via a sideband interface that complements the die-to-die interface between the first and second chiplets. In such embodiments, the die-to-die interface designates communication between the first and second chiplets, and the sideband interface provides another interface between the first and second chiplets. Using the sideband interface, additional communication functionality is provided between the first and second chiplets beyond that provided by the die-to-die interface. Exemplary communication functionality provided by the sideband interface includes additional security, debug capabilities, higher bandwidth input / output connections compared to the die-to-die interface, lower latency input / output connections compared to the die-to-die interface, and other functionality. Thus, the sideband interface extends the die-to-die interface between the first and second chiplets by providing functionality in addition to that provided by the die-to-die interface. In various embodiments, the functionality provided by the sideband interface is based on the combination of the first chiplet and the second chiplet, allowing different combinations of the first chiplet and the second chiplet to have different functionality provided by the sideband interface. In some embodiments, template 800 is stored in association with the combination of the first chiplet and the second chiplet to simplify subsequent retrieval of template 800 to form a substrate supporting the die-to-die interface and the sideband interface between the first chiplet and the second chiplet.

[0052] To implement a sideband interface, the template 800 shown in FIG. 8 includes a sideband region 815 at a first location and a second sideband region 820 at a second location 120. A connection in the sideband region 815 at the first location 110 is coupled to a connection in the second sideband region 820 at the second location 120. This enables a substrate formed from the template 800 to extend communication between a first chiplet and a second chiplet via a standardized interface with a sideband interface that provides additional functionality at the location designated by the sideband region 815. As described further below in connection with FIG. 11, the connection in the sideband region 815 at the first location 110 is coupled to a connection in the sideband region 820 at the second location 120 via one or more conductive paths included in a substrate fabricated based on the template 800, as described further below in connection with FIG. 11. In some embodiments, the distance between connections on the substrate in sideband region 815 is different from the distance between connections on the substrate in standardized interface region 805. Similarly, in various embodiments, the distance between connections on the substrate in second sideband region 820 is different from the distance between connections on the substrate in standardized interface region 810. In other embodiments, the distance between connections is consistent between standardized interface region 805 and sideband region 815, and between standardized interface region 810 and second sideband region 820.

[0053] In addition, template 800 includes external connection region 825 at second location 120. External connection region 825 is a location on the substrate that includes connections that couple the second chiplet to one or more components external to the integrated circuit device that includes the substrate formed from template 800. External connection region 825 designates a location on the substrate for a connection that connects directly to an external connection. In various embodiments, the connection is on a surface of the substrate closest to the second chiplet, and the external connection is on the opposite surface of the substrate. Examples of external connections include pins, solder bumps, or other conductive connections. A connection path through the substrate couples the connection in external connection region 825 to the external connection. The connection path is a conductive material that is coupled to both the connection and the external connection. In some embodiments, the conductive path is coupled to the connection at a first end and to the external connection at a second end. The template 800 specifies locations on the substrate for connections in the external connection region 825, locations on the substrate for the external connections, and information for routing one or more connection paths from connections in the external connection region 825 to the external connections.

[0054] Thus, external connection region 825 allows template 800 to specify locations on the substrate for direct connection of the second chiplet to other components external to the substrate. Exemplary components that may be coupled to the second chiplet via connections in external connection region 825 are a display, a network adapter, a Universal Serial Bus (USB) device, a Serial Advanced Technology Attachment (SATA) device, straps for coupling the second chiplet to a test interface or other device, and other components may be or are coupled to the chiplet via connections in external connection region 825 in various embodiments. Selection of template 800 to form a substrate simplifies placement of connections between the second chiplet and one or more external components using external connection region 825. By including external connection region 825 in template 800, substrates fabricated from template 800 may simplify one or more connections between the second chiplet and other external components via one or more connections included in external connection region 825.

[0055] 8 includes sideband region 815, sideband region 820, and external connections region 825, the template may include information to support either a sideband interface or external connections for a second chiplet. For example, a different template 800 may include sideband region 815 and second sideband region 820 but not external connections region 825. An alternative template may include external connections region 825 but not sideband region 815 or second sideband region 820. Thus, different templates provide different capabilities for communication between the second chiplet and the first chiplet or between the second chiplet and external components.

[0056] 8 illustrates an example template 800 in which the sideband region 815 is included in the interface region 117 of the first location 110, although in other embodiments, the sideband region 815 is in a different position than the interface region 117 in the first location 110. Similarly, in some embodiments, the second sideband region 820 of the second location 120 is in a position within the second location 120 that is outside the interface region 127 of the second location 120. While FIG. 8 illustrates the external connection region 825 of the second location 120 as being physically adjacent to the interface region 127 of the second location, in other embodiments, the external connection region 825 is within the second location 120 but is separate from the interface region 127 of the second location. Thus, in different embodiments, the template 800 can identify different positions of the sideband region 815 within the first location 110 and different positions of the second sideband region 820 and the external connection region 825 within the second location 120.

[0057] Forming a substrate based on template 800 allows different combinations of first and second chiplets to be coupled to the substrate. A second chiplet that communicates with a first chiplet using a die-to-die interface and a sideband interface is coupled to connections in interface region 127 of second location 120 and connections in second sideband region 820 of second location 120. If the second chiplet is also configured to be coupled to one or more external components, the second chiplet is also coupled to connections in external connection region 825 of the second location. However, if the second chiplet is not configured to communicate with the first chiplet using a sideband interface, the second chiplet is coupled to connections in second sideband region 820 of second location 120, but in various embodiments, the connections in second sideband region 820 are internally connected to power or ground. Similarly, when a second chiplet that is not configured to be coupled to an external component is coupled to a connection in external connection region 825, the second chiplet internally connects the connection in external connection region 825 to power or ground. This allows a second chiplet that does not use a sideband interface or is not configured to be coupled to an external component to be coupled to a substrate produced from template 800, allowing increased reuse of template 800 for various combinations of first and second chiplets.

[0058] 9 is a cross-sectional view of an example integrated circuit device 900 including a semiconductor assembly formed from a design based on a reusable template according to embodiments of the present disclosure. The example integrated circuit device 900 can be implemented in various computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, smartphones, etc. (as shown in FIG. 10 ). The example integrated circuit device 900 of FIG. 9 includes a semiconductor assembly 905 including a first chiplet 605 and a second chiplet 610. The first chiplet 605 and the second chiplet 610 are coupled to a substrate 910 fabricated based on the template 100 via one or more connections 615. In various embodiments, the connections 615 are solder balls placed on the substrate 910 at coordinates specified by a layout file generated from the specified template 100.

[0059] The substrate 910 is a piece of material that provides mechanical support for coupled components, such as the semiconductor assembly 905. In some embodiments, the substrate 910 electrically couples various components attached to the substrate 910 via conductive traces, tracks, pads, etc. The substrate 910 electrically couples components of the semiconductor assembly 905 to one or more other components via connecting traces and connections, such as solder joints formed from solder balls coupled to conductive pads. In other embodiments, the substrate 910 uses different types of connections to couple one or more components to the semiconductor assembly 905. Examples of other connections include through holes, sockets, and pins. For example, the substrate 910 electrically couples the first chiplet 605 and the second chiplet 610 through connections 615 and traces within the substrate 910. In various embodiments, the different connections 615 are positioned on the substrate 910 at coordinates specified by a layout file generated from a selected template. 9 , connections 615 in power region 115 on substrate 910 couple first chiplet 605 to power or ground, while connections in interface region 117 are coupled to connections in interface region 127 via traces or the like in substrate 910. In various embodiments, substrate 910 is an organic packaging substrate. In other embodiments, substrate 910 is a silicon interposer that includes connections between first chiplet 605 and one or more second chiplets 610. In other examples, substrate 910 is a glass interposer, an organic interposer, or other structure that includes connectors for coupling to chiplets and conductive paths between different connectors.

[0060] In some embodiments, the connections 615 coupling the semiconductor assembly 905 to the substrate 910 are included in a socket (not shown), and the semiconductor assembly 905 is soldered or otherwise attached to the socket. In other embodiments, as shown in Figure 9, the connections 615 couple the semiconductor assembly 905 to the substrate 910 via direct solder connections or other connections, as can be appreciated. In some embodiments, the semiconductor assembly 905 is coupled to the substrate 910 using a land grid array (LGA), pin grid array (PGA), or other packaging technology, as can be appreciated.

[0061] In one example, semiconductor assembly 905 includes one or more processors 1005 of a computing device 1000, as shown in Figure 10. Computing device 1000 may be implemented as, for example, a desktop computer, a laptop, a server, a game console, a smartphone, a tablet, etc. In addition to one or more processors 1005, computing device 1000 includes memory 1010. Memory 1010 may include random access memory (RAM) or other volatile memory. Memory 1010 may also include non-volatile memory, such as disk storage, solid-state storage, etc.

[0062] In some embodiments, computing device 1000 also includes one or more network interfaces 1015. In some embodiments, network interface 1015 includes a wired network interface 1015, such as an Ethernet or another wired network connection, as may be appreciated. In some embodiments, network interface 1015 includes a wireless network interface 1015, such as a Wi-Fi, BLUETOOTH, cellular, or other wireless network interface 1015, as may be appreciated. In some embodiments, computing device 1000 includes one or more input devices 1020 for accepting user input. Exemplary input devices 1020 include a keyboard, touchpad, touchscreen interface, etc. Those skilled in the art will understand that in some embodiments, input device 1020 includes peripheral devices such as an external keyboard, mouse, etc.

[0063] In some embodiments, computing device 1000 includes a display 1025. In some embodiments, display 1025 includes an external display connected via a video or display port. In some embodiments, display 1025 is contained within the housing of computing device 1000. For example, display 1025 includes the screen of a tablet, laptop, smartphone, or other mobile device. In embodiments in which display 1025 includes a touchscreen, display 1025 also functions as input device 1020.

[0064] 11 is a cross-sectional view of an example integrated circuit device 1100 including a substrate formed based on a reusable template specifying one or more external connections for a second chiplet, according to an embodiment of the present disclosure. The example integrated circuit device 1100 may be implemented in a variety of computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, smartphones, etc. (as further described above in connection with FIG. 10 ). The example integrated circuit device 1100 of FIG. 11 includes a semiconductor assembly 905 including a first chiplet 605 and a second chiplet 610. The first chiplet 605 and the second chiplet 610 are coupled to a substrate 1105 via one or more connections 615. In various embodiments, the connections 615 are solder balls located at coordinates on the substrate 1105 specified by a layout file generated from the template 100.

[0065] In the example illustrated by FIG. 11 , substrate 1105 is formed from a reusable template that specifies coordinates of external connection region 825 of second chiplet 610. For example, substrate 1105 is fabricated from reusable template 800, as further described above in connection with FIG. 8. As further described above in connection with FIG. 8, external connection region 825 includes one or more connections 615 configured to couple second chiplet 610 to one or more components external to integrated circuit device 1100. For example, external connection region 825 provides input / output connections between second chiplet 610 and components external to integrated circuit device 1100. Exemplary components external to integrated circuit device 1100 include a display, a network adapter, a Universal Serial Bus (USB) device, a Serial Advanced Technology Attachment (SATA) device, straps for coupling second chiplet 610 to a test interface or other device, and other components may be or have been coupled to the chiplet via connections in external connection region 825 in various embodiments. Substrate 1105 includes connection 615 in external connection region 825 and connection via 1110 coupled to external connection 1115. Connection via 1110 is a conductive material coupled at one end to connection 615 in external connection region 825 and at the opposite end to external connection 1115. External connection 1115 is external to substrate 1105 and is configured to be coupled to a component external to integrated circuit device 1100. Examples of external connections include pins, solder bumps, or other conductive connections.

[0066] 11 is formed from a layout file based on a reusable template that includes an interface region 117 at a first location 110, an interface region at a second location 120, a sideband region 815 at the first location, and a second sideband region 820 at the second location 120. As further described above in connection with FIGS. 1-6 , connections 615 in the interface region 117 at the first location 110 are coupled to connections 615 in the interface region 127 at the second location 120. These connections provide a die-to-die interface for exchanging data between the first chiplet 605 and the second chiplet 610. For illustrative purposes, FIG. 11 shows conductive paths 1120A, 1120B in the substrate 1105 coupling connections 615 in the interface region 127 at the first location 110 to connections 615 in the interface region 117 at the second location 120. The layout file generated from the reusable template contains instructions for routing conductive paths 1120A, 1120B through the substrate 1105.

[0067] 8 , to provide additional functionality for communication between the first chiplet 605 and the second chiplet 610, the substrate includes a connection 615 in the sideband region 815 at the first location 110 and a connection in the second sideband region 820 at the second location 120. The connection 615 in the sideband region 815 at the first location 110 is coupled to the connection 615 in the second sideband region 820 at the second location 120 through the substrate 1105. FIG. 11 shows a conductive path 1125A coupling the connection 615 in the sideband region 820 at the first location 110 to the connection 615 in the sideband region 815 at the second location 120 through the substrate 1105. 11 shows a conductive path 1125B coupling a second connection 615 in the sideband region 815 at the first location 110 to a second connection 615 in the second sideband region 820 at the second location 120 through the substrate 1105. The layout file generated from the reusable template includes instructions for routing the conductive paths 1125A, 1125B through the substrate 1105.

[0068] 11 includes connections 615 for die-to-die interfaces between the first chiplet 605 and the second chiplet 610 and for sideband communication channels. Additionally, the substrate 1105 enables coupling of the second chiplet 610 to one or more components external to the integrated circuit device 1100 through connections in the external connection region 825, connection paths 1110, and external connections 1115. As shown in FIGS. 9 and 11 , different reusable templates enable different arrangements of the connections 615 on the substrate, allowing for the inclusion of different types of connections between the first chiplet 605 and the second chiplet 610 and other components within the substrate.

[0069] For further explanation, FIG. 12 is a flowchart of an exemplary method for manufacturing a semiconductor assembly having a substrate formed from template 100. In various embodiments, the method described in connection with FIG. 12 is performed by an electronic design automation (EDA) system. In various embodiments, the EDA system includes a processor and a memory encoded with instructions that, when executed by the processor, cause the processor to obtain information describing the placement of one or more components on the substrate and generate one or more layout files that specify the positioning of the one or more components on the substrate and the connections between the components on the substrate. In some embodiments, the EDA system is similar to computing device 1000, further described above in connection with FIG. 10.

[0070] The EDA system obtains 1205 a first location 110 on the substrate for bonding a first chiplet to the substrate and obtains 1210 a second location 120 on the substrate for bonding one or more additional chiplets to the substrate. In various embodiments, the EDA system obtains 1205 the first location 110 and obtains 1210 the second location 120 from one or more inputs provided by a user, such as a designer. For example, the EDA system receives dimensions of the substrate from the user and information identifying a position of the first location 110 and a position of the second location 120 on the substrate from the user. The one or more inputs received from the user specify dimensions of the first location 110 and dimensions of the second location 120. In another example, the EDA system retrieves the positions of the first location 110 and the second location 120 on the substrate from stored data. For example, the EDA system searches for a template that specifies the first location 110 and the second location 120 on the substrate. In some embodiments, the EDA system retrieves the template based on a template selection from a user, while in other embodiments, the EDA system retrieves the template based on one or more stored instructions. In other embodiments, the EDA system retrieves (1205) the first location 110 and retrieves (1210) the second location based on one or more criteria acquired by the EDA system and one or more rules maintained by or received by the EDA system. Exemplary criteria include characteristics (e.g., dimensions, functionality, type) of one or more additional chiplets or characteristics (e.g., dimensions, functionality, type) of the first chiplet. Exemplary rules acquired by the EDA system include the number of additional chiplets, the type of die-to-die interface between the first chiplet and the one or more additional chiplets, the spacing between the first chiplet and the one or more additional chiplets on the substrate, or other rules. The EDA system determines the first location 110 and the second location 120 according to one or more of the rules acquired or maintained by the EDA system.

[0071] In some embodiments, the first location 110 is obtained from a selection of a stored template from a set of templates (1205). Similarly, the second location 120 is obtained from a selection of a stored template from the set of templates (1210). Each template in the set defines a first location 110 for bonding a first chiplet to the substrate and a second location 120 for bonding one or more additional chiplets to the substrate. Different templates in the set include different dimensions of the second location 120 for bonding one or more additional chiplets to the substrate.

[0072] As further described above in connection with FIG. 1 , second location 120 includes power area 125. Power area 125 specifies a location on the substrate for a power interface, including connections for coupling one or more additional chiplets to power through the substrate. In various embodiments, the connections for providing power to the one or more additional chiplets are solder bumps, and the substrate includes the solder bumps at the first location specified by power area 125. Other exemplary connection types include conductive pillars, pins, pads, one or more silicon bridges, one or more silicon interposers, and InFO connections. Power area 125, in various embodiments, specifies the density of the solder bumps or the spacing between the solder bumps. Additionally, second location 120 includes interface area 127 to enable communication between the additional chiplet in second location 120 and the first chiplet in first location 110. Template 100 specifies coordinates on the substrate for connections in interface area 127 where the die-to-die interface of the additional chiplet is coupled to the substrate. Connections in interface region 127 are coupled to connections in interface region 117 of first location 110 to enable communication between the first chiplet and the additional chiplets. Different templates 100 include different dimensions for second locations 120 where one or more additional chiplets are coupled to the substrate. In various embodiments, different templates 100 of the set include one or more different dimensions of power regions 125 on the substrate included in second locations 120.

[0073] From the first location 110 and the second location 120, the EDA system generates (1215) a layout file for the substrate. As further described above in connection with FIG. 1 , the layout file includes coordinates on the substrate for the first location 110 for coupling the first chiplet to the substrate and coordinates within the first location 110 for placement of connections for coupling the first chiplet to the substrate in the first location 110. The layout file also includes coordinates on the substrate for the second location 120 and for placement of connections for one or more die-to-die interfaces in an interface region 127 of the second location 120 on the substrate based on the selected template. In addition, the layout file includes coordinates on the substrate for connections of the power interface in a power region 125 of the second location 120 on the substrate based on the selected template. In various embodiments, the layout file is a GDSII file that specifies the positions of the first location 110 and the second location 120 relative to a reference location on the substrate, and the coordinates of connections within the first location 110, the power region 125, and the interface region 127 relative to the reference location on the substrate, as well as connections between different connections through the substrate (e.g., connections between connections in the interface region 127 and connections in the interface region 117). In other embodiments, the layout file is an alternative manufacturing instruction for the substrate that includes information specifying the positions of the first location 110 and the second location 120 on the substrate and the coordinates within the first location 110 and the second location 120 for connections for coupling the first chiplet and the additional chiplet to the substrate, respectively. In some embodiments, the layout file specifies the location on the substrate of the second location 120 relative to the location on the substrate of the first location 110. In other embodiments, the layout file specifies the location on the substrate of the second location 120 relative to the location on the substrate of the first location 110.The layout file also includes instructions for placing and routing conductive traces that couple connections in the interface region 117 of the first location 110 to connections in the interface region 127 of the second location 120 .

[0074] In some embodiments, a dedicated interface region 705 for a second die-to-die interface having one or more characteristics for coupling to at least one additional chiplet is identified in the first location 110. The layout file further includes coordinates on the substrate for connections in the second interface region of the first location and coordinates on the substrate for connections in the second interface region that are within the interface region of the second location, and in such embodiments, the connections in the second interface region are coupled to the connections in the second interface region. The inclusion of a dedicated interface region 705 in the first location 110 to enable use of the second die-to-die interface is further described above in connection with FIG. 7.

[0075] The EDA system stores 1220 the generated layout file. For example, the EDA system stores 1220 the generated layout file in a non-volatile storage device. However, in other embodiments, the EDA system stores 1220 the generated layout file in another type of storage device. Storing 1220 the generated layout file allows the EDA system to subsequently retrieve the layout file for modification or send it to one or more devices for manufacturing a substrate having a first location 110 for coupling a first chiplet to locations specified by the layout file and a second location 120 for coupling one or more additional chiplets, and having connections in the first location 110 and the second location 120 at coordinates specified by the layout file.

[0076] In some embodiments, the method optionally includes forming 1225 a substrate based on the layout file. Forming 1225 the substrate includes forming connections for one or more die-to-die interfaces at coordinates on the substrate within interface region 127 of second location 120 and forming connections for power interfaces at coordinates on the substrate within power region 125 of second location 120. In various embodiments, forming 1225 the substrate includes forming connections at coordinates within first location 110 specified by the layout file. In various embodiments, a first chiplet is coupled to first location 110 and an additional chiplet is coupled to second location 120. The additional chiplet, in various embodiments, is selected from a set of additional chiplets. Each additional chiplet in the set of additional chiplets has dimensions no greater than the dimensions of second location 120 for which the layout file was generated 1215. The additional chiplet coupled to the second location 120 has at least one dimension that does not exceed the corresponding dimension of the second location 120, as further described above in connection with Figures 2-7.

[0077] The substrate formed from the layout file includes connections for the first chiplet at first location 110 and connections on the substrate for one or more additional chiplets at second location 120 on the substrate. Second location 120 on the substrate includes interface area 127 for connections for one or more die-to-die interfaces between the first chiplet and the one or more additional chiplets. Second location 120 also includes power area 125 on the substrate in the second location for a power interface including connections for the one or more additional chiplets and dimensions for the power interface. The substrate further includes connections for the one or more die-to-die interfaces in interface area 127 of second location 120 on the substrate based on the selected template. In addition, the substrate includes connections for the power interface in the power area of ​​second location 120.

[0078] A substrate formed from a layout file allows a second chiplet having different dimensions to be coupled to the second location 120 and coupled to power and ground via connections in the second location 120. Similarly, the second location 120 of the substrate allows communication between the first chiplet in the first location 110 and the second chiplet having different dimensions via connections in the interface region 127 of the second location 120 and connections in the interface region 117 of the first location 110. The connections at the second location 120 of the substrate allow a second chiplet having different dimensions not exceeding the dimensions of the second location 120 to be coupled to the substrate, communicate with the first chiplet, and receive power and ground via the substrate. This ability to accommodate second chiplets having a range of dimensions allows a substrate formed from a layout file to be more easily used for different semiconductor assemblies, as opposed to a conventional substrate formed to accommodate a specific second chiplet. Because a conventional substrate is formed for a specific chiplet, other chiplets having dimensions different from the specific chiplet cannot be coupled to the conventional substrate. In contrast, forming a substrate from a layout file results in a substrate with connections in locations that can accommodate chiplets having various dimensions, simplifying the reuse of the substrate from the layout file across different semiconductor assemblies or with a different second chiplet that provides similar functionality but has different physical dimensions.

[0079] 1-12 describe a layout file that specifies second locations 120 to allow different chiplets having different dimensions to be coupled to the second locations 120, in various embodiments, the template or layout file specifies first locations 110 such that different first chiplets having different dimensions can be coupled to the substrate via the first locations 110. Thus, the description of second locations 120 of a substrate formed from the template with respect to FIGS. 2-10 is also applicable to first locations 110 in various embodiments. In some embodiments, the template specifies dimensions and connections for both first locations 110 and second locations 120, allowing a substrate formed from the template to accommodate first chiplets having a range of dimensions bounded by the dimensions of the first locations 110 and second chiplets having a range of dimensions bounded by the dimensions of the second locations 120. In other embodiments, the template specifies dimensions of the first location 110, allowing a substrate formed from the template 100 to accommodate a first chiplet having a range of dimensions bounded by the dimensions of the first location 110, while having a second location 120 with dimensions and connections for a particular second chiplet. Thus, the teachings discussed above in connection with Figures 1-11 can be applied to the substrate's first location 110, the substrate's second location 120, or both the substrate's first location 110 and second location 120 to form a substrate that can accommodate a first chiplet or second chiplet having a range of dimensions.

[0080] The semiconductor assembly is formed from a substrate formed from the layout file and includes a first chiplet coupled to connections on the substrate at a first location 110, and includes additional chiplets coupled to at least one set of connections in an interface region 127 on the substrate at a second location 120 and a set of connections in a power region 125 on the substrate at the second location 120. In some embodiments, at least a subset of the connections on the substrate at the second location 120 for coupling one or more additional chiplets to the substrate are not coupled to the additional chiplets. Thus, a different additional chiplet having dimensions that do not exceed the dimensions of the second location 120 can be coupled to the substrate at the second location 120. Thus, the dimensions of the second location 120 form a limit on the dimensions of the additional chiplets that can be coupled to the substrate at the second location 120. In some embodiments, the additional chiplets are selected from a set of additional chiplets, each additional chiplet of the set having dimensions that do not exceed the dimensions of the second location 120. In some embodiments, the additional chiplet has at least one dimension that is smaller than the corresponding dimension of the second location 120.

[0081] In some embodiments, the semiconductor assembly further includes a second additional chiplet coupled to an additional set of connections in interface area 127 at second location 120 on the substrate and coupled to an additional set of connections in power area 125 on the substrate at second location 120. The combined dimensions of the additional chiplet and the second additional chiplet are within a range of dimensions that do not exceed the dimensions of second location 120. The semiconductor assembly, in some embodiments, further includes a layer of material coupled to a subset of the connections on the substrate at second location 120 for coupling one or more additional chiplets not coupled to the additional chiplet to the substrate. Furthermore, in some embodiments, the substrate includes connections in dedicated interface area 805 at first location 110 and connections in dedicated interface area 810 at second location 120, where dedicated interface area 805 and dedicated interface area 810 are for implementing a second die-to-die interface having one or more characteristics. Connections in the dedicated interface area 805 at the first location 110 are coupled to connections in the dedicated interface area 810 at the second location 120. Additional chiplets, in some embodiments, are coupled to sets of connections in the dedicated interface area 810 at the second location 120.

[0082] For further explanation, FIG. 13 is a flowchart of an exemplary method for generating a template 100 for forming a substrate. In various embodiments, the method described in connection with FIG. 13 is performed by an electronic design automation (EDA) system. The EDA system receives input from a user specifying dimensions of the substrate (1305). The user input also specifies a first location 110 on the substrate for coupling a first chiplet to the substrate and a second location 120 on the substrate for coupling one or more additional chiplets to the substrate. The second location 120 includes an interface area on the substrate for one or more die-to-die interfaces between the first chiplet and the one or more additional chiplets. In addition, the second location 120 includes a power area 125 including a power interface, the power interface including connections for the one or more additional chiplets.

[0083] In some embodiments, the user input further specifies a dedicated interface region 705 in the first location 110 and a dedicated interface region 710 in the second location 120 for a second die-to-die interface. As described further above in connection with FIG. 7 , the connections in the dedicated interface region 705 are coupled to the connections in the dedicated interface region 710 through conductive paths in the substrate (specified by the user input). Using the connections in the dedicated interface region 705 and the connections in the dedicated interface region 710, the first chiplet and the additional chiplet communicate using a second die-to-die interface. As described further above in connection with FIG. 7 , the second die-to-die interface has one or more characteristics for communication between the first chiplet and the second chiplet.

[0084] 8 and 11 , the user input further specifies a sideband region 815 at the first location 110 and a second sideband region 820 at the second location 120. The connections in the sideband region 815 at the first location 110 are coupled to connections in the second sideband region 820 at the second location 120. The sideband region 815 at the first location 110 and the sideband region 820 at the second location 120 are for a sideband interface between the first chiplet and one or more second chiplets that extends the die-to-die interface, as described above in connection with FIG. 8 . In some embodiments, the user input additionally or alternatively specifies an external connection region 825 at the second location 120. The external connection region 825 includes connections for coupling to additional chiplets and connection paths 1110 through the substrate that couple the connections to the external connections 1115. As further described above in connection with Figures 8 and 11, external connection regions 825 allow components external to the integrated circuit device, including the substrate, to be directly coupled to additional chiplets.

[0085] Based on the received input, the EDA system generates 1310 a template for the substrate, including a first location and a second location, as further described above in connection with FIGS. 1, 7, and 8. In some embodiments, the EDA system stores 1315 the template in a repository for later retrieval. In some embodiments, the repository is an online system that hosts multiple templates. Storing the template in an online system allows the EDA system or other computing devices to access the template from various locations. This simplifies the use of the template to form substrates.

[0086] FIG. 14 shows a flowchart illustrating an exemplary method for manufacturing a semiconductor assembly from a layout file based on a template described herein. The method of FIG. 14 includes receiving (1405) a layout file for a substrate. The manufacturing tool can receive the layout file in various ways. For example, the manufacturing tool can load the layout file from a storage location or a network location. The layout file specifies a first location for coupling a first chiplet to the substrate and a second location for coupling one or more additional chiplets to the substrate. The second location includes an interface area and a power area. The interface area includes a plurality of interface connections for one or more die-to-die interfaces of the one or more additional chiplets. The power area includes power connections for the one or more additional chiplets.

[0087] 14 also includes forming 1410 connections on the substrate at coordinates within first locations included in the layout file. Such connections may be formed as solder bumps applied onto pads of the substrate. Prior to applying the bumps to the pads, a formation tool may place various vias, traces, and pads to support application of the solder bumps to the pads. Additional layers typical of substrate formation may also be applied before or after forming the connections as described herein.

[0088] The method of FIG. 14 also includes forming (1415) an interface connection on the substrate at coordinates within an interface region of a second location included in the layout file, and forming a power connection for the power interface at coordinates on the substrate within a power region of the second location included in the layout file.

[0089] 14 also includes forming one or more traces between the connections at the first location and the interface connections at the second location (1420). In some examples, forming the traces between the connections at the two locations can be performed before applying the connections themselves. Once the substrate is formed, chiplets can be arranged at the first and second locations according to a particular design.

[0090] In view of the above discussion, the reader will appreciate that utilizing a set of templates to generate a layout file for a substrate enables the layout file to be used to generate a substrate for a semiconductor assembly including additional chiplets having different dimensions coupled to a first chiplet via a substrate. The layout file enables coordinates on the substrate for connections coupling the first chiplet and one or more additional chiplets to the substrate to be used to couple additional chiplets having dimensions within a range specified by the layout file, allowing additional chiplets of different sizes to be coupled to the substrate. Thus, the layout file increases the range of additional chiplets that can be coupled to the substrate, providing greater flexibility in design options for semiconductor assembly manufacturing. Furthermore, substrates generated from a layout file reduce the amount of time to manufacture a semiconductor assembly by allowing different combinations of chiplets having different dimensions supported by a substrate to be coupled to an existing substrate, unlike traditional manufacturing methods in which a substrate is custom designed and manufactured for a specific combination of chiplets. Enabling the reuse of a common substrate for different combinations of chiplets having different dimensions increases the number of chiplets that can be used in a semiconductor assembly and enables the use of a common substrate without forming different substrates specifically designed for the dimensions of a specific combination of chiplets.

[0091] Aspects of the present disclosure may be implemented as a system, method, and / or computer program product, which may include a computer-readable storage medium having computer-readable program instructions thereon for causing a processor to perform aspects of the present disclosure.

[0092] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves having instructions recorded thereon, and any suitable combination thereof. As used herein, a computer-readable storage medium should not be construed as being an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), such as an electric wave or other freely propagating electromagnetic wave, or a transitory signal per se, such as an electrical signal transmitted through a wire.

[0093] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers, or combinations thereof. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transmits the computer-readable program instructions to a computer-readable storage medium in the respective computing / processing device for storage.

[0094] The computer-readable program instructions for carrying out the operations of the present disclosure may be either assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and traditional procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry to perform aspects of the present disclosure.

[0095] Aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0096] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, produce a machine that generates means for performing the functions / acts specified in the blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams, and that can direct a computer, programmable data processing apparatus, and / or other device, or combination thereof, to function in a particular manner.

[0097] Furthermore, computer-readable program instructions can be loaded into a computer, other programmable data processing apparatus, or other device and cause a series of operational steps to be executed on the computer, other programmable apparatus, or other device to create a computer-executed process, such that the instructions executing on the computer, other programmable apparatus, or other device perform the functions / acts specified in the flowchart and / or block diagram blocks.

[0098] It will be understood from the foregoing description that modifications and variations can be made in various embodiments of the present disclosure. The description herein is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. A substrate, including locations for coupling one or more chiplets to the substrate, the locations having dimensions bounded by dimensions of a chiplet that is bondable to the substrate at the locations; The location is: an interface region including one or more die-to-die interface connections of the one or more chiplets; a power domain including a power interface having connections for the one or more chiplets; substrate.

2. further comprising an additional location for coupling a first chiplet to the substrate; the additional location includes a connection for coupling the first chiplet to the substrate. The substrate of claim 1 .

3. the substrate includes a connection between the interface region at the location and the interface region at the additional location; The substrate of claim 2.

4. the interface area and the power area are configured to receive a plurality of different chiplets having combined dimensions that do not exceed the dimensions of the location. The substrate of claim 1 .

5. the interface area and the power area are configured to receive a plurality of different chiplets having different widths; the combination of said different widths does not exceed the width of said location; The substrate of claim 1 .

6. the interface region and the power region are configured to receive a plurality of different chiplets having different lengths; the combination of the different lengths does not exceed the length of the location; The substrate of claim 1 .

7. the location includes a sideband region; the substrate includes a connection between the sideband region and a second sideband region at the different location for a sideband interface between a chiplet at the location and another chiplet at a different location; the sideband interface extends the die-to-die interface; The substrate of claim 1 .

8. the locations include external connections including connections that couple the chiplets to one or more components external to a semiconductor assembly that includes the substrate; the substrate includes a connection path from a connection portion within an external connection portion region to an external connection portion; The semiconductor assembly of claim 1 .

9. 1. A semiconductor assembly comprising: A substrate; at least one chiplet; The substrate is a location for coupling one or more chiplets to the substrate, the location having dimensions bounded by dimensions of additional chiplets that can be coupled to the substrate at the location; The location is: an interface region including one or more die-to-die interface connections of the one or more chiplets; a power domain including a power interface having connections for the one or more chiplets; The at least one chiplet coupled to at least a subset of the connections in the interface region and a subset of the connections in the power region, the dimension of the location not exceeding the dimension of the location; Semiconductor assembly.

10. The substrate is further comprising an additional location for coupling a first chiplet to the substrate; the additional location includes a connection for coupling the first chiplet to the substrate. The semiconductor assembly of claim 9.

11. the first chiplet coupled to the additional location; The semiconductor assembly of claim 10.

12. the at least one chiplet includes a plurality of chiplets; the combined width of the plurality of chiplets does not exceed the width of the location; The semiconductor assembly of claim 9.

13. each of the plurality of chiplets having a different width; The semiconductor assembly of claim 12.

14. the at least one chiplet includes a plurality of chiplets; the combined length of the plurality of chiplets does not exceed the length of the location; The semiconductor assembly of claim 9.

15. each of the plurality of chiplets having a different length; The semiconductor assembly of claim 14.

16. a subset of the connections within the power domain of the location are not coupled to a chiplet; The semiconductor assembly of claim 9.

17. a subset of connections within the interface region at the second location are not coupled to a chiplet; The semiconductor assembly of claim 9.

18. the location includes a sideband region; the substrate includes a connection between the sideband region and a second sideband region at the different location for a sideband interface between a chiplet at the location and another chiplet at a different location; the sideband interface extends the die-to-die interface; the chiplet is coupled to one or more connections in the sideband region; The semiconductor assembly of claim 9.

19. the locations include external connections including connections that couple the chiplets to one or more components external to a semiconductor assembly that includes the substrate; the substrate includes a connection path from a connection portion within an external connection portion region to an external connection portion; The semiconductor assembly of claim 9.

20. 1. A method comprising: generating, in a graphical user interface, a graphical representation of the substrate based on a layout specified by the substrate template; generating a graphical representation of locations for coupling one or more chiplets to the substrate, the locations including an interface area and a power area, the interface area including a plurality of interface connections for one or more die-to-die interfaces of the chiplets, and the power area including power connections for the chiplets; method.

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