Etching with sulfur-based oxygen-free passivators

Abstract

A method is provided for selectively etching a dielectric material relative to a semiconductor material, wherein the dielectric material is etched and the semiconductor material is passivated by providing a passivation gas that includes an oxygen-free, non-thiol sulfur-based component.

Description

[Background technology]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of priority to U.S. Application No. 63 / 430,744, filed December 7, 2022, which is incorporated herein by reference for all purposes.

[0002] The Background Art set forth herein is intended to present the contents of the present disclosure generally, and the inventions of the presently named inventors are not admitted expressly or impliedly as prior art to the present disclosure to the extent described in this Background Art section and in aspects of the description that are not prior art at the time of filing.

[0003] When forming a semiconductor device, the dielectric layer can be selectively etched relative to the semiconductor layer to form the semiconductor device. Some dielectric layers can be silicon oxide (SiO2)-based materials or silicon nitride (SiN)-based materials. Dielectric materials are materials with high electrical resistance. Some semiconductor layers can be silicon (Si), germanium (Ge), or silicon germanium (SiGe) layers. Semiconductor materials are materials with electrical conductivity between that of conductors and that of dielectric or insulator materials. Summary of the Invention

[0004] To achieve the foregoing in accordance with the objectives of the present disclosure, a method is provided for selectively etching a dielectric material relative to a semiconductor material, wherein the dielectric material is etched, and the semiconductor material is passivated by providing a passivation gas that includes an oxygen-free, non-thiol sulfur-based component.

[0005] These and other features of the present disclosure are described in more detail below in the detailed description taken in conjunction with the following figures. [Brief explanation of the drawings]

[0006] The present disclosure is illustrated by way of example, and not limitation, in the figures of the accompanying drawings, in which like reference numerals refer to like elements and in which:

[0007] [Figure 1] 1 is a high-level flowchart of an embodiment.

[0008] [Figure 2A] 1 is a schematic diagram of a laminate processed according to some embodiments. [Figure 2B] 1 is a schematic diagram of a laminate processed according to some embodiments. [Figure 2C] 1 is a schematic diagram of a laminate processed according to some embodiments. [Figure 2D] 1 is a schematic diagram of a laminate processed according to some embodiments.

[0009] [Figure 3] 1 is a schematic diagram of a semiconductor processing chamber that can be used in some embodiments.

[0010] [Figure 4] FIG. 1 is a schematic diagram of a computer system that may be used to implement some embodiments.

[0011] In the drawings, the same reference numbers may be used to designate similar structural elements. It should also be recognized that the depictions in the figures are schematic and not to scale. DETAILED DESCRIPTION OF THE INVENTION

[0012] The present disclosure will now be described in detail with reference to certain preferred embodiments thereof, as illustrated in the accompanying drawings. In the following description, certain specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process steps and / or structures have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0013] Some etching techniques rely on fluorocarbons and / or hydrofluorocarbons to provide selective etching of SiO2- or SiN-based dielectric materials while protecting underlying epitaxial layers of semiconductor materials (e.g., Si, SiGe, and Ge). This approach generally does not provide a sufficient process window to control both semiconductor material loss and healthy etching (excellent contact resistance and low incidence of under-etched features). Carbon-based passivation methods tend to consume several nanometers (nm) of semiconductor material before providing sufficient protection against etching. While increased carbon deposition may reduce semiconductor loss, it tends to increase low contact resistance and / or incidence of under-opening.

[0014] An alternative passivation using carbonyl sulfide (COS) as an etching additive shows some improvement but is still not sufficient to meet the needs of more advanced nodes due to the oxidation of semiconductor materials by the oxygen in the COS molecule.

[0015] Some embodiments introduce a form of sulfur-based passivation that avoids oxidation of the semiconductor material. In some embodiments, this is achieved by avoiding the presence of oxygen in the passivation molecules. In some embodiments, the affinity of sulfur atoms to Si and Ge promotes rapid passivation when Si and Ge films are exposed during silicon oxide or silicon nitride etching, resulting in reduced semiconductor material loss. Furthermore, sulfur-based passivation is less likely to cause lower contact resistance and / or increased incidence of non-opening compared to carbon-based passivation. In some embodiments, sulfur passivators may form conductive carbon polysulfide polymers.

[0016] FIG. 1 is a high-level flowchart of a process used in some embodiments for ease of understanding. In some embodiments, a stack of layers is placed in an etch chamber (step 104). FIG. 2A is a cross-sectional view of a stack of layers 200 that may be processed in some embodiments. The stack of layers 200 includes a substrate 204 underlying a dielectric layer 208. The dielectric layer 208 includes a fin field-effect transistor (FinFET) structure 220. In some embodiments, the dielectric layer 208 is a SiN-based layer or a SiO2-based layer. The SiN-based layer or the SiO2-based layer is made of pure SiN or pure SiO2 material, or a material that is mostly SiN or SiO by weight, and may contain dopants. The FinFET structure 220 is made of a semiconductor material such as SiGe, Si, or a combination thereof. The SiGe or Si includes doped and undoped SiGe or Si. The top of the FinFET structure 220 is extended using epitaxy to form an epitaxial layer 224. The stack of layers 200 further includes a metal-containing layer 228. A metal-containing layer is formed over the dielectric layer 208 to act as an etch mask. In some embodiments, the metal-containing layer 228 is tungsten carbide.

[0017] The dielectric layer 208 of the stack 200 is etched selectively with respect to the semiconductor material (step 108). In some embodiments, the selective etching may include a cyclic process of providing a dielectric layer etching step (step 112) and a semiconductor material passivation step (step 116) at different times. In some embodiments, the different times may overlap. In some embodiments, the different times do not overlap. In some embodiments, the dielectric layer etching step (step 112) may be one or more of atomic layer etching (ALE), reactive ion etching (RIE), and thermal etching. FIG. 2B is a cross-sectional view of the stack 200 after the dielectric layer step 208 has been partially etched to expose a portion of the semiconductor material that will form the FinFET structure 220.

[0018] A passivation step is provided (step 116) to passivate the semiconductor material of the exposed portions of FinFET structure 220. In some embodiments, a passivation gas including an oxygen-free, non-thiol sulfur-based component is provided. In some embodiments, all passivation gases including non-thiol sulfur-based components are oxygen-free. In some embodiments, because the passivation gas provides the passivation, in some embodiments, the passivation step is a plasma-free process. In some embodiments, the passivation gas is turned into a plasma, and the plasma provides the passivation. In some embodiments, the passivation gas includes hydrogen sulfide (HS). In some embodiments, metal-containing layer 228 is also passivated. FIG. 2C is a cross-sectional view of stack 200 after the semiconductor and metal-containing layer 228 of the exposed portions of FinFET structure 220 have been passivated with passivation layer 232.

[0019] The cycle of providing a dielectric layer etching step (step 112) and a passivation step (step 116) is repeated multiple times until the desired etching is complete. Figure 2D is a cross-sectional view of stack 200 after etching of dielectric layer step 208 is complete. Feature 240 has been etched into dielectric layer 208 with minimal etching of semiconductor finFET structure 220.

[0020] In some embodiments, an optional post-etch treatment is provided (step 120). In some embodiments, the post-etch treatment removes etch residues. In some embodiments, the removed etch residues are remaining passivation layers. In some embodiments, the etch residues are etch contaminants and / or etch masks. In some embodiments, the post-etch treatment is a strip treatment. In some embodiments, other post-etch treatments (e.g., plasma treatments, which can be performed in the same chamber, or wet cleans, which can be performed in separate chambers) may be performed.

[0021] In some embodiments, the sulfur passivator reduces or eliminates etching of the semiconductor material. In some embodiments, the absence of oxygen in the passivator reduces or eliminates oxidation of the semiconductor material. The use of sulfur instead of carbon as a passivator allows for improved electrical contact with the semiconductor material.

[0022] In some embodiments, other non-thiol sulfur-based chemicals that do not contain oxygen are used as additives in the etching process. Thiols are a class of organic molecules similar to alcohols and phenols, but containing sulfur atoms instead of oxygen atoms. Thiol molecules may be of the RSH type (R is an alkyl or other organic molecule). Non-thiol sulfur-based molecules contain sulfur but may not be of the RSH type (R is an organic molecule). These non-thiol sulfur-based compounds include carbon disulfide (CS), cyanoisothiocyanate (CNS), dimethyl sulfide (S(CH)), and other compounds based on carbon-bonded sulfur. Using H2S as a passivation agent provides a carbon-free passivation gas and offers the benefits of being carbon-free. In some embodiments, the passivation agent further includes nitrogen gas (N2). The addition of N2 can be used to enhance the passivation of polythiazyl (SN) x (where x is an integer and the polythiazyl functions as a passivator). In some embodiments, the passivation gas further comprises at least one of hydrogen gas (H), N, a hydrocarbon, and a hydrofluorocarbon. Thiols may be required for passivation in plasma treatments. Oxygen-free, non-thiol sulfur-based chemicals have unexpectedly been discovered to provide improved passivation in plasma-free thermal treatments. H2S has unexpectedly been discovered to provide improved passivation in plasma-free thermal treatments.

[0023] In some embodiments, the step of etching the dielectric layer (step 112) and the step of passivating the semiconductor material (step 116) are performed simultaneously. In some embodiments, the step of etching the dielectric layer (step 112) and the step of passivating the semiconductor material (step 116) are performed simultaneously in one step to both etch the dielectric layer and passivate the semiconductor material.

[0024] In some embodiments, the semiconductor material is deposited by epitaxial deposition. Epitaxial deposition is a deposition process that deposits an oriented crystalline layer on a seed layer. An example of epitaxial deposition is molecular beam epitaxy. In some embodiments, the semiconductor material is crystalline. In some embodiments, the semiconductor material is amorphous or polycrystalline. In some embodiments, the semiconductor material is at least one of silicon, germanium, and silicon germanium. In some embodiments, the semiconductor material is doped. In some embodiments, the semiconductor material is undoped.

[0025] In some embodiments, the etching process is a cyclic etching process, such as atomic layer etching. In some embodiments, the etching process is a continuous etching process.

[0026] 3 is a schematic diagram of an etch chamber 300 for plasma processing a substrate, according to some embodiments. In some embodiments, the etch chamber 300 includes a gas distribution plate 306 that provides a gas inlet and an electrostatic chuck (ESC) 316 within an etch chamber 304 surrounded by chamber walls 350. Within the etch chamber 304, the stack 200 is positioned above the ESC 316. The ESC 316 can receive a bias from an ESC power supply 348. A gas source 310 is connected to the etch chamber 304 through the gas distribution plate 306. An ESC temperature regulator 351 is connected to the ESC 316 and provides temperature regulation of the ESC 316. A radio frequency (RF) power supply 330 provides RF power to the ESC 316 and an upper electrode. In this embodiment, the upper electrode is the gas distribution plate 306. In a preferred embodiment, 400 kilohertz (kHz), 13.56 megahertz (MHz), 1 MHz, 2 MHz, 60 MHz, and / or 27 MHz power sources, if desired, comprise the RF power source 330 and the ESC power source 348. A controller 335 is controllably connected to the RF power source 330, the ESC power source 348, the exhaust pump 320, and the gas source 310. A high-flow liner 360 is a liner within the etching chamber 304 that confines gas from the gas source and has a slot 362. The slot 362 maintains a controlled flow of gas passing from the gas source 310 to the exhaust pump 320. An example of such an etching chamber is the Flex® Etch System manufactured by Lam Research Corporation of Fremont, California. The processing chamber may be a CCP (capacitively coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0027] FIG. 4 is a high-level block diagram illustrating a computer system 400 for implementing a controller 335 used in embodiments of the present invention. Computer systems can have a variety of physical forms, ranging from integrated circuits, printed circuit boards, and small handheld devices to large supercomputers. The computer system 400 may include one or more processors 402 and may further include an electronic display device 404 (for displaying images, text, and other data), a main memory 406 (e.g., random access memory (RAM)), a storage device 408 (e.g., a hard disk drive), a removable storage device 410 (e.g., an optical disk drive), a user interface device 412 (e.g., a keyboard, touch screen, keypad, mouse or other pointing device, etc.), and / or a communication interface 414 (e.g., a wireless network interface). The communication interface 414 may allow software and / or data to be transferred between the computer system 400 and external devices via a link. The system may also include a communication infrastructure 416 (e.g., a communication bus, crossover bar, or network) to which the aforementioned devices / modules can be connected.

[0028] Information transferred through communications interface 414 may be in the form of electronic, electromagnetic, optical, or other signals that can be received by communications interface 414 over a communications link that carries signals, which may be implemented using wire or cable, fiber optics, telephone line, cellular phone link, radio frequency link, and / or other communications channel. It is contemplated that such communications interfaces may enable one or more processors 402 to receive information from a network or output information to a network in the course of performing the method steps described above. Furthermore, method embodiments may be performed solely on a processor or may be performed in conjunction with a remote processor and across a network, such as the Internet, that shares a portion of the processing.

[0029] The term "non-transitory computer-readable medium" is used generally to refer to media (e.g., primary storage, secondary storage, removable storage, and storage devices (e.g., hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory)) and is not to be construed to include transitory objects (e.g., carrier waves or signals). Examples of computer code include machine code (e.g., what a compiler produces) and files containing high-level code that are executed by a computer using an interpreter. A computer-readable medium may also be computer code embodied in a carrier wave and transmitted by a computer data signal representing a sequence of instructions executable by a processor.

[0030] While this disclosure has been described in terms of several preferred embodiments, there are alterations, modifications, substitutions, and various substitute equivalents that fall within the scope of this disclosure. It should also be noted that there are various alternative ways of implementing the methods and apparatuses of this disclosure. It is therefore intended that the following appended claims be interpreted to include all such alterations, modifications, substitutions, and various substitute equivalents that fall within the true spirit and scope of the present disclosure.

Claims

1. 1. A method for selectively etching a dielectric material relative to a semiconductor material, comprising: Etching the dielectric material; passivating the semiconductor material, the passivation gas comprising an oxygen-free, non-thiol sulfur-based component; A method comprising:

2. 10. The method of claim 1, The method, wherein the semiconductor material comprises at least one of silicon and germanium.

3. 10. The method of claim 1, The method, wherein the dielectric material comprises at least one of a silicon oxide based material and a silicon nitride based material.

4. 10. The method of claim 1 further comprising: forming the passivating gas into a plasma.

5. 10. The method of claim 1, The method wherein the step of providing a passivating gas is simultaneous with the step of etching the dielectric material.

6. 10. The method of claim 1, The method, wherein the step of providing the passivating gas is at a different time than the step of etching the dielectric material, and the method includes multiple cycles of the steps of etching the dielectric material and passivating the semiconductor material.

7. 10. The method of claim 1, The passivation gas is H 2 S, CS 2 , S(CH 3 ) 2 , and C 2 N 2 The method includes at least one of:

8. 8. The method of claim 7, The passivation gas may further comprise H 2 , N 2 , hydrocarbons, and hydrofluorocarbons.

9. 10. The method of claim 1, A method wherein passivating the semiconductor material provides a passivation layer, the method further comprising removing the passivation layer.

10. 10. The method of claim 1, The method, wherein the dielectric material underlies a metal-containing mask, and wherein etching the dielectric material selectively etches the dielectric material relative to the metal-containing mask and the semiconductor material.

11. 11. The method of claim 10, The method of claim 1, wherein providing a step of passivating the semiconductor material passivates the metal-containing layer and the semiconductor material.

12. 10. The method of claim 1, The passivation gas is H 2 A method comprising:

13. 13. The method of claim 12, The passivation gas may further comprise H 2 , N 2 , hydrocarbons, and hydrofluorocarbons.

14. 10. The method of claim 1, The passivation gas may further comprise H 2 , N 2 , hydrocarbons, and hydrofluorocarbons.

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