Fixed asymmetry compensation for multiplication and accumulation operations.

Abstract

Systems and methods for compensating multiplication and accumulation (MAC) operations are described. A processor may send an input vector to a first portion of a memory device. The first portion may store synaptic weights of a trained artificial neural network (ANN). The processor may read a first result of the MAC operation performed on the input vector and synaptic weights stored in the first portion. The processor may send an inverse of the input vector to a second portion of the memory device. The processor may read a second result of the MAC operation performed on the inverse of the input vector and the inverse of the synaptic weights stored in the second portion. The processor may combine the first result and the second result to generate a final result. The final result may be a compensated version of the first result.

Description

[Background technology]

[0001] This application relates generally to analog memory-based artificial neural networks, and more particularly to techniques for compensating for fixed asymmetries for multiplication and accumulation operations.

[0002] An artificial neural network (ANN) can include multiple layers of nodes, such as an input layer, one or more hidden layers, and an output layer. Each node is connected to another node and has an associated weight and threshold. If the output of any individual node exceeds a specified threshold, that node is activated and sends data to the next layer of the network; otherwise, the data is not sent to the next layer of the network. ANNs rely on training data to learn and can improve their accuracy over time. Once the accuracy of an ANN is fine-tuned, it can be used for inference (e.g., classifying and predicting input data).

[0003] Analog memory-based neural networks, for example, may utilize the storage capabilities and physical properties of memory devices to implement artificial neural networks. This type of in-memory computing hardware offers increased speed and energy efficiency, potentially improving performance. Rather than moving data from a memory device to a processor to perform the calculation, analog neural network chips can perform calculations in the same location where the data is stored (e.g., in analog memory). Because there is no data movement, tasks can be performed faster and require less energy. Summary of the Invention

[0004] This summary of the disclosure is provided to aid in understanding systems and methods for compensating for fixed asymmetries in multiplication and accumulation (MAC) operations in analog memory-based artificial neural networks, which can provide efficiencies, and is not intended to limit the disclosure or the invention. It should be understood that various aspects and features of the disclosure can be used advantageously separately in some instances, or can be used advantageously in other instances in combination with other aspects and features of the disclosure. Accordingly, variations and modifications may be made to the system and / or its method of operation to achieve different advantages.

[0005] In one embodiment, a memory device for compensating multiplication and accumulation (MAC) operations is generally described. The memory device may include a plurality of memory elements arranged in a plurality of memory blocks. Each memory block may include a first set of memory elements of the plurality of memory elements and a second set of memory elements of the plurality of memory elements. The first set of memory elements may be configured to store synaptic weights of a trained artificial neural network (ANN). The second set of memory elements may be configured to store inverses of the synaptic weights stored in the first set of memory elements.

[0006] Advantageously, the memory device in one aspect may compensate for fixed asymmetries and improve the accuracy of MAC operations.

[0007] In one embodiment, a method for compensating multiplication and accumulation (MAC) operations is generally described. The method may include transmitting an input vector to a first portion of a memory device. The first portion may store synaptic weights of a trained artificial neural network (ANN). The method may further include retrieving a first result of the multiplication and accumulation (MAC) operations performed on the input vector and synaptic weights stored in the first portion. The method may further include transmitting an inverse of the input vector to a second portion of the memory device. The method may further include retrieving a second result of the MAC operations performed on the inverse of the input vector and the inverse of the synaptic weights stored in the second portion. The method may further include combining the first result and the second result to generate a final result. The final result may be a compensated result of the MAC operations performed on the input vector and synaptic weights stored in the first portion.

[0008] Advantageously, the method in one aspect may compensate for fixed asymmetries and improve the accuracy of the MAC calculation.

[0009] In one embodiment, a system for compensating multiplication and accumulation (MAC) operations is generally described. The system may include a memory device and a processor. The processor may be configured to send an input vector to a first portion of the memory device. The first portion may store synaptic weights of a trained artificial neural network (ANN). The processor may be further configured to retrieve a first result of the multiplication and accumulation (MAC) operation performed on the input vector and synaptic weights stored in the first portion. The processor may be further configured to send an inverse of the input vector to a second portion of the memory device. The processor may be further configured to retrieve a second result of the MAC operation performed on the inverse of the input vector and the inverse of the synaptic weights stored in the second portion. The processor may be further configured to combine the first result and the second result to generate a final result. The final result may compensate for the result of the MAC operation performed on the input vector and synaptic weights stored in the first portion.

[0010] Advantageously, the system in one aspect may compensate for fixed asymmetries and improve the accuracy of the MAC calculation.

[0011] Further features, as well as the structure and operation of various embodiments, are described in detail below with reference to the accompanying drawings, where like reference numbers indicate identical or functionally similar elements. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 10 illustrates an example in which fixed asymmetry compensation for multiplication and accumulation operations may be implemented in one embodiment.

[0013] [Figure 2] FIG. 1 illustrates details of an analog memory-based device that can implement fixed asymmetry compensation for multiplication and accumulation operations in one embodiment.

[0014] [Figure 3A] FIG. 10 illustrates details of a tile that can implement fixed asymmetry compensation for multiplication and accumulation operations in one embodiment.

[0015] [Figure 3B] 3B illustrates an exemplary implementation of the tile shown in FIG. 3A in one embodiment.

[0016] [Figure 3C] FIG. 3C illustrates further details of the example implementation of FIG. 3B, in one embodiment.

[0017] [Figure 4] FIG. 1 is a flow diagram illustrating a method for fixed asymmetry compensation for multiplication and accumulation operations in one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0018] Analog neural network chips can perform parallel vector multiplication operations, such as multiplication and accumulation (MAC) operations. The analog neural network chips can receive input data, which can be excitation vectors. These excitation vectors can be applied to multiple row lines of the analog neural network chip to perform MAC operations across a matrix of stored weights encoded in the conductance values ​​of the analog memory elements. In one aspect, the analog memory elements in the analog neural network chips can be sensitive to fixed asymmetries, including, but not limited to, shifts between positive and negative weights, positive and negative inputs, or asymmetries in the surrounding circuitry. These fixed asymmetries can affect the accuracy of the MAC operation calculations.

[0019] FIG. 1 illustrates an analog memory-based device that implements a hardware neural network in one embodiment. An analog memory-based device 114 ("device 114") is shown in FIG. 1. Device 114 may be a coprocessor or accelerator, and device 114 may sometimes be referred to as an analog fabric (AF) engine. One or more digital processors 110 may communicate with device 114 to facilitate the operation or function of device 114. In one embodiment, digital processor 110 may be a field programmable gate array (FPGA) board. Device 114 may also interface with components such as digital-to-analog converters (DACs) that can provide power, voltage, and current to device 114. Digital processor 110 may implement digital logic to interface with device 114 and other components, such as DACs.

[0020] In one embodiment, device 114 may include multiple multiply-accumulate (MAC) hardware having a crossbar structure or array. There may be multiple crossbar structures or arrays arranged as multiple tiles, such as tile 102. While FIG. 1 shows two MAC hardware (two tiles), there may be additional (e.g., more than two) MAC tiles integrated into device 114. By way of example, tile 102 may include electronic devices such as multiple memory elements 112. The memory elements 112 may be arranged at crosspoints of the crossbar array. At each crosspoint or junction of the crossbar structure or crossbar array, there may be at least one memory element 112 including analog memory elements such as resistive RAM (ReRAM), conductive bridge RAM (CBRAM), NOR flash, magnetic RAM (MRAM), and phase-change memory (PCM). In one embodiment, such analog memory elements may be programmed to store synaptic weight values ​​for an artificial neural network (ANN).

[0021] In one aspect, each tile 102 may represent at least a portion of a layer of an ANN. Each memory element 112 may be connected to a respective one of a plurality of input lines 104 and a respective one of a plurality of output lines 106. The memory elements 112 may be arranged in an array such that the distance between intersections in the horizontal and vertical directions of the substrate surface is constant. Each tile 102 may perform vector-matrix multiplication. By way of example, the tile 102 may include peripheral circuitry such as a pulse width modulator 120 and a readout circuit 122.

[0022] Electrical pulses 116 or voltage signals can be input (or applied) to the input lines 104 of the tiles 102. Output currents can be obtained from the output lines 106 of the crossbar structure, for example, according to a multiply-accumulate (MAC) operation based on the input pulses or voltage signals 116 applied to the input lines 104 and the values ​​(synaptic weight values) stored in the memory elements 112.

[0023] The tile 102 may include N input lines 104 and M output lines 106. A controller 108 (e.g., a global controller) may program memory elements 112 to store synaptic weight values ​​of the ANN, e.g., to have electrical conductances (or resistances) representative of such values. The controller 108 may include (or be connected to) a signal generator (not shown) for coupling an input signal (e.g., applying a pulse duration or voltage bias) to the input lines 104 or directly to the output.

[0024] In one embodiment, readout circuitry 122 may be connected or coupled to read out the M output signals (currents) obtained from the M output lines 106. Readout circuitry 122 may be implemented by multiple analog-to-digital converters (ADCs). Readout circuitry 122 reads the currents output directly from the crossbar array, which may be provided to another hardware or circuitry 118 that can process the currents, such as to perform compensation or determine errors.

[0025] The processor 110 may be configured to input a set of input activation vectors to the crossbar array (e.g., via the controller 108). In one embodiment, the set of input activation vectors input to the tile 102 are encoded as electrical pulse durations. In another embodiment, the set of input activation vectors input to the tile 102 may be encoded as voltage signals. The processor 110 may also be configured to read, via the controller 108, output activation vectors from the plurality of output lines 106 of the tile 102. The output activation vectors may represent the output of an operation (e.g., a MAC operation) performed on the crossbar array based on the set of input activation vectors and synaptic weights stored in the memory elements 112. In one aspect, the input activation vectors are multiplied by values ​​(e.g., synaptic weights) stored in the memory elements 112 of the tile 102, and the resulting products are accumulated (added) column-wise to generate output activation vectors in each one of those columns (output lines 106). These output activation vectors may further be passed through respective activation functions to activate respective neurons.

[0026] Additionally, processor 110 may be further configured to train the ANN by adjusting the synaptic weight values ​​of the ANN stored in the crossbar array. Processor 110 may iteratively adjust the synaptic weight values ​​stored in the crossbar array until the error between the expected result and the result predicted by the ANN converges to a target accuracy. Once the error converges to the target accuracy, processor 110 may deploy the ANN to perform inference, such as classification or prediction of input data. In one aspect, once the ANN is deployed, the synaptic weight values ​​stored in the crossbar array may remain fixed or unchanged. However, when retraining the ANN using new training data, the synaptic weight values ​​stored in the crossbar array may be adjustable.

[0027] 2 is a detailed diagram of an analog memory-based device that may implement fixed asymmetry compensation for multiplication and accumulation operations in one embodiment. In the embodiment shown in FIG. 2, each one of the tiles 102 may include a first portion 210 and a second portion 212 in the device 114. Additionally, each one of the tiles 102 may include multiple memory elements 202 arranged in multiple memory blocks 204. Each memory block 204 may include at least two memory elements 202. In one embodiment, each memory block 204 stores the synaptic weights w of the trained ANN. k a first set of memory elements configured to store: k The synaptic weights w are labeled k The synaptic weight value w may include a second set of memory elements configured to store the inverse of the synaptic weight value w k The memory elements storing the inverse value -w form the first portion 210. k may form the second portion 212. In the embodiment shown in FIG. 2, the first set of memory elements in memory block 204 may store w k and a second set of memory elements in memory block 204 may include a pair of memory elements (e.g., two memory elements) that store -w k In an embodiment in which the two memory elements store one synaptic weight value (or one reciprocal value), the synaptic weight value (or reciprocal value) may be represented by the difference between the conductances of the two memory elements. In another embodiment, the first set of memory elements and the second set of memory elements in memory block 204 may each include one memory element, such that the synaptic weight value and its reciprocal value are each represented by a respective conductance. The number of memory elements in the first set of memory elements and the second set of memory elements may be arbitrary, for example, the first set of memory elements and the second set of memory elements may include the same number of memory elements. For example, other configurations of memory elements may be envisioned. The synaptic weight value w kis fixed, so that the input data coming in at the row lines of the tile 102 is weighted by the stored fixed weights w k and the sum of the products for each row may be accumulated and output from the column lines of the tile 102.

[0028] The plurality of memory elements 202 may be analog non-volatile memory elements such as resistive random access memory (RRAM), conductive bridging random access memory (CBRAM), ferroelectric field effect transistors (FeFET), ferroelectric tunnel junctions, or electrochemical random access memory (ECRAM). Then, if a tile 102 has N rows of memory elements 202 and M columns of memory elements 202, the tile 102 may include N×M / 4 memory blocks 204, and the tile 102 may store N×M / 4 synaptic weight values.

[0029] In one embodiment, the processor 110 may sequentially enable the first portion 210 and the second portion 212 of the memory elements 202 in the tile 102. The processor 110 may also sequentially provide input data to the tiles 102 for inference (e.g., classification, prediction, clustering, or other types of inference). As an example, the processor 110 may send control signals to generate synaptic weight values ​​w k Then, when the first portion 210 is enabled, the inverse value −w k A second portion 212 of the memory element 202 storing the first portion 210 may be disabled. The first portion 210 and the second portion 212 of the memory element 202 are enabled separately, such that when the first portion 210 is enabled by the processor 110, the second portion 212 is disabled, and vice versa.

[0030] In one embodiment, in response to enabling first portion 210, processor 110 may provide first input data 206 representing vector U to first portion 210. Memory elements of enabled first portion 210 receive input data 206 and store the vector U and synaptic weight values ​​w kThe processor 110 may perform a MAC operation on the vector elements of the input data 206 and the synaptic weight values ​​w from the first portion 210. k In response to reading the result 216, the processor 110 may enable (or activate) the second portion 212 of the memory element 202 and disable (or deactivate) the first portion 210.

[0031] In response to enabling the second portion 212, the processor 110 may provide second input data 208 representing the vector -U to the second portion 212. The vector -U may be the inverse of the vector U, such that the vector elements of the vector -U may be the inverse of the corresponding vector elements of the vector U. The tile 102 receives the input data 208 and stores the vector elements of the vector -U and the inverse values ​​-w stored in the second portion 212. k The processor 110 may perform a MAC operation on the input data 208 and the inverse value -w from the second portion 212. k The processor 110 may retrieve the result 218 of the MAC operation performed on {overscore (x)}. The processor 110 may combine the results 216, 218 to generate a final MAC operation result, which may be a compensated version of the result 216.

[0032] FIG. 3A illustrates details of a tile that can implement fixed asymmetry compensation for multiplication and accumulation operations in one embodiment. A portion of a crossbar array in a tile 102 is shown in FIG. 3A. In the embodiment illustrated in FIG. 3, each memory element 202 (shown in FIG. 2) can include analog memory elements such as resistors and switches (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)). A memory block 300 (e.g., one of the memory blocks 204 in FIG. 2) can include four memory elements, and the memory block 300 can be configured to store synaptic weight values ​​w1 and the reciprocal of w1, labeled −w1. The column lines of the crossbar array in the tile 102 are connected to capacitors C, where the capacitance of capacitor C represents the accumulated output from the columns of memory elements 202, and the accumulated output is the result from the MAC operation.

[0033] As an example, switch S11 and resistor R11 may form a first memory element in memory block 300. Switch S21 and resistor R21 may form a second memory element in memory block 300. The first and second memory elements in memory block 300 may be associated with a synaptic weight w k The switch S31 and resistor R31 may form a third memory element in the memory block 300, and the switch S41 and resistor R41 may form a fourth memory element in the memory block 300. The third and fourth memory elements in the memory block 300 store the inverse value -w k Another memory block configured to store synaptic weight values ​​w2 and reciprocal values ​​−w2 may include memory elements having resistors R12, R22, R32, R42 and corresponding switches S12, S22, S32, S42.

[0034] The switches in the first portion 210 may be connected to control lines 310. For example, gate terminals of switches S11, S21, S12, and S22 may be connected to control lines 310. Processor 110 may send control signals to the switches in the first portion 210 using control lines 310 to enable or disable memory elements in the first portion 210. The switches in the second portion 212 may be connected to control lines 312. For example, gate terminals of switches S31, S41, S32, and S42 may be connected to control lines 312. Processor 110 may send control signals to the switches in the second portion 212 using control lines 312 to enable or disable memory elements in the second portion 212.

[0035] In one embodiment, for each memory element 202, an analog memory element (e.g., a resistor) may be connected to a column line, and a switch may be connected between the analog memory element and a row line. Using resistor R11 and switch S11 as an example, when switch S11 is enabled, resistor R11 remains connected to both column line 306 and row line 304. When switch S11 is disabled, resistor R11 is isolated from row line 304, and current does not flow through resistor R11. In one embodiment, processor 110 may independently switch control lines 310 and 312 on or off. As an example, processor 110 may switch control line 310 on and switch control line 312 off to provide a control signal to the complete crossbar array. The switch connected to control line 310 is thereby enabled by the control signal, while the switch connected to control line 312 is disabled. Similarly, processor 110 may switch off control line 310 and switch on control line 312 to provide a control signal to the complete crossbar array, such that the switch connected to control line 310 is disabled by the control signal, while the switch connected to control line 312 is enabled. Thus, independent control of the gate terminals of the switches using different control lines 310, 312 may allow processor 110 to selectively enable or disable first portion 210 and second portion 212.

[0036] FIG. 3B illustrates an exemplary implementation of the tile illustrated in FIG. 3A , in one embodiment. In one embodiment, processor 110 may send a control signal on control line 310 to enable first portion 210 of memory element 202. In response to first portion 210 being enabled, resistors R11, R21, R12, and R22 may be connected to their corresponding column and row lines. Because control line 310 is separate from control line 312, processor 110 may send a control signal on control line 310 but not on control line 312 to selectively enable first portion 210 and disable second portion 212. In response to first portion 210 being enabled and second portion being disabled, resistors R31, R41, R32, and R42 may be disconnected from their corresponding row lines (e.g., as indicated by the dotted lines in FIG. 3B ).

[0037] In response to first portion 210 being enabled, processor 110 may provide input data 206 to first portion 210 via row lines. Input data 206 may include synaptic weight values ​​w k 3B , in response to the first portion 210 being enabled, the vector elements u1 and u2 of the input data 206 may be input to the tile 102 and multiplied by the synaptic weight values ​​w1 and w2, respectively. Because the second portion 212 is disabled, the vector elements u1 and u2 do not reach the separate resistors R31, R41, R32, and R42. The input data 206 and the synaptic weight values ​​w k The products of the vector elements of are accumulated in capacitor C to produce a result 216, where the result 216 is the sum of the input data 206 and the synaptic weight values ​​w kis the result of a MAC operation performed on capacitor C. In one embodiment, control line 310 and control line 312 may be the same control line, and processor 110 may selectively connect or disconnect the column lines to capacitor C. As an example, processor 100 may connect the column lines including resistors R11, R21, R12, and R22 to capacitor C and disconnect the column lines including resistors R31, R41, R32, and R42 from capacitor C. Thus, even if u1 and u2 reach resistors R31, R41, R32, and R42, the products u1(-w1) and u2(w2) are not output to capacitor C.

[0038] 3C illustrates, in one embodiment, further details of the exemplary implementation of FIG. 3B. In response to tile 102 outputting result 216, processor 110 may send another control signal on control line 312 to enable second portion 212. In response to second portion 212 being enabled, resistors R31, R41, R32, and R42 may be connected to their corresponding column and row lines, and first portion 210 may be disabled. In response to second portion 212 being enabled and first portion 210 being disabled, resistors R31, R41, R32, and R42 may be disconnected from their corresponding row lines (e.g., as indicated by the dotted lines in FIG. 3C).

[0039] In response to the second portion 212 being enabled, the processor 110 may provide the input data 208 to the tile 102. The input data 208 may be the inverse of the input data 206 and thus may include vector elements -u1 and -u2. In the example shown in FIG. 3C, in response to the second portion 212 being enabled, the vector elements -u1 and -u2 of the input data 208 may be input to the tile 102 and multiplied by the inverse values ​​-w1 and -w2, respectively. Because the first portion 210 is disabled, the vector elements -u1 and -u2 do not reach the separate resistors R11, R21, R12, and R22. k The products of the vector elements of are accumulated in capacitor C to produce a result 218, where the result 218 is the product of the input data 208 and the reciprocal value -w kFurthermore, since the vector elements -u1, -u2, and -w1, -w2 are negative values, the input data 208 and the inverse value -w k The product of the vector elements of can be positive.

[0040] Input data 206 and synaptic weight values ​​w k and the input data 208 and the inverse value -w k In response to completing the second MAC operation on (see FIG. 3B ), capacitor C may store the sum of result 216 and result 218. The sum of results 216, 218 may be read by processor 110, which may determine a final result of the first MAC operation. As an example, due to a fixed asymmetry between analog memory elements (e.g., resistors) in first portion 210 and second portion 212, result 216 may be 1.9 and result 218 may be 2.1. Processor 110 may determine the average value between 1.9 and 2.1 to determine a final result of 2.0. Thus, 2.0 may be a compensated version of MAC operation result 216, which indicates 1.9. Result 216 without compensation from result 218 deviates from the average value of 2.0 by a deviation value of −0.1.

[0041] Under ideal circumstances, for example, u1w1 is equal to (-u1)(-w1), so the results 216, 218 are identical. However, the results 216, 218 may differ from each other due to positive or negative weights, positive or negative inputs, or any fixed mismatch or asymmetry between the peripheral circuitry (e.g., mismatch between the current paths of the first and second MAC operations). The systems and methods described herein may average the difference between the currents generated during the first and second MAC operations to provide compensation for the fixed asymmetry. The inverse value -w k Store and input -w k Compensation may be provided to the first MAC operation by performing a second MAC operation on the inverse of , which may improve the accuracy of the first MAC operation.

[0042] 4 is a flow diagram illustrating, in one embodiment, a method for fixed asymmetry compensation for multiplication and accumulation operations. Process 400 in FIG. 4 may be implemented using, for example, device 114 described above. Process 400 may include one or more operations, acts, or functions represented by one or more of blocks 402, 404, 406, 408, and / or 410. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, eliminated, performed in a different order, or performed in parallel, depending on the desired implementation.

[0043] Process 400 may begin at block 402. At block 402, a processor (e.g., processor 110 in FIG. 1 ) may send an input vector to a first portion of a memory device. The first portion may store synaptic weights of a trained artificial neural network (ANN). Process 400 may proceed from block 402 to block 404. At block 404, the processor may read a first result of a multiplication and accumulation (MAC) operation performed on the input vector and synaptic weights stored in the first portion.

[0044] Process 400 may proceed from block 404 to block 406. At block 406, the processor may send the inverse of the input vector to a second portion of the memory device. Process 400 may proceed from block 406 to block 408. At block 408, the processor may read a second result of the MAC operation performed on the inverse of the input vector and the inverse of the synaptic weights stored in the second portion.

[0045] Process 400 may proceed from block 408 to block 410. At block 410, the processor may combine the first result and the second result to generate a final result. The final result may be a compensated result of the MAC operation performed on the input vectors and synaptic weights stored in the first portion. In one embodiment, the processor may combine the first result and the second result by averaging the first result and the second result to generate the final result.

[0046] In one embodiment, the memory device may include a plurality of memory elements arranged in a plurality of memory blocks. The first portion may include a first set of memory elements in each of the plurality of memory blocks. The second portion may include a second set of memory elements in each of the plurality of memory blocks. In one embodiment, the first set of memory elements may include a first pair of memory elements, and the second set of memory elements may include a second pair of memory elements. In one embodiment, the memory device may be an analog nonvolatile memory device.

[0047] In one embodiment, the processor may enable a first portion of the memory device, and the step of sending the input vector to the first portion may be performed in response to enabling the first portion. The processor may disable the first portion in response to the step of reading the first result. The processor may enable a second portion in response to the step of disabling the first portion. The processor further enables the second portion of the memory device, and the step of sending the reciprocal of the input vector to the second portion is performed in response to the step of enabling the second portion.

[0048] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be implemented substantially simultaneously, or the blocks may be implemented in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, are implemented by a dedicated hardware-based system that performs the specified functions or actions or executes a combination of dedicated hardware and computer instructions.

[0049] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. As used herein, the term "or" is an inclusive operator and can mean "and / or" unless the context expressly or clearly dictates otherwise. It will be further understood that as used herein, the term "comprise," "comprises," "comprising," "include," "including," "having," or combinations thereof, can specify the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups, or combinations thereof. As used herein, the phrase "in one embodiment" may, but does not necessarily, refer to the same embodiment. As used herein, the phrase "in one embodiment" may, but does not necessarily, refer to the same embodiment. As used herein, the phrase "in another embodiment" does not necessarily refer to a different embodiment, but may. Furthermore, embodiments and / or components of embodiments may be freely combined with each other unless they are mutually exclusive.

[0050] As used herein, a "module" or "unit" may include hardware (e.g., circuitry such as an application-specific integrated circuit), firmware, and / or software executable by hardware (e.g., a processor or microcontroller), and / or combinations thereof, for performing various operations disclosed herein. For example, the processor or hardware may include one or more integrated circuits configured to perform function mapping or polynomial fitting based on readings of currents output from one or more output lines of the crossbar array at different times and / or apply a function to subsequent outputs to correct or compensate for temporal conductance variations of the crossbar array. The same processor or another processor may include circuitry configured to input activation vectors encoded as electrical pulse durations and / or voltage signals across the input lines for the crossbar array to perform its operations.

[0051] All means or steps in the following claims and corresponding structure, material, acts, and equivalents of functional elements (if any) are intended to include any structure, material, or acts for performing a function in combination with other claimed elements as specifically claimed. While the description of the present invention has been presented for purposes of illustration and description, it is not intended to be exhaustive or to limit the invention to the form disclosed. Many changes and modifications that do not depart from the scope of the invention will be apparent to those skilled in the art. These embodiments were chosen and described in order to best explain the principles and practical applications of the invention and to enable those skilled in the art to understand the invention in various embodiments with various modifications suited to the particular use contemplated.

Claims

1. A plurality of memory elements arranged in a plurality of memory blocks, each memory block comprising: a first set of memory elements of the plurality of memory elements, the first set of memory elements configured to store synaptic weights of a trained artificial neural network (ANN); and a second set of memory elements of the plurality of memory elements, the second set of memory elements configured to store the inverses of the synaptic weights stored in the first set of memory elements; A plurality of memory elements, including A memory device comprising:

2. The memory device of claim 1 , wherein the plurality of memory elements are analog non-volatile memory elements.

3. the first set of memory elements includes a first pair of memory elements; and The second set of memory elements includes a second pair of memory elements. The memory device of claim 1 .

4. 10. The memory device of claim 1, wherein the first set of memory elements and the second set of memory elements are separately enabled to perform multiply and accumulate (MAC) operations.

5. the first set of memory elements further comprising: receiving a vector element of an input vector; and performing a MAC operation on the vector elements and the synaptic weights; It is configured as follows: the second set of memory elements further comprising: receiving the inverse of the vector element; performing a MAC operation on the reciprocals of the vector elements and the reciprocals of the synaptic weights; It is configured as follows: The memory device of claim 1 .

6. each one of the plurality of memory elements is connected to a switch; a first set of switches of the memory elements in the memory block are connected to a first control line; and The switches of the second set of memory elements in the memory block are connected to a second control line. The memory device of claim 1 .

7. sending an input vector to a first portion of a memory device, the first portion storing synaptic weights of a trained artificial neural network (ANN); reading a first result of a multiplication and accumulation (MAC) operation performed on the input vector and the synaptic weights stored in the first portion; transmitting the inverse of the input vector to a second portion of the memory device; reading a second result of a MAC operation performed on the reciprocal of the input vector and the reciprocal of the synaptic weight stored in the second portion; and combining the first result and the second result to generate a final result, the final result being a compensated result of the MAC operation performed on the input vector and the synaptic weights stored in the first portion. A method for providing the above.

8. enabling the first portion of the memory device, wherein transmitting the input vector to the first portion is performed in response to enabling the first portion; and enabling the second portion of the memory device, wherein transmitting the inverse of the input vector to the second portion is performed in response to enabling the second portion. The method of claim 7 further comprising:

9. invalidating the first portion in response to reading the first result; and enabling the second portion in response to disabling the first portion. The method of claim 8 further comprising:

10. The memory device is a plurality of memory elements arranged in a plurality of memory blocks; the first portion of the plurality of memory blocks, each memory block including a first set of memory elements; and a second portion of the plurality of memory blocks, each memory block including a second set of memory elements; The method of claim 7, comprising:

11. the first set of memory elements includes a first pair of memory elements; and The second set of memory elements includes a second pair of memory elements. The method of claim 10.

12. The method of claim 7 , wherein the memory device is an analog non-volatile memory device.

13. 8. The method of claim 7, wherein combining the first result and the second result comprises averaging the first result and the second result to produce the final result.

14. a memory device; and sending an input vector to a first portion of the memory device, wherein the first portion stores synaptic weights of a trained artificial neural network (ANN); reading a first result of a multiplication and accumulation (MAC) operation performed on the input vector and the synaptic weights stored in the first portion; sending the inverse of the input vector to a second portion of the memory device; reading a second result of a MAC operation performed on the reciprocal of the input vector and the reciprocal of the synaptic weights stored in the second portion; and combining the first result and the second result to generate a final result, wherein the final result is a compensated result of the MAC operation performed on the input vector and the synaptic weights stored in the first portion. A processor configured to A system comprising:

15. The processor: enabling the first portion of the memory device, wherein transmitting the input vector to the first portion is performed in response to the first portion being enabled; and enabling the second portion of the memory device, wherein transmitting the inverse of the input vector to the second portion is performed in response to the second portion being enabled. The system of claim 14 configured to:

16. The processor: invalidating the first portion in response to reading the first result; and Enabling the second portion in response to disabling the first portion. The system of claim 15 configured to:

17. The memory device is a plurality of memory elements arranged in a plurality of memory blocks; the first portion of the plurality of memory blocks, each memory block including a first set of memory elements; and a second portion of the plurality of memory blocks, each memory block including a second set of memory elements; The system of claim 14 , comprising:

18. the first set of memory elements includes a first pair of memory elements; and The second set of memory elements includes a second pair of memory elements.

20. The system of claim 17.

19. 15. The system of claim 14, wherein the memory device is an analog non-volatile memory device.

20. 15. The system of claim 14, wherein the processor is configured to combine the first result and the second result by averaging the first result and the second result to produce the final result.

21. A computer program comprising a program code which, when said program is run on a computer, causes said computer to carry out the steps of the method according to any one of claims 7 to 13.

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