Semiconductor device

Abstract

To provide a semiconductor device capable of improving breakdown voltage characteristics.SOLUTION: A first potential region (11) including a drain region (14) extending in a first direction (Y), a second potential region (12) surrounding the first potential region, and a drift region, a field insulating film covering the drift region, and a field resistance film provided on the field insulating film, wherein the first potential region is continuously connected to a first linear region (111) and a first end portion (111a) of the first linear region, and an end portion region (112A) having a curved first outer edge (1121), the second end portion (11a) of the first potential region is located on the first outer edge, and a length (14a) between the third end portion (d2) and the second end portion of the drain region is shorter than a length (d1) between the drain region and the second outer edge (111c) of the first linear region in the second direction (X).SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having a high potential region, a low potential region, and a drift region. The drift region is formed in a region between the high potential region and the low potential region. The semiconductor device described in Patent Document 1 further includes a field insulating film covering the drift region, and a field resistive film provided on the field insulating film and electrically connected to the high potential region and the low potential region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-129053

[0004] [overview] SUMMARY OF THE INVENTION It is an object of one aspect of the present disclosure to provide a semiconductor device that can achieve improved breakdown voltage.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor substrate, a semiconductor layer located on the semiconductor substrate, the semiconductor layer having, in a plan view, a first potential region including a drain region extending in a first direction and to which a first potential is applied, a second potential region including a source region and surrounding the first potential region and to which a second potential is applied, and a drift region located between the drain region and the second potential region, a field insulating film covering the drift region, and a field insulating film provided on the field insulating film and electrically connected to the first potential region and the second potential region. and a resistive film, wherein the first potential region has, in a planar view, a first linear region that includes at least a portion of the drain region and extends in the first direction, and an end region that, in a planar view, is continuously connected to a first end of the first linear region in the first direction and has a curved first outer edge, wherein a second end of the first potential region in the first direction is located on the first outer edge, and the length between the third end of the drain region and the second end in the first direction is shorter than the length between the drain region and the second outer edge of the first linear region in a second direction that intersects the first direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a chip of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is an enlarged view of region II shown in FIG. [Figure 3] FIG. 3 is a schematic diagram for explaining the first potential region and the second potential region of the transistor region shown in FIG. [Figure 4] FIG. 4 is a partially enlarged view of the cross-sectional configuration of the transistor region taken along the dashed line IV shown in FIG. [Figure 5] FIG. 5 is a partially enlarged view of the cross-sectional configuration of the transistor region at the position of the dashed dotted line V shown in FIG. [Figure 6] FIG. 6 is a partially enlarged view of the cross-sectional configuration of the transistor region taken along the dashed line VI in FIG. [Figure 7]FIG. 7 is a diagram for explaining an end region of the first potential region. [Figure 8] FIG. 8 is a schematic diagram showing the first potential region according to the first modification. [Figure 9] FIG. 9 is a schematic diagram showing the first potential region according to the second modification.

[0007] [Detailed explanation] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, identical elements or elements having the same functions will be designated by the same reference numerals, and redundant explanations will be omitted. In this specification, the terms "same" and similar words are not limited to "completely same." Since the drawings are intended to conceptually explain the embodiments, the dimensions and ratios of the components shown may differ from those in reality.

[0008] FIG. 1 is a plan view showing a chip of a semiconductor device according to this embodiment. FIG. 2 is an enlarged view of region II shown in FIG. 1. FIG. 3 is a schematic diagram for explaining the first potential region and the second potential region of the transistor region shown in FIG. 2. FIG. 4 is a partially enlarged view of the cross-sectional configuration of the transistor region taken along dashed line IV in FIG. 3. FIG. 4 shows an example of the cross-sectional configuration of an operating region OR (see FIG. 2), which will be described later. FIG. 5 is a partially enlarged view of the cross-sectional configuration of the transistor region taken along dashed line V in FIG. 3. FIG. 6 is a partially enlarged view of the cross-sectional configuration of the transistor region taken along dashed line VI in FIG. 3. FIGS. 5 and 6 show an example of the cross-sectional configuration of a termination region TR (see FIG. 2), which will be described later.

[0009] 1, semiconductor device 1 includes a rectangular parallelepiped silicon chip 2 (semiconductor chip). Chip 2 is one of multiple devices formed on a silicon wafer, for example, with a diameter of 300 mm (approximately 12 inches).

[0010] The chip 2 has a pair of main surfaces, a first main surface 3 and a second main surface 4, and a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D that connect the first main surface 3 and the second main surface 4. Hereinafter, the extension direction of the first side surface 5A and the second side surface 5B in a plan view is referred to as the X direction (second direction), the extension direction of the third side surface 5C and the fourth side surface 5D in a plan view is referred to as the Y direction (first direction), and the normal direction of the first main surface 3 and the second main surface 4 is referred to as the Z direction. The Y direction is a direction that intersects with the X direction in a plan view, and the Z direction corresponds to the thickness direction of the chip 2.

[0011] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from the Z direction, but are not limited to this. In this embodiment, the first main surface 3 is the top surface, and the second main surface 4 is the bottom surface. Therefore, a configuration located near the first main surface 3 in the Z direction corresponds to a configuration located on the top surface side (upper side) of the semiconductor device 1, and a configuration located near the second main surface 4 in the Z direction corresponds to a configuration located on the bottom surface side (lower side) of the semiconductor device 1.

[0012] The semiconductor device 1 includes a semiconductor region 6 (see FIGS. 4 to 6) located in an upper region within the chip 2. The semiconductor region 6 is a region having a first conductivity type and has a layer shape extending along the first main surface 3. For this reason, the semiconductor region 6 is also sometimes referred to as a semiconductor layer. The semiconductor region 6 is at least a part of an epitaxial semiconductor layer. The semiconductor region 6 is exposed from the first main surface 3 and the first side surface 5A, the second side surface 5B, the third side surface 5C, and the fourth side surface 5D. The thickness of the semiconductor region 6 is, for example, 5 μm or more and 20 μm or less. In this embodiment, the first conductivity type is n-type. The n-type impurity concentration of the semiconductor region 6 is, for example, 1.0×10 13 cm -3 Over 1.0 x 10 15 cm -3 The following is the result.

[0013] The semiconductor device 1 includes a semiconductor region 7 located in a lower region within the chip 2. The semiconductor region 7 is a region that has a second conductivity type and is fixed at a predetermined potential, and has a layer shape extending along the second main surface 4. The semiconductor region 7 is exposed from the second main surface 4 and the first side surface 5A, the second side surface 5B, the third side surface 5C, and the fourth side surface 5D. In this embodiment, the semiconductor region 7 is fixed to a back gate potential. The back gate potential may be a reference potential that serves as a reference for circuit operation, or may be a ground potential. In this embodiment, the second conductivity type is p-type. The p-type impurity concentration of the semiconductor region 7 is, for example, 1.0×10 12 cm -3 Over 1.0 x 10 14 cm -3 The following is the result.

[0014] The semiconductor region 7 is connected to the semiconductor region 6. The thickness of the semiconductor region 7 may be 50 μm or more and 400 μm or less. The semiconductor region 7 is at least a part of a p-type semiconductor substrate. That is, the chip 2 has the semiconductor region 6 included in the epitaxial semiconductor layer and the semiconductor region 7 included in the semiconductor substrate. In other words, the chip 2 has a layered structure including the semiconductor substrate and the epitaxial semiconductor layer located on the semiconductor substrate.

[0015] The semiconductor device 1 includes a plurality of device regions 8 defined on the first main surface 3. In the semiconductor device 1, the number and arrangement of the plurality of device regions 8 are determined as appropriate. Each of the plurality of device regions 8 includes a functional device formed using regions inside and outside the chip 2. The functional device includes, for example, at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may also include a circuit network that combines at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device.

[0016] The semiconductor switching device may include, for example, at least one of a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a JFET. The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0017] The plurality of device regions 8 includes at least one transistor region 9. The transistor region 9 includes a FET structure (transistor structure). In this embodiment, the FET structure has a so-called LDMISFET (Lateral Double Diffused MISFET) structure. The FET structure is a high-voltage device to which a drain voltage of 800 V or more can be applied in the off state, for example. The structure of the transistor region 9 will be described below with reference to FIGS. 2 to 6.

[0018] The transistor region 9 is a region defined by an isolation region, and includes an n-type impurity region 10 located within the semiconductor region 6.

[0019] In this embodiment, the impurity region 10 is a part of the semiconductor region 6 that is partitioned by the separation region. The n-type impurity concentration of the impurity region 10 is, for example, equal to the n-type impurity concentration of the semiconductor region 6. The impurity region 10 has an oval shape in a planar view, but is not limited to this. The impurity region 10 may also have a circular shape, an elliptical shape, a polygonal shape (e.g., a rectangular shape), or the like.

[0020] The transistor region 9 includes a first potential region 11, a second potential region 12, and a drift region 13. The first potential region 11 is a region to which a first potential is applied. The second potential region 12 is a region to which a second potential is applied. For example, the first potential region 11 is a high potential region to which a high potential (first potential) is applied, and the second potential region 12 is a low potential region to which a low potential (second potential) less than the high potential is applied. The drift region 13 is a region between the drain region 14 and the second potential region 12 included in the first potential region 11. In the following, unless otherwise specified, the first potential region 11 is a high potential region, and the second potential region 12 is a low potential region.

[0021] The first potential region 11 is located in the center of the impurity region 10 in a plan view. The first potential region 11 has an oval shape with the Y direction as the major axis and the X direction as the minor axis. Specifically, as shown in FIG. 3, the first potential region 11 has a linear region (first linear region) 111 and two end regions 112A and 112B. For ease of explanation, in FIG. 3, the boundary between the linear region 111 and the end region 112 and the boundary between the linear region 111 and the end region 112B are indicated by solid lines.

[0022] The linear region 111 is a strip-shaped region extending in the Y direction.

[0023] The end region 112A is a region that includes the end (second end) 11a in the Y direction of the first potential region 11. The end region 112B is a region that includes the end (second end) 11b in the Y direction of the first potential region 11. The end 11b is an end opposite to the end 11a in the Y direction.

[0024] The end region 112A is continuously connected to an end (first end) 111a in the Y direction of the linear region 111, and the end region 112B is continuously connected to an end (first end) 111b in the Y direction of the linear region 111. The end 111b is an end located opposite the end 111a in the Y direction.

[0025] The outer edge (first outer edge) 1121 of each of the end regions 112A and 112B has a curved shape. In a plan view, the shape of the outer edge 1121 is, for example, an arc. The end region 112A is a region defined by the end 111a and the outer edge 1121. The end region 112B is a region defined by the end 111b and the outer edge 1121.

[0026] The first potential region 11 includes a drain region 14 and a well region 15 (see FIGS. 4 to 6). The drain region 14 and the well region (first semiconductor region) 15 are provided above the semiconductor region 6, respectively.

[0027] The drain region 14 constitutes a part of the first main surface 3. The drain region 14 extends in the Y direction in a plan view. At least a part of the drain region 14 is included in the linear region 111.

[0028] In this embodiment, the drain region 14 extends in the Y direction in plan view and has an oval shape with rounded ends. Specifically, as shown in Fig. 3, the drain region 14 has a strip-shaped linear region 141 extending in the Y direction and two end regions 142A and 142B.

[0029] The linear region 141 is included in the linear region 111 in plan view. The length of the linear region 141 in the Y direction is the same as the length of the linear region 111. The end region 142A is continuously connected to one end of the linear region 141 and is included in the end region 112A. An end (third end) 14a of the drain region 14 is located in the end region 142A. The end region 142B is continuously connected to the other end of the linear region 141 and is included in the end region 112B. An end (third end) 14b of the drain region 14 is located in the end region 142B. The linear region 141 of the drain region 14 is the part that substantially functions as a drain in a transistor.

[0030] In a plan view, the well region 15 surrounds the drain region 14. In a plan view, the drain region 14 is spaced apart from the periphery of the well region 15. That is, the drain region 14 is located inside the periphery of the well region 15. In a plan view, the outer edge of the well region 15 defines the outer edge of the first potential region 11. The well region 15 is in contact with the drain region 14. Therefore, the potential of the well region 15 is fixed to a potential (drain potential) equal to the potential of the drain region 14.

[0031] The n-type impurity concentration of the drain region 14 is higher than the n-type impurity concentration of the well region 15. The n-type impurity concentration of the drain region 14 is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The n-type impurity concentration of the well region 15 is higher than the n-type impurity concentration of the impurity region 10. The n-type impurity concentration of the well region 15 is, for example, 1.0×10 15 cm -3 Over 1.0 x 10 18 cm -3 The following is the result.

[0032] In a plan view, the second potential region 12 is located within the separation region and surrounds the first potential region 11. The second potential region 12 has an elliptical ring shape with the Y direction as the major axis and the X direction as the minor axis. As shown in Figures 2 and 3, the second potential region 12 has two linear regions (second linear regions) 12A and 12B and two curved regions 12C and 12D.

[0033] The linear regions 12A and 12B are located opposite each other in the X direction across the first potential region 11. The linear regions 12A and 12B are linear portions (or strip-shaped portions) extending along the Y direction in a plan view, and extend parallel to each other.

[0034] The length of each of the linear regions 12A and 12B in the Y direction is the same as the length of the linear region 111. The positions of the linear regions 12A and 12B in the Y direction are the same as the position of the linear region 111. As shown by dashed lines in FIG. 3, the position of one end 121a of each of the linear regions 12A and 12B in the Y direction is the same as the position of the end 111a of the linear region 111, and the position of the other end 121b of each of the linear regions 12A and 12B in the Y direction is the same as the position of the end 111b of the linear region 111. The dashed lines in FIG. 3 are intended to indicate the positional relationship of the linear regions 12A and 12B with respect to the linear region 111. In this embodiment, the lengths of the linear regions 12A and 12B and their positional relationship with respect to the linear region 111 are not limited to the illustrated form.

[0035] The curved region (first curved region) 12C connects one end 121a of the linear region 12A with one end 121a of the linear region 12B. The curved region 12C extends in an arc-like band shape between the one end 121a of the linear region 12A and the one end 121a of the linear region 12B. The outer edge 12a and the inner edge 12b of the second potential region 12 may have the same radius of curvature in the curved region 12C.

[0036] The curved region (second curved region) 12D connects the other end 121b of the linear region 12A to the other end of the linear region 12B. The curved region 12D extends in an arc-like band shape between the other end 121b of the linear region 12A and the other end of the linear region 12B. The radii of curvature of the outer edge 12a and the inner edge 12b of the second potential region 12 in the curved region 12D may be the same. The radii of curvature of the outer edge 12a and the inner edge 12b of the second potential region 12 in the curved region 12D may be the same.

[0037] The second potential region 12 includes a p-type body region 16 (see FIGS. 4 to 6) located between the isolation region and the well region 15. The body region 16 extends, for example, along the periphery of the impurity region 10. Specifically, the body region (second semiconductor region) 16 has an oval ring shape surrounding the impurity region 10. The outer edge of the body region 16 defines an outer edge 12a of the second potential region 12.

[0038] 4 to 6, the body region 16 extends in the Z direction from the first main surface 3 to the boundary between the semiconductor region 6 and the semiconductor region 7. In this embodiment, the body region 16 has a first body region 161 and a second body region 162.

[0039] The first body region 161 is formed at the boundary between the semiconductor region 7 and the impurity region 10. The first body region 161 is formed at a distance from the first main surface 3 and the second main surface 4 in the Z direction. The first body region 161 is electrically connected to the semiconductor region 7. The first body region 161 has a higher p-type impurity concentration than the semiconductor region 7. The p-type impurity concentration of the first body region 161 is, for example, 2.0×10 15 cm -3 Over 2.0 x 10 18 cm -3 The following is the result.

[0040] The second body region 162 is formed in a region between the first main surface 3 and the first body region 161. The second body region 162 is electrically connected to the first body region 161. As shown in FIGS. 4 to 6, the second body region 162 may extend beyond the first body region 161 toward the drain region 14. The second body region 162 has a lower p-type impurity concentration than the first body region 161. The p-type impurity concentration of the second body region 162 is, for example, 1.0×10 15 cm -3 Over 1.0 x 10 18 cm -3 The following is the result.

[0041] As described above, the first body region 161 is electrically connected to the semiconductor region 7, and the second body region 162 is electrically connected to the first body region 161. Therefore, the first body region 161 and the second body region are fixed to the potential of the semiconductor region 7 (for example, the back gate potential).

[0042] In the above example, the body region 16 includes the first body region 161 and the second body region 162. However, the body region 16 may be a single region in which the first body region 161 and the second body region 162 are integrated. In other words, the p-type impurity concentrations of the first body region 161 and the second body region 162 may be the same. In this case, the p-type impurity concentration may be, for example, 1.0×10 15 cm -3 Over 1.0 x 10 18 cm -3 In this case as well, the body region 16 is electrically connected to the semiconductor region 7, and the potential of the body region 16 is fixed to the potential of the semiconductor region 7 (for example, the back gate potential).

[0043] 2, the body region 16 is divided into a first region 16A, a second region 16B, a third region 16C, and a fourth region 16D. The first region 16A and the second region 16B are each a linear portion (or a strip-shaped portion) extending along the Y direction in a plan view, and extend parallel to each other. The first region 16A is included in the linear region 12A. The second region 16B is included in the linear region 12B.

[0044] The third region 16C is a curved portion connecting one end of the first region 16A in the Y direction and one end of the second region 16B in the Y direction. In the present embodiment, the third region 16C is included in the curved region 12C. The third region 16C extends in the shape of an arc band between one end of the first region 16A and one end of the second region 16B.

[0045] The fourth region 16D is a curved portion connecting the other end of the first region 16A in the Y direction and the other end of the second region 16B in the Y direction. In this embodiment, the fourth region 16D is included in the curved region 12D. The fourth region 16D extends in an arc band shape between the other end of the first region 16A and the other end of the second region 16B.

[0046] The semiconductor device 1 includes a source region 17 provided in the body region 16. In this embodiment, the semiconductor device 1 includes multiple source regions 17, but is not limited to this. Each of the multiple source regions 17 is an n-type region and is fixed to a source potential. Specifically, a source potential is applied to each of the multiple source regions 17 from outside the chip 2. In the impurity region 10, a p-type channel region 18 in the FET structure is formed between the source region 17 and the drift region 13 in the X direction. Therefore, a current path extending in the X direction is formed in the impurity region 10 between the source region 17 and the drift region 13 in the X direction. The source potential corresponds to the second potential.

[0047] The n-type impurity concentration of the source region 17 is higher than the n-type impurity concentration of the well region 15. The n-type impurity concentration of the source region 17 may be equal to the n-type impurity concentration of the drain region 14. The n-type impurity concentration of the source region 17 is, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The channel region 18 controls whether the current path between the drain region 14 and the source region 17 is conductive or non-conductive.

[0048] Each of the source regions 17 has a band shape in a plan view. Each of the source regions 17 is located in the body region 16 and inside the outer edge of the body region 16. Each of the source regions 17 constitutes a part of the first major surface 3, i.e., a part of the surface layer of the body region 16. A part of the source regions 17 is located in the first region 16A. Ends of the part in the Y direction are located inside the ends of the first region 16A in the Y direction, but this is not limited to this. Other parts of the source regions 17 are located in the second region 16B. Ends of the part in the Y direction are located inside the ends of the second region 16B in the Y direction, but this is not limited to this. None of the source regions 17 is located in the third region 16C or the fourth region 16D. The length of each source region 17 in the Y direction is, for example, equal to or shorter than the length of the drain region 14. For example, when one source region 17 is located in the body region 16, the source region 17 is located in at least one of the first region 16A and the second region 16B of the body region 16.

[0049] The second potential region 12 includes a contact region 19 provided in the body region 16. In this embodiment, the contact region 19 has a band shape in plan view and is located inside the body region 16 relative to the outer edge of the body region 16. The contact region 19 is formed in an oval ring shape along the body region 16 in plan view. The contact region 19 constitutes part of the first main surface 3, i.e., part of the surface layer of the body region 16.

[0050] The contact region 19 is a p-type region. The p-type impurity concentration of the contact region 19 may be higher than the p-type impurity concentration of the body region 16. For example, the p-type impurity concentration of the contact region 19 may be, for example, 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The following is the result.

[0051] In the portion of the body region 16 where the source region 17 exists (for example, the first region 16A and the second region 16B), the contact region 19 is located between the source region 17 and the outer edge of the body region 16 in a plan view. The contact region 19 is located closer to the outer edge of the body region 16 than the source region 17. The contact region 19 may be adjacent to the source region 17.

[0052] In this way, the width of the contact region 19 may be narrower in the portion adjacent to the source region 17 than in the other portions. The width of the contact region 19 is the length in a direction perpendicular to the extending direction of the contact region 19 in a plan view. The width of the contact region 19 may be the same as the width of the body region 16 except for the portion juxtaposed with the source region 17.

[0053] Instead of one oval ring-shaped contact region 19, the semiconductor device 1 may have multiple contact regions 19. In this case, the multiple contact regions 19 include a contact region 19 arranged in the first region 16A and a contact region 19 arranged in the second region 16B.

[0054] The semiconductor device 1 includes an n-type drift region 13 located between the drain region 14 and the second potential region 12 and in a surface layer portion of the impurity region 10. The drift region 13 has, for example, an oval ring shape surrounding the drain region 14 in a plan view.

[0055] In this embodiment, drift region 13 has a first portion (straight portion) extending in the Y direction so as to be parallel to first region 16A and second region 16B, and a second portion (arc portion) extending in an arc shape so as to be parallel to third region 16C and fourth region 16D. Drift region 13 forms a current path in the portion along first region 16A and second region 16B, but does not form a current path in the portion along third region 16C and fourth region 16D.

[0056] The width of the drift region 13 corresponds to the distance between the drain region 14 and the second potential region 12. The width of the arc portion of the drift region 13 may increase from the linear portion toward the center of the arc. The width of the linear portion of the drift region 13 may be approximately constant.

[0057] The semiconductor device 1 includes insulating films 22 and 23 that selectively cover the first main surface 3 in the transistor region 9. Each of the insulating films 22 and 23 includes silicon oxide. Each of the insulating films 22 and 23 includes a LOCOS film (Local Oxidation of Silicon Film) formed by selective oxidation of the first main surface 3, a buried oxide film (STI: Shallow Trench Isolation) that fills shallow trenches provided in the first main surface 3, and the like. The insulating films 22 and 23 may have a single-layer structure or a multilayer structure.

[0058] The insulating film (field insulating film) 22 is located on the semiconductor region 6 and covers the region between the drain region 14 and the second potential region 12 on the first main surface 3. The insulating film 22 is located, for example, on the drift region 13 in the impurity region 10 and has an oval ring shape surrounding the drain region 14 in a plan view, and includes an inner edge portion 22a and an outer edge portion 22b.

[0059] 2, the outer edge 22b is indicated by a dashed line. The inner edge 22a of the insulating film 22 is located outside the drain region 14. The outer edge 22b is located inside the inner edge of the body region 16 in a plan view. In this embodiment, the outer edge 22b defines the inner edge 12b of the second potential region 12. In other words, in this embodiment, the second potential region 12 extends from the outer edge 22b of the insulating film 22 to the outer edge of the body region 16 in a plan view. Portions of the body region 16, the source region 17, the contact region 19, and the drift region 13 are exposed from the insulating film 22.

[0060] The insulating film 22 is defined into a first region 22c (see FIG. 4) in which an operating region OR of a field resistive film 25 (described later) is provided, and a second region 22d (see FIGS. 5 and 6) in which a termination region TR of the field resistive film 25 is provided. Although not shown, in this embodiment, the insulating film 22 is defined into a pair of first regions 22c and a pair of second regions 22d.

[0061] The insulating film 23 covers the region outside the transistor region 9. The thickness of the insulating film 23 may be equal to that of the insulating film 22, and the material of the insulating film 23 may be the same as that of the insulating film 22. The insulating film 23 covers the outer periphery of the body region 16.

[0062] 2 and 4 to 6, the semiconductor device 1 includes a field resistive film 25 located on the insulating film 22 in the transistor region 9. The field resistive film 25 has functions such as suppressing electric field disturbances in the semiconductor region 6, suppressing localized electric field concentration, and monitoring the high drain-gate voltage Vdg, and is a high-resistivity film connected to the first potential region 11 and the second potential region 12. The "field resistive film" may also be referred to as a field electrode, a field plate, or the like.

[0063] The field resistance film 25 is located on the drift region 13 in the Z direction. In this embodiment, the field resistance film 25 does not overlap the channel region 18 in the Z direction. The field resistance film 25 includes, for example, polysilicon. The field resistance film 25 is electrically connected to at least the drain region 14.

[0064] In this embodiment, the field resistive film 25 forms a potential gradient that gradually changes from the first potential region 11 to the second potential region 12. By providing such a field resistive film 25, bias in the electric field distribution in the drift region 13 is suppressed. The thickness of the field resistive film 25 is, for example, not less than 50 nm and not more than 100 nm.

[0065] As shown in FIG. 2, the field resistive film 25 has an active region OR located between the drain region 14 and the source region 17, and a termination region TR located outside the active region OR in a plan view.

[0066] In this embodiment, the active region OR of the field resistive film 25 is located between a pair of termination regions TR in the Y direction. Each termination region TR is located outside the active region OR in the Y direction. In other words, each termination region TR is located outside the active region OR in a direction intersecting or perpendicular to the current path. Alternatively, one of the termination regions TR can be said to be located between the drain region 14 and the curved region 12C of the second potential region 12 (or the third region 16C of the body region 16) in a planar view, and the other of the termination regions TR can be said to be located between the drain region 14 and the curved region 12D of the second potential region 12 (or the fourth region 16D of the body region 16) in a planar view.

[0067] The active region OR is a region including a portion of the field resistive film 25 that overlaps with the current path. In a plan view, one end of the active region OR in the Y direction is located between one end 17a of the source region 17 and the end 14a of the drain region 14 in the Y direction, but is not limited to this. For example, in a plan view, one end of the active region OR in the Y direction may be aligned with one end 17a of the source region 17 in the Y direction, or with the end 14a of the drain region 14 in the Y direction, or with one end of a linear portion of the drain region 14 in the Y direction. In a plan view, the other end of the active region OR in the Y direction is located between the other end 17b of the source region 17 and the end 14b of the drain region 14 in the Y direction, but is not limited to this. For example, in a plan view, the other end of the operating region OR in the Y direction may be aligned with the other end 17b of the source region 17 in the Y direction, or with the end 14b of the drain region 14 in the Y direction, or with the other end of the straight portion of the drain region 14 in the Y direction.

[0068] The one end of the operating region OR corresponds to the boundary between the operating region OR and one termination region TR, and overlaps with the boundary in the Y direction between each of the first regions 22c and one of the second regions 22d of the insulating film 22. The other end of the operating region OR corresponds to the boundary between the operating region OR and the other termination region TR, and overlaps with the boundary in the Y direction between each of the first regions 22c and the other of the second regions 22d of the insulating film 22. Therefore, each of the one end and the other end of the operating region OR can be considered to be the boundary.

[0069] The operating region OR has a plurality of first line portions 25a. Each of the plurality of first line portions 25a extends linearly along the Y direction and is spaced apart from one another in the X direction. Each first line portion 25a overlaps a linear portion of the drift region 13 in the Z direction via a corresponding first region 22c of the insulating film 22. An end of the first line portion 25a in the Y direction may overlap an arc portion of the drift region 13. In this case, the end may extend in an arc shape.

[0070] The entirety or most of each termination region TR is a region including a portion of the field resistive film 25 that does not overlap the current path. Each termination region TR has a plurality of second line portions 25b. Each of the plurality of second line portions 25b extends in an arc shape in the X direction and is spaced apart from one another in the Y direction. Each second line portion 25b overlaps an arc portion of the drift region 13 in the Z direction via a corresponding second region 22d of the insulating film 22 (see FIGS. 5 and 6). An end of the second line portion 25b in the X direction may overlap a linear portion of the drift region 13. In this case, the end may extend linearly. Each of the plurality of second line portions 25b is connected to a corresponding first line portion 25a. As a result, the field resistive film 25 is routed in a linear shape on the insulating film 22.

[0071] For example, the field resistive film 25 concentrically surrounds the first potential region 11 including the drain region 14 multiple times in a plan view. The field resistive film 25 may have a spiral shape surrounding the first potential region 11 in a plan view.

[0072] The field resistance film 25 has a first end 26 located near the drain region 14, a second end 27 located near the second potential region 12, and a spiral portion 28 extending between the first end 26 and the second end 27. The first end 26 and the second end 27 may be positioned arbitrarily.

[0073] The first end 26 is a connection portion electrically connected to the drain region 14 and is the innermost portion (innermost periphery) of the field resistive film 25. For example, in a plan view, the first end 26 corresponds to the first line portion 25a that is the innermost of the multiple first line portions 25a. The potential applied to the first end 26 is a first potential or a potential nearby the first potential. The first end 26 may overlap the well region 15 in the Z direction.

[0074] The second end 27 is the outermost portion (outermost periphery) of the field resistive film 25. The second end 27 corresponds to, for example, the outermost first line portion 25a of the multiple first line portions 25a in a planar view. The potential applied to the second end 27 is the second potential or a potential nearby the second potential. The second end 27 may overlap the drift region 13 in the Z direction. The spiral portion 28 is a portion (connection portion) that connects the first end 26 and the second end 27, and is wound in an elliptical spiral shape from the first end 26 to the second end 27 so as to surround the drain region 14 in a planar view. The spiral portion 28 overlaps the drift region 13 in the Z direction. A portion of the spiral portion 28 may overlap the well region 15.

[0075] The field resistive film 25 forms a potential gradient in the spiral direction from the first end 26 to the second end 27. The field resistive film 25 also forms a potential gradient that gradually decreases in a direction perpendicular to the spiral direction from the first potential region 11 to the second potential region 12 in accordance with the winding pitch of the spiral portion 28. The field resistive film 25 thins out the electric field in the drift region 13, suppressing bias in the electric field distribution in the drift region 13.

[0076] The field resistive film 25 may have a line width of 0.5 μm or more and 5 μm or less. The line width is defined by the width in a direction perpendicular to the extension direction (i.e., the spiral direction) of the field resistive film 25. The field resistive film 25 may have a resistance value of 10 MΩ or more and 100 MΩ or less. The line width of the first line portion 25a and the line width of the second line portion 25b may each be approximately constant. When the width of the drift region 13 gradually increases toward the center of the arc, the line width of the second line portion 25b may gradually increase toward the center of the arc.

[0077] The pitch of the field resistive film 25 may be 1 μm or more and 10 μm or less. The pitch of the field resistive film 25 is defined by the distance between adjacent line portions (i.e., the winding pitch of the spiral portion 28). The number of turns of the field resistive film 25 is, for example, 5 to 100. The number of turns may be 75 or less, or 50 or less.

[0078] The semiconductor device 1 includes an inner field resistive film 29 located on the insulating film 22 and connected to the field resistive film 25. The inner field resistive film 29 is located closer to the drain region 14 than the field resistive film 25 in a planar view. In this embodiment, the inner field resistive film 29 is located in a region surrounded by the field resistive film 25 in a planar view. The potential of the inner field resistive film 29 is fixed to a first potential. The inner field resistive film 29 may be a part of the field resistive film 25. In this case, the inner field resistive film 29 functions as the innermost part of the field resistive film 25. The inner field resistive film 29 includes the same material as the field resistive film 25, such as conductive polysilicon described below.

[0079] The inner field resistive film 29 is disposed at a position spaced apart from the drain region 14 in plan view. In this embodiment, the inner field resistive film 29 has an oval ring shape surrounding the drain region 14. The inner field resistive film 29 may overlap the well region 15 in the Z direction. The inner field resistive film 29 includes an inner edge portion 29a and an outer edge portion 29b. The inner edge portion 29a is provided, for example, at a position spaced at a substantially constant distance from the drain region 14 in plan view. The outer edge portion 29b is provided, for example, at a substantially constant distance from the spiral portion 28 of the field resistive film 25. The distance between the inner field resistive film 29 and the spiral portion 28 is, for example, equal to the pitch of the field resistive film 25.

[0080] In this embodiment, the width of the inner field resistive film 29 is non-uniform along the circumferential direction. The inner field resistive film 29 has a protruding portion 30 at its outer edge 29b. The protruding portion 30 protrudes toward the field resistive film 25 so as to contact the first end 26 of the field resistive film 25. To suppress bias in the electric field caused by the first end 26 of the field resistive film 25, the protruding portion 30 maintains a substantially constant distance between the inner field resistive film 29 and the field resistive film 25. The protruding portion 30 is connected to the first end 26, but this is not a limitation. In other words, the inner field resistive film 29 does not have to be connected to the first end 26 as long as it is fixed at the same potential as the first end 26. Therefore, the protruding portion 30 may face the tip of the first end 26 in the spiral direction. The inner field resistive film 29 may or may not be provided.

[0081] The width of the inner field resistive film 29 is, for example, 1 μm or more and 15 μm or less. The inner field resistive film 29 may be formed wider than the field resistive film 25. In this case, the width of the inner field resistive film 29 is, for example, 1.5 times or more and 5 times or less the width of the field resistive film 25. The width of the inner field resistive film 29 may be equal to or less than the line width of the field resistive film 25.

[0082] The semiconductor device 1 includes a gate insulating film 31 that contacts the semiconductor region 6 and is located on the channel region 18. A portion of the gate insulating film 31 overlaps the insulating film 22. The thickness of the gate insulating film 31 is less than that of the insulating film 22, and is, for example, 10 nm to 200 nm. The gate insulating film 31 has a single-layer structure or a multilayer structure and includes, for example, a silicon oxide film. In this embodiment, the gate insulating film 31 has an oval ring shape surrounding the insulating film 22 in a plan view. The gate insulating film 31 covers a portion of the drift region 13 and a portion of the body region 16.

[0083] The semiconductor device 1 includes a gate electrode 32 located on a gate insulating film 31. The gate electrode 32 includes, for example, a metal film, an alloy film, or conductive polysilicon. When the gate electrode 32 includes conductive polysilicon, the conductive polysilicon includes at least one of an n-type region and a p-type region. The gate electrode 32 overlaps not only the channel region 18 but also the drift region 13 in the Z direction. The gate electrode 32 has an oval ring shape extending along the channel region 18 in a plan view, but is not limited to this. The gate electrode 32 has an extension portion 33 extending from the gate insulating film 31 onto the insulating film 22. The extension portion 33 has an oval ring shape surrounding a field resistive film 25 (described later) in a plan view and is located above the drift region 13. The entire gate electrode 32 is located outside the field resistive film 25 in a plan view.

[0084] The gate electrode 32 includes an inner edge portion 32a and an outer edge portion 32b. The inner edge portion 32a is formed by an extension portion 33. The outer edge portion 32b is located in a region overlapping the body region 16 in a plan view. In this embodiment, the width of the gate electrode 32 is non-uniform along the circumferential direction, but this is not limited to this. Specifically, as shown in FIG. 2 , the gate electrode 32 has a gate extension portion 34 that extends toward the drain region 14 at the outer edge portion 32b (extension portion 33). The gate extension portion 34 is a portion that is provided according to the shape of the field resistive film 25, which will be described later. By providing the gate extension portion 34, the distance between the gate electrode 32 and the field resistive film 25 is maintained approximately constant in a plan view.

[0085] As shown in FIGS. 4 to 6, the semiconductor device 1 includes an insulating layer 40 that covers a plurality of device regions 8 on the first main surface 3. The insulating layer 40 has a layered structure including a plurality of interlayer insulating films 41 stacked on top of each other. The number of stacked interlayer insulating films 41 is arbitrary and is not limited to a specific number. The insulating layer 40 may include three or more interlayer insulating films 41. FIGS. 4 to 6 show a first interlayer insulating film 41A and a second interlayer insulating film 41B out of the plurality of interlayer insulating films 41.

[0086] The first interlayer insulating film 41A and the second interlayer insulating film 41B are stacked in this order in the Z direction. The first interlayer insulating film 41A covers at least the first main surface 3, the insulating film 22, the gate insulating film 31, and the gate electrode 32. The second interlayer insulating film 41B covers the first interlayer insulating film 41A. The thicknesses of the first interlayer insulating film 41A and the second interlayer insulating film 41B are determined depending on, for example, the function required of the field resistive film 25, the thickness of the insulating film 22, and the like. The first interlayer insulating film 41A and the second interlayer insulating film 41B each include at least one of a silicon oxide film and a silicon nitride film. Therefore, the first interlayer insulating film 41A and the second interlayer insulating film 41B may each have a single-layer structure or a multilayer structure.

[0087] A plurality of wiring films 42 are provided within the insulating layer 40. In this embodiment, a plurality of interlayer insulating films 41 and a plurality of wiring films 42 are alternately stacked, thereby providing a multilayer wiring structure on the semiconductor region 6. The number of stacked wiring films 42 is arbitrary and is not limited to a specific number. FIGS. 4 to 6 show, of the plurality of wiring films 42, a first wiring film 42A located on a first interlayer insulating film 41A and a second wiring film 42B located on a second interlayer insulating film 41B. Each wiring film 42 includes, for example, at least one of an Al film, a Cu film, an AlSiCu alloy film, an AlSi alloy film, and an AlCu alloy film. Therefore, each of the first wiring film 42A and the second wiring film 42B may have a single-layer structure or a multilayer structure.

[0088] A plurality of first vias 43 and a plurality of second vias 49 are provided in the insulating layer 40. Each of the plurality of first vias 43 is a conductive portion that electrically connects conductive portions, such as the first potential region 11, the second potential region 12, and the field resistance film 25, located below the first interlayer insulating film 41A to the first wiring film 42A, and penetrates the first interlayer insulating film 41A. Each of the plurality of second vias 49 is a conductive portion that electrically connects conductive portions, such as the first wiring film 42A located below the second interlayer insulating film 41B, to the second wiring film 42B, and penetrates the second interlayer insulating film 41B. Each of the plurality of first vias 43 and the plurality of second vias 49 is, for example, a tungsten plug.

[0089] The first wiring film 42A includes, for example, a first drain wiring 44, a first source wiring 45, a first gate wiring 46, a field wiring 47, and a field wiring 48.

[0090] The first drain wiring 44 is electrically connected to the drain region 14 through one or more first vias 43. The first source wiring 45 is electrically connected to the source region 17 through one or more first vias 43. The first source wiring 45 may be electrically connected to the source region 17 through one or more first vias 43, for example, in the termination region TR. The first gate wiring 46 is electrically connected to the gate electrode 32 through one or more first vias 43.

[0091] The field wiring 47 is electrically connected to the first end 26 of the field resistive film 25 through one or more first vias 43. The field wiring 47 is electrically connected to the inner field resistive film 29, for example, through one or more first vias 43. The field wiring 47 may be part of the first drain wiring 44. The field wiring 48 is electrically connected to the second end 27 of the field resistive film 25 through one or more first vias 43. The field wiring 48 may be part of the first source wiring 45.

[0092] The plurality of second wiring films 42B include, for example, second drain wirings 50, second source wirings 51, and second gate wirings (not shown).

[0093] The second drain wiring 50 is electrically connected to the first drain wiring 44 and the field wiring 47 through a plurality of second vias 49. The second drain wiring 50 overlaps the drain region 14 and the field wiring 47. The second drain wiring 50 may overlap the entire drain region 14 and the entire field wiring 47. The second drain wiring 50 may overlap the inner field resistive film 29.

[0094] The second source wiring 51 is electrically connected to the first source wiring 45 and the field wiring 48 via a plurality of second vias 49. The second source wiring 51 has a ring shape extending along the body region 16 in a plan view. The second source wiring 51 may overlap the gate electrode 32 and the field wiring 48. The second source wiring 51 may overlap the entire body region 16, the entire gate electrode 32, and the entire field wiring 48. The wiring form is not limited to the form illustrated. For example, the source region 17 may be wired so as to be fixed at a potential different from that of the contact region 19.

[0095] Next, the first potential region 11 will be further described with reference to Fig. 7 in addition to Fig. 4 to Fig. 6. Specifically, the conditions that the end region 112A and the end region 112B of the first potential region 11 must satisfy will be described. Since the end region 112A and the end region 112B must satisfy the same conditions, the end region 112A will be used as an example for the description.

[0096] 7 is a diagram for explaining the end region. In FIG. 7, the vicinity of the end region 112A is shown enlarged, and for the sake of explanation, the linear region 12A, the linear region 12B, and the curved region 12C of the second potential region 12 are also shown. Unless otherwise specified, the first potential region 11 is symmetrical with respect to the center line of the linear region 111 in the X direction. The center line is a line that passes through the center of the linear region 111 in the X direction and extends in the Y direction.

[0097] As described above, the first potential region 11 includes the drain region 14. In a plan view, the drain region 14 is located in the center of the first potential region 11 in the X direction. The length d1 between the outer edge (second outer edge) 111c of the linear region 111 of the first potential region 11 and the linear region 141 of the drain region 14 is constant in the Y direction.

[0098] The first potential region 11 has an end region 112A that is continuously connected to the end 111a of the linear region 111. The outer edge 1121 of the end region 112A has a curved shape. The end 11a of the first potential region 11 is located on the outer edge 1121.

[0099] 7, the length between the drain region 14 and the outer edge 1121 is referred to as length d. Length d may be the length between the drain region 14 and the outer edge 1121 along a line (the dashed line shown in FIG. 7) connecting the midpoint C of the end 111a in the X direction and an arbitrary point P on the outer edge 1121.

[0100] When point P is the intersection P1 of outer edge 1121 and outer edge (side) 111c, length d is length d1. The length between end 11a and end 14a along the Y direction is referred to as length d2. In this embodiment, end 14a and end 11a are located on the center line, so length d2 corresponds to length d when point P is located at the intersection of the center line and outer edge 1121. Length d2 may be 0 (zero).

[0101] The first potential region 11 is a region that satisfies the condition that "length d2 is shorter than length d1 in the Y direction" (hereinafter referred to as "condition A").

[0102] The shape of the outer edge 1121 may be an arc. In this case, the radius of curvature of the outer edge 1121 may be the same as the radius of curvature of the inner edge 12b of the curved region 12C. In this embodiment, by forming the first potential region 11 (specifically, the well region 15) so that the center of curvature O of the outer edge 1121 is located within the straight region 111, the first potential region 11 that satisfies the above condition A can be formed.

[0103] The length d between the drain region 14 and the outer edge 1121 may decrease from the intersection P1 of the outer edge 1121 and the outer edge 111c along the outer edge 1121 toward the end 11a, as shown in FIG.

[0104] As mentioned above, the condition A satisfied by the first potential region 11 has been described using the end region 112A as an example, but the same applies to the condition satisfied by the end region 112B. Specifically, in the description of the end region 112A, the end region 112A, the end 14a, and the end 111a, the end region 112B, the end 14b, and the end 111b should be read as the end region 112B, the end 14b, and the end 111b.

[0105] In the semiconductor device 1, the transistor region 9 includes the insulating film 22 and the field resistance film 25, thereby ensuring the breakdown voltage of the transistor region 9.

[0106] In the semiconductor device 1, both end regions in the Y direction of the first potential region 11 (end regions 112A, 112B) satisfy the above condition A. This improves the breakdown voltage characteristics in the transistor region 9. This point will be explained.

[0107] The Y-direction ends of the first potential region 11 and the drain region 14 are rounded to alleviate electric field concentration. When the ends are rounded in this manner, the Y-direction ends of the first potential region 11 and the drain region 14 usually have an arc shape in plan view, and the ends of the first potential region 11 and the drain region 14 are formed so that the length d shown in FIG. 7 is constant. This case where the length d is constant is referred to as a reference example. The dashed dotted lines in FIGS. 5 and 6 indicate the drain-side well region that defines the first potential region in the reference example.

[0108] In contrast, in the semiconductor device 1, the first potential region 11 satisfies condition A. In this case, in the termination region TR shown in FIG. 2, as shown in FIGS. 5 and 6, the outer edge of the well region 15 that defines the first potential region 11 is formed closer to the drain region 14 than in the reference example (in the case of the dashed-dotted line shown in FIGS. 5 and 6). As a result, the length between the second potential region 12 and the first potential region 11 in the termination region TR is longer. In this case, the depletion layer is more likely to expand in the termination region TR. As a result, the breakdown voltage of the transistor region 9 is improved.

[0109] The outer shape of the first potential region 11 in a planar view is determined by the well region 15. Therefore, the breakdown voltage can be improved by adjusting the formation area of ​​the well region 15. In this case, the configuration is the same as that of the above-mentioned reference example, except that the layer structure of the transistor region 9 (the multiple layers and stacked state of the multiple layers that the transistor region 9 has) and the outer shape of the well region 15 are adjusted. Although the layer structure of the transistor region 9 affects the on-resistance, the layer structure itself of the transistor region 9 is not changed, so the on-resistance characteristics are substantially maintained. In other words, the semiconductor device 1 can improve the breakdown voltage characteristics while maintaining the on-resistance characteristics.

[0110] The length d between the drain region 14 and the outer edge 1121 may decrease from the intersection P1 between the outer edge 1121 and the outer edge 111c along the outer edge 1121 toward the end 11a. In this case, the outer edge 1121 at the Y-direction end of the first potential region 11 forms a smooth curve, making electric field concentration less likely to occur. This makes it easier to improve the breakdown voltage characteristics.

[0111] The shape of the end of the first potential region 11 in the Y direction is not limited as long as it satisfies condition A. For example, the first potential region may have the end shapes described in the following modified examples 1 and 2. Because the shapes of both end regions in the Y direction of the first potential region are similar, modified examples 1 and 2 will be described focusing on the end region 112A side, as in the case of FIG.

[0112] (Variation 1) Fig. 8 is a schematic diagram showing a first potential region according to Modification 1. Fig. 8 corresponds to a diagram in which the first potential region 11 in Fig. 7 is replaced with a first potential region 11-1 according to Modification 1.

[0113] The first potential region 11-1 has a linear region 111 and an end region 112A-1. The linear region 111 and the drain region 14 included in the linear region 111 are the same as those in the first potential region 11, and therefore a description thereof will be omitted.

[0114] The edge region 112A-1 differs from the edge region 112A in that it is formed flatter than the edge region 112A. That is, the edge region 112A-1 is compressed closer to the drain region 14 in the vicinity of the edge 11a than the edge region 112A.

[0115] The end region 112A-1 also satisfies the condition A. Therefore, a semiconductor device that employs the first potential region 11-1 instead of the first potential region 11 also has the same effects as the semiconductor device 1.

[0116] (Variation 2) 9 is a schematic diagram showing a first potential region according to Modification 2. In FIG. 9, the first potential region 11 in FIG. 7 is replaced with a first potential region 11-2 according to Modification 2.

[0117] The first potential region 11-2 has a linear region 111 and an end region 112A-2. The linear region 111 and the drain region 14 included in the linear region 111 are the same as those in the first potential region 11, and therefore a description thereof will be omitted.

[0118] The width of the end region 112A-2 in the X direction is shorter than the width (corresponding to twice the length d1) of the linear region 111. For example, the end region 112A-2 has a semicircular shape centered at the midpoint C and having a radius shorter than the length d1.

[0119] The end region 112A-2 also satisfies the condition A. Therefore, a semiconductor device that employs the first potential region 11-1 instead of the first potential region 11 also has the same effects as the semiconductor device 1.

[0120] The above describes in detail embodiments and variations relating to one aspect of the present disclosure, but these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims.

[0121] For example, in a plan view, the inner edge of the second potential region may be regarded as the inner edge of the source-side body region (body region 16 shown in FIGS. 4 to 6). As long as the first potential region is formed so as to satisfy condition A, the first potential region is not limited to the configuration symmetrical with respect to the center line described above. While the first conductivity type has been described as n-type and the second conductivity type as p-type, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0122] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0123] [A1] (Embodiment, Figures 2 to 7) A semiconductor substrate (7), a semiconductor layer (6, 10) located on the semiconductor substrate, the semiconductor layer (6, 10) having, in a plan view, a first potential region (11) including a drain region (14) extending in a first direction (Y) and to which a first potential is applied, a second potential region (12) including a source region (17) and surrounding the first potential region and to which a second potential is applied, and a drift region (13) located between the drain region and the second potential region; a field insulating film (22) covering the drift region; a field resistive film (25) provided on the field insulating film and electrically connected to the first potential region and the second potential region; Preparation, The first potential region is a first linear region (111) that includes at least a portion of the drain region and extends in the first direction in a plan view; end regions (112A, 112B) that are continuously connected to a first end (111a) of the first linear region in the first direction in a plan view and have a curved first outer edge (1121); and a second end (11a, 11b) of the first potential region in the first direction is located on the first outer edge, a length (d2) between a third end (14a, 14b) of the drain region and the second end in a second direction (X) intersecting the first direction is shorter than a length (d1) between the drain region and a second outer edge (111c) of the first linear region in the first direction; Semiconductor Devices

[0124] [A2] (Embodiment, Figure 7) The length (d) between the drain region and the first outer edge decreases from the intersection (P1) of the first end and the first outer edge toward the second end. The semiconductor device according to [A1].

[0125] [A3] (Embodiment, Figure 3) The second potential region is a pair of second linear regions (12A, 12B) including the source region and extending in the first direction in a plan view; a first curved region (12C) connecting one ends (121a) of the pair of second linear regions in a plan view; a second curved region (12D) connecting the other ends (121b) of the pair of second linear regions in a plan view; and The radius of curvature of the first outer edge, the radius of curvature of the first curved region, and the radius of curvature of the second curved region are the same. The semiconductor device according to [A1] or [A2].

[0126] [A4] (Embodiment, Figure 3) In a plan view, the first potential region has an elliptical shape, In a plan view, the second potential region has an oval ring shape, the first direction is a major axis direction of the first potential region and the second potential region, the second direction is a minor axis direction of the first potential region and the second potential region; The semiconductor device according to any one of [A1] to [A3].

[0127] [A5] (Embodiment, Figure 7) In a plan view, the shape of the first outer edge is an arc, and a center of curvature (O) of the arc is located within the first linear region. The semiconductor device according to any one of [A1] to [A4].

[0128] [A6] (Embodiment, Figures 4 to 6) the first potential region is in contact with the drain region and has a first semiconductor region (15) surrounding the drain region in a plan view; The second potential region is in contact with the source region and has a second semiconductor region (16) that is aligned with the second potential region in a plan view. The semiconductor device according to any one of [A1] to [A5].

[0129] [A7] (Embodiment, Figures 4 to 6) a gate insulating film (31) provided between the source region and the field insulating film in a plan view; a gate electrode (32) provided on the gate insulating film; Further comprising: The semiconductor device according to any one of [A1] to [A6].

[0130] [A8] The second potential is lower than the first potential. The semiconductor device according to any one of [A1] to [A7]. [Explanation of symbols]

[0131] 1...Semiconductor device 2...Chip (semiconductor chip) 3...First main surface 4...Second main surface 5A…1st side 5B…Second side 5C…Third side 5D…Fourth side 6...Semiconductor region (semiconductor layer) 7...Semiconductor region (semiconductor substrate) 8...Device area 9...Transistor area 10…Impurity region 11, 11-1, 11-2...first potential region 11a...End (second end) 11b...End (second end) 111...Straight line area (first straight line area) 111a...End part (first part) 111b...End (first end) 111c...Outer edge (second outer edge) 112,112A,112A-1,112A-2...End area 112B...End area 1121...Outer edge (first outer edge) 12…Second potential region 12a...Outer edge 12b...Common-law marriage 12A, 12B…Line line area (second line area) 12C...Curve area (first curve area) 12D…Curve area (second curve area) 121a...one end 121b...other end 13...Drift region 14...Drain region 14a...End (third end) 14b...End (third end) 141…Straight line area 142A…End area 142B...End area 15...Well region (first semiconductor region) 16...Body region (second semiconductor region) 16A…First area 16B…Second area 16C...Third area 16D…4th area 161...First body region 162...Second body region 17...Source region 17a…one end 17b...other end 18...Channel region 19...Contact area 22...Insulating film (field insulating film) 22a...inner edge 22b...outer edge 22c…First area 22d…Second area 23...Insulating film 25...Field resistive film 25a...First line section 25b...Second line section 26...First end 27…Second end 28...Spiral part 29...Inner field resistive film 29a...inner edge 29b...Outer edge 30...Protruding part 31...Gate insulating film 32...Gate electrode 32a...inner edge 32b...outer edge portion, outer edge portion (drawing portion 33) 33...Drawer section 34...Gate overhang 40...insulating layer 41...Interlayer insulating film 41A...First interlayer insulating film 41B...Second interlayer insulating film 42...Wiring film 42A…1st wiring film 42B…Second wiring film 43...First via 44...First drain wiring 45...First source wiring 46...First gate wiring 47...Field wiring 48...Field wiring 49...Second via 50...Second drain wiring 51...Second source wiring C...midpoint O…center of curvature OR…Operating area TR…Terminal area P…point P1...intersection

Claims

1. a semiconductor substrate; a semiconductor layer located on the semiconductor substrate, the semiconductor layer having, in a plan view, a first potential region including a drain region extending in a first direction and to which a first potential is applied, a second potential region including a source region and surrounding the first potential region and to which a second potential is applied, and a drift region located between the drain region and the second potential region; a field insulating film covering the drift region; a field resistive film provided on the field insulating film and electrically connected to the first potential region and the second potential region; Preparation, The first potential region is a first linear region that includes at least a portion of the drain region and extends in the first direction in a plan view; an end region that is continuously connected to a first end of the first linear region in the first direction in a plan view and has a curved first outer edge; and a second end of the first potential region in the first direction is located on the first outer edge; a length between a third end and the second end of the drain region in the first direction is shorter than a length between the drain region and a second outer edge of the first linear region in a second direction intersecting the first direction; Semiconductor device.

2. a length between the drain region and the first outer edge decreases from an intersection of the first end and the first outer edge toward the second end; The semiconductor device according to claim 1 .

3. The second potential region is a pair of second linear regions extending in the first direction and including the source region in a plan view; a first curved region connecting one end of each of the pair of second linear regions in a plan view; a second curved region connecting the other ends of the pair of second linear regions in a plan view; and The radius of curvature of the first outer edge, the radius of curvature of the first curved region, and the radius of curvature of the second curved region are the same.

3. The semiconductor device according to claim 1.

4. The first potential region has an elliptical shape in a plan view, In a plan view, the second potential region has an oval ring shape, the first direction is a major axis direction of the first potential region and the second potential region, the second direction is a minor axis direction of the first potential region and the second potential region; 3. The semiconductor device according to claim 1.

5. In a plan view, the shape of the first outer edge is an arc, and a center of curvature of the arc is located within the first linear region.

3. The semiconductor device according to claim 1.

6. the first potential region is in contact with the drain region and has a first region surrounding the drain region in a plan view; the second potential region is in contact with the source region and has a second region that is aligned with the second potential region in a plan view; 3. The semiconductor device according to claim 1.

7. a gate insulating film provided between the source region and the field insulating film in a plan view; a gate electrode provided on the gate insulating film; Further comprising:

3. The semiconductor device according to claim 1.

8. the second potential is lower than the first potential; 3. The semiconductor device according to claim 1.

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