Chip resistor and method of manufacturing the same

Abstract

To provide a chip resistor having lower electric resistance and more stable quality.SOLUTION: The chip resistor 1 includes a metal resistor 10, a first plated electrode 15, and a second plated electrode 16. The metal resistor 10 has a top surface 11 and a bottom surface 12 opposite to the top surface 11. The first plated electrode 15 is disposed on the bottom surface 12. The second plated electrode 16 is disposed on the bottom surface 12 and is separated from the first plated electrode 15. The top surface 11 is a flat surface.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a chip resistor and a method for manufacturing the same. [Background technology]

[0002] International Publication No. 2012 / 157435 (Patent Document 1) discloses a chip resistor including a resistor portion, a first electrode, and a second electrode. The first electrode is bent and welded to one end of the resistor portion. The second electrode is bent and welded to the other end of the resistor portion. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2012 / 157435

[0004] [overview] An object of the present disclosure is to provide a chip resistor with lower electrical resistance and more consistent quality.

[0005] The chip resistor of the present disclosure includes a metal resistor element, a first plated electrode, and a second plated electrode. The metal resistor element has a top surface and a bottom surface opposite the top surface. The first plated electrode is disposed on the bottom surface. The second plated electrode is disposed on the bottom surface and is spaced apart from the first plated electrode. The top surface is flat. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of the chip resistors according to the first and third embodiments. [Figure 2] FIG. 2 is a schematic bottom view of the chip resistors according to the first and third embodiments. [Figure 3] FIG. 3 is a schematic cross-sectional view of the chip resistor according to the first embodiment taken along the cross-sectional line III-III shown in FIG. [Figure 4]FIG. 4 is a schematic perspective view showing one step of the method for manufacturing the chip resistors according to the first and second embodiments. [Figure 5] FIG. 5 is a schematic perspective view showing a step subsequent to the step shown in FIG. 4 in the method for manufacturing the chip resistor according to the first and second embodiments. [Figure 6] FIG. 6 is a schematic perspective view showing a step subsequent to the step shown in FIG. 5 in the method for manufacturing the chip resistor according to the first embodiment. [Figure 7] FIG. 7 is a schematic perspective view showing a step subsequent to the step shown in FIG. 6 in the method for manufacturing the chip resistor according to the first embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view of a chip resistor according to a first modified example of the first embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view of a circuit board on which a chip resistor according to a first modification of the first embodiment is mounted. [Figure 10] FIG. 10 is a schematic cross-sectional view of a chip resistor according to a second modified example of the first embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view of a circuit board on which a chip resistor according to a second modification of the first embodiment is mounted. [Figure 12] FIG. 12 is a schematic plan view of the chip resistors according to the second and fourth embodiments. [Figure 13] FIG. 13 is a schematic bottom view of the chip resistors according to the second and fourth embodiments. [Figure 14] FIG. 14 is a schematic cross-sectional view of the chip resistor according to the second embodiment taken along the cross-sectional line XIV-XIV shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view of a circuit board on which the chip resistor of the second embodiment is mounted. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 6 in the method for manufacturing the chip resistor according to the second embodiment. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 16 in the method for manufacturing the chip resistor according to the second embodiment. [Figure 18]FIG. 18 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 17 in the method for manufacturing the chip resistor according to the second embodiment. [Figure 19] FIG. 19 is a schematic cross-sectional view of a chip resistor according to a modification of the second embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view of a circuit board on which a chip resistor according to a modification of the second embodiment is mounted. [Figure 21] FIG. 21 is a schematic cross-sectional view of the chip resistor according to the third embodiment taken along the cross-sectional line XXI-XXI shown in FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view of a circuit board on which the chip resistor of the third embodiment is mounted. [Figure 23] FIG. 23 is a schematic perspective view showing one step of the method for manufacturing the chip resistors according to the third and fourth embodiments. [Figure 24] FIG. 24 is a schematic perspective view showing a step subsequent to the step shown in FIG. 23 in the method for manufacturing the chip resistor according to the third and fourth embodiments. [Figure 25] FIG. 25 is a schematic perspective view showing a step subsequent to the step shown in FIG. 24 in the method for manufacturing the chip resistor according to the third embodiment. [Figure 26] FIG. 26 is a schematic cross-sectional view of the chip resistor according to the fourth embodiment taken along the cross-sectional line XXVI-XXVI shown in FIG. [Figure 27] FIG. 27 is a schematic cross-sectional view of a circuit board on which the chip resistor of the fourth embodiment is mounted. [Figure 28] FIG. 28 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 24 in the method for manufacturing the chip resistor according to the fourth embodiment. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 28 in the method for manufacturing the chip resistor according to the fourth embodiment. [Figure 30] FIG. 30 is a schematic cross-sectional view of a chip resistor according to a modification of the fourth embodiment. [Figure 31] FIG. 31 is a schematic cross-sectional view of a circuit board on which a chip resistor according to a modification of the fourth embodiment is mounted. [Figure 32] FIG. 32 is a schematic plan view of the chip resistors according to the fifth and sixth embodiments. [Figure 33] FIG. 33 is a schematic bottom view of the chip resistors according to the fifth and sixth embodiments. [Figure 34] FIG. 34 is a schematic cross-sectional view of the chip resistor according to the fifth embodiment taken along the cross-sectional line XXXIV-XXXIV shown in FIG. [Figure 35] FIG. 35 is a schematic perspective view showing one step of the method for manufacturing the chip resistors according to the fifth and seventh embodiments. [Figure 36] FIG. 36 is a schematic perspective view showing a step subsequent to the step shown in FIG. 35 in the method for manufacturing the chip resistor according to the fifth embodiment. [Figure 37] FIG. 37 is a schematic perspective view showing a step subsequent to the step shown in FIG. 36 in the method for manufacturing the chip resistor according to the fifth embodiment. [Figure 38] FIG. 38 is a schematic cross-sectional view of the chip resistor according to the sixth embodiment taken along the cross-sectional line XXXVIII-XXXVIII shown in FIG. [Figure 39] FIG. 39 is a schematic perspective view showing one step of the method for manufacturing the chip resistor according to the sixth embodiment. [Figure 40] FIG. 40 is a schematic perspective view showing a step subsequent to the step shown in FIG. 39 in the method for manufacturing the chip resistor according to the sixth embodiment. [Figure 41] FIG. 41 is a schematic perspective view showing a step subsequent to the step shown in FIG. 40 in the method for manufacturing the chip resistor according to the sixth embodiment. [Figure 42] FIG. 42 is a schematic perspective view showing a step subsequent to the step shown in FIG. 41 in the method for manufacturing the chip resistor according to the sixth embodiment. [Figure 43] FIG. 43 is a schematic plan view of the chip resistors according to the seventh and eighth embodiments. [Figure 44] FIG. 44 is a schematic bottom view of the chip resistors according to the seventh and eighth embodiments. [Figure 45]FIG. 45 is a schematic cross-sectional view of the chip resistor according to the seventh embodiment taken along the cross-sectional line LXV-LXV shown in FIG. [Figure 46] FIG. 46 is a schematic cross-sectional view of a circuit board on which the chip resistor of the seventh embodiment is mounted. [Figure 47] FIG. 47 is a schematic perspective view showing a step subsequent to the step shown in FIG. 35 in the method for manufacturing the chip resistor according to the seventh embodiment. [Figure 48] FIG. 48 is a schematic perspective view showing a step subsequent to the step shown in FIG. 47 in the method for manufacturing the chip resistor according to the seventh embodiment. [Figure 49] FIG. 49 is a schematic cross-sectional view of the chip resistor according to the eighth embodiment taken along the cross-sectional line LXIXV-LXIX shown in FIG. [Figure 50] FIG. 50 is a schematic cross-sectional view of a circuit board on which the chip resistor of the eighth embodiment is mounted. [Figure 51] FIG. 51 is a schematic perspective view showing one step of the method for manufacturing the chip resistor according to the eighth embodiment. [Figure 52] FIG. 52 is a schematic perspective view showing a step subsequent to the step shown in FIG. 51 in the method for manufacturing the chip resistor according to the eighth embodiment. [Figure 53] FIG. 53 is a schematic perspective view showing a step subsequent to the step shown in FIG. 52 in the method for manufacturing the chip resistor according to the eighth embodiment. [Figure 54] FIG. 54 is a schematic perspective view showing a step subsequent to the step shown in FIG. 53 in the method for manufacturing the chip resistor according to the eighth embodiment.

[0007] [Detailed explanation] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated. At least some of the configurations of the embodiments described below may be combined in any manner.

[0008] (Embodiment 1) A chip resistor 1 according to a first embodiment will be described with reference to Figures 1 to 3. The chip resistor 1 is, for example, a shunt resistor. A shunt resistor is used, for example, to measure the magnitude of a current. The chip resistor 1 includes a metal resistive element 10, a first plated electrode 15, and a second plated electrode 16.

[0009] 1 to 3, the metal resistor 10 is made of, for example, a copper-manganese (CuMn) based alloy, a copper-nickel (CuNi) based alloy, or a nickel-chromium (NiCr) based alloy.

[0010] The metal resistor 10 has a top surface 11, a bottom surface 12 opposite the top surface 11, a first end surface 13, and a second end surface 14 opposite the first end surface 13. The top surface 11 and the bottom surface 12 are both end surfaces of the metal resistor 10 in the thickness direction. The top surface 11 is a flat surface. When the chip resistor 1 is mounted on a circuit board, the bottom surface 12 faces the circuit board. The bottom surface 12 is the mounting surface of the chip resistor 1. The first end surface 13 and the second end surface 14 are connected to the top surface 11 and the bottom surface 12, respectively. The first end surface 13 and the second end surface 14 are both end surfaces of the metal resistor 10 in the longitudinal direction. The first end surface 13 is one end surface of the metal resistor 10 in the direction in which the first plated electrode 15 and the second plated electrode 16 are spaced apart from each other. The second end surface 14 is the other end surface of the metal resistor 10 in the direction in which the first plated electrode 15 and the second plated electrode 16 are spaced apart from each other.

[0011] The first plated electrode 15 and the second plated electrode 16 are electrodes formed by plating. The first plated electrode 15 and the second plated electrode 16 are formed of a material having a lower electrical resistivity than the metal resistor 10. The first plated electrode 15 and the second plated electrode 16 are formed of, for example, copper (Cu) or a copper-based alloy. The first plated electrode 15 and the second plated electrode 16 are spaced apart from each other. The first plated electrode 15 and the second plated electrode 16 are disposed on the bottom surface 12 of the metal resistor 10.

[0012] The first plating electrode 15 has a first surface 15a opposite to the metal resistor 10, a first inner end face 15b facing the second plating electrode 16, and a first outer end face 15c opposite to the first inner end face 15b. The first inner end face 15b is, for example, perpendicular to the bottom surface 12. The first surface 15a and the first inner end face 15b are connected at a first connection portion 15d. The first outer end face 15c may be flush with the first end face 13 of the metal resistor 10.

[0013] The second plating electrode 16 has a second surface 16a opposite to the metal resistor 10, a second inner end face 16b facing the first plating electrode 15, and a second outer end face 16c opposite to the second inner end face 16b. The second inner end face 16b is, for example, perpendicular to the bottom surface 12. The second surface 16a and the second inner end face 16b are connected at a second connection portion 16d. The second outer end face 16c may be flush with the second end face 14 of the metal resistor 10.

[0014] An example of a method for manufacturing the chip resistor 1 of this embodiment will be described with reference to FIGS.

[0015] 4 to 6, the laminate 5 is formed. Forming the laminate 5 includes forming a first plated partial layer 37a and a second plated partial layer 37b on the first main surface 31 of the metal resistor plate 30. A groove 40 is formed between the first plated partial layer 37a and the second plated partial layer 37b.

[0016] Specifically, referring to Fig. 4, a metal resistor plate 30 is prepared. The metal resistor plate 30 is made of the same material as the metal resistor 10 (see Figs. 1 to 3). The metal resistor plate 30 has a first main surface 31 and a second main surface 32 opposite to the first main surface 31.

[0017] 4, a mask 35 is formed on the second main surface 32 of the metal resistor plate 30. The mask 35 is made of an insulating material such as a resist. The first main surface 31 of the metal resistor plate 30 is exposed from the mask 35.

[0018] 5, a plating layer 37 is formed on the first main surface 31 of the metal resistor plate 30 by plating. The plating layer 37 is made of the same material as the first plating electrode 15 (see FIGS. 2 and 3) and the second plating electrode 16 (see FIGS. 2 and 3). In addition to the first main surface 31, the plating layer 37 may also be formed on the side surfaces of the metal resistor plate 30 that are connected to the first main surface 31 and the second main surface 32 and that are exposed from the mask 35. Then, the mask 35 is removed.

[0019] Referring to FIG. 6 , a groove 40 is formed in the plating layer 37 by cutting, forming a first plating portion layer 37a and a second plating portion layer 37b from the plating layer 37. The first plating portion layer 37a and the second plating portion layer 37b are formed on the first main surface 31. The groove 40 is formed between the first plating portion layer 37a and the second plating portion layer 37b. In the groove 40, the first main surface 31 of the metal resistor plate 30 is exposed from the first plating portion layer 37a and the second plating portion layer 37b. A method for removing a portion of the plating layer 37 is, for example, machining such as cutting or milling using a cutting tool 43. In this way, a laminate 5 is formed, which includes the metal resistor plate 30, the first plating portion layer 37a, and the second plating portion layer 37b.

[0020] Referring to FIG. 7, the laminate 5 is punched out across the grooves 40. The laminate 5 is punched, for example, in a direction from the second main surface 32 toward the first main surface 31. By punching the laminate 5, the metal resistor 10 is formed from the metal resistor plate 30, the first plated electrode 15 is formed from the first plated portion layer 37a, and the second plated electrode 16 is formed from the second plated portion layer 37b. The bottom surface 12 of the metal resistor 10 is part of the first main surface 31 of the metal resistor plate 30. The top surface 11 of the metal resistor 10 is part of the second main surface 32 of the metal resistor plate 30. In this way, the chip resistor 1 shown in FIGS. 1 to 3 is obtained.

[0021] The operation of the chip resistor 1 of this embodiment will be described in comparison with a chip resistor of a comparative example. The chip resistor of the comparative example has a configuration similar to the chip resistor 1 of this embodiment, but has a first electrode and a second electrode instead of the first plated electrode 15 and the second plated electrode 16. The first electrode is bent and welded to one end of the metal resistor 10. The second electrode is bent and welded to the other end of the metal resistor 10.

[0022] In the chip resistor of the comparative example, the distance between the first and second electrodes cannot be reduced to avoid the adverse effects of heat when welding the first and second electrodes to the metal resistor 10. Furthermore, voids and other defects occur in the first welded portion between the first electrode and the metal resistor 10 and in the second welded portion between the second electrode and the metal resistor 10. The electrical resistance of the first welded portion and the electrical resistance of the second welded portion increase. As a result, the electrical resistance of the chip resistor of the comparative example increases. Furthermore, when welding the first and second electrodes to the metal resistor 10, at least one of the metal resistor 10, the first electrode, and the second electrode deforms, and the amount of voids generated varies from chip resistor to chip resistor of the comparative example. Therefore, the quality of the chip resistor of the comparative example is unstable.

[0023] In contrast, in the chip resistor 1 of this embodiment, the first plated electrode 15 and the second plated electrode 16 are formed on the metal resistor 10 by plating. Because there is no adverse effect of heat during welding, the distance between the first plated electrode 15 and the second plated electrode 16 can be reduced. Furthermore, no voids are generated due to welding. Furthermore, the top surface 11 of the metal resistor 10 is flat, and the metal resistor 10 is not bent. Reducing the distance between the first plated electrode 15 and the second plated electrode 16 does not degrade the accuracy of the resistance value of the chip resistor 1. Therefore, the electrical resistance of the chip resistor 1 of this embodiment can be reduced. When the chip resistor 1 is a shunt resistor, it becomes possible to measure a larger current using the chip resistor 1.

[0024] In addition, welding does not cause voids or deformation of at least one of the metal resistor element 10, the first plated electrode 15, or the second plated electrode 16. Therefore, the chip resistor 1 of this embodiment has more stable quality.

[0025] (Variation) 8 and 9, in the chip resistor 1 of the first modified example of this embodiment, in a plan view of the top surface 11, the first plated electrode 15 protrudes from the first end surface 13 of the metal resistor 10, and the second plated electrode 16 protrudes from the second end surface 14 of the metal resistor 10. At least a portion of the first end surface 13 is covered with the first plated electrode 15. At least a portion of the second end surface 14 is covered with the second plated electrode 16.

[0026] A first protrusion length L1 of the first plating electrode 15 from the first end face 13 in a plan view of the top face 11 is smaller than a first thickness t1 of the first plating electrode 15 at the first connection portion 15d. A second protrusion length L2 of the second plating electrode 16 from the second end face 14 in a plan view of the top face 11 is smaller than a second thickness t2 of the second plating electrode 16 at the second connection portion 16d. The first protrusion length L1 may be 0.5 times or less the distance G between the first plating electrode 15 and the second plating electrode 16. The second protrusion length L2 may be 0.5 times or less the distance G.

[0027] In a plan view of the top surface 11, the protruding portion of the first plating electrode 15 from the first end surface 13 and the protruding portion of the second plating electrode 16 from the second end surface 14 are formed when the laminate 5 is punched in the direction from the second main surface 32 toward the first main surface 31. Burrs generated during the punching process of the laminate 5 become the protruding portion of the first plating electrode 15 from the first end surface 13 and the protruding portion of the second plating electrode 16 from the second end surface 14.

[0028] Referring to FIG. 9 , the chip resistor 1 is mounted on a circuit board 50. Specifically, the circuit board 50 includes an insulating substrate 51 and electrical wiring 52 and 53. The electrical wiring 52 and 53 are formed on the insulating substrate 51. The circuit board 50 is, for example, a printed circuit board. The first plating electrode 15 is joined to the electrical wiring 52 using a conductive bonding member 54 such as solder. The second plating electrode 16 is joined to the electrical wiring 53 using a conductive bonding member 55 such as solder. The conductive bonding member 54 is formed on the first surface 15a, the first inner end face 15b, and the first outer end face 15c of the first plating electrode 15. The conductive bonding member 54 is also formed on the protruding portion of the first plating electrode 15 from the first end face 13. The conductive bonding member 55 is formed on the second surface 16a, the second inner end face 16b, and the second outer end face 16c of the second plating electrode 16. The conductive bonding member 55 is also formed on the protruding portion of the second plating electrode 16 from the second end surface 14.

[0029] 10, in the chip resistor 1 of the second modified example of this embodiment, the first inner end surface 15b of the first plated electrode 15 and the second inner end surface 16b of the second plated electrode 16 are flat surfaces inclined with respect to the bottom surface 12. For example, the shape of the blade of the cutting tool 43 (see FIG. 6) is modified to form flat surfaces inclined with respect to the first main surface 31 of the metal resistor plate 30 on the end surface of the first plated portion layer 37a facing the second plated portion layer 37b and the end surface of the second plated portion layer 37b facing the first plated portion layer 37a. Then, the laminate 5 is punched out. The end surface of the first plated portion layer 37a facing the second plated portion layer 37b becomes the first inner end surface 15b. The end surface of the second plated portion layer 37b facing the first plated portion layer 37a becomes the second inner end surface 16b.

[0030] 11, the chip resistor 1 is mounted on a circuit board 50. Specifically, the first plating electrode 15 is joined to an electrical wiring 52 using a conductive bonding member 54 such as solder. The second plating electrode 16 is joined to an electrical wiring 53 using a conductive bonding member 55 such as solder. The conductive bonding member 54 is formed on the first surface 15a, the first inner end face 15b, and the first outer end face 15c of the first plating electrode 15. The conductive bonding member 55 is formed on the second surface 16a, the second inner end face 16b, and the second outer end face 16c of the second plating electrode 16.

[0031] The effects of the chip resistor 1 of this embodiment and the manufacturing method thereof will be described.

[0032] The chip resistor 1 of this embodiment includes a metal resistor 10, a first plated electrode 15, and a second plated electrode 16. The metal resistor 10 has a top surface 11 and a bottom surface 12 opposite the top surface 11. The first plated electrode 15 is disposed on the bottom surface 12. The second plated electrode 16 is disposed on the bottom surface 12 and is spaced apart from the first plated electrode 15. The top surface 11 is a flat surface.

[0033] The first plated electrode 15 and the second plated electrode 16 are formed on the metal resistor 10 by plating, not welding. Because there is no adverse effect of heat during welding, the gap between the first plated electrode 15 and the second plated electrode 16 can be reduced. Furthermore, no voids are generated due to welding. Furthermore, the top surface 11 of the metal resistor 10 is flat, and the metal resistor 10 is not bent. Reducing the gap between the first plated electrode 15 and the second plated electrode 16 does not degrade the accuracy of the resistance value of the chip resistor 1. Therefore, the electrical resistance of the chip resistor 1 can be reduced. Additionally, voids and deformation of at least one of the metal resistor 10, the first plated electrode 15, and the second plated electrode 16 due to welding are not generated. Therefore, the chip resistor 1 has more stable quality.

[0034] In the chip resistor 1 of this embodiment, the first plated electrode 15 has a first inner end surface 15b facing the second plated electrode 16. The second plated electrode 16 has a second inner end surface 16b facing the first plated electrode 15. The first inner end surface 15b and the second inner end surface 16b are flat surfaces inclined with respect to the bottom surface 12.

[0035] Therefore, the angle of the first plated electrode 15 at the first connection portion 15d and the angle of the second plated electrode 16 at the second connection portion 16d are obtuse angles. This reduces stress applied to the conductive bonding members 54, 55 for fixing the chip resistor 1 to the circuit board 50. This prevents cracks from occurring in the conductive bonding members 54, 55. Furthermore, the lengths of the first inner end face 15b and the second inner end face 16b are increased. This prevents the conductive bonding member 54 from creeping up the first inner end face 15b and coming into contact with the metal resistor 10. This prevents the conductive bonding member 55 from creeping up the second inner end face 16b and coming into contact with the metal resistor 10. This prevents fluctuations in the resistance value of the chip resistor 1 after the chip resistor 1 is mounted on the circuit board 50.

[0036] In the chip resistor 1 of this embodiment, the metal resistor 10 has a first end face 13 and a second end face 14 opposite the first end face 13. The first end face 13 and the second end face 14 are connected to the top face 11 and the bottom face 12, respectively. In a plan view of the top face 11, the first plated electrode 15 protrudes from the first end face 13, and the second plated electrode 16 protrudes from the second end face 14.

[0037] Therefore, when the chip resistor 1 is mounted on the circuit board 50, the conductive bonding member 54 is also formed on the portion of the first plated electrode 15 that protrudes from the first end face 13, and the conductive bonding member 55 is also formed on the portion of the second plated electrode 16 that protrudes from the second end face 14. The bonding area between the first plated electrode 15 and the conductive bonding member 54 and the bonding area between the second plated electrode 16 and the conductive bonding member 55 are increased. The chip resistor 1 can be fixed to the circuit board 50 more firmly.

[0038] The chip resistor 1 of this embodiment is a shunt resistor.

[0039] The chip resistor 1 of this embodiment has a lower electrical resistance, and therefore, according to the chip resistor 1 of this embodiment, it is possible to provide a shunt resistor that can measure a larger current.

[0040] In the manufacturing method of the chip resistor 1 of this embodiment, the chip resistor 1 includes a metal resistor 10 having a top surface 11 and a bottom surface 12 opposite the top surface 11, a first plated electrode 15 disposed on the bottom surface 12, and a second plated electrode 16 disposed on the bottom surface 12 and spaced apart from the first plated electrode 15. The top surface 11 is a flat surface. The manufacturing method of the chip resistor 1 of this embodiment includes forming a laminate 5. Forming the laminate 5 includes forming a first plated portion layer 37a and a second plated portion layer 37b on the first main surface 31 of the metal resistor plate 30. A first groove (groove 40) is formed between the first plated portion layer 37a and the second plated portion layer 37b. The manufacturing method of the chip resistor 1 of this embodiment includes punching out the laminate 5 so as to cross the first groove. By punching out the laminate 5, a metal resistor 10 is formed from the metal resistor plate 30, a first plated electrode 15 is formed from the first plated portion layer 37a, and a second plated electrode 16 is formed from the second plated portion layer 37b.

[0041] The first plated electrode 15 and the second plated electrode 16 are formed on the metal resistor 10 by plating, not welding. Because there is no adverse effect of heat during welding, the gap between the first plated electrode 15 and the second plated electrode 16 can be reduced. Furthermore, no voids are generated due to welding. Furthermore, the top surface 11 of the metal resistor 10 is flat, and the metal resistor 10 is not bent. Reducing the gap between the first plated electrode 15 and the second plated electrode 16 does not degrade the accuracy of the resistance value of the chip resistor 1. Therefore, the electrical resistance of the chip resistor 1 can be reduced. Additionally, voids and deformation of at least one of the metal resistor 10, the first plated electrode 15, and the second plated electrode 16 due to welding are not generated. Therefore, the chip resistor 1 has more stable quality.

[0042] In the manufacturing method of the chip resistor 1 of this embodiment, forming the first plating portion layer 37a and the second plating portion layer 37b on the first main surface 31 of the metal resistor plate 30 includes forming a first plating layer (plating layer 37) on the first main surface 31 of the metal resistor plate 30, and forming a first groove (groove 40) in the first plating layer by cutting to form the first plating portion layer 37a and the second plating portion layer 37b from the first plating layer.

[0043] The first plated electrode 15 and the second plated electrode 16 are formed on the metal resistor 10 by plating, not welding. Because there is no adverse effect of heat during welding, the gap between the first plated electrode 15 and the second plated electrode 16 can be reduced. Furthermore, no voids are generated due to welding. Furthermore, the top surface 11 of the metal resistor 10 is flat, and the metal resistor 10 is not bent. Reducing the gap between the first plated electrode 15 and the second plated electrode 16 does not degrade the accuracy of the resistance value of the chip resistor 1. Therefore, the electrical resistance of the chip resistor 1 can be reduced. Additionally, voids and deformation of at least one of the metal resistor 10, the first plated electrode 15, and the second plated electrode 16 due to welding are not generated. Therefore, the chip resistor 1 has more stable quality.

[0044] In the manufacturing method of the chip resistor 1 of this embodiment, the end face of the first plated portion layer 37a facing the second plated portion layer 37b and the end face of the second plated portion layer 37b facing the first plated portion layer 37a are flat surfaces inclined with respect to the first main surface 31.

[0045] Therefore, the area of ​​the first inner end face 15b and the area of ​​the second inner end face 16b increase. When the chip resistor 1 is mounted on the circuit board 50, the bonding area between the first plated electrode 15 and the conductive bonding member 54 and the bonding area between the second plated electrode 16 and the conductive bonding member 55 increase. The chip resistor 1 can be fixed to the circuit board 50 more firmly.

[0046] In the manufacturing method of the chip resistor 1 of this embodiment, punching out the laminate 5 means punching out the laminate 5 in a direction from the second main surface 32 of the metal resistor plate 30 opposite the first main surface 31 toward the first main surface 31. The metal resistor 10 has a first end face 13 and a second end face 14 opposite the first end face 13. The first end face 13 and the second end face 14 are connected to the top face 11 and the bottom face 12, respectively. The first end face 13 is one end face of the metal resistor 10 in a direction in which the first plated electrode 15 and the second plated electrode 16 are spaced apart from each other. The second end face 14 is the other end face of the metal resistor 10 in that direction. In a plan view of the top face 11 of the metal resistor 10, the first plated electrode 15 protrudes from the first end face 13, and the second plated electrode 16 protrudes from the second end face 14.

[0047] Therefore, when the chip resistor 1 is mounted on the circuit board 50, the conductive bonding member 54 is also formed on the portion of the first plated electrode 15 that protrudes from the first end face 13, and the conductive bonding member 55 is also formed on the portion of the second plated electrode 16 that protrudes from the second end face 14. The bonding area between the first plated electrode 15 and the conductive bonding member 54 and the bonding area between the second plated electrode 16 and the conductive bonding member 55 are increased. The chip resistor 1 can be fixed to the circuit board 50 more firmly.

[0048] In the method for manufacturing the chip resistor 1 of this embodiment, the chip resistor 1 is a shunt resistor.

[0049] The chip resistor 1 of this embodiment has a lower electrical resistance. Therefore, according to the manufacturing method of the chip resistor 1 of this embodiment, a shunt resistor capable of measuring a larger current can be manufactured.

[0050] (Embodiment 2) The chip resistor 1 of embodiment 2 will be described with reference to Figures 12 to 15. The chip resistor 1 of this embodiment has a similar configuration to the chip resistor 1 of embodiment 1, but differs from the chip resistor 1 of embodiment 1 in that it further includes a first plating coating layer 21 and a second plating coating layer 22.

[0051] The first plating coating layer 21 is disposed on the first surface 15a of the first plating electrode 15. The first surface 15a is covered with the first plating coating layer 21. The first inner end face 15b is exposed from the first plating coating layer 21. The first outermost surface 21a of the first plating coating layer 21 has higher solder wettability than the first plating electrode 15. The first outermost surface 21a is formed of, for example, tin (Sn) or nickel (Ni). The first plating coating layer 21 may be formed of a single layer or multiple layers. The first plating coating layer 21 may be formed of a single layer of tin (Sn), a single layer of nickel (Ni), or two layers of an Sn layer and an Ni layer.

[0052] The second plating coating layer 22 is disposed on the second surface 16a of the second plating electrode 16. The second surface 16a is covered with the second plating coating layer 22. The second inner end face 16b is exposed from the second plating coating layer 22. The second outermost surface 22a of the second plating coating layer 22 has higher solder wettability than the second plating electrode 16. The second outermost surface 22a is formed of, for example, tin (Sn) or nickel (Ni). The second plating coating layer 22 may be formed as a single layer or as multiple layers. The second plating coating layer 22 may be formed as a single layer of tin (Sn), a single layer of nickel (Ni), or two layers of an Sn layer and an Ni layer.

[0053] 15, the chip resistor 1 is mounted on a circuit board 50. The first plated electrode 15 coated with the first plated coating layer 21 is joined to the electrical wiring 52 of the circuit board 50 using a conductive joining member 54 such as solder. The second plated electrode 16 coated with the second plated coating layer 22 is joined to the electrical wiring 53 of the circuit board 50 using a conductive joining member 55 such as solder.

[0054] An example of a method for manufacturing the chip resistor 1 of the present embodiment will be described with reference to Figures 4, 5, and 16 to 18. The method for manufacturing the chip resistor 1 of the present embodiment includes the same steps as the method for manufacturing the chip resistor 1 of embodiment 1, but differs from the method for manufacturing the chip resistor 1 of embodiment 1 mainly in the following points.

[0055] In the manufacturing method of the chip resistor 1 of this embodiment, forming the laminate 5 includes forming a first plated partial covering layer 45b on the first plated partial layer 37a and forming a second plated partial covering layer 45c on the second plated partial layer 37b. The outermost surface of the first plated partial covering layer 45b has higher solder wettability than the first plated partial layer 37a. The outermost surface of the second plated partial covering layer 45c has higher solder wettability than the second plated partial layer 37b.

[0056] Specifically, with reference to Fig. 4, a mask 35 is formed on the second main surface 32 of the metal resistor plate 30. With reference to Fig. 5, a plating layer 37 is formed on the first main surface 31 of the metal resistor plate 30 by plating. With reference to Fig. 16, a plating layer 45 is formed on the plating layer 37 by plating. An outermost surface 45a of the plating layer 45 has higher solder wettability than the plating layer 37. The plating layer 45 is formed of the same material as the first plating coating layer 21 (see Fig. 14) and the second plating coating layer 22 (see Fig. 14). Then, the mask 35 is removed.

[0057] 17 , grooves 40 are formed in plating layer 37 by cutting, forming a first plating partial layer 37a and a second plating partial layer 37b from plating layer 37, and forming a first plating partial coating layer 45b and a second plating partial coating layer 45c from plating layer 45. The first plating partial layer 37a and the second plating partial layer 37b are formed on first main surface 31. The first plating partial coating layer 45b is formed on first plating partial layer 37a. The second plating partial coating layer 45c is formed on second plating partial layer 37b. The outermost surface of first plating partial coating layer 45b is part of the outermost surface 45a of plating layer 45. The outermost surface of second plating partial coating layer 45c is part of the outermost surface 45a of plating layer 45.

[0058] Grooves 40 are formed between the first plated partial layer 37a and the second plated partial layer 37b and between the first plated partial coating layer 45b and the second plated partial coating layer 45c. In the grooves 40, the first main surface 31 of the metal resistor plate 30 is exposed from the first plated partial layer 37a, the second plated partial layer 37b, the first plated partial coating layer 45b, and the second plated partial coating layer 45c. A method for removing portions of the plating layer 37 and portions of the plating layer 45 is, for example, machining such as cutting or milling using a cutting tool 43 (see FIG. 6). In this way, a laminate 5 is formed, including the metal resistor plate 30, the first plated partial layer 37a, the second plated partial layer 37b, the first plated partial coating layer 45b, and the second plated partial coating layer 45c.

[0059] 18, the laminate 5 is punched out across the grooves 40. The laminate 5 is punched out, for example, in a direction from the second main surface 32 toward the first main surface 31. By punching the laminate 5, the metal resistor 10 is formed from the metal resistor plate 30, the first plated electrode 15 is formed from the first plated partial layer 37a, the second plated electrode 16 is formed from the second plated partial layer 37b, the first plated coating layer 21 is formed from the first plated partial coating layer 45b, and the second plated coating layer 22 is formed from the second plated partial coating layer 45c. In this way, the chip resistor 1 shown in FIGS. 12 to 14 is obtained.

[0060] 19 and 20 , in a chip resistor 1 according to a modification of the present embodiment, in a plan view of the top surface 11, the first plated electrode 15 and the first plated coating layer 21 protrude from the first end surface 13 of the metal resistor 10, and the second plated electrode 16 and the second plated coating layer 22 protrude from the second end surface 14 of the metal resistor 10. At least a portion of the first end surface 13 is covered with the first plated electrode 15 and the first plated coating layer 21. At least a portion of the second end surface 14 is covered with the second plated electrode 16 and the second plated coating layer 22.

[0061] A first protrusion length L1 of the first plating electrode 15 from the first end face 13 in a plan view of the top face 11 is smaller than a first thickness t1 of the first plating electrode 15 at the first connection portion 15d. A second protrusion length L2 of the second plating electrode 16 from the second end face 14 in a plan view of the top face 11 is smaller than a second thickness t2 of the second plating electrode 16 at the second connection portion 16d. The first protrusion length L1 may be 0.5 times or less the distance G between the first plating electrode 15 and the second plating electrode 16. The second protrusion length L2 may be 0.5 times or less the distance G.

[0062] In a plan view of the top surface 11, the protruding portions of the first plating electrode 15 and the first plating coating layer 21 from the first end surface 13 and the protruding portions of the second plating electrode 16 and the second plating coating layer 22 from the second end surface 14 are formed when the laminate 5 is punched in a direction from the second main surface 32 toward the first main surface 31. Burrs generated during the punching process of the laminate 5 become the protruding portions of the first plating electrode 15 and the first plating coating layer 21 from the first end surface 13 and the protruding portions of the second plating electrode 16 and the second plating coating layer 22 from the second end surface 14.

[0063] 20, the chip resistor 1 is mounted on a circuit board 50. The first plated electrode 15 coated with the first plated coating layer 21 is joined to an electrical wiring 52 using a conductive bonding member 54 such as solder. The second plated electrode 16 coated with the second plated coating layer 22 is joined to an electrical wiring 53 using a conductive bonding member 55 such as solder. The conductive bonding member 54 is also formed on the portion of the first plated coating layer 21 protruding from the first end surface 13. The conductive bonding member 55 is also formed on the portion of the second plated coating layer 22 protruding from the second end surface 14.

[0064] The chip resistor 1 and the manufacturing method thereof according to this embodiment have the following advantages in addition to the advantages of the chip resistor 1 and the manufacturing method thereof according to the first embodiment.

[0065] The chip resistor 1 of this embodiment further includes a first plating coating layer 21 and a second plating coating layer 22. The first plating coating layer 21 is disposed on a first surface 15a of the first plating electrode 15 opposite the metal resistor 10. The first outermost surface 21a of the first plating coating layer 21 has higher solder wettability than the first plating electrode 15. The second plating coating layer 22 is disposed on a second surface 16a of the second plating electrode 16 opposite the metal resistor 10. The second outermost surface 22a of the second plating coating layer 22 has higher solder wettability than the second plating electrode 16.

[0066] Therefore, even if the first plated electrode 15 and the second plated electrode 16 are formed of a material with low solder wettability, there is no need to form the first plated coating layer 21 and the second plated coating layer 22 on the first plated electrode 15 and the second plated electrode 16 when mounting the chip resistor 1 on the circuit board 50. This improves the mountability of the chip resistor 1 on the circuit board 50.

[0067] In the chip resistor 1 of this embodiment, the metal resistor 10 has a first end face 13 and a second end face 14 opposite the first end face 13. The first end face 13 and the second end face 14 are connected to the top face 11 and the bottom face 12, respectively. In a plan view of the top face 11, the first plated electrode 15 and the first plated coating layer 21 protrude from the first end face 13, and the second plated electrode 16 and the second plated coating layer 22 protrude from the second end face 14.

[0068] Therefore, when the chip resistor 1 is mounted on the circuit board 50, the conductive bonding member 54 is also formed on the portion of the first plating coating layer 21 that protrudes from the first end face 13, and the conductive bonding member 55 is also formed on the portion of the second plating coating layer 22 that protrudes from the second end face 14. The bonding area between the first plating coating layer 21 and the conductive bonding member 54 and the bonding area between the second plating coating layer 22 and the conductive bonding member 55 are increased. This allows the chip resistor 1 to be more firmly fixed to the circuit board 50.

[0069] In the manufacturing method of the chip resistor 1 of this embodiment, the chip resistor 1 includes a first plating coating layer 21 disposed on the first plating electrode 15 and a second plating coating layer 22 disposed on the second plating electrode 16. Forming the laminate 5 includes forming a first plating partial coating layer 45b on the first plating partial layer 37a and forming a second plating partial coating layer 45c on the second plating partial layer 37b. The outermost surface (part of the outermost surface 45a) of the first plating partial coating layer 45b has higher solder wettability than the first plating partial layer 37a. The outermost surface (part of the outermost surface 45a) of the second plating partial coating layer 45c has higher solder wettability than the second plating partial layer 37b. By punching out the laminate 5, the first plating coating layer 21 is formed from the first plating partial coating layer 45b, and the second plating coating layer 22 is formed from the second plating partial coating layer 45c.

[0070] Therefore, even if the first plated electrode 15 and the second plated electrode 16 are formed of a material with low solder wettability, there is no need to form the first plated coating layer 21 and the second plated coating layer 22 on the first plated electrode 15 and the second plated electrode 16 when mounting the chip resistor 1 on the circuit board 50. This improves the mountability of the chip resistor 1 on the circuit board 50.

[0071] In the manufacturing method of the chip resistor 1 of this embodiment, punching out the laminate 5 means punching out the laminate 5 in a direction from the second main surface 32 of the metal resistor plate 30 opposite the first main surface 31 toward the first main surface 31. The metal resistor 10 has a first end face 13 and a second end face 14 opposite the first end face 13. The first end face 13 and the second end face 14 are connected to the top face 11 and the bottom face 12, respectively. The first end face 13 is one end face of the metal resistor 10 in a direction in which the first plated electrode 15 and the second plated electrode 16 are spaced apart from each other. The second end face 14 is the other end face of the metal resistor 10 in that direction. In a plan view of the top face 11 of the metal resistor 10, the first plated electrode 15 and the first plated coating layer 21 protrude from the first end face 13, and the second plated electrode 16 and the second plated coating layer 22 protrude from the second end face 14.

[0072] Therefore, when the chip resistor 1 is mounted on the circuit board 50, the conductive bonding member 54 is also formed on the portion of the first plating coating layer 21 that protrudes from the first end face 13, and the conductive bonding member 55 is also formed on the portion of the second plating coating layer 22 that protrudes from the second end face 14. The bonding area between the first plating coating layer 21 and the conductive bonding member 54 and the bonding area between the second plating coating layer 22 and the conductive bonding member 55 are increased. This allows the chip resistor 1 to be more firmly fixed to the circuit board 50.

[0073] (Embodiment 3) The chip resistor 1 of the third embodiment will be described with reference to Figures 1, 2, 21, and 22. The chip resistor 1 of the present embodiment has a similar configuration to the chip resistor 1 of the first embodiment, but differs from the chip resistor 1 of the first embodiment mainly in the following points.

[0074] 21 , in the present embodiment, the first inner end face 15b and the second inner end face 16b of the first plating electrode 15 are rounded end faces. The first inner end face 15b is an end face that curves convexly toward the second plating electrode 16. The second inner end face 16b of the second plating electrode 16 is an end face that curves convexly toward the first plating electrode 15.

[0075] 22, the chip resistor 1 is mounted on a circuit board 50. Specifically, the first plating electrode 15 is joined to an electrical wiring 52 using a conductive bonding member 54 such as solder. The second plating electrode 16 is joined to an electrical wiring 53 using a conductive bonding member 55 such as solder. The conductive bonding member 54 is formed on the first surface 15a, the first inner end face 15b, and the first outer end face 15c of the first plating electrode 15. The conductive bonding member 55 is formed on the second surface 16a, the second inner end face 16b, and the second outer end face 16c of the second plating electrode 16.

[0076] An example of a method for manufacturing the chip resistor 1 of this embodiment will be described with reference to Figures 23 to 25. The method for manufacturing the chip resistor 1 of this embodiment includes the same steps as the method for manufacturing the chip resistor 1 of embodiment 1, but differs from the method for manufacturing the chip resistor 1 of embodiment 1 in the steps of forming the first plated portion layer 37a and the second plated portion layer 37b.

[0077] 23 , a mask 35 is formed on the second main surface 32 of the metal resistor plate 30, and a mask 36 is formed on the first main surface 31 of the metal resistor plate 30. The masks 35 and 36 are made of an insulating material such as resist. Portions of the first main surface 31 on both sides of the mask 36 are exposed from the mask 36.

[0078] Referring to FIG. 24 , a plating layer 37 is formed on the first main surface 31 of the metal resistor plate 30 by plating. The plating layer 37 is formed on both sides of the mask 36. The first plating portion layer 37a is a portion of the plating layer 37 on one side facing the mask 36. The second plating portion layer 37b is a portion of the plating layer 37 on the other side facing the mask 36. A groove 40 is formed between the first plating portion layer 37a and the second plating portion layer 37b. The plating layer 37 grows isotropically near the mask 36. Therefore, the end face of the first plating portion layer 37a facing the mask 36 and the end face of the second plating portion layer 37b facing the mask 36 are rounded end faces. In this way, a laminate 5 is formed of the metal resistor plate 30, the first plating portion layer 37a, and the second plating portion layer 37b. The laminate 5 may include the mask 36.

[0079] Referring to FIG. 25, the laminate 5 is punched out across the grooves 40. The laminate 5 is punched out, for example, in a direction from the second main surface 32 toward the first main surface 31. By punching the laminate 5, the metal resistor 10 is formed from the metal resistor plate 30, the first plated electrode 15 is formed from the first plated portion layer 37a, and the second plated electrode 16 is formed from the second plated portion layer 37b. The mask 36 is then removed. In this way, the chip resistor 1 shown in FIG. 21 is obtained.

[0080] The chip resistor 1 and the manufacturing method thereof according to this embodiment have the following advantages in addition to the advantages of the chip resistor 1 and the manufacturing method thereof according to the first embodiment.

[0081] In the chip resistor 1 of this embodiment, the first plated electrode 15 has a first inner end surface 15b facing the second plated electrode 16. The second plated electrode 16 has a second inner end surface 16b facing the first plated electrode 15. The first inner end surface 15b and the second inner end surface 16b are rounded end surfaces.

[0082] Therefore, the area of ​​the first inner end face 15b and the area of ​​the second inner end face 16b increase. When the chip resistor 1 is mounted on the circuit board 50, the bonding area between the first plated electrode 15 and the conductive bonding member 54 and the bonding area between the second plated electrode 16 and the conductive bonding member 55 increase. The chip resistor 1 can be fixed to the circuit board 50 more firmly.

[0083] In the manufacturing method of the chip resistor 1 of this embodiment, forming the first plating portion layer 37a and the second plating portion layer 37b on the first main surface 31 of the metal resistor plate 30 includes forming a first mask (mask 36) on the first main surface 31 of the metal resistor plate 30, and forming a first plating layer (plating layer 37) on both sides of the first mask to form the first plating portion layer 37a and the second plating portion layer 37b.

[0084] Therefore, the end face of the first plated portion layer 37a facing the first mask (mask 36) and the end face of the second plated portion layer 37b facing the first mask are rounded end faces. By punching out the laminate 5, the first inner end face 15b, which is a rounded end face, is formed from the first plated portion layer 37a, and the second inner end face 16b is formed from the second plated portion layer 37b. The areas of the first inner end face 15b and the second inner end face 16b are increased. When the chip resistor 1 is mounted on the circuit board 50, the bonding area between the first plated electrode 15 and the conductive bonding member 54 and the bonding area between the second plated electrode 16 and the conductive bonding member 55 are increased. The chip resistor 1 can be more firmly fixed to the circuit board 50.

[0085] (Fourth embodiment) A chip resistor 1 of embodiment 4 will be described with reference to Figures 12, 13, 26, and 27. The chip resistor 1 of this embodiment has a similar configuration to the chip resistor 1 of embodiment 3, but differs from the chip resistor 1 of embodiment 3 in that it further includes a first plating coating layer 21 and a second plating coating layer 22. The first plating coating layer 21 of this embodiment is similar to the first plating coating layer 21 of embodiment 2, but further covers the first inner end surface 15b of the first plating electrode 15. The second plating coating layer 22 of this embodiment is similar to the second plating coating layer 22 of embodiment 2, but further covers the second inner end surface 16b of the second plating electrode 16.

[0086] 27, the chip resistor 1 is mounted on a circuit board 50. The first plated electrode 15 coated with the first plated coating layer 21 is joined to the electrical wiring 52 of the circuit board 50 using a conductive joining member 54 such as solder. The second plated electrode 16 coated with the second plated coating layer 22 is joined to the electrical wiring 53 of the circuit board 50 using a conductive joining member 55 such as solder.

[0087] An example of a method for manufacturing the chip resistor 1 of this embodiment will be described with reference to Figures 23, 24, 28, and 29. The method for manufacturing the chip resistor 1 of this embodiment includes the same steps as the method for manufacturing the chip resistor 1 of embodiment 3, but differs from the method for manufacturing the chip resistor 1 of embodiment 3 mainly in the following points.

[0088] Forming the laminate 5 in the manufacturing method of the chip resistor 1 of the present embodiment includes forming a first plated partial covering layer 45b on the first plated partial layer 37a and forming a second plated partial covering layer 45c on the second plated partial layer 37b, similar to forming the laminate 5 in the manufacturing method of the chip resistor 1 of embodiment 2. The outermost surface of the first plated partial covering layer 45b has higher solder wettability than the first plated partial layer 37a. The outermost surface of the second plated partial covering layer 45c has higher solder wettability than the second plated partial layer 37b.

[0089] Specifically, referring to FIG. 23, a mask 35 is formed on the second main surface 32 of the metal resistor plate 30, and a mask 36 is formed on the first main surface 31 of the metal resistor plate 30.

[0090] Referring to FIG. 24, a plating layer 37 is formed on the first main surface 31 of the metal resistor plate 30 by plating. The plating layer 37 is formed on both sides of the mask 36. The first plating portion layer 37a is a portion of the plating layer 37 on one side facing the mask 36. The second plating portion layer 37b is a portion of the plating layer 37 on the other side facing the mask 36. In the vicinity of the mask 36, the plating layer 37 grows isotropically. Therefore, the end face of the first plating portion layer 37a facing the mask 36 and the end face of the second plating portion layer 37b facing the mask 36 are rounded end faces.

[0091] Referring to FIG. 28, a plating layer 45 is formed on the plating layer 37 by plating. An outermost surface 45a of the plating layer 45 has higher solder wettability than the plating layer 37. The plating layer 45 is formed of the same material as the first plating coating layer 21 (see FIG. 14) and the second plating coating layer 22 (see FIG. 14). Grooves 40 are formed between the first plating partial layer 37a and the second plating partial layer 37b and between the first plating partial coating layer 45b and the second plating partial coating layer 45c. In the grooves 40, the first main surface 31 of the metal resistor plate 30 is exposed from the first plating partial layer 37a, the second plating partial layer 37b, the first plating partial coating layer 45b, and the second plating partial coating layer 45c. Then, the mask 35 is removed. In this way, a laminate 5 is formed of the metal resistor plate 30, the first plated partial layer 37a, the second plated partial layer 37b, the first plated partial covering layer 45b, and the second plated partial covering layer 45c. The laminate 5 may include a mask 36.

[0092] Referring to FIG. 25 , the laminate 5 is punched across the grooves 40. The laminate 5 is punched, for example, in a direction from the second main surface 32 toward the first main surface 31. By punching the laminate 5, the metal resistor 10 is formed from the metal resistor plate 30, the first plated electrode 15 is formed from the first plated partial layer 37a, the second plated electrode 16 is formed from the second plated partial layer 37b, the first plated coating layer 21 is formed from the first plated partial coating layer 45b, and the second plated coating layer 22 is formed from the second plated partial coating layer 45c. The outermost surface of the first plated partial coating layer 45b is part of the outermost surface 45a of the plating layer 45. The outermost surface of the second plated partial coating layer 45c is part of the outermost surface 45a of the plating layer 45. The mask 36 is then removed. In this way, the chip resistor 1 shown in FIG. 26 is obtained.

[0093] 30 and 31 , in a chip resistor 1 according to a modification of the present embodiment, in a plan view of the top surface 11, the first plated electrode 15 and the first plated coating layer 21 protrude from the first end surface 13 of the metal resistor 10, and the second plated electrode 16 and the second plated coating layer 22 protrude from the second end surface 14 of the metal resistor 10. At least a portion of the first end surface 13 is covered with the first plated electrode 15 and the first plated coating layer 21. At least a portion of the second end surface 14 is covered with the second plated electrode 16 and the second plated coating layer 22.

[0094] A first protrusion length L1 of the first plating electrode 15 from the first end face 13 in a plan view of the top face 11 is smaller than a first thickness t1 of the first plating electrode 15 at the first connection portion 15d. A second protrusion length L2 of the second plating electrode 16 from the second end face 14 in a plan view of the top face 11 is smaller than a second thickness t2 of the second plating electrode 16 at the second connection portion 16d. The first protrusion length L1 may be 0.5 times or less the distance G between the first plating electrode 15 and the second plating electrode 16. The second protrusion length L2 may be 0.5 times or less the distance G.

[0095] In a plan view of the top surface 11, the protruding portions of the first plating electrode 15 and the first plating coating layer 21 from the first end surface 13 and the protruding portions of the second plating electrode 16 and the second plating coating layer 22 from the second end surface 14 are formed when the laminate 5 is punched in a direction from the second main surface 32 toward the first main surface 31. Burrs generated during the punching process of the laminate 5 become the protruding portions of the first plating electrode 15 and the first plating coating layer 21 from the first end surface 13 and the protruding portions of the second plating electrode 16 and the second plating coating layer 22 from the second end surface 14.

[0096] 31 , the chip resistor 1 is mounted on a circuit board 50. The first plated electrode 15 coated with the first plated coating layer 21 is joined to an electrical wiring 52 using a conductive bonding member 54 such as solder. The second plated electrode 16 coated with the second plated coating layer 22 is joined to an electrical wiring 53 using a conductive bonding member 55 such as solder. The conductive bonding member 54 is also formed on the portion of the first plated coating layer 21 protruding from the first end surface 13. The conductive bonding member 55 is also formed on the portion of the second plated coating layer 22 protruding from the second end surface 14.

[0097] The chip resistor 1 and its manufacturing method according to the present embodiment have the same effects as the chip resistor 1 and its manufacturing method according to the second embodiment and the same effects as the chip resistor 1 and its manufacturing method according to the third embodiment.

[0098] (Embodiment 5) The chip resistor 1 of embodiment 5 will be described with reference to Figures 32 to 34. The chip resistor 1 of this embodiment has a similar configuration to the chip resistor 1 of embodiment 1, but differs from the chip resistor 1 of embodiment 1 in that it further includes a first plated heat dissipation layer 25.

[0099] The first plated heat dissipation layer 25 is formed of a material having a higher thermal conductivity than the metal resistor 10. The first plated heat dissipation layer 25 is formed of, for example, copper (Cu) or a copper-based alloy. The first plated heat dissipation layer 25 may be formed of the same material as the first plated electrode 15 and the second plated electrode 16. The first plated heat dissipation layer 25 is disposed on the top surface 11. In a plan view of the top surface 11, the first plated heat dissipation layer 25 overlaps the center 18 of the metal resistor 10 in the direction in which the first end face 13 and the second end face 14 are spaced apart from each other, and is spaced apart from the first end face 13 and the second end face 14.

[0100] The first plated heat dissipation layer 25 has an end face 25a and an end face 25b opposite to the end face 25a. The end face 25a is proximate to the first end face 13. The end face 25b is proximate to the second end face 14. The end faces 25a and 25b are, for example, perpendicular to the top face 11.

[0101] An example of a method for manufacturing the chip resistor 1 of this embodiment will be described with reference to Figures 35 to 37. The method for manufacturing the chip resistor 1 of this embodiment includes the same steps as the method for manufacturing the chip resistor 1 of embodiment 1, but differs from the method for manufacturing the chip resistor 1 of embodiment 1 mainly in the following points.

[0102] In the manufacturing method of the chip resistor 1 of this embodiment, forming the laminate 5 includes forming a first plating portion layer 37a and a second plating portion layer 37b on the first main surface 31 of the metal resistor plate 30, and forming a third plating portion layer 37c on the second main surface 32 of the metal resistor plate 30 opposite the first main surface 31.

[0103] Specifically, referring to Fig. 35, a metal resistor plate 30 is prepared. The metal resistor plate 30 has a first main surface 31 and a second main surface 32 opposite to the first main surface 31.

[0104] 35, a plating layer 37 is formed on the first main surface 31 and the second main surface 32 of the metal resistor plate 30 by plating. In addition to the first main surface 31 and the second main surface 32, the plating layer 37 may also be formed on the side surfaces of the metal resistor plate 30 that are connected to the first main surface 31 and the second main surface 32 and that are exposed from the mask 35. The plating layer 37 is formed from the same material as the first plated electrode 15 (see FIGS. 33 and 34), the second plated electrode 16 (see FIGS. 33 and 34), and the first plated heat dissipation layer 25 (see FIGS. 32 and 34).

[0105] Referring to FIG. 36 , grooves 40, 41, and 42 are formed in the plating layer 37 by cutting, thereby forming a first plating portion layer 37a, a second plating portion layer 37b, and a third plating portion layer 37c from the plating layer 37. The first plating portion layer 37a and the second plating portion layer 37b are formed on the first main surface 31 of the metal resistor plate 30. The groove 40 is formed between the first plating portion layer 37a and the second plating portion layer 37b. In the groove 40, the first main surface 31 is exposed from the first plating portion layer 37a and the second plating portion layer 37b. The third plating portion layer 37c is formed on the second main surface 32 of the metal resistor plate 30. The grooves 41 and 42 are formed on both sides of the third plating portion layer 37c. In the grooves 41 and 42, the second main surface 32 is exposed from the third plating portion layer 37c. The method for removing a portion of plating layer 37 is, for example, machining such as cutting or milling using cutting tool 43 (see FIG. 6 ), thereby forming laminate 5 of metal resistor plate 30, first plating partial layer 37a, second plating partial layer 37b, and third plating partial layer 37c.

[0106] Referring to FIG. 37, the laminate 5 is punched out so as to cross the groove 40. A portion of the groove 41 and a portion of the groove 42 are also punched out. The laminate 5 is punched out, for example, in a direction from the second main surface 32 toward the first main surface 31. By punching the laminate 5, the metal resistor 10 is formed from the metal resistor plate 30, the first plated electrode 15 is formed from the first plated portion layer 37a, the second plated electrode 16 is formed from the second plated portion layer 37b, and the first plated heat dissipation layer 25 is formed from the third plated portion layer 37c. In this way, the chip resistor 1 shown in FIGS. 32 to 34 is obtained.

[0107] The chip resistor 1 and the manufacturing method thereof according to this embodiment have the following advantages in addition to the advantages of the chip resistor 1 and the manufacturing method thereof according to the first embodiment.

[0108] The chip resistor 1 of this embodiment further includes a first plated heat dissipation layer 25 disposed on the top surface 11. The metal resistor 10 has a first end surface 13 and a second end surface 14 opposite the first end surface 13. The first end surface 13 and the second end surface 14 are connected to the top surface 11 and the bottom surface 12, respectively. In a plan view of the top surface 11, the first plated heat dissipation layer 25 overlaps with a center 18 of the metal resistor 10 in the direction in which the first end surface 13 and the second end surface 14 are spaced apart from each other, and is spaced apart from the first end surface 13 and the second end surface 14.

[0109] The heat generated in the chip resistor 1 while a current is flowing through the chip resistor 1 causes the temperature of the center 18 of the metal resistive element 10 of the chip resistor 1 to become the highest. This heat is spread by the first plated heat dissipation layer 25 and dissipated to the periphery of the chip resistor 1. This allows the rated power of the chip resistor 1 to be increased.

[0110] In the manufacturing method of the chip resistor 1 of this embodiment, the chip resistor 1 includes a first plated heat dissipation layer 25 disposed on the top surface 11. The metal resistor 10 has a first end surface 13 and a second end surface 14 opposite the first end surface 13. The first end surface 13 and the second end surface 14 are connected to the top surface 11 and the bottom surface 12, respectively. In a plan view of the top surface 11, the first plated heat dissipation layer 25 overlaps the center 18 of the metal resistor 10 in the direction in which the first end surface 13 and the second end surface 14 are spaced apart from each other, and is spaced apart from the first end surface 13 and the second end surface 14. Forming the laminate 5 includes forming a third plated partial layer 37c on the second main surface 32 of the metal resistor plate 30 opposite the first main surface 31. By punching out the laminate 5, the first plated heat dissipation layer 25 is formed from the third plated partial layer 37c.

[0111] The heat generated in the chip resistor 1 while a current is flowing through the chip resistor 1 causes the temperature of the center 18 of the metal resistive element 10 of the chip resistor 1 to become the highest. This heat is spread by the first plated heat dissipation layer 25 and dissipated to the periphery of the chip resistor 1. This allows the rated power of the chip resistor 1 to be increased.

[0112] (Sixth embodiment) The chip resistor 1 of the sixth embodiment will be described with reference to Figures 32, 33, and 38. The chip resistor 1 of the sixth embodiment has a similar configuration to the chip resistor 1 of the fifth embodiment, but differs from the chip resistor 1 of the fifth embodiment mainly in the following points.

[0113] 38, in the present embodiment, the first inner end face 15b of the first plating electrode 15, the second inner end face 16b of the second plating electrode 16, and the end faces 25a, 25b of the first plating heat dissipation layer 25 are rounded end faces. The first inner end face 15b is an end face that is convexly curved toward the second plating electrode 16. The second inner end face 16b is an end face that is convexly curved toward the first plating electrode 15. The end face 25a is an end face that is convexly curved toward the first end face 13. The end face 26a is an end face that is convexly curved toward the second end face 14.

[0114] An example of a method for manufacturing the chip resistor 1 of the present embodiment will be described with reference to Figures 39 to 42. The method for manufacturing the chip resistor 1 of the present embodiment includes the same steps as the method for manufacturing the chip resistor 1 of embodiment 5, but differs from the method for manufacturing the chip resistor 1 of embodiment 5 in the steps of forming the first plated portion layer 37a, the second plated portion layer 37b, and the third plated portion layer 37c.

[0115] 39 , masks 35 and 38 are formed on the second main surface 32 of the metal resistor plate 30, and a mask 36 is formed on the first main surface 31 of the metal resistor plate 30. The masks 35, 36, and 38 are made of an insulating material such as resist. Portions of the first main surface 31 on both sides of the mask 36 are exposed from the mask 36. The mask 38 is spaced from the mask 35. Portions of the second main surface 32 on both sides of the mask 35 and portions of the second main surface 32 on both sides of the mask 38 are exposed from the masks 35 and 38. In a plan view of the second main surface 32, the mask 36 is disposed between the mask 35 and the mask 38.

[0116] Referring to FIG. 40 , plating layers 37 are formed on the first and second main surfaces 31, 32 of the metal resistor plate 30 by plating. The plating layers 37 are formed on both sides of each of the masks 35, 36, and 38. The first plating portion layer 37a is a portion of the plating layer 37 on one side facing the mask 36. The second plating portion layer 37b is a portion of the plating layer 37 on the other side facing the mask 36. The third plating portion layer 37c is a portion of the plating layer 37 between the masks 35 and 38. The first plating portion layer 37a and the second plating portion layer 37b are formed on the first main surface 31. A groove 40 is formed between the first plating portion layer 37a and the second plating portion layer 37b. The third plating portion layer 37c is formed on the second main surface 32.

[0117] The plating layer 37 grows isotropically near each of the masks 35, 36, and 38. Therefore, the end face of the first plating portion layer 37a facing the mask 36 and the end face of the second plating portion layer 37b facing the mask 36 are rounded end faces. The end face of the third plating portion layer 37c facing the mask 35 and the end face of the fourth plating portion layer 37d facing the mask 38 are rounded end faces.

[0118] 41, the masks 35, 36, and 38 are removed. In this way, the laminate 5 is formed, which includes the metal resistor plate 30, the first plated partial layer 37a, the second plated partial layer 37b, and the third plated partial layer 37c.

[0119] 42, the laminate 5 is punched out so as to cross the groove 40. A portion of the groove 41 and a portion of the groove 42 are also punched out. The laminate 5 is punched out, for example, in a direction from the second main surface 32 toward the first main surface 31. By punching the laminate 5, the metal resistor 10 is formed from the metal resistor plate 30, the first plated electrode 15 is formed from the first plated portion layer 37a, the second plated electrode 16 is formed from the second plated portion layer 37b, and the first plated heat dissipation layer 25 is formed from the third plated portion layer 37c. In this way, the chip resistor 1 shown in FIG. 38 is obtained.

[0120] The chip resistor 1 and the manufacturing method thereof according to this embodiment have the same effects as the chip resistor 1 and the manufacturing method thereof according to the fifth embodiment and the third embodiment.

[0121] (Embodiment 7) The chip resistor 1 of the seventh embodiment will be described with reference to Figures 43 to 45. The chip resistor 1 of the seventh embodiment has a similar configuration to the chip resistor 1 of the fifth embodiment, but differs from the chip resistor 1 of the fifth embodiment in that it further includes a second plated heat dissipation layer 26.

[0122] The second plated heat dissipation layer 26 is formed of a material having a higher thermal conductivity than the metal resistor 10. The second plated heat dissipation layer 26 is formed of, for example, copper (Cu) or a copper-based alloy. The second plated heat dissipation layer 26 may be formed of the same material as the first plated electrode 15, the second plated electrode 16, and the first plated heat dissipation layer 25.

[0123] The second plated heat dissipation layer 26 is disposed on the top surface 11 of the metal resistor 10. The second plated heat dissipation layer 26 is spaced apart from the first plated heat dissipation layer 25 in the direction in which the first end surface 13 and the second end surface 14 are spaced apart from each other.

[0124] In a plan view of the top surface 11, the first plated heat dissipation layer 25 is offset from the center 18 of the metal resistor 10 in the direction in which the first end surface 13 and the second end surface 14 are spaced apart from each other, and extends to the first end surface 13 of the metal resistor 10. The first plated heat dissipation layer 25 has an end surface 25a and an end surface 25b opposite to the end surface 25a. The end surface 25a is proximate to the first end surface 13. The end surface 25a of the first plated heat dissipation layer 25 may be flush with the first end surface 13. The end surface 25b is proximate to the second plated heat dissipation layer 26. The end surfaces 25a and 25b are, for example, perpendicular to the top surface 11.

[0125] In a plan view of the top surface 11, the second plated heat dissipation layer 26 overlaps the center 18 of the metal resistor 10 and extends to the second end surface 14 of the metal resistor 10. The second plated heat dissipation layer 26 has an end surface 26a and an end surface 26b opposite to the end surface 26a. The end surface 26a is proximate to the second end surface 14. The end surface 26a may be flush with the second end surface 14. The end surface 26b is proximate to the first plated heat dissipation layer 25. The end surfaces 26a and 26b are, for example, perpendicular to the top surface 11.

[0126] 46, the chip resistor 1 is mounted on a circuit board 50. Specifically, the first plating electrode 15 is joined to an electrical wiring 52 using a conductive bonding member 54 such as solder. The second plating electrode 16 is joined to an electrical wiring 53 using a conductive bonding member 55 such as solder. The conductive bonding member 54 is formed on the first surface 15a, the first inner end face 15b, and the first outer end face 15c of the first plating electrode 15. The conductive bonding member 55 is formed on the second surface 16a, the second inner end face 16b, and the second outer end face 16c of the second plating electrode 16.

[0127] An example of a method for manufacturing the chip resistor 1 of the present embodiment will be described with reference to Figures 35, 47, and 48. The method for manufacturing the chip resistor 1 of the present embodiment includes the same steps as the method for manufacturing the chip resistor 1 of embodiment 5, but differs from the method for manufacturing the chip resistor 1 of embodiment 5 mainly in the following points.

[0128] In the manufacturing method of the chip resistor 1 of this embodiment, forming the laminate 5 includes forming a first plating portion layer 37a and a second plating portion layer 37b on the first main surface 31 of the metal resistor plate 30, and forming a third plating portion layer 37c and a fourth plating portion layer 37d on the second main surface 32 of the metal resistor plate 30 opposite the first main surface 31.

[0129] Referring to FIG. 47, grooves 40 and 41 are formed in plating layer 37 by cutting, and plating layer 37 is divided into first plated partial layer 37a, second plated partial layer 37b, third plated partial layer 37c, and fourth plated partial layer 37d.

[0130] The first plating portion layer 37a and the second plating portion layer 37b are formed on the first main surface 31 of the metal resistor plate 30. A groove 40 is formed between the first plating portion layer 37a and the second plating portion layer 37b. At the groove 40, the first main surface 31 is exposed from the first plating portion layer 37a and the second plating portion layer 37b. The third plating portion layer 37c and the fourth plating portion layer 37d are formed on the second main surface 32 of the metal resistor plate 30. A groove 41 is formed between the third plating portion layer 37c and the fourth plating portion layer 37d. At the groove 41, the second main surface 32 is exposed from the third plating portion layer 37c and the fourth plating portion layer 37d. In a plan view of the first main surface 31, the groove 41 is offset from the groove 40. A method for removing a portion of the plating layer 37 includes, for example, machining such as cutting using a cutting tool 43 (see FIG. 6) or milling. In this way, a laminate 5 is formed, which includes the metal resistor plate 30, the first plated partial layer 37a, the second plated partial layer 37b, the third plated partial layer 37c, and the fourth plated partial layer 37d.

[0131] 48, the laminate 5 is punched out across the grooves 40, 41. The laminate 5 is punched out, for example, in a direction from the second main surface 32 toward the first main surface 31. By punching the laminate 5, the metal resistor 10 is formed from the metal resistor plate 30, the first plated electrode 15 is formed from the first plated portion layer 37a, the second plated electrode 16 is formed from the second plated portion layer 37b, the first plated heat dissipation layer 25 is formed from the third plated portion layer 37c, and the second plated heat dissipation layer 26 is formed from the fourth plated portion layer 37d. In this way, the chip resistor 1 shown in FIGS. 43 to 45 is obtained.

[0132] The chip resistor 1 and the manufacturing method thereof according to this embodiment have the following advantages in addition to the advantages of the chip resistor 1 and the manufacturing method thereof according to the first embodiment.

[0133] The chip resistor 1 of this embodiment further includes a first plated heat dissipation layer 25 disposed on the top surface 11 and a second plated heat dissipation layer 26 disposed on the top surface 11 and spaced apart from the first plated heat dissipation layer 25. The metal resistor 10 has a first end face 13 and a second end face 14 opposite the first end face 13. The first end face 13 and the second end face 14 are connected to the top surface 11 and the bottom surface 12, respectively. In a plan view of the top surface 11, the first plated heat dissipation layer 25 is offset from a center 18 of the metal resistor 10 in the direction in which the first end face 13 and the second end face 14 are spaced apart from each other, and extends to the first end face 13. In a plan view of the top surface 11, the second plated heat dissipation layer 26 overlaps the center 18 of the metal resistor 10 and extends to the second end face 14.

[0134] Therefore, the temperature of the center 18 of the metal resistive element 10 of the chip resistor 1 becomes highest due to the heat generated in the chip resistor 1 while a current is flowing through the chip resistor 1. This heat is spread by the first plated heat dissipation layer 25 and the second plated heat dissipation layer 26 and dissipated to the periphery of the chip resistor 1, and is also dissipated to the circuit board through the first plated heat dissipation layer 25, the second plated heat dissipation layer 26, the first plated electrode 15, and the second plated electrode 16. The rated power of the chip resistor 1 can be increased.

[0135] In the manufacturing method of the chip resistor 1 of this embodiment, the chip resistor 1 includes a first plated heat dissipation layer 25 disposed on the top surface 11 and a second plated heat dissipation layer 26 disposed on the top surface 11 and spaced apart from the first plated heat dissipation layer 25. The metal resistor 10 has a first end face 13 and a second end face 14 opposite the first end face 13. The first end face 13 and the second end face 14 are connected to the top surface 11 and the bottom surface 12, respectively. In a plan view of the top surface 11, the first plated heat dissipation layer 25 is offset from the center 18 of the metal resistor 10 in the direction in which the first end face 13 and the second end face 14 are spaced apart from each other, and extends to the first end face 13. In a plan view of the top surface 11, the second plated heat dissipation layer 26 overlaps the center 18 of the metal resistor 10 and extends to the second end face 14. Forming the laminate 5 includes forming a third plated partial layer 37c and a fourth plated partial layer 37d on the second main surface 32 of the metal resistor plate 30 opposite the first main surface 31. A second groove (groove 41) is formed between the third plated partial layer 37c and the fourth plated partial layer 37d. By punching the laminate 5 across the first groove (groove 40) and the second groove, the first plated heat dissipation layer 25 is formed from the third plated partial layer 37c, and the second plated heat dissipation layer 26 is formed from the fourth plated partial layer 37d.

[0136] Therefore, the temperature of the center 18 of the metal resistive element 10 of the chip resistor 1 becomes highest due to the heat generated in the chip resistor 1 while a current is flowing through the chip resistor 1. This heat is spread by the first plated heat dissipation layer 25 and the second plated heat dissipation layer 26 and dissipated to the periphery of the chip resistor 1, and is also dissipated to the circuit board through the first plated heat dissipation layer 25, the second plated heat dissipation layer 26, the first plated electrode 15, and the second plated electrode 16. The rated power of the chip resistor 1 can be increased.

[0137] (Embodiment 8) The chip resistor 1 of the eighth embodiment will be described with reference to Figures 43, 44, and 49. The chip resistor 1 of the present embodiment has a similar configuration to the chip resistor 1 of the seventh embodiment, but differs from the chip resistor 1 of the seventh embodiment mainly in the following points.

[0138] 49, in the present embodiment, the first inner end face 15b of the first plating electrode 15, the second inner end face 16b of the second plating electrode 16, the end face 25b of the first plating heat dissipation layer 25, and the end face 26b of the second plating heat dissipation layer 26 are rounded end faces. The first inner end face 15b is an end face that is convexly curved toward the second plating electrode 16. The second inner end face 16b is an end face that is convexly curved toward the first plating electrode 15. The end face 25b is an end face that is convexly curved toward the second plating heat dissipation layer 26. The end face 26b is an end face that is convexly curved toward the first plating heat dissipation layer 25.

[0139] 50, the chip resistor 1 is mounted on a circuit board 50. Specifically, the first plating electrode 15 is joined to an electrical wiring 52 using a conductive bonding member 54 such as solder. The second plating electrode 16 is joined to an electrical wiring 53 using a conductive bonding member 55 such as solder. The conductive bonding member 54 is formed on the first surface 15a, the first inner end face 15b, and the first outer end face 15c of the first plating electrode 15. The conductive bonding member 55 is formed on the second surface 16a, the second inner end face 16b, and the second outer end face 16c of the second plating electrode 16.

[0140] An example of a method for manufacturing the chip resistor 1 of the present embodiment will be described with reference to Figures 51 to 54. The method for manufacturing the chip resistor 1 of the present embodiment includes the same steps as the method for manufacturing the chip resistor 1 of embodiment 7, but differs from the method for manufacturing the chip resistor 1 of embodiment 7 in the steps of forming the first plated portion layer 37a, the second plated portion layer 37b, the third plated portion layer 37c, and the fourth plated portion layer 37d.

[0141] 51 , a mask 35 is formed on the second main surface 32 of the metal resistor plate 30, and a mask 36 is formed on the first main surface 31 of the metal resistor plate 30. The masks 35, 36 are made of an insulating material such as resist. In a plan view of the first main surface 31, portions of the first main surface 31 on both sides of the mask 36 are exposed from the mask 36. In a plan view of the second main surface 32, the mask 35 is offset from the mask 36.

[0142] Referring to FIG. 52 , plating layers 37 are formed on the first and second main surfaces 31 and 32 of the metal resistor plate 30 by plating. The plating layers 37 are formed on both sides of each of the masks 35 and 36. The first plating portion layer 37a is a portion of the plating layer 37 on one side facing the mask 36. The second plating portion layer 37b is a portion of the plating layer 37 on the other side facing the mask 36. The third plating portion layer 37c is a portion of the plating layer 37 on one side facing the mask 35. The fourth plating portion layer 37d is a portion of the plating layer 37 on the other side facing the mask 35. The first plating portion layer 37a and the second plating portion layer 37b are formed on the first main surface 31. A groove 40 is formed between the first plating portion layer 37a and the second plating portion layer 37b. The third plating portion layer 37c and the fourth plating portion layer 37d are formed on the second main surface 32. A groove 41 is formed between the third plated partial layer 37c and the fourth plated partial layer 37d.

[0143] The plating layer 37 grows isotropically near each of the masks 35 and 36. Therefore, the end face of the first plating portion layer 37a facing the mask 36 and the end face of the second plating portion layer 37b facing the mask 36 are rounded end faces. The end face of the third plating portion layer 37c facing the mask 35 and the end face of the fourth plating portion layer 37d facing the mask 35 are rounded end faces.

[0144] 53, the masks 35 and 36 are removed. In this way, a laminate 5 is formed, which includes the metal resistor plate 30, the first plated partial layer 37a, the second plated partial layer 37b, the third plated partial layer 37c, and the fourth plated partial layer 37d.

[0145] 54, the laminate 5 is punched out across the grooves 40, 41. The laminate 5 is punched out, for example, in a direction from the second main surface 32 toward the first main surface 31. By punching the laminate 5, the metal resistor 10 is formed from the metal resistor plate 30, the first plated electrode 15 is formed from the first plated portion layer 37a, the second plated electrode 16 is formed from the second plated portion layer 37b, the first plated heat dissipation layer 25 is formed from the third plated portion layer 37c, and the second plated heat dissipation layer 26 is formed from the fourth plated portion layer 37d. In this way, the chip resistor 1 shown in FIG. 49 is obtained.

[0146] The chip resistor 1 and the manufacturing method thereof according to this embodiment have the same effects as the chip resistor 1 and the manufacturing method thereof according to the seventh embodiment and the same effects as the chip resistor 1 and the manufacturing method thereof according to the third embodiment.

[0147] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) A metal resistor; a first plating electrode; a second plating electrode; the metal resistor has a top surface and a bottom surface opposite to the top surface, the first plating electrode is disposed on the bottom surface; the second plating electrode is disposed on the bottom surface and spaced apart from the first plating electrode; A chip resistor, wherein the top surface is a flat surface. (Appendix 2) the first plating electrode has a first inner end surface facing the second plating electrode; the second plating electrode has a second inner end surface facing the first plating electrode; 2. The chip resistor according to claim 1, wherein the first inner end surface and the second inner end surface are flat surfaces inclined with respect to the bottom surface. (Appendix 3) the first plating electrode has a first inner end surface facing the second plating electrode; the second plating electrode has a second inner end surface facing the first plating electrode; 2. The chip resistor according to claim 1, wherein the first inner end surface and the second inner end surface are rounded end surfaces. (Appendix 4) the metal resistor has a first end face and a second end face opposite to the first end face, the first end face and the second end face being connected to the top face and the bottom face, respectively; A chip resistor described in any one of Appendix 1 to Appendix 3, wherein, in a planar view of the top surface, the first plated electrode protrudes from the first end surface and the second plated electrode protrudes from the second end surface. (Appendix 5) a first plating coating layer; Further comprising a second plating coating layer, the first plating coating layer is disposed on a first surface of the first plating electrode opposite the metal resistor, and a first outermost surface of the first plating coating layer has higher solder wettability than the first plating electrode; A chip resistor described in any one of Appendix 1 to Appendix 3, wherein the second plating coating layer is arranged on a second surface of the second plating electrode opposite the metal resistor, and the second outermost surface of the second plating coating layer has higher solder wettability than the second plating electrode. (Appendix 6) the metal resistor has a first end face and a second end face opposite to the first end face, the first end face and the second end face being connected to the top face and the bottom face, respectively; A chip resistor as described in Appendix 5, wherein, in a planar view of the top surface, the first plating electrode and the first plating coating layer protrude from the first end surface, and the second plating electrode and the second plating coating layer protrude from the second end surface. (Appendix 7) a first plated heat dissipation layer disposed on the top surface; the metal resistor has a first end face and a second end face opposite to the first end face, the first end face and the second end face being connected to the top face and the bottom face, respectively; A chip resistor described in any one of Appendix 1 to Appendix 6, wherein, in a planar view of the top surface, the first plated heat dissipation layer overlaps the center of the metal resistor in the direction in which the first end face and the second end face are separated from each other, and is separated from the first end face and the second end face. (Appendix 8) a first plated heat dissipation layer disposed on the top surface; a second plated heat spreader layer disposed on the top surface and spaced apart from the first plated heat spreader layer; the metal resistor has a first end face and a second end face opposite to the first end face, the first end face and the second end face being connected to the top face and the bottom face, respectively; In a plan view of the top surface, the first plated heat dissipation layer is offset from the center of the metal resistor in a direction in which the first end face and the second end face are spaced apart from each other, and extends to the first end face; A chip resistor described in any one of Appendix 1 to Appendix 6, wherein, in the planar view of the top surface, the second plated heat dissipation layer overlaps the center of the metal resistor and extends to the second end surface. (Appendix 9) 9. The chip resistor according to claim 1, wherein the chip resistor is a shunt resistor. (Appendix 10) A method for manufacturing a chip resistor, the chip resistor including a metal resistive element having a top surface and a bottom surface opposite to the top surface, a first plated electrode disposed on the bottom surface, and a second plated electrode disposed on the bottom surface and spaced apart from the first plated electrode, the top surface being a flat surface, the method comprising: forming a laminate, the forming of the laminate including forming a first plating partial layer and a second plating partial layer on a first main surface of the metal resistor plate, a first groove being formed between the first plating partial layer and the second plating partial layer; A method for manufacturing a chip resistor, comprising punching the laminate across the first groove, wherein by punching the laminate, the metal resistor is formed from the metal resistor plate, the first plated electrode is formed from the first plated portion layer, and the second plated electrode is formed from the second plated portion layer. (Appendix 11) Forming the first plated portion layer and the second plated portion layer on the first main surface includes: forming a first plating layer on the first main surface of the metal resistor plate; A method for manufacturing a chip resistor as described in Appendix 10, comprising forming the first groove in the first plating layer by cutting, and forming the first plating portion layer and the second plating portion layer from the first plating layer. (Appendix 12) A method for manufacturing a chip resistor described in Appendix 11, wherein the end face of the first plated portion layer facing the second plated portion layer and the end face of the second plated portion layer facing the first plated portion layer are flat surfaces inclined with respect to the first main surface. (Appendix 13) Forming the first plated portion layer and the second plated portion layer on the first main surface includes: forming a first mask on the first main surface of the metal resistor plate; A method for manufacturing a chip resistor described in Appendix 10, comprising forming a first plating layer on both sides of the first mask to form the first plating portion layer and the second plating portion layer. (Appendix 14) punching the laminate in a direction from a second main surface of the metal resistor plate opposite to the first main surface toward the first main surface, the metal resistor has a first end face and a second end face opposite to the first end face, the first end face and the second end face being connected to the top face and the bottom face, respectively, the first end face being one end face of the metal resistor in a direction in which the first plated electrode and the second plated electrode are spaced apart from each other, and the second end face being the other end face of the metal resistor in the same direction; A method for manufacturing a chip resistor described in any one of Appendix 10 to Appendix 13, wherein, in a planar view of the top surface of the metal resistor, the first plated electrode protrudes from the first end face and the second plated electrode protrudes from the second end face. (Appendix 15) the chip resistor includes a first plating coating layer disposed on the first plating electrode and a second plating coating layer disposed on the second plating electrode; forming the laminate includes forming a first plating portion coating layer on the first plating portion layer and forming a second plating portion coating layer on the second plating portion layer; the outermost surface of the first plated partial covering layer has higher solder wettability than the first plated partial layer; the outermost surface of the second plated partial covering layer has higher solder wettability than the second plated partial layer; A method for manufacturing a chip resistor described in any one of Appendix 10 to Appendix 13, wherein the first plating coating layer is formed from the first plating partial coating layer and the second plating coating layer is formed from the second plating partial coating layer by punching the laminate. (Appendix 16) punching the laminate in a direction from a second main surface of the metal resistor plate opposite to the first main surface toward the first main surface, the metal resistor has a first end face and a second end face opposite to the first end face, the first end face and the second end face being connected to the top face and the bottom face, respectively, the first end face being one end face of the metal resistor in a direction in which the first plated electrode and the second plated electrode are spaced apart from each other, and the second end face being the other end face of the metal resistor in the same direction; A method for manufacturing a chip resistor described in Appendix 15, wherein, in a planar view of the top surface of the metal resistor, the first plated electrode and the first plated coating layer protrude from the first end face, and the second plated electrode and the second plated coating layer protrude from the second end face. (Appendix 17) the chip resistor includes a first plated heat dissipation layer disposed on the top surface; the metal resistor has a first end face and a second end face opposite to the first end face, the first end face and the second end face being connected to the top face and the bottom face, respectively; In a plan view of the top surface, the first plated heat dissipation layer overlaps a center of the metal resistor in a direction in which the first end face and the second end face are spaced apart from each other, and is spaced apart from the first end face and the second end face; forming the laminate includes forming a third plating portion layer on a second main surface of the metal resistor plate opposite the first main surface; A method for manufacturing a chip resistor described in any one of Appendix 10 to Appendix 16, wherein the first plated heat dissipation layer is formed from the third plated portion layer by punching out the laminate. (Appendix 18) the chip resistor includes a first plated heat dissipation layer disposed on the top surface, and a second plated heat dissipation layer disposed on the top surface and spaced apart from the first plated heat dissipation layer; the metal resistor has a first end face and a second end face opposite to the first end face, the first end face and the second end face being connected to the top face and the bottom face, respectively; In a plan view of the top surface, the first plated heat dissipation layer is offset from the center of the metal resistor in a direction in which the first end face and the second end face are spaced apart from each other, and extends to the first end face; In the plan view of the top surface, the second plated heat dissipation layer overlaps the center of the metal resistor and extends to the second end surface, forming the laminate includes forming a third plating portion layer and a fourth plating portion layer on a second main surface of the metal resistor plate opposite the first main surface, and a second groove is formed between the third plating portion layer and the fourth plating portion layer; A method for manufacturing a chip resistor described in any one of Appendix 10 to Appendix 16, wherein the first plated heat dissipation layer is formed from the third plated portion layer and the second plated heat dissipation layer is formed from the fourth plated portion layer by punching the laminate across the first groove and the second groove. (Appendix 19) The method for manufacturing a chip resistor according to any one of Supplementary Note 10 to Supplementary Note 18, wherein the chip resistor is a shunt resistor.

[0148] The presently disclosed embodiments 1-8 and their modifications should be considered to be illustrative in all respects and not restrictive. At least two of the presently disclosed embodiments 1-8 and their modifications may be combined, provided there is no contradiction. For example, the first plating coating layer 21 and the second plating coating layer 22 of embodiments 2 and 4 and their modifications may be added to the chip resistor 1 of embodiments 5-8. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0149] 1 chip resistor, 5 laminate, 10 metal resistor, 11 top surface, 12 bottom surface, 13 first end surface, 14 second end surface, 15 first plated electrode, 15a first surface, 15b first inner end surface, 15c first outer end surface, 15d first connection portion, 16 second plated electrode, 16a second surface, 16b second inner end surface, 16c second outer end surface, 16d second connection portion, 18 center, 21 first plated coating layer, 21a first outermost surface, 22 second plated coating layer, 22a second outermost surface, 25 first plated heat dissipation layer, 25a, 25b, 26a, 26b end surface, 26 second plated heat dissipation layer, 30 metal resistor plate, 31 first main surface, 32 second main surface, 35, 36, 38 mask, 37, 45 plating layer, 37a First plating partial layer, 37b second plating partial layer, 37c third plating partial layer, 37d fourth plating partial layer, 40, 41, 42 groove, 43 cutting tool, 45a outermost surface, 45b first plating partial coating layer, 45c second plating partial coating layer, 50 circuit board, 51 insulating substrate, 52, 53 electrical wiring, 54, 55 conductive joining member.

Claims

1. A metal resistor; a first plating electrode; a second plating electrode; the metal resistor has a top surface and a bottom surface opposite to the top surface, the first plating electrode is disposed on the bottom surface; the second plating electrode is disposed on the bottom surface and spaced apart from the first plating electrode; A chip resistor, wherein the top surface is a flat surface.

2. the first plating electrode has a first inner end surface facing the second plating electrode; the second plating electrode has a second inner end surface facing the first plating electrode; The chip resistor according to claim 1 , wherein the first inner end surface and the second inner end surface are flat surfaces inclined with respect to the bottom surface.

3. the first plating electrode has a first inner end surface facing the second plating electrode; the second plating electrode has a second inner end surface facing the first plating electrode; The chip resistor according to claim 1 , wherein the first inner end surface and the second inner end surface are rounded end surfaces.

4. the metal resistor has a first end surface and a second end surface opposite to the first end surface, the first end surface and the second end surface being connected to the top surface and the bottom surface, respectively; A chip resistor described in any one of claims 1 to 3, wherein, in a planar view of the top surface, the first plated electrode protrudes from the first end surface and the second plated electrode protrudes from the second end surface.

5. a first plating coating layer; Further provided with a second plating coating layer, the first plating coating layer is disposed on a first surface of the first plated electrode opposite the metal resistor, and a first outermost surface of the first plating coating layer has higher solder wettability than the first plated electrode; A chip resistor described in any one of claims 1 to 3, wherein the second plating coating layer is arranged on a second surface of the second plating electrode opposite the metal resistor, and the second outermost surface of the second plating coating layer has higher solder wettability than the second plating electrode.

6. the metal resistor has a first end surface and a second end surface opposite to the first end surface, the first end surface and the second end surface being connected to the top surface and the bottom surface, respectively; A chip resistor as described in claim 5, wherein, in a planar view of the top surface, the first plating electrode and the first plating coating layer protrude from the first end surface, and the second plating electrode and the second plating coating layer protrude from the second end surface.

7. a first plated heat dissipation layer disposed on the top surface; the metal resistor has a first end surface and a second end surface opposite to the first end surface, the first end surface and the second end surface being connected to the top surface and the bottom surface, respectively; A chip resistor described in any one of claims 1 to 3, wherein, in a planar view of the top surface, the first plated heat dissipation layer overlaps the center of the metal resistor in the direction in which the first end face and the second end face are separated from each other, and is separated from the first end face and the second end face.

8. a first plated heat dissipation layer disposed on the top surface; a second plated heat spreader layer disposed on the top surface and spaced apart from the first plated heat spreader layer; the metal resistor has a first end surface and a second end surface opposite to the first end surface, the first end surface and the second end surface being connected to the top surface and the bottom surface, respectively; In a plan view of the top surface, the first plated heat dissipation layer is offset from the center of the metal resistor in a direction in which the first end face and the second end face are spaced apart from each other, and extends to the first end face; A chip resistor according to any one of claims 1 to 3, wherein, in the planar view of the top surface, the second plated heat dissipation layer overlaps the center of the metal resistor and extends to the second end face.

9. The chip resistor according to claim 1 , wherein the chip resistor is a shunt resistor.

10. A method for manufacturing a chip resistor, the chip resistor including a metal resistive element having a top surface and a bottom surface opposite to the top surface, a first plated electrode disposed on the bottom surface, and a second plated electrode disposed on the bottom surface and spaced apart from the first plated electrode, the top surface being a flat surface, the method comprising: forming a laminate, the forming of the laminate including forming a first plating portion layer and a second plating portion layer on a first main surface of the metal resistor plate, a first groove being formed between the first plating portion layer and the second plating portion layer; A method for manufacturing a chip resistor, comprising punching the laminate across the first groove, wherein by punching the laminate, the metal resistor is formed from the metal resistor plate, the first plating electrode is formed from the first plating portion layer, and the second plating electrode is formed from the second plating portion layer.

11. Forming the first plated portion layer and the second plated portion layer on the first main surface includes: forming a first plating layer on the first main surface of the metal resistor plate; The method for manufacturing a chip resistor according to claim 10, further comprising forming the first groove in the first plating layer by cutting to form the first plating portion layer and the second plating portion layer from the first plating layer.

12. The method for manufacturing a chip resistor described in claim 11, wherein the end surface of the first plating portion layer facing the second plating portion layer and the end surface of the second plating portion layer facing the first plating portion layer are flat surfaces inclined with respect to the first main surface.

13. Forming the first plated portion layer and the second plated portion layer on the first main surface includes: forming a first mask on the first main surface of the metal resistor plate; The method for manufacturing a chip resistor according to claim 10 , further comprising forming a first plating layer on both sides of the first mask to form the first plating portion layer and the second plating portion layer.

14. punching the laminate in a direction from a second main surface of the metal resistor plate opposite to the first main surface toward the first main surface, the metal resistor has a first end face and a second end face opposite to the first end face, the first end face and the second end face being connected to the top face and the bottom face, respectively, the first end face being one end face of the metal resistor in a direction in which the first plated electrode and the second plated electrode are spaced apart from each other, and the second end face being the other end face of the metal resistor in the direction; A method for manufacturing a chip resistor described in any one of claims 10 to 13, wherein, in a planar view of the top surface of the metal resistor, the first plated electrode protrudes from the first end face and the second plated electrode protrudes from the second end face.

15. the chip resistor includes a first plating coating layer disposed on the first plating electrode and a second plating coating layer disposed on the second plating electrode; forming the laminate includes forming a first plated partial coating layer on the first plated partial layer and forming a second plated partial coating layer on the second plated partial layer; an outermost surface of the first plated partial covering layer has higher solder wettability than the first plated partial layer; the outermost surface of the second plated partial covering layer has higher solder wettability than the second plated partial layer; 14. A method for manufacturing a chip resistor according to claim 10, wherein the first plating coating layer is formed from the first plating partial coating layer and the second plating coating layer is formed from the second plating partial coating layer by punching out the laminate.

16. punching the laminate in a direction from a second main surface of the metal resistor plate opposite to the first main surface toward the first main surface, the metal resistor has a first end face and a second end face opposite to the first end face, the first end face and the second end face being connected to the top face and the bottom face, respectively, the first end face being one end face of the metal resistor in a direction in which the first plated electrode and the second plated electrode are spaced apart from each other, and the second end face being the other end face of the metal resistor in the direction; 16. A method for manufacturing a chip resistor as described in claim 15, wherein, in a planar view of the top surface of the metal resistor, the first plating electrode and the first plating coating layer protrude from the first end face, and the second plating electrode and the second plating coating layer protrude from the second end face.

17. the chip resistor includes a first plated heat dissipation layer disposed on the top surface; the metal resistor has a first end surface and a second end surface opposite to the first end surface, the first end surface and the second end surface being connected to the top surface and the bottom surface, respectively; In a plan view of the top surface, the first plated heat dissipation layer overlaps a center of the metal resistor in a direction in which the first end face and the second end face are spaced apart from each other, and is spaced apart from the first end face and the second end face; forming the laminate includes forming a third plating partial layer on a second main surface of the metal resistor plate opposite the first main surface; The method for manufacturing a chip resistor according to claim 10 , wherein the first plated heat dissipation layer is formed from the third plated portion layer by punching out the laminate.

18. the chip resistor includes a first plated heat dissipation layer disposed on the top surface, and a second plated heat dissipation layer disposed on the top surface and spaced apart from the first plated heat dissipation layer; the metal resistor has a first end surface and a second end surface opposite to the first end surface, the first end surface and the second end surface being connected to the top surface and the bottom surface, respectively; In a plan view of the top surface, the first plated heat dissipation layer is offset from the center of the metal resistor in a direction in which the first end face and the second end face are spaced apart from each other, and extends to the first end face; In the plan view of the top surface, the second plated heat dissipation layer overlaps the center of the metal resistor and extends to the second end surface, forming the laminate includes forming a third plating portion layer and a fourth plating portion layer on a second main surface of the metal resistor plate opposite the first main surface, and a second groove is formed between the third plating portion layer and the fourth plating portion layer; 14. A method for manufacturing a chip resistor according to claim 10, wherein the first plated heat dissipation layer is formed from the third plated portion layer and the second plated heat dissipation layer is formed from the fourth plated portion layer by punching the laminate across the first groove and the second groove.

19. The method for manufacturing a chip resistor according to claim 10 , wherein the chip resistor is a shunt resistor.

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