Chip resistor and method of manufacturing the same

Abstract

To provide a chip resistor capable of improving reliability and mountability on a circuit board.SOLUTION: The chip resistor 1 includes a metal resistor 10, a first electrode 15, a second electrode 16, a first plating layer 21, and a second plating layer 26. The first plating layer 21 includes a first nickel plating layer 22 and a first tin plating layer 23. The first outermost 21a of the first plating layer 21 is formed by the first tin plating layer 23. The thickness of the first nickel plating layer 22 is smaller than the thickness of the first tin plating layer 23. The second plating layer 26 includes a second nickel plating layer 27 and a second tin plating layer 28. A second outermost 26a portion of the second plating layer 26 is formed of a second tin plating layer 28. The thickness of the second nickel plating layer 27 is smaller than the thickness of the second tin plating layer 28.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a chip resistor and a method for manufacturing the same. [Background technology]

[0002] International Publication No. 2023 / 157435 (Patent Document 1) discloses a chip resistor including a resistive element, a first electrode, and a second electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 157435

[0004] [overview] An object of the present disclosure is to provide a chip resistor that can improve reliability and ease of mounting on a circuit board.

[0005] The chip resistor of the present disclosure includes a metal resistor, a first electrode, a second electrode, a first plating layer, and a second plating layer. The metal resistor has a first main surface and a second main surface opposite the first main surface. The first electrode is disposed on the second main surface. The second electrode is disposed on the second main surface and is spaced apart from the first electrode. The metal resistor and the first electrode are joined to each other by a metallic bond. The metal resistor and the second electrode are joined to each other by a metallic bond. The first plating layer is disposed on a first surface of the first electrode opposite the metal resistor, and includes a first nickel plating layer and a first tin plating layer. The first nickel plating layer is disposed between the first electrode and the first tin plating layer. A first outermost surface of the first plating layer is formed of the first tin plating layer and has higher solder wettability than the first electrode. The first thickness of the first nickel plating layer is smaller than the second thickness of the first tin plating layer. The second plating layer is disposed on a second surface of the second electrode opposite the metal resistor, and includes a second nickel plating layer and a second tin plating layer. The second nickel plating layer is disposed between the second electrode and the second tin plating layer. The second outermost surface of the second plating layer is formed of the second tin plating layer and has higher solder wettability than the second electrode. The third thickness of the second nickel plating layer is smaller than the fourth thickness of the second tin plating layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of a chip resistor according to an embodiment. [Figure 2] FIG. 2 is a schematic bottom view of the chip resistor according to the embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view of the chip resistor according to the embodiment taken along the cross-sectional line III-III shown in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of a circuit board on which the chip resistor according to the embodiment is mounted. [Figure 5] FIG. 5 is a schematic perspective view showing one step of the method for manufacturing the chip resistor according to the embodiment. [Figure 6]FIG. 6 is a schematic perspective view showing a step subsequent to the step shown in FIG. 5 in the method for manufacturing a chip resistor according to the embodiment. [Figure 7] FIG. 7 is a schematic partially enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 6 in the method for manufacturing a chip resistor according to the embodiment. [Figure 8] FIG. 8 is a schematic enlarged partial cross-sectional view showing a step subsequent to the step shown in FIG. 7 in the method for manufacturing a chip resistor according to the embodiment. [Figure 9] FIG. 9 is a schematic partially enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 8 in the method for manufacturing a chip resistor according to the embodiment. [Figure 10] FIG. 10 is a schematic partially enlarged cross-sectional view showing a step subsequent to the step shown in FIG. 9 in the method for manufacturing a chip resistor according to the embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view of a chip resistor according to a modified example of the embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view of a circuit board on which a chip resistor according to a modified example of the embodiment is mounted.

[0007] [Detailed explanation] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated. At least some of the configurations of the embodiments described below may be combined in any manner.

[0008] A chip resistor 1 according to an embodiment will be described with reference to FIGS. 1 to 4. The chip resistor 1 is, for example, a shunt resistor. The shunt resistor is used, for example, to measure the magnitude of a current flowing through the shunt resistor. The chip resistor 1 includes a metal resistor 10, a first electrode 15, a second electrode 16, a first plating layer 21, and a second plating layer 26.

[0009] 1 to 4, the metal resistor 10 is made of, for example, a copper-manganese (CuMn) based alloy, a copper-nickel (CuNi) based alloy, or a nickel-chromium (NiCr) based alloy.

[0010] The metal resistor 10 has a first main surface 11, a second main surface 12 opposite the first main surface 11, a first end surface 13, and a second end surface 14 opposite the first end surface 13. The first main surface 11 and the second main surface 12 are both end surfaces of the metal resistor 10 in the thickness direction. The first main surface 11 is a flat surface. As shown in FIG. 4 , when the chip resistor 1 is mounted on a circuit board 30, the second main surface 12 faces the circuit board 30. The second main surface 12 is the mounting surface of the chip resistor 1. The first end surface 13 and the second end surface 14 are connected to the first main surface 11 and the second main surface 12, respectively. The first end surface 13 and the second end surface 14 are both end surfaces of the metal resistor 10 in the longitudinal direction. The first end surface 13 is one end surface of the metal resistor 10 in the direction in which the first electrode 15 and the second electrode 16 are spaced apart from each other. The second end face 14 is the other end face of the metal resistor 10 in the direction in which the first electrode 15 and the second electrode 16 are spaced apart from each other.

[0011] 3 and 4, the first electrode 15 is formed of a material having a lower electrical resistivity than the metal resistor 10. The first electrode 15 is formed of, for example, copper (Cu) or a copper-based alloy. The first electrode 15 is disposed on the second main surface 12 (more specifically, a first end portion of the second main surface 12 that is proximal to the first end surface 13). The metal resistor 10 and the first electrode 15 are joined to each other by a metallic bond. The first electrode 15 has a first surface 15a opposite to the metal resistor 10, a first inner end surface 15b facing the second electrode 16, and a first outer end surface 15c opposite to the first inner end surface 15b. The first surface 15a and the first inner end surface 15b are connected at a first connection portion 15d. The first outer end surface 15c may be flush with the first end surface 13 of the metal resistor 10.

[0012] 3 and 4, the second electrode 16 is formed of a material having a lower electrical resistivity than the metal resistor 10. The second electrode 16 is formed of, for example, copper (Cu) or a copper-based alloy. The second electrode 16 is disposed on the second main surface 12 (more specifically, a second end portion of the second main surface 12 proximal to the second end surface 14) and is spaced apart from the first electrode 15. The metal resistor 10 and the second electrode 16 are joined to each other by a metallic bond. The second electrode 16 has a second surface 16a opposite to the metal resistor 10, a second inner end surface 16b facing the first electrode 15, and a second outer end surface 16c opposite to the second inner end surface 16b. The second surface 16a and the second inner end surface 16b are connected at a second connection portion 16d. The second outer end surface 16c may be flush with the second end surface 14 of the metal resistor 10.

[0013] 2 to 4, the first plating layer 21 is disposed on the first surface 15a of the first electrode 15. The first surface 15a is covered with the first plating layer 21. The first inner end face 15b is exposed from the first plating layer 21. The first plating layer 21 includes a first nickel plating layer 22 and a first tin plating layer 23. The first nickel plating layer 22 is disposed between the first electrode 15 and the first tin plating layer 23. Specifically, the first nickel plating layer 22 is formed on the first surface 15a of the first electrode 15. The first tin plating layer 23 is formed on the first nickel plating layer 22. The first outermost surface 21a of the first plating layer 21 is formed of the first tin plating layer 23 and has higher solder wettability than the first electrode 15. The first thickness t1 of the first nickel plating layer 22 is smaller than the second thickness t2 of the first tin plating layer 23. The first thickness t1 of the first nickel plating layer 22 is, for example, not less than 4 μm and not more than 10 μm.

[0014] 2 to 4, the second plating layer 26 is disposed on the second surface 16a of the second electrode 16. The second surface 16a is covered with the second plating layer 26. The second inner end surface 16b is exposed from the second plating layer 26. The second plating layer 26 includes a second nickel plating layer 27 and a second tin plating layer 28. The second nickel plating layer 27 is disposed between the second electrode 16 and the second tin plating layer 28. Specifically, the second nickel plating layer 27 is formed on the second surface 16a of the second electrode 16. The second tin plating layer 28 is formed on the second nickel plating layer 27. The second outermost surface 26a of the second plating layer 26 is formed of the second tin plating layer 28 and has higher solder wettability than the second electrode 16. The third thickness t3 of the second nickel plating layer 27 is smaller than the fourth thickness t4 of the second tin plating layer 28. The third thickness t3 of the second nickel plating layer 27 is, for example, not less than 4 μm and not more than 10 μm.

[0015] 4, the chip resistor 1 is mounted on a circuit board 30. Specifically, the circuit board 30 includes an insulating substrate 31 and electrical wiring 32 and 33. The electrical wiring 32 and 33 are formed on the insulating substrate 31. The first electrode 15, which is covered with the first plating layer 21, is joined to the electrical wiring 32 of the circuit board 30 using a conductive bonding member 34 such as solder. The second electrode 16, which is covered with the second plating layer 26, is joined to the electrical wiring 33 of the circuit board 30 using a conductive bonding member 35 such as solder.

[0016] An example of a method for manufacturing the chip resistor 1 of this embodiment will be described with reference to FIGS.

[0017] 5, a clad metal 40 is prepared in which a metal resistor plate 41 and a metal plate 42 are laminated. The metal resistor plate 41 is made of the same material as the metal resistor 10 (see FIG. 3, etc.). The metal plate 42 is made of the same material as the first electrode 15 (see FIG. 3, etc.) and the second electrode 16 (see FIG. 3, etc.).

[0018] The clad metal 40 is formed by bonding the metal resistor plate 41 and the metal plate 42 together while applying pressure to them. The metal resistor plate 41 and the metal plate 42 are bonded together by metal bonding. Specifically, the metal resistor plate 41 has a main surface 41a facing the metal plate 42 and a main surface 41b opposite to the main surface 41a. The metal plate 42 has a main surface 42a facing the metal resistor plate 41 and a main surface 42b opposite to the main surface 42a. The main surfaces 41a and 42a are bonded together by metal bonding.

[0019] 6 to 8, a plating layer 45 (see FIGS. 7 and 8) is formed on the main surface 42b of the metal plate 42 opposite the metal resistor plate 41 to form a laminate 44 (see FIGS. 7 and 8) of the clad metal 40 and the plating layer 45. The plating layer 45 includes a nickel plating layer 45a and a tin plating layer 45b. The nickel plating layer 45a is formed between the metal plate 42 and the tin plating layer 45b. The outermost surface of the plating layer 45 is formed of the tin plating layer 45b, and has higher solder wettability than the metal plate 42.

[0020] Specifically, referring to FIG. 6, a mask 43 is formed on the main surface 41b of the metal resistor plate 41 opposite the metal plate 42. The mask 43 is made of an insulating material such as resist. The main surface 42b of the metal plate 42 is exposed through the mask 43. Referring to FIG. 7, a plating layer 45 is formed on the main surface 42b of the metal plate 42. Specifically, a nickel plating layer 45a is formed on the main surface 42b. The thickness T1 of the nickel plating layer 45a is equal to the first thickness t1 of the first nickel plating layer 22 and equal to the third thickness t3 of the second nickel plating layer 27. Then, a tin plating layer 45b is formed on the nickel plating layer 45a. The thickness T2 of the tin plating layer 45b is equal to the second thickness t2 of the first tin plating layer 23 and equal to the fourth thickness t4 of the second tin plating layer 28. The plating layer 45 may be formed not only on the main surface 42a but also on the side surfaces of the metal resistor plate 41 and the metal plate 42 that are exposed from the mask 43. Referring to Fig. 8, the mask 43 is removed. In this way, a laminate 44 of the clad metal 40 and the plating layer 45 is formed.

[0021] 9, a portion of the plating layer 45 and a portion of the metal plate 42 are removed from a laminate 44 of a clad metal 40 and a plating layer 45, thereby forming grooves 46 in the plating layer 45 and the metal plate 42. In the grooves 46, the main surface 41a of the metal resistor plate 41 is exposed from the metal plate 42. The method for removing the portion of the plating layer 45 and the portion of the metal plate 42 is, for example, machining such as cutting using a cutting tool 48 or milling.

[0022] 10, the laminate 44 is punched out by punching or the like, from which part of the plating layer 45 and part of the metal plate 42 have been removed. The laminate 44 is punched out so as to cross the grooves 46. The laminate 44 is punched out, for example, in a direction from the metal resistor plate 41 toward the metal plate 42. In this way, the chip resistor 1 is obtained.

[0023] The metal resistor 10 is formed from the metal resistor plate 41. The first main surface 11 of the metal resistor 10 is a part of the main surface 41b of the metal resistor plate 41 and is a flat surface. The second main surface 12 of the metal resistor 10 is a part of the main surface 41a of the metal resistor plate 41. By punching out the laminate 44, the first electrode 15 and the second electrode 16 are formed from the metal plate 42. The first surface 15a of the first electrode 15 and the second surface 16a of the second electrode 16 are part of the main surface 42b of the metal plate 42. By punching out the laminate 44, the first plating layer 21 and the second plating layer 26 are formed from the plating layer 45. The first plating layer 21 is formed on the first surface 15a of the first electrode 15. The second plating layer 26 is formed on the second surface 16a of the second electrode 16. By punching the laminate 44, the first nickel plating layer 22 and the second nickel plating layer 27 are formed from the nickel plating layer 45a, and the first tin plating layer 23 and the second tin plating layer 28 are formed from the tin plating layer 45b.

[0024] (Variation) A modification of this embodiment will be described with reference to FIGS.

[0025] In the chip resistor 1 of this modified example of the present embodiment, in a plan view of the first main surface 11, the first electrode 15 and the first plating layer 21 protrude from the first end face 13, and the second electrode 16 and the second plating layer 26 protrude from the second end face 14. At least a portion of the first outer end face 15c is covered with the first plating layer 21. At least a portion of the second outer end face 16c is covered with the second plating layer 26.

[0026] A first protrusion length L1 of the first electrode 15 from the first end face 13 in a plan view of the first main surface 11 is smaller than a thickness t5 of the first electrode 15 at the first connection portion 15d. A second protrusion length L2 of the second electrode 16 from the second end face 14 in a plan view of the first main surface 11 is smaller than a thickness t6 of the second electrode 16 at the second connection portion 16d. The first protrusion length L1 may be equal to or smaller than 0.5 times the distance G between the first electrode 15 and the second electrode 16. The second protrusion length L2 may be equal to or smaller than 0.5 times the distance G.

[0027] In the manufacturing method of the chip resistor 1 according to the modified example of the present embodiment, when viewed from above in the thickness direction of the metal resistor 10 (i.e., when viewed from above in the first main surface 11), the protruding portions of the first electrode 15 and the first plating layer 21 from the first end face 13 and the protruding portions of the second electrode 16 and the second plating layer 26 from the second end face 14 are formed during the punching process of the laminate 44 shown in Fig. 10. Burrs generated during the punching process of the laminate 44 become the protruding portions of the first electrode 15 and the first plating layer 21 from the first end face 13 and the protruding portions of the second electrode 16 and the second plating layer 26 from the second end face 14.

[0028] 12, the chip resistor 1 is mounted on a circuit board 30. A conductive bonding member 34 is also formed on the portion of the first plating layer 21 that protrudes from the first end face 13. A conductive bonding member 35 is also formed on the portion of the second plating layer 26 that protrudes from the second end face 14.

[0029] The effects of the chip resistor 1 of this embodiment and the manufacturing method thereof will be described.

[0030] The chip resistor 1 of this embodiment includes a metal resistor 10, a first electrode 15, a second electrode 16, a first plating layer 21, and a second plating layer 26. The metal resistor 10 has a first main surface 11 and a second main surface 12 opposite the first main surface 11. The first electrode 15 is disposed on the second main surface 12. The second electrode 16 is disposed on the second main surface 12 and is spaced apart from the first electrode 15. The metal resistor 10 and the first electrode 15 are joined to each other by a metallic bond. The metal resistor 10 and the second electrode 16 are joined to each other by a metallic bond. The first plating layer 21 is disposed on a first surface 15a of the first electrode 15 opposite the metal resistor 10, and includes a first nickel plating layer 22 and a first tin plating layer 23. The first nickel plating layer 22 is disposed between the first electrode 15 and the first tin plating layer 23. The first outermost surface 21a of the first plating layer 21 is formed of the first tin plating layer 23 and has higher solder wettability than the first electrode 15. The first thickness t1 of the first nickel plating layer 22 is smaller than the second thickness t2 of the first tin plating layer 23. The second plating layer 26 is disposed on the second surface 16a of the second electrode 16 opposite the metal resistor 10 and includes a second nickel plating layer 27 and a second tin plating layer 28. The second nickel plating layer 27 is disposed between the second electrode 16 and the second tin plating layer 28. The second outermost surface 26a of the second plating layer 26 is formed of the second tin plating layer 28 and has higher solder wettability than the second electrode 16. The third thickness t3 of the second nickel plating layer 27 is smaller than the fourth thickness t4 of the second tin plating layer 28.

[0031] Because the chip resistor 1 includes the first plating layer 21 and the second plating layer 26, it is not necessary to form plating layers on the first electrode 15 and the second electrode 16 when mounting the chip resistor 1 on the circuit board 30. This improves the mountability of the chip resistor 1 on the circuit board 30. Furthermore, the first thickness t1 of the first nickel plating layer 22 is smaller than the second thickness t2 of the first tin plating layer 23, and the third thickness t3 of the second nickel plating layer 27 is smaller than the fourth thickness t4 of the second tin plating layer 28. This prevents peeling of the first plating layer 21 from the first electrode 15 due to stress strain applied to the first nickel plating layer 22 and peeling of the second plating layer 26 from the second electrode 16 due to stress strain applied to the second nickel plating layer 27. This improves the reliability of the chip resistor 1.

[0032] In the chip resistor 1 of this embodiment, the first main surface 11 is a flat surface.

[0033] Because the metal resistor 10 is not bent, even if the gap G between the first electrode 15 and the second electrode 16 is reduced, the accuracy of the resistance value of the chip resistor 1 does not deteriorate. Therefore, the chip resistor 1 can be made smaller. The electrical resistance of the chip resistor 1 can be reduced.

[0034] In the chip resistor 1 of the present embodiment, the first thickness t1 of the first nickel plating layer 22 and the third thickness t3 of the second nickel plating layer 27 are each not less than 4 μm and not more than 10 μm.

[0035] The first thickness t1 of the first nickel plating layer 22 and the third thickness t3 of the second nickel plating layer 27 are each 10 μm or less, which prevents peeling of the first plating layer 21 from the first electrode 15 due to stress strain applied to the first nickel plating layer 22 and peeling of the second plating layer 26 from the second electrode 16 due to stress strain applied to the second nickel plating layer 27. This further improves the reliability of the chip resistor 1. Furthermore, the first thickness t1 of the first nickel plating layer 22 and the third thickness t3 of the second nickel plating layer 27 are each 4 μm or more, which prevents Kirkendall voids from occurring at the first interface between the first electrode 15 and the first nickel plating layer 22 and the second interface between the second electrode 16 and the second nickel plating layer 27. This further improves the reliability of the chip resistor 1.

[0036] In the chip resistor 1 of this embodiment, the metal resistor 10 further has a first end face 13 and a second end face 14 opposite the first end face 13. The first end face 13 and the second end face 14 are connected to the first main surface 11 and the second main surface 12, respectively. In a plan view of the first main surface 11, the first electrode 15 and the first plating layer 21 protrude from the first end face 13, and the second electrode 16 and the second plating layer 26 protrude from the second end face 14.

[0037] Conductive bonding members 34, 35 used to mount the chip resistor 1 on the circuit board 30 are also formed on the protruding portion of the first plating layer 21 from the first end face 13 and on the protruding portion of the second plating layer 26 from the second end face 14. This allows the chip resistor 1 to be fixed to the circuit board 30 more firmly.

[0038] In the chip resistor 1 of this embodiment, the first electrode 15 has a first inner end surface 15b facing the second electrode 16. The second electrode 16 has a second inner end surface 16b facing the first electrode 15. A first protrusion length L1 of the first electrode 15 from the first end surface 13 in a plan view of the first main surface 11 is smaller than a thickness t5 of the first electrode 15 at a first connection portion 15d between the first surface 15a and the first inner end surface 15b. A second protrusion length L2 of the second electrode 16 from the second end surface 14 in a plan view of the first main surface 11 is smaller than a thickness t6 of the second electrode 16 at a second connection portion 16d between the second surface 16a and the second inner end surface 16b.

[0039] Conductive bonding members 34, 35 used to mount the chip resistor 1 on the circuit board 30 are also formed on the protruding portion of the first plating layer 21 from the first end face 13 and on the protruding portion of the second plating layer 26 from the second end face 14. This allows the chip resistor 1 to be fixed to the circuit board 30 more firmly.

[0040] The chip resistor 1 of this embodiment is a shunt resistor.

[0041] Therefore, the shunt resistor can be more easily mounted on the circuit board 30.

[0042] The manufacturing method of the chip resistor 1 of this embodiment includes preparing a clad metal 40 in which a metal resistor plate 41 and a metal plate 42 are laminated, and forming a plating layer 45 on a main surface 42b of the metal plate 42 opposite the metal resistor plate 41 to form a laminate 44 of the clad metal 40 and the plating layer 45. The plating layer 45 includes a nickel plating layer 45a and a tin plating layer 45b. The nickel plating layer 45a is formed between the metal plate 42 and the tin plating layer 45b. The outermost surface of the plating layer 45 is formed of the tin plating layer 45b and has higher solder wettability than the metal plate 42. The thickness T1 of the nickel plating layer 45a is smaller than the thickness T2 of the tin plating layer 45b. The manufacturing method of the chip resistor 1 of this embodiment includes forming grooves 46 in the plating layer 45 and the metal plate 42 by removing a portion of the plating layer 45 and a portion of the metal plate 42 from the laminate 44, and punching the laminate 44 so as to cross the grooves 46. The chip resistor 1 includes a metal resistor 10, a first electrode 15 disposed on the metal resistor 10, a second electrode 16 disposed on the metal resistor 10 and spaced apart from the first electrode 15, a first plating layer 21 formed on the first electrode 15, and a second plating layer 26 formed on the second electrode 16. By punching the laminate 44, the metal resistor 10 is formed from the metal resistor plate 41, the first electrode 15 and the second electrode 16 are formed from the metal plate 42, and the first plating layer 21 and the second plating layer 26 are formed from the plating layer 45.

[0043] The chip resistor 1 obtained by the manufacturing method of the chip resistor 1 according to the present embodiment includes the first plating layer 21 and the second plating layer 26. Therefore, when mounting the chip resistor 1 on the circuit board 30, it is not necessary to form plating layers on the first electrode 15 and the second electrode 16. This improves the mountability of the chip resistor 1 on the circuit board 30. Furthermore, the thickness T1 of the nickel plating layer 45a is smaller than the thickness T2 of the tin plating layer 45b. This prevents peeling of the first plating layer 21 from the first electrode 15 due to stress strain applied to the first nickel plating layer 22, and peeling of the second plating layer 26 from the second electrode 16 due to stress strain applied to the second nickel plating layer 27. This improves the reliability of the chip resistor 1.

[0044] In the method for manufacturing the chip resistor 1 of this embodiment, the main surface (first main surface 11) of the metal resistor 10 opposite to the first electrode 15 and the second electrode 16 is a flat surface.

[0045] Because the metal resistor 10 is not bent, even if the gap G between the first electrode 15 and the second electrode 16 is reduced, the accuracy of the resistance value of the chip resistor 1 does not deteriorate. Therefore, the chip resistor 1 can be made smaller. The electrical resistance of the chip resistor 1 can be reduced.

[0046] In the method for manufacturing the chip resistor 1 of the present embodiment, the thickness T1 of the nickel plating layer 45a is not less than 4 μm and not more than 10 μm.

[0047] Because the thickness T1 of the nickel plating layer 45a is 10 μm or less, peeling of the first plating layer 21 from the first electrode 15 due to stress strain applied to the first nickel plating layer 22 and peeling of the second plating layer 26 from the second electrode 16 due to stress strain applied to the second nickel plating layer 27 can be prevented. This further improves the reliability of the chip resistor 1. In addition, because the thickness T1 of the nickel plating layer 45a is 4 μm or more, this can prevent Kirkendall voids from occurring at the first interface between the first electrode 15 and the first nickel plating layer 22 and the second interface between the second electrode 16 and the second nickel plating layer 27. This further improves the reliability of the chip resistor 1.

[0048] In the manufacturing method of the chip resistor 1 of this embodiment, punching out the laminate 44 means punching out the laminate 44 in the direction from the metal resistor plate 41 toward the metal plate 42. The metal resistor 10 further has a first end face 13 and a second end face 14 opposite the first end face 13. The first end face 13 is one end face of the metal resistor 10 in the direction in which the first electrode 15 and the second electrode 16 are spaced apart from each other. The second end face 14 is the other end face of the metal resistor 10 in the direction in which the first electrode 15 and the second electrode 16 are spaced apart from each other. In a plan view of the metal resistor 10 in the thickness direction, the first electrode 15 and the first plating layer 21 protrude from the first end face 13, and the second electrode 16 and the second plating layer 26 protrude from the second end face 14.

[0049] Conductive bonding members 34, 35 used to mount the chip resistor 1 on the circuit board 30 are also formed on the protruding portion of the first plating layer 21 from the first end face 13 and on the protruding portion of the second plating layer 26 from the second end face 14. This allows the chip resistor 1 to be fixed to the circuit board 30 more firmly.

[0050] Furthermore, by punching the laminate 44 in the direction from the metal resistor plate 41 toward the metal plate 42, the protruding portions of the first electrode 15 and the first plating layer 21 from the first end face 13 and the protruding portions of the second electrode 16 and the second plating layer 26 from the second end face 14 are formed. There is no need to add a process for forming the protruding portions of the first electrode 15 and the first plating layer 21 from the first end face 13 and the protruding portions of the second electrode 16 and the second plating layer 26 from the second end face 14 in addition to the process for punching the laminate 44. The protruding portions of the first electrode 15 and the first plating layer 21 from the first end face 13 and the protruding portions of the second electrode 16 and the second plating layer 26 from the second end face 14 can be formed through a simpler process.

[0051] In the manufacturing method of the chip resistor 1 of this embodiment, the first electrode 15 has a first inner end surface 15b facing the second electrode 16. The second electrode 16 has a second inner end surface 16b facing the first electrode 15. A first protrusion length L1 of the first electrode 15 from the first end surface 13 in a plan view in the thickness direction of the metal resistor 10 is smaller than a thickness t5 of the first electrode 15 at a first connection portion 15d between the first surface 15a of the first electrode 15 and the first inner end surface 15b on the side opposite the metal resistor 10. A second protrusion length L2 of the second electrode 16 from the second end surface 14 in a plan view in the thickness direction of the metal resistor 10 is smaller than a thickness t6 of the second electrode 16 at a second connection portion 16d between the second surface 16a of the second electrode 16 and the second inner end surface 16b on the side opposite the metal resistor 10.

[0052] Conductive bonding members 34, 35 used to mount the chip resistor 1 on the circuit board 30 are also formed on the protruding portion of the first plating layer 21 from the first end face 13 and on the protruding portion of the second plating layer 26 from the second end face 14. This allows the chip resistor 1 to be fixed to the circuit board 30 more firmly.

[0053] In the method for manufacturing the chip resistor 1 of this embodiment, the chip resistor 1 is a shunt resistor.

[0054] Therefore, the shunt resistor can be more easily mounted on the circuit board 30.

[0055] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) A metal resistor; A first electrode; A second electrode; a first plating layer; a second plating layer; the metal resistor has a first main surface and a second main surface opposite to the first main surface, the first electrode is disposed on the second major surface; the second electrode is disposed on the second major surface and is spaced apart from the first electrode; the metal resistor and the first electrode are joined to each other by metallic bonding, the metal resistor and the second electrode are joined to each other by a metallic bond, the first plating layer is disposed on a first surface of the first electrode opposite to the metal resistor, and includes a first nickel plating layer and a first tin plating layer, the first nickel plating layer is disposed between the first electrode and the first tin plating layer, a first outermost surface of the first plating layer is formed by the first tin plating layer, and the first nickel plating layer has higher solder wettability than the first electrode, and a first thickness of the first nickel plating layer is smaller than a second thickness of the first tin plating layer, A chip resistor, wherein the second plating layer is disposed on a second surface of the second electrode opposite the metal resistor and includes a second nickel plating layer and a second tin plating layer, the second nickel plating layer is disposed between the second electrode and the second tin plating layer, a second outermost surface of the second plating layer is formed by the second tin plating layer and has higher solder wettability than the second electrode, and a third thickness of the second nickel plating layer is smaller than a fourth thickness of the second tin plating layer. (Appendix 2) 2. The chip resistor according to claim 1, wherein the first main surface is a flat surface. (Appendix 3) The chip resistor according to claim 1 or 2, wherein the first thickness and the third thickness are each 4 μm or more and 10 μm or less. (Appendix 4) the metal resistor further has a first end face and a second end face opposite to the first end face, the first end face and the second end face being connected to the first main surface and the second main surface, respectively; A chip resistor described in any one of Appendix 1 to Appendix 3, wherein, in a planar view of the first main surface, the first electrode and the first plating layer protrude from the first end face, and the second electrode and the second plating layer protrude from the second end face. (Appendix 5) the first electrode has a first inner end surface facing the second electrode; the second electrode has a second inner end surface facing the first electrode; a first protrusion length of the first electrode from the first end face in the plan view of the first main surface is smaller than a thickness of the first electrode at a first connection portion between the first surface and the first inner end face; A chip resistor as described in Appendix 4, wherein a second protrusion length of the second electrode from the second end face in the planar view of the first main surface is smaller than a thickness of the second electrode at a second connection portion between the second surface and the second inner end face. (Appendix 6) 6. The chip resistor according to claim 1, wherein the chip resistor is a shunt resistor. (Appendix 7) A method for manufacturing a chip resistor, the chip resistor comprising: a metal resistor; a first electrode disposed on the metal resistor; a second electrode disposed on the metal resistor and spaced apart from the first electrode; a first plating layer formed on the first electrode; and a second plating layer formed on the second electrode, the method comprising: preparing a clad metal in which a metal resistor plate and a metal plate are laminated; forming a plating layer on a main surface of the metal plate opposite to the metal resistor plate to form a laminate of the clad metal and the plating layer, the plating layer including a nickel plating layer and a tin plating layer, the nickel plating layer being formed between the metal plate and the tin plating layer, the outermost surface of the plating layer being formed of the tin plating layer and having higher solder wettability than the metal plate, the thickness of the nickel plating layer being smaller than the thickness of the tin plating layer, forming grooves in the plating layer and the metal plate by removing a portion of the plating layer and a portion of the metal plate from the laminate; and punching the laminate across the groove, wherein by punching the laminate, the metal resistor is formed from the metal resistor plate, the first electrode and the second electrode are formed from the metal plate, and the first plating layer and the second plating layer are formed from the plating layer. (Appendix 8) 8. The method for manufacturing a chip resistor according to claim 7, wherein a main surface of the metal resistor opposite to the first electrode and the second electrode is a flat surface. (Appendix 9) 9. The method for manufacturing a chip resistor according to claim 7 or 8, wherein the thickness of the nickel plating layer is 4 μm or more and 10 μm or less. (Appendix 10) punching the laminated body in a direction from the metal resistor plate toward the metal plate; the metal resistor further has a first end face and a second end face opposite to the first end face, the first end face being one end face of the metal resistor in a direction in which the first electrode and the second electrode are spaced apart from each other, and the second end face being the other end face of the metal resistor in the direction in which the first electrode and the second electrode are spaced apart from each other, A method for manufacturing a chip resistor described in any one of Appendix 7 to Appendix 9, wherein, in a planar view from the thickness direction of the metal resistor, the first electrode and the first plating layer protrude from the first end face, and the second electrode and the second plating layer protrude from the second end face. (Appendix 11) the first electrode has a first inner end surface facing the second electrode; the second electrode has a second inner end surface facing the first electrode; a first protrusion length of the first electrode from the first end face in the plan view is smaller than a thickness of the first electrode at a first connection portion between the first inner end face and a first surface of the first electrode opposite to the metal resistor; A method for manufacturing a chip resistor as described in Appendix 10, wherein a second protrusion length of the second electrode from the second end face in the planar view is smaller than a thickness of the second electrode at a second connection portion between a second surface of the second electrode opposite the metal resistor and the second inner end face. (Appendix 12) 12. The method for manufacturing a chip resistor according to claim 7, wherein the chip resistor is a shunt resistor.

[0056] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0057] 1 chip resistor, 10 metal resistor, 11 first main surface, 12 second main surface, 13 first end surface, 14 second end surface, 15 first electrode, 15a first surface, 15b first inner end surface, 15c first outer end surface, 15d first connection portion, 16 second electrode, 16a second surface, 16b second inner end surface, 16c second outer end surface, 16d second connection portion, 21 first plating layer, 21a first outermost surface, 22 first nickel plating layer, 23 first tin plating layer, 26 second plating layer, 26a second outermost surface, 27 second nickel plating layer, 28 second tin plating layer, 30 circuit board, 31 insulating substrate, 32, 33 electrical wiring, 34, 35 conductive bonding member, 40 clad metal, 41 metal resistor plate, 41a, 41b main surface, 42 Metal plate, 42a, 42b main surfaces, 43 mask, 44 laminate, 45 plating layer, 45a nickel plating layer, 45b tin plating layer, 46 groove, 48 cutting tool.

Claims

1. A metal resistor; A first electrode; A second electrode; a first plating layer; a second plating layer; the metal resistor has a first main surface and a second main surface opposite to the first main surface, the first electrode is disposed on the second major surface; the second electrode is disposed on the second major surface and is spaced apart from the first electrode; the metal resistor and the first electrode are joined to each other by metallic bonding, the metal resistor and the second electrode are joined to each other by metallic bonding, the first plating layer is disposed on a first surface of the first electrode opposite to the metal resistor, and includes a first nickel plating layer and a first tin plating layer, the first nickel plating layer is disposed between the first electrode and the first tin plating layer, a first outermost surface of the first plating layer is formed by the first tin plating layer, and the first plating layer has higher solder wettability than the first electrode, and a first thickness of the first nickel plating layer is smaller than a second thickness of the first tin plating layer, The second plating layer is disposed on a second surface of the second electrode opposite the metal resistor, and includes a second nickel plating layer and a second tin plating layer, the second nickel plating layer is disposed between the second electrode and the second tin plating layer, a second outermost surface of the second plating layer is formed by the second tin plating layer and has higher solder wettability than the second electrode, and a third thickness of the second nickel plating layer is smaller than a fourth thickness of the second tin plating layer.

2. The chip resistor according to claim 1 , wherein the first main surface is a flat surface.

3. 3. The chip resistor according to claim 1, wherein the first thickness and the third thickness are each 4 μm or more and 10 μm or less.

4. the metal resistor further has a first end face and a second end face opposite to the first end face, the first end face and the second end face being connected to the first main surface and the second main surface, respectively; A chip resistor as described in claim 1 or claim 2, wherein, in a planar view of the first main surface, the first electrode and the first plating layer protrude from the first end face, and the second electrode and the second plating layer protrude from the second end face.

5. the first electrode has a first inner end surface facing the second electrode; the second electrode has a second inner end surface facing the first electrode; a first protrusion length of the first electrode from the first end face in the plan view of the first main surface is smaller than a thickness of the first electrode at a first connection portion between the first surface and the first inner end face; The chip resistor of claim 4, wherein a second protrusion length of the second electrode from the second end face in the planar view of the first main surface is smaller than a thickness of the second electrode at a second connection portion between the second surface and the second inner end face.

6. The chip resistor according to claim 1 , wherein the chip resistor is a shunt resistor.

7. A method for manufacturing a chip resistor, the chip resistor comprising: a metal resistor; a first electrode disposed on the metal resistor; a second electrode disposed on the metal resistor and spaced apart from the first electrode; a first plating layer formed on the first electrode; and a second plating layer formed on the second electrode, the method comprising: preparing a clad metal in which a metal resistor plate and a metal plate are laminated; forming a plating layer on a main surface of the metal plate opposite to the metal resistor plate to form a laminate of the clad metal and the plating layer, the plating layer including a nickel plating layer and a tin plating layer, the nickel plating layer being formed between the metal plate and the tin plating layer, the outermost surface of the plating layer being formed of the tin plating layer and having higher solder wettability than the metal plate, the thickness of the nickel plating layer being smaller than the thickness of the tin plating layer, forming grooves in the plating layer and the metal plate by removing a portion of the plating layer and a portion of the metal plate from the laminate; and punching the laminate across the groove, wherein by punching the laminate, the metal resistor is formed from the metal resistor plate, the first electrode and the second electrode are formed from the metal plate, and the first plating layer and the second plating layer are formed from the plating layer.

8. The method for manufacturing a chip resistor according to claim 7 , wherein a main surface of the metal resistor opposite to the first electrode and the second electrode is flat.

9. 9. The method for manufacturing a chip resistor according to claim 7, wherein the thickness of the nickel plating layer is 4 μm or more and 10 μm or less.

10. punching the laminated body in a direction from the metal resistor plate toward the metal plate; the metal resistor further has a first end face and a second end face opposite to the first end face, the first end face being one end face of the metal resistor in a direction in which the first electrode and the second electrode are spaced apart from each other, and the second end face being the other end face of the metal resistor in the direction in which the first electrode and the second electrode are spaced apart from each other, 9. A method for manufacturing a chip resistor as described in claim 7 or claim 8, wherein, when viewed in a planar view from the thickness direction of the metal resistor, the first electrode and the first plating layer protrude from the first end face, and the second electrode and the second plating layer protrude from the second end face.

11. the first electrode has a first inner end surface facing the second electrode; the second electrode has a second inner end surface facing the first electrode; a first protrusion length of the first electrode from the first end face in the plan view is smaller than a thickness of the first electrode at a first connection portion between a first surface of the first electrode opposite to the metal resistor and the first inner end face; 11. A method for manufacturing a chip resistor as described in claim 10, wherein a second protrusion length of the second electrode from the second end face in the planar view is smaller than a thickness of the second electrode at a second connection portion between a second surface of the second electrode opposite the metal resistor and the second inner end face.

12. The method for manufacturing a chip resistor according to claim 7 or 8, wherein the chip resistor is a shunt resistor.

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