Manufacturing method of FCBGA carrier plate salient points

Abstract

The invention relates to the technical field of IC (integrated circuit) packaging carrier plates, in particular to an FCBGA carrier plate bump manufacturing method, which comprises the following steps of: printing developing ink on a pattern plate in a solder resist manner, pasting an anti-plating PET (polyethylene terephthalate) film, punching copper cylinder holes in preset positions of the pattern plate by using a laser punching technology, filling the copper cylinder holes by using electroplating to form copper cylinders, and forming bumps on the pattern plate. And tinning the top of the copper column in a chemical tinning mode, forming Bump on the exposed part of the top of the pattern plate, and tearing off the anti-plating PET film to finish processing. Solder resist exposure and solder resist development procedures in a traditional solder ball implanting process are avoided, and the problem that the opening caliber is larger than 50 microns and the distance is larger than 90 microns due to the solder resist ink characteristic and the solder ball characteristic is avoided.

Description

Technical Field

[0001] This application relates to the field of IC packaging substrate technology, specifically to a method for fabricating bumps on an FCBGA substrate. Background Technology

[0002] With the increase in the number of chip I / Os, IC substrates, which serve as chip carriers, are also developing towards high density and refinement. In particular, FCBGA substrates, which are concentrated in high-end, high-computing-power, and high-transmission demand scenarios, require smaller diameters and smaller bump spacing for the bumps that connect to the chips.

[0003] The existing method for manufacturing bumps is as follows: First, solder resist ink is printed on a graphic board, then light exposure and development are performed to expose the solder resist opening pattern, and then a solder ball implantation process is used to form a bump.

[0004] Due to the characteristics of solder resist ink, the smallest solder resist opening after exposure and development can only be 50um or more, and the spacing can only be 90um or more. At the same time, due to the limitations of solder ball manufacturing process, the smallest solder ball diameter can only be 50um or more. Existing processes cannot meet the refined requirements of chip I / O for increased connection to the carrier board bump. Summary of the Invention

[0005] This application provides a method for fabricating bumps on an FCBGA carrier board to solve or partially solve the problems mentioned in the background art.

[0006] This application provides a method for fabricating bumps on an FCBGA carrier board, including the following steps: S1: Solder resist printing on the graphic board, followed by coating with developer ink; S2: Apply an anti-plating PET film over the developing ink layer; S3: Using a target alignment method, laser drilling technology is used to drill copper pillar holes at preset positions on the graphic board; S4: Electroplating is used to fill the holes in the copper pillar to form a copper pillar; S5: Use chemical tin plating to tin the top of the copper pillar to form a bump on the exposed part at the top of the graphic board; S6: Use a film peeling machine to peel off the anti-plating PET film to complete the processing.

[0007] Preferably, in step S1, the pattern board is an FCBGA pattern board that uses a glass substrate as the base material to complete the basic circuit layer fabrication.

[0008] Preferably, in step S1, the substrate is printed using a roller coating process to apply the developing ink to the substrate surface, ensuring that the ink thickness uniformity error is ≤±3μm. After roller coating, the substrate is pre-baked in an oven to make the ink reach a touch-dry state.

[0009] Preferably, the developing ink uses a halogen-free, high-heat-resistant resin as a base, and adds photosensitizers, ultrafine fillers, flame retardants, and adhesion promoters.

[0010] Preferably, in step S2, the surface of the developing ink layer is first subjected to plasma treatment to remove surface oil and oxide layer, improve the adhesion between the PET film and the developing ink, and then a vacuum laminating machine is used to laminate the film under preset temperature and pressure conditions. The anti-plating PET film must completely cover the ink layer, with the edge extending 5-10mm beyond the effective area of ​​the graphic board.

[0011] Preferably, in step S3, a positioning system is formed by selecting a bottom-layer graphic positioning target and a CCD vision grasping target. Ultraviolet picosecond laser is used to process interlayer blind holes. After drilling, a de-adhesive plasma device is used to remove the PET film and developing ink that adhered to the hole wall and bottom after laser drilling, ensuring that the copper pads at the bottom of the hole are completely exposed.

[0012] Preferably, in step S4, chemical copper plating and electroplating are used, and the height of the electroplated copper pillar is higher than the preset height of the surface of the developing ink layer; The copper sulfate concentration is 200-250 g / L, the sulfuric acid concentration is 30-60 g / L, and the height of the electroplated copper pillar is 5±3 μm higher than the surface of the developing ink layer.

[0013] Preferably, the pattern board is subjected to micro-etching treatment after electroplating, using a mixture of 5% sulfuric acid and 0.5% hydrogen peroxide at a temperature of 30°C for 50-60 seconds, with an etching depth of 1µm, to ensure the removal of chemical copper plating on the PET.

[0014] Preferably, in step S5, the surface of the copper pillar is first degreased, then activated with sulfuric acid to remove the oxide film and electroplating residue on the surface of the copper pillar, the graphic board is immersed in tin plating solution for tin plating, and after tin plating, it is cleaned with deionized water and dried in an oven.

[0015] Preferably, the bump formed in steps S4 and S5 includes an exposed copper pillar top and a tin plating layer.

[0016] Compared with the prior art, the beneficial effects of this application are as follows: This application utilizes a method of applying PET film, laser drilling, electroplating, and chemical tin plating to fabricate bumps. This avoids the solder resist exposure and development processes in traditional solder ball processes, and avoids the problems of bump diameters exceeding 50µm and spacing exceeding 90µm caused by the characteristics of solder resist ink and the solder balls themselves. The bump diameter and hole spacing are only limited by the positioning accuracy of the laser drilling equipment, without needing to consider the stability of ink bridges. This method can meet the requirements for bump fabrication with a diameter of less than 50µm and a spacing of less than 90µm. Attached Figure Description

[0017] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0018] Fig. 1 This is a schematic diagram of the method flow of this application. Fig. 2 This is a schematic diagram illustrating the implementation of this application. Detailed Implementation

[0019] The specification and claims use certain terms to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on differences in function. The term "comprising" throughout the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to." "Approximately" means that within an acceptable margin of error, those skilled in the art can solve the technical problem and substantially achieve the technical effect within a certain margin of error.

[0020] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "horizontal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0022] Example 1 With the increase in the number of chip I / Os, IC substrates, which serve as chip carriers, are also developing towards high density and refinement. In particular, FCBGA substrates, which are concentrated in high-end, high-computing-power, and high-transmission demand scenarios, will develop the bumps that connect to the chip to a diameter of less than 50um and a spacing of less than 90um.

[0023] The existing method for manufacturing bumps is as follows: First, solder resist ink is printed on a graphic board, then light exposure and development are performed to expose the solder resist opening pattern, and then a solder ball implantation process is used to form a bump.

[0024] Specifically, in the solder resist process, the surface of the glass substrate (graphic board) is first roughened to increase the adhesion between the ink and the substrate. The ink is then uniformly coated onto the glass substrate using a vacuum laminator. In the solder resist exposure process, the ink that needs to be retained is cured by UV irradiation. In the solder resist development process, sodium carbonate solution is used to dissolve and remove the uncured ink. After surface treatment, solder balls are implanted on the surface of the glass substrate, thus finally completing the production of the IC carrier board product.

[0025] Solder resist developing ink is composed of resin, photosensitizer, filler, and other components. The size of these particles is usually in the range of several micrometers to tens of micrometers. When exposed to light, the light will diffract and scatter. When the target opening is less than 50um, the particles cannot be precisely avoided, which will lead to blurred opening edges and bridging. Development is to dissolve the unexposed ink area with chemical agents. The ink has limited uniformity of dissolution rate and etch resistance. When the opening is too small, the agent is difficult to penetrate evenly, which can easily lead to residue or over-etching, resulting in uncontrolled opening size. At the same time, the small opening increases the aspect ratio of the ink sidewalls, making the sidewalls prone to collapse and peeling after development. When the spacing is less than 90um, the width of the ink bridge between adjacent openings is insufficient and cannot withstand the mechanical stress of subsequent processes such as balling.

[0026] In summary, due to the characteristics of solder resist ink, the smallest solder resist opening after exposure and development can only be 50µm or larger, with a spacing of 90µm or larger. At the same time, limited by the solder ball manufacturing process, the smallest solder ball diameter can only be 50µm or larger. Existing processes cannot meet the development needs of chip I / O increasing the connection to the carrier board, requiring bumps with a diameter of less than 50µm and a spacing of less than 90µm.

[0027] like Figs. 1-2 As shown, this application provides a method for fabricating bumps on an FCBGA carrier board, which specifically includes the following steps: S1: Solder resist printing on the graphic board, followed by coating with developer ink; S2: Apply an anti-plating PET film over the developing ink layer; S3: Using a target alignment method, laser drilling technology is used to drill copper pillar holes at preset positions on the graphic board; S4: Electroplating is used to fill the holes in the copper pillar to form a copper pillar; S5: Use chemical tin plating to tin the top of the copper pillar to form a bump on the exposed part at the top of the graphic board; S6: Use a film peeling machine to peel off the anti-plating PET film to complete the processing.

[0028] Specifically, in step S1, the pattern board is an FCBGA pattern board that uses a glass substrate as the base material to complete the basic circuit layer preparation such as line etching and pupil fabrication.

[0029] Specifically, in step S1, a roller coating process is used to print on the substrate, so that the developing ink is applied to the surface of the substrate, ensuring that the uniformity error of the ink thickness is ≤±3μm. After roller coating, the substrate is pre-baked in an oven to make the ink reach a touch-dry state.

[0030] Furthermore, the developing ink of this application uses halogen-free high heat-resistant resin (such as modified epoxy resin or cyanate ester resin) as a base, and adds photosensitizer (used to assist in subsequent process positioning, eliminating the need for development and dissolution), ultrafine filler (particle size 1-3μm, such as silica or alumina, to improve ink hardness and laser ablation resistance), flame retardant (such as phosphorus-based flame retardant), and adhesion promoter (such as silane coupling agent), with viscosity controlled at 5000-8000 mPa. s (25℃).

[0031] Traditional developing inks require light exposure and the addition of a high proportion of soluble photosensitive resins. However, the developing ink of this application does not require dissolution and focuses more on hardness, heat resistance and laser compatibility. The filler particle size is smaller (the filler particle size of traditional inks is 5-10μm), avoiding the generation of large particle residues during laser drilling.

[0032] Specifically, in step S2, the surface of the developing ink layer is first subjected to plasma treatment to remove surface oil and oxide layers, thereby improving the adhesion between the PET film and the developing ink. A vacuum laminating machine is then used to laminate the film under preset temperature and pressure conditions (e.g., temperature 60-80℃, pressure 0.3-0.5 MPa) to ensure that there are no bubbles or wrinkles and to prevent film displacement in subsequent processes. Furthermore, the anti-plating PET film must completely cover the ink layer, with its edges extending 5-10mm beyond the effective area of ​​the graphic board.

[0033] Furthermore, the anti-plating PET film is made of a high-temperature resistant PET film with a thickness of 25-50μm as the substrate, and coated with an anti-plating coating (such as a polyimide modified coating or a fluorocarbon coating) with a thickness of 3-5μm. The coating must have acid resistance (resistant to 20% sulfuric acid and 5% hydrochloric acid, and no corrosion after immersion at 60℃ for 1 hour), low adhesion (can be peeled off without residue) and high flatness (surface roughness Ra≤0.1μm).

[0034] This application uses an anti-plating PET film to protect the non-perforated areas of the developing ink layer, preventing copper ion deposition during subsequent copper electroplating and preventing the chemical tin plating solution from corroding the developing ink surface.

[0035] Specifically, in step S3, a positioning system is formed by selecting a bottom-layer graphic positioning target and a CCD vision grasping target. Ultraviolet picosecond laser is used to process interlayer blind holes. After drilling, a de-adhesive plasma device is used to remove the PET film and developing ink that adhered to the hole wall and bottom after laser drilling, ensuring that the copper pads at the bottom of the hole are completely exposed.

[0036] This application uses laser drilling to avoid the problem of traditional light-exposed development being limited by ink resolution. It can precisely control the hole diameter to below 30μm, and the hole spacing is only limited by the positioning accuracy of the equipment, without having to consider the stability of ink bridges.

[0037] Specifically, chemical copper plating and electroplating are used, with the height of the electroplated copper pillars being higher than the preset height of the developing ink layer surface; The copper sulfate concentration is 200-250 g / L, the sulfuric acid concentration is 30-60 g / L, and the height of the electroplated copper pillar is 5±3 μm higher than the surface of the developing ink layer.

[0038] Preferably, the pattern board is subjected to micro-etching treatment after electroplating, using a mixture of 5% sulfuric acid and 0.5% hydrogen peroxide at a temperature of 30°C for 50-60 seconds, with an etching depth of 1µm, to ensure the removal of chemical copper plating on the PET.

[0039] Specifically, in step S5, the surface of the copper pillar is first degreased, then activated with sulfuric acid to remove the oxide film and electroplating residue on the surface of the copper pillar, the graphic board is immersed in tin plating solution for tin plating, and after tin plating, it is cleaned with deionized water and dried in an oven.

[0040] Furthermore, an alkaline degreasing solution is used for degreasing, and 10% sulfuric acid is used for sulfuric acid activation.

[0041] Specifically, in step S6, the anti-plating PET film is slowly peeled off along the edge of the graphic board. After peeling off the film, the graphic board is cleaned as a whole (ultrasound + deionized water) to remove any possible film debris. Finally, it is baked for a preset time to cure the developing ink layer and the tin plating layer, thereby improving the overall stability.

[0042] The bumps formed in steps S4 and S5 of this application include the exposed copper pillar top and the tin plating layer. Compared with the traditional tin ball process, the bonding force between the tin layer and the copper pillar and the conductor performance are superior.

[0043] This application, through steps S1 to S5, avoids the solder resist exposure and development processes in the traditional solder ball implantation process, thus avoiding the problems of large bump diameter and spacing caused by the characteristics of solder resist ink and solder balls.

[0044] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.

Claims

1. A method for fabricating bumps on an FCBGA carrier board, characterized in that, Includes the following steps: S1: Solder resist printing on the graphic board, followed by coating with developer ink; S2: Apply an anti-plating PET film over the developing ink layer; S3: Using a target alignment method, laser drilling technology is used to drill copper pillar holes at preset positions on the graphic board; S4: Electroplating is used to fill the holes in the copper pillar to form a copper pillar; S5: Use chemical tin plating to tin the top of the copper pillar to form a bump on the exposed part at the top of the graphic board; S6: Use a film peeling machine to peel off the anti-plating PET film to complete the processing.

2. The method for fabricating bumps on an FCBGA carrier board according to claim 1, characterized in that: In step S1, the pattern board is an FCBGA pattern board that uses a glass substrate as the base material to complete the basic circuit layer fabrication.

3. The method for fabricating bumps on an FCBGA carrier board according to claim 1, characterized in that: In step S1, the substrate is printed using a roller coating process to apply the developing ink to the substrate surface, ensuring that the ink thickness uniformity error is ≤±3μm. After roller coating, the substrate is pre-baked in an oven to make the ink reach a touch-dry state.

4. A method for fabricating FCBGA carrier board bumps according to claim 1 or any of claims 3, characterized in that: The developing ink uses halogen-free high heat-resistant resin as a base, and adds photosensitizers, ultrafine fillers, flame retardants and adhesion promoters.

5. The method for fabricating bumps on an FCBGA carrier board according to claim 1, characterized in that: In step S2, the surface of the developing ink layer is first subjected to plasma treatment to remove surface oil and oxide layer, and improve the adhesion between the PET film and the developing ink. A vacuum laminating machine is used to laminate the film under preset temperature and pressure conditions. The anti-plating PET film must completely cover the ink layer, with the edge extending 5-10mm beyond the effective area of ​​the graphic board.

6. The method for fabricating bumps on an FCBGA carrier board according to claim 1, characterized in that: In step S3, a positioning system is formed by selecting a bottom-layer graphic positioning target and a CCD vision target. Ultraviolet picosecond laser is used to process interlayer blind holes. After drilling, a de-adhesive plasma device is used to remove the PET film and developing ink that adhered to the hole wall and bottom after laser drilling, ensuring that the copper pads at the bottom of the hole are completely exposed.

7. The method for fabricating bumps on an FCBGA carrier board according to claim 1, characterized in that: In step S4, chemical copper plating and electroplating are used, and the height of the electroplated copper pillar is higher than the preset height of the developing ink layer surface. The copper sulfate concentration is 200-250 g / L, the sulfuric acid concentration is 30-60 g / L, and the height of the electroplated copper pillar is 5±3 μm higher than the surface of the developing ink layer.

8. The method for fabricating bumps on an FCBGA carrier board according to claim 7, characterized in that: After electroplating, the graphic board is micro-etched using a mixture of 5% sulfuric acid and 0.5% hydrogen peroxide at a temperature of 30°C for 50-60 seconds, with an etching depth of 1µm, to ensure the removal of chemical copper plating on the PET.

9. The method for fabricating bumps on an FCBGA carrier board according to claim 1, characterized in that: In step S5, the surface of the copper pillar is first degreased, then activated with sulfuric acid to remove the oxide film and electroplating residue on the surface of the copper pillar. The graphic board is then immersed in tin plating solution for tin plating. After tin plating, it is cleaned with deionized water and dried in an oven.

10. The method for fabricating bumps on an FCBGA carrier board according to claim 1, characterized in that: The bumps formed in steps S4 and S5 include the exposed top of the copper pillar and the tin plating layer.

Images