Crystal, stacked structure, semiconductor device, electronic device, and system

Abstract

To provide a crystal and a laminated structure having excellent electric characteristics useful for a semiconductor device or the like.SOLUTION: A crystal containing germanium dioxide as a main component, having a sheet resistance of 300 Ω / square or less, having a film shape, being a single crystal, being a semiconductor, containing a dopant, and having a rutile-type crystal structure in which the dopant contains a group 15 element in the periodic table is used and applied to, for example, a semiconductor device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a crystal and a layered structure useful for semiconductor devices. [Background technology]

[0002] In recent years, rutile-structure germanium dioxide (r-GeO2) has attracted attention as a promising ultra-wide bandgap (UWBG) semiconductor for future power electronics devices. r-GeO2 has a bandgap of 4.68 eV, making it possible to realize n-type and p-type semiconductors, and it can be fabricated inexpensively, making it a promising candidate for next-generation semiconductor devices.

[0003] Non-Patent Document 1, Patent Document 1, Patent Document 2, and Patent Document 3 discuss a layered structure in which an r-GeO2 crystalline film is stacked on an r-TiO2 (001) substrate. However, Non-Patent Document 2 was submitted as an erratum (Non-Patent Document 2) after the peer review of Non-Patent Document 1. It was found that the crystal grains (abnormal grains) described in Non-Patent Document 1 and Patent Document 1 were rutile germanium dioxide crystals, and the remaining portions were amorphous. In other words, only the amorphous phase was formed in the majority of the structure, and even if a crystalline phase was formed, crystal grains were only formed in a small area. Therefore, a method for producing a crystalline film with excellent crystallinity that can be electrically controlled has been eagerly awaited. Furthermore, Non-Patent Document 3 reports that an alloy thin film of r-(Ge,Sn)O2 was prepared by mixing easily crystallizable tin dioxide (r-SnO2) with r-GeO2, and n-type conductivity was confirmed. However, because the band gap of r-SnO2 is 3.7 eV, which is smaller than that of r-GeO2, the properties of r-GeO2 could not be utilized in an r-(Ge,Sn)O2 alloy thin film, and it was also difficult to control the composition of Ge and Sn. Therefore, a method to obtain conductivity in a single-phase r-GeO2 thin film was eagerly awaited. Also, Non-Patent Document 4 describes the fabrication of a vertical SBD element by laminating an undoped r-GeO2 thin film on a conductive r-TiO2 substrate using an r-SnGeO2 mixed crystal thin film with a composition gradient as a buffer layer, and was published after the first filing date of the present application. However, in the semiconductor device of Non-Patent Document 4, the r-Sn x Ge 1-x It is difficult to control the composition of the O2 thin film, so we developed r-Sn x Ge 1-x It was even more difficult to control the electrical properties of the O2 thin film. x Ge 1-x Non-Patent Document 4 describes a semiconductor device using a r-GeO2 thin film fabricated on an O2 mixed crystal thin film, but the ON / OFF ratio is in the double digits, and it is difficult to increase the area, so it is not yet suitable for industrial use. Therefore, a method has been desired that allows electrical control and enables the production of excellent single crystal films that can be used industrially. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] H. Takane, K. Kaneko., “Establishment of a growth route of crystallized rutile GeO2 thin film (≧ 1 mm / h) and its structural properties”, Applied Physics Letters Vol.119, pp.062104(1-6) (2021). [Non-patent document 2] H.Takane, K. Kaneko., Erratum: “Establishment of a growth route of crystallized rutile GeO2 thin film (≧1 μm / h) and its structural properties”, Applied Physics Letters Vol.120, 099903(1-3) (2022). [Non-patent document 3] H. Takane,et,al., “Band-gap engineering of rutile-structured SnO2-GeO2-SiO2 alloy system”, PHYSICAL REVIEW MATERIALS 6, 084604 (2022). [Non-patent document 4] Kazutaka Kanegae et al., “Nirutile GeO2 vertical Schottky barrier diode on Nb-doped TiO2substrate using Sb-doped graded Gey Sn1-y O2 buffer layers”, Appl. Phys. Express, (2025). [Patent documents]

[0005] [Patent Document 1] International Publication No. 2023 / 008452 [Patent Document 2] International Publication No. 2023 / 008453 [Patent Document 3] International Publication No. 2023 / 008454 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a crystal and a layered structure having excellent electrical properties that are useful for semiconductor devices and the like. [Means for solving the problem]

[0007] As a result of intensive research to achieve the above-mentioned object, the inventors have newly developed a mist CVD apparatus using a guide partition, and by using the mist CVD apparatus using the guide partition, have succeeded in creating a crystal containing germanium dioxide as its main component and having a sheet resistance of 300 Ω / □ or less. They have found that the obtained crystal can be easily produced at low cost, has excellent crystallinity and excellent electrical properties, and is useful for semiconductor devices, etc., and have discovered that such a crystal can solve all of the above-mentioned conventional problems in one fell swoop. Furthermore, after obtaining the above findings, the present inventors conducted further studies and completed the present invention.

[0008] That is, the present invention relates to the following inventions. [1] A crystal containing germanium dioxide as its main component, characterized in that the sheet resistance is 300 Ω / □ or less. [2] The crystal according to [1] above, which is in the form of a membrane. [3] The crystal according to [1] above, which is a single crystal film. [4] The crystal according to [1] above, which contains a dopant. [5] The crystal according to [4] above, wherein the dopant contains an element of Group 15 of the periodic table. [6] The crystal according to [1] above, which is a semiconductor. [7] The crystal according to [1] above, having a rutile crystal structure. [8] A laminated structure in which a crystalline film is laminated on a crystalline substrate directly or via another layer, the crystalline film being a crystalline film containing germanium dioxide as its main component, and the sheet resistance of the crystalline film being 300 Ω / □ or less. [9] The layered structure according to [8], wherein the crystalline substrate has a rutile crystalline structure.

[10] The layered structure according to [8], wherein the crystalline film has a rutile crystal structure.

[11] A semiconductor device including a crystal or a laminated structure, wherein the crystal is the crystal described in [1] above, and the laminated structure is the laminated structure described in [8] above.

[12] The semiconductor device according to

[11] , wherein the crystal or the crystal film of the laminated structure is in contact with an ohmic electrode to form an ohmic contact.

[13] The semiconductor device according to

[11] , which is a power device.

[14] The semiconductor device according to

[11] , wherein the ON / OFF ratio is 1,000,000 or more.

[15] The ON current is 10mA / cm when a forward voltage of 10V is applied. 2 The semiconductor device according to

[11] above.

[16] The semiconductor device according to

[11] , which is a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal semiconductor field effect transistor (MESFET), a static induction transistor (SIT), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), or a light emitting diode (LED).

[17] An electronic device including a semiconductor device, characterized in that the semiconductor device is the semiconductor device described in

[11] above.

[18] A system including an electronic device, characterized in that the electronic device is the electronic device described in

[17] above. [Effects of the Invention]

[0009] The crystal and layered structure of the present invention are useful for semiconductor devices and the like, and exhibit excellent electrical properties. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic diagram illustrating an example of a film-forming apparatus that can be suitably used in the present invention. [Figure 2] 1 is a diagram schematically illustrating an atomization device preferably used in the present invention. [Figure 3] 1 is a schematic cross-sectional side view of an atomization device preferably used in the present invention. FIG. [Figure 4] 1 is a diagram schematically illustrating a preferred example of a Schottky barrier diode (SBD) according to the present invention. [Figure 5] 1 is a diagram schematically illustrating a preferred example of a high electron mobility transistor (HEMT) of the present invention. [Figure 6] FIG. 1 is a diagram schematically illustrating a preferred example of a metal oxide semiconductor field effect transistor (MOSFET) of the present invention. [Figure 7] 1 is a diagram schematically illustrating a preferred example of a junction field effect transistor (JFET) of the present invention. [Figure 8] 1 is a diagram schematically illustrating a preferred example of an insulated gate bipolar transistor (IGBT) according to the present invention. [Figure 9] 1 is a diagram schematically illustrating a preferred example of a light-emitting element (LED) of the present invention. [Figure 10] 1 is a diagram schematically illustrating a preferred example of a junction barrier Schottky diode (JBS) of the present invention. [Figure 11] 1 is a diagram schematically illustrating a preferred example of a metal semiconductor field effect transistor (MESFET) of the present invention. [Figure 12] FIG. 1 is a diagram schematically illustrating a preferred example of a static induction transistor (SIT) of the present invention. [Figure 13] 13 is a schematic diagram for explaining a part of the manufacturing process of the SIT of FIG. 12. [Figure 14] FIG. 1 is a diagram showing the 2θ / ω results of XRD diffraction in Example 1. [Figure 15] FIG. 1 is a diagram showing the results of an ω scan in the XRD diffraction results in Example 1. [Figure 16] FIG. 2 is a diagram showing an AFM image in Example 1. [Figure 17] FIG. 2 is a diagram showing an SEM image in Example 1. [Figure 18] FIG. 1 is a diagram showing an EDS image in Example 1. [Figure 19] 2 is a diagram schematically showing a sample in which an ohmic electrode is formed on a crystal film in Example 1. FIG. [Figure 20] FIG. 20 is a diagram showing the results of ohmic measurement using FIG. 19. [Figure 21] FIG. 10 is a diagram showing the 2θ / ω results of XRD diffraction in Example 2. [Figure 22] FIG. 10 is a diagram showing the 2θ / ω results of XRD diffraction in Example 3. [Figure 23] FIG. 10 is a diagram showing the 2θ / ω results of XRD diffraction in the formation of a buffer layer in Example 4, 1. [Figure 24] FIG. 10 is a diagram showing the results of an ω scan in the XRD diffraction results for the formation of the buffer layer in Example 4, 1. [Figure 25] FIG. 10 is a diagram showing the results of 2θ / ω in the XRD diffraction results in the formation of an n-type semiconductor layer in Example 4. [Figure 26] 2. A diagram showing the results of an ω scan in the XRD diffraction results for the formation of an n-type semiconductor layer in Example 4. [Figure 27] FIG. 1 is a schematic cross-sectional view of an SBD having a completely vertical structure. [Figure 28] 2. A diagram showing a surface image of a sample in Example 4 in which an electrode is formed on a single crystal film made of an n-type semiconductor layer. [Figure 29] 1 is a diagram showing the results of IV measurement in Example 4, in which the vertical axis represents current (A / cm 2 ) and the horizontal axis represents voltage (V). [Figure 30] 10 is a table showing the relationship between carrier concentration and depth derived from the results of CV measurement in Example 4, where the vertical axis represents carrier concentration and the horizontal axis represents depth. [Figure 31] FIG. 10 is a schematic cross-sectional view of a sample prepared in Example 5. [Figure 32] FIG. 10 is a diagram showing the results of evaluation of ohmic characteristics by IV measurement in Example 5. [Figure 33] FIG. 10 is a diagram showing the results of an ω scan in the XRD diffraction results in Example 3. [Figure 34] FIG. 10 is a diagram schematically showing a sample in which an ohmic electrode is formed on a crystal film in Example 3. [Figure 35] FIG. 35 shows the results of ohmic measurement using FIG. 34. DETAILED DESCRIPTION OF THE INVENTION

[0011] The crystal of the present invention is characterized by being a crystal containing germanium dioxide as a main component and having a sheet resistance of 300 Ω / □ or less. The laminated structure of the present invention is characterized by a laminated structure in which a crystalline film is laminated on a crystalline substrate directly or via another layer, the crystalline film containing germanium dioxide as a main component, and the sheet resistance of the crystalline film being 300 Ω / □ or less. In the present invention, the sheet resistance is preferably 200 Ω / □ or less. In this specification, "film" can be read as "layer." A "laminated structure" is a structure containing one or more crystalline layers, and may also contain layers other than crystalline layers (e.g., amorphous layers). The crystalline film is preferably a single crystalline layer, but may also be a polycrystalline layer.

[0012] In the present invention, the crystal is preferably in the form of a film, and is preferably a single crystal. 2 It is preferable that the crystal has an area of ​​at least 1000 nm. It is also preferable that the crystal is a semiconductor. Within these preferable ranges, the crystal can have a better breakdown voltage and can obtain better electrical properties.

[0013] In the present invention, the term "major component" refers to a content of crystals containing germanium dioxide in the crystals that is 50% or more in terms of composition ratio in the crystals. In an embodiment of the present invention, the content of germanium dioxide in the crystals is preferably 70% or more, more preferably 90% or more, in terms of composition ratio in the crystals. It is also preferable that the crystals contain germanium dioxide as a major component. This preferred range results in a better interface, improved electrical properties, and improved semiconductor properties. The crystals may also contain metals other than germanium dioxide. Examples of such metals include one or more metals selected from Group 14 metals of the periodic table other than germanium (e.g., tin or silicon) and Group 4 metals of the periodic table (e.g., titanium, zirconia, or hafnium). The composition ratio of germanium among the metal elements in the crystals is preferably 0.5 or more. By setting the atomic ratio of germanium in this preferred range, a crystalline film with better semiconductor properties can be realized. Furthermore, the crystal is not particularly limited in terms of crystal structure, and may be a tetragonal rutile crystal structure, a trigonal α-quartz structure, an orthorhombic CaCl2 crystal structure, an α-PbO2 crystal structure, or a tetragonal pyrite crystal structure. In the present invention, however, a tetragonal rutile structure is preferred. By setting the atomic ratio in this preferred range, better semiconductor properties can be achieved.

[0014] The above-described preferred crystal or laminated structure can be more easily obtained, for example, by using a film-forming apparatus as shown in FIG. 1. The thickness of the crystal film is not particularly limited as long as it does not impede the object of the present invention, but in the present invention, it is preferably 0.1 μm or more. Furthermore, the surface roughness (RMS) of the crystal film is preferably 10 nm or less. By achieving such a preferred thickness or surface roughness, when the laminated structure is applied to a semiconductor device, it is possible to impart superior electrical properties, such as voltage resistance, to the semiconductor device. The surface roughness (RMS) refers to a value calculated in accordance with JIS B0601 using the results of surface profile measurement of a 10 μm square area using an atomic force microscope (AFM).

[0015] The crystal of the present invention is not particularly limited as long as it does not impede the object of the present invention, but preferably contains a dopant. The dopant is not particularly limited as long as it does not impede the object of the present invention, but preferably contains a Group 15 element of the periodic table. Examples of the Group 15 element of the periodic table include nitrogen, phosphorus, arsenic, antimony, and bismuth. Within such a preferred range, better electrical properties can be obtained and the crystal can be more easily produced.

[0016] Furthermore, the crystal substrate is not particularly limited as long as it does not impede the objectives of the present invention. It may be a known substrate, such as an insulating substrate, a conductive substrate, or a semiconductor substrate. It may be a single crystal substrate or a polycrystalline substrate. The crystal substrate may also have a metal film on its surface. When the crystal substrate is a conductive substrate, a vertical device can be fabricated without removing the substrate. The crystal structure of the crystal substrate preferably has a rutile crystal structure. Examples of substrates having a rutile crystal structure include a rutile-structure GeO2 substrate, a magnesium fluoride substrate, and a rutile-structure TiO2 substrate. The crystal substrate may have an off-axis angle. According to such a preferred range, electrical properties can be further improved, better crystallinity can be achieved, and the crystal substrate can be more easily applied to semiconductor devices, etc.

[0017] In the present invention, a film may be formed directly on the substrate, but a layer different from the semiconductor layer (for example, an n-type semiconductor layer, n + n-type semiconductor layer - The semiconductor layer may be formed on the substrate via other layers, such as a silicon-doped semiconductor layer (e.g., a silicon-doped semiconductor layer), an insulator layer (including a semi-insulator layer), or a buffer layer. A buffer layer is particularly suitable for reducing the difference in lattice constant between the crystal substrate and the semiconductor layer. Examples of materials for the buffer layer include SnO2, TiO2, VO2, MnO2, RuO2, CsO2, IrO2, GeO2, CuO2, PbO2, AgO2, CrO2, SiO2, SiC, GaN, Pt, and mixed crystals thereof.

[0018] In the present invention, it is preferable that the crystal or the crystal film of the multilayer structure be in contact with an ohmic electrode to form an ohmic contact. The ohmic electrode is not particularly limited as long as it does not impede the object of the present invention and may be a known metal element. Preferably, the ohmic electrode contains one or more metal elements selected from d-block metal elements and / or p-block metal elements of the periodic table. Examples of the d-block metal elements include Sc, Y, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Tc, Re, Fe, Ru, Os, Co, Rh, Ir, Pt, Au, Hg, Zn, Cd, and Pd. Examples of the p-block metal elements include Al, Ga, In, Sn, Pb, Tl, Bi, and Po. Furthermore, it is more preferable in the present invention that the ohmic electrode contains indium. Within these preferred ranges, better ohmic characteristics can be achieved.

[0019] The crystals can be more easily obtained by forming a crystalline film containing germanium dioxide as a main component and a mixed crystal film thereof using, for example, the film forming apparatus shown in FIG. 1 . Furthermore, doping can also be performed appropriately using the film forming apparatus. The doped crystals can be suitably used as semiconductor films or semiconductor layers, and n-type or p-type dopants can be applied using conventional doping methods for oxide semiconductors. Examples of n-type dopants include antimony (Sb), arsenic (As), bismuth (Bi), phosphorus (P), fluorine (F), niobium (Nb), vanadium (V), tantalum (Ta), and tungsten (W). Examples of p-type dopants include aluminum (Al), gallium (Ga), and indium (In). The present invention also encompasses stacked structures obtained in this manner.

[0020] The laminated structure can be used as is or after known processing such as substrate peeling, for example, by known means, for semiconductor devices. Examples of such semiconductor devices include Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSs), metal semiconductor field-effect transistors (MESFETs), static induction transistors (SITs), high electron mobility transistors (HEMTs), metal oxide semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), insulated gate bipolar transistors (IGBTs), and light-emitting diodes (LEDs). The present invention may also be applied to modules incorporating such semiconductor devices, electronic devices incorporating such semiconductor devices, and components thereof. These semiconductor devices are useful for a variety of applications, particularly power devices. Semiconductor devices can be classified into horizontal devices (horizontal devices) in which an electrode is formed on one side of the semiconductor layer, and vertical devices (vertical devices) in which electrodes are formed on both the front and back sides of the semiconductor layer. In the present invention, the semiconductor device can be used as either a horizontal device or a vertical device.

[0021] The single crystal film of the present invention may be used as a buffer layer, and n + By forming it on the layer, it is possible to obtain a Schottky barrier diode with an ON / OFF ratio of 1,000,000 or more, or an ON current of 10 mA / cm when a forward voltage of 10 V is applied. 2 The above Schottky barrier diode can be easily fabricated. + A laminated structure in which a single crystal film is laminated on a semiconductor layer is preferred, and within such a preferred range, a semiconductor device having better electrical characteristics can be obtained.

[0022] Examples of semiconductor devices suitable for use in the present invention will be described in more detail below with reference to the drawings, but the present invention is not limited to these examples. Preferred examples in which a crystal layer containing germanium dioxide as a main component in the present invention is used as a semiconductor layer are shown below.

[0023] (SBD) Figure 4 shows the - type semiconductor layer 101a,n + 1 shows a preferred example of a Schottky barrier diode (SBD) including a p-type semiconductor layer 101b, a p-type semiconductor layer 102, a metal layer 103, an insulator layer 104, a Schottky electrode 105a, and an ohmic electrode 105b. The metal layer 103 is made of a metal such as Al, and covers the Schottky electrode 105a.

[0024] (HEMT) FIG. 5 shows an n-type semiconductor layer 121a having a wide band gap, an n-type semiconductor layer 121b having a narrow band gap, and an n-type semiconductor layer 121c having a narrow band gap. + 1 shows a preferred example of a high electron mobility transistor (HEMT) including a p-type semiconductor layer 121c, a p-type semiconductor layer 123, a gate electrode 125a, a source electrode 125b, a drain electrode 125c, and a substrate 129.

[0025] (MOSFET) Figure 6 shows the - The first n-type semiconductor layer 131a + type semiconductor layer 131b, second n +1 shows a preferred example of a metal oxide semiconductor field effect transistor (MOSFET) including a p-type semiconductor layer 131c, a p-type semiconductor layer 132, a p+-type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c. Note that the p+-type semiconductor layer 132a may be a p-type semiconductor layer or may be the same as the p-type semiconductor layer 132.

[0026] (JFET) Figure 7 shows the - The first n-type semiconductor layer 141a + type semiconductor layer 141b, second n + 1 shows a preferred example of a junction field effect transistor (JFET) including a p-type semiconductor layer 141c, a p-type semiconductor layer 142, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

[0027] (IGBT) FIG. 8 shows the n-type semiconductor layer 151, - type semiconductor layer 151a,n + 1 shows a preferred example of an insulated gate bipolar transistor (IGBT) including a p-type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c.

[0028] (LED) An example of a case where the semiconductor device of the present invention is a light-emitting diode (LED) is shown in Fig. 9. The semiconductor light-emitting device of Fig. 9 has an n-type semiconductor layer 161 on a second electrode 165b, and a light-emitting layer 163 is stacked on the n-type semiconductor layer 161. A p-type semiconductor layer 162 is stacked on the light-emitting layer 163. A translucent electrode 167 that transmits light generated by the light-emitting layer 163 is provided on the p-type semiconductor layer 162, and a first electrode 165a is stacked on the translucent electrode 167. The semiconductor light-emitting device of Fig. 9 may be covered with a protective layer except for the electrode portion.

[0029] Examples of materials for the translucent electrode include conductive oxide materials containing indium (In) or titanium (Ti). More specifically, examples include In2O3, ZnO, SnO2, Ga2O3, TiO2, CeO2, or mixed crystals of two or more of these, or doped materials thereof. The translucent electrode can be formed by depositing these materials using known means such as sputtering. After the translucent electrode is formed, it may be subjected to thermal annealing to make the translucent electrode transparent.

[0030] In the semiconductor light-emitting device of Figure 9, the first electrode 165a is a positive electrode and the second electrode 165b is a negative electrode, and by passing a current through them to the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161, the light-emitting layer 163 emits light.

[0031] Examples of materials for the first electrode 165a and the second electrode 165b include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof. The method for forming the electrodes is not particularly limited, and they can be formed on the substrate by a method appropriately selected from wet methods such as printing, spraying, and coating; physical methods such as vacuum deposition, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into consideration their suitability for the material.

[0032] (JBS) 10 shows the main part of a junction barrier Schottky diode (JBS) which is one of the preferred embodiments of the present invention. The JBS in FIG. 10 has an ohmic electrode 1020, n - type semiconductor layers 1010a,n +10, the semiconductor device includes a p-type semiconductor layer 1010b, a Schottky electrode 1030, and an electric field relaxation region 1060. The Schottky electrode 1030 is composed of a metal layer 1030a, a metal layer 1030b, and a metal layer 1030c. In the semiconductor device of FIG. 10, the outer end of the metal layer 1030a and / or the metal layer 1030b serving as the second electrode layer is located outside the outer end of the metal layer 1030c serving as the first electrode layer. In the semiconductor device of FIG. 10, the electric field relaxation region 1060 includes at least two electric field relaxation regions 1060 in a plane including at least a part of a portion of the second electrode layer that is located outside the outer end of the first electrode layer and the outer end of the second electrode. In the semiconductor device of FIG. 10, the electric field relaxation region 1060 is composed of a p-type semiconductor, and - A PN junction is formed between the first and second semiconductor layers 1010a and 1010b.

[0033] The means for forming each layer in Fig. 10 is not particularly limited as long as it does not impede the object of the present invention, and may be any known means, such as forming a film by vacuum deposition, CVD, sputtering, or various coating techniques, followed by patterning by photolithography, or directly patterning by printing or the like.

[0034] (MESFET) 11 shows an example of a metal semiconductor field effect transistor (MESFET) according to the present invention. The MESFET of FIG. - type semiconductor layers 111a,n + The semiconductor layer 111b includes a buffer layer 118, a semi-insulating layer 114, a gate electrode 115a, a source electrode 115b, and a drain electrode 115c.

[0035] The materials for the gate electrode, drain electrode, and source electrode may be known electrode materials, such as metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; or mixtures thereof. The gate electrode, drain electrode, and source electrode can be formed by known means such as vacuum deposition or sputtering.

[0036] The semi-insulating layer 114 may be made of a semi-insulating material, and examples of the semi-insulating material include those containing semi-insulating dopants such as magnesium (Mg), ruthenium (Ru), iron (Fe), beryllium (Be), cesium (Cs), strontium (Sr), and barium (Ba), as well as those that have not been doped.

[0037] In the MESFET shown in FIG. 11, a good depletion layer is formed under the gate electrode, so that the current flowing from the drain electrode to the source electrode can be efficiently controlled.

[0038] (SIT) 12 shows an example of the semiconductor device of the present invention being an SIT. - type semiconductor layer 241a,n + The gate electrode 245a, the source electrode 245b and the drain electrode 245c are provided.

[0039] On the drain electrode 245c, for example, a 100 nm to 100 μm thick n + The n-type semiconductor layer 241b is formed. + On the type semiconductor layer 241b, for example, an n-type semiconductor layer having a thickness of 100 nm to 100 μm is formed. - The n-type semiconductor layer 241a is formed.- On the n-type semiconductor layer 241a, + The n-type semiconductor layer 241c is formed. + A source electrode 145b is formed on the type semiconductor layer 241c.

[0040] Also, the n - The n-type semiconductor layer 241a contains + The n - A plurality of trenches are formed to a depth that reaches halfway through the semiconductor layer 241a. - A gate electrode 245a is formed on the type semiconductor layer 241a.

[0041] In the on-state of the SIT shown in FIG. 12, when a voltage is applied between the source electrode 245b and the drain electrode 245c and a positive voltage is applied to the gate electrode 245a with respect to the source electrode 245b, the n - A channel layer is formed in the n-type semiconductor layer 241a, and electrons - The off state is achieved by setting the voltage of the gate electrode to 0V, which prevents the formation of a channel layer and turns the n-type semiconductor layer 241a on. - The semiconductor layer is filled with a depletion layer, and the device is turned off.

[0042] 13A and 13B show a part of the manufacturing process of the SIT of FIG. 12. For example, using a stacked body as shown in FIG. 13A, - type semiconductor layer 241a and n + An etching mask is provided in a predetermined region of the n-type semiconductor layer 241c, and anisotropic etching is performed using the etching mask by, for example, reactive ion etching, to remove the n-type semiconductor layer 241c as shown in FIG. 13(b). + The n-type semiconductor layer 241c surface - A trench groove is formed to a depth that reaches halfway through the n-type semiconductor layer 241a. Next, a gate electrode material such as polysilicon is deposited in the trench groove by a CVD method, a vacuum deposition method, a sputtering method, or the like. -The n-type semiconductor layer 241a is formed to a thickness equal to or less than that of the n-type semiconductor layer 241a. + A source electrode 245b is formed on the n-type semiconductor layer 241c. + A drain electrode 245c is formed on the type semiconductor layer 241b, thereby manufacturing an SIT. The electrode materials for the source electrode and the drain electrode may be known electrode materials, such as metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof.

[0043] Although the above example shows an example in which a p-type semiconductor is not used, the present invention is not limited to this and a p-type semiconductor may be used. Note that the p-type semiconductor may be the same material as the n-type semiconductor and contain a p-type dopant, or may be a different p-type semiconductor. [Example]

[0044] Example 1 FIG. 1 shows a preferred embodiment of a film-forming apparatus according to the present invention. The film-forming apparatus 19 comprises a film-forming sample 20, a sample stage 21, carrier gas sources 22a and 22b, flow control valves 23a and 23b, a film-forming chamber 27, a heater 28, and an atomization device 30. The atomization device 30 comprises a raw material partition wall 24, a raw material liquid to be atomized 24a, an ultrasonically-transmitting substrate 24b, a stage 24c, an ultrasonic vibrator 26, a guide partition wall 31, an ultrasonic-transmitting liquid tank 35, and an ultrasonic-transmitting liquid 36. FIG. 2 shows another preferred embodiment of a film-forming apparatus when the atomization device according to the present invention is used as a film-forming atomization stage. The atomization device 30 comprises a raw material partition wall 24, a raw material liquid to be atomized 24a, an ultrasonically-transmitting substrate 24b, a stage 24c, an ultrasonic vibrator 26, a guide partition wall 31, an ultrasonic-transmitting liquid tank 35, and an ultrasonic-transmitting liquid 36. The sample stage 21 is made of quartz, and the surface on which the film-forming sample 20 is placed is inclined from the horizontal. By fabricating both the film-forming chamber 27 and the sample stage 21 from quartz, impurities originating from the device are prevented from being mixed into the crystalline film formed on the film-forming sample 20. The concentration of antimony chloride relative to the concentration of germanium in the atomization raw material solution 24a was adjusted to 5 mol%. The atomization raw material solution 24a was contained in the mist generating source 24. The guide partition 31 was in contact with the ultrasonic-transmitting substrate 38. Figure 3 is a schematic diagram showing a cross-sectional side view of the atomization device used in the present invention. The atomization device 30 in Figure 3 consists of the raw material partition 24, the ultrasonic-transmitting substrate 24b, the base 24c, the ultrasonic vibrator 26, the guide partition 31, and the ultrasonic-transmitting liquid tank 35. The guide partition 31 is in contact with the ultrasonic-transmitting liquid tank 35. The ultrasonic waves generated by the ultrasonic vibrator 26 are transmitted to the raw material partition wall 24 more efficiently by using the guide partition wall 31 .

[0045] Next, a TiO2 (001) substrate with a rutile crystal structure, 10 mm square and an average thickness of 500 μm, was placed on sample stage 21 as film deposition sample 20, and heater 28 was operated to raise the temperature inside film deposition chamber 27 to 700°C. Next, flow control valve 23 was opened to supply carrier gas from carrier gas source 22 into film deposition chamber 27. After the atmosphere inside film deposition chamber 27 was thoroughly replaced with carrier gas, the flow rate of the carrier gas was adjusted to 1 L / min. Nitrogen gas was used as the carrier gas.

[0046] Next, the ultrasonic vibrator 26 was vibrated at 3.0 MHz, and the vibration was propagated to the atomization raw material liquid 24a through the ultrasonic transmitter 25a, thereby atomizing the atomization raw material liquid 24a to generate raw material fine particles. These raw material fine particles were introduced into the film deposition chamber 27 by the carrier gas, and reacted in the film deposition chamber 27, forming a tetragonal GeO2 crystal film on the film deposition sample 20 by a CVD reaction on the film deposition surface of the film deposition sample 20. The film thickness was 200 nm.

[0047] The obtained GeO2 crystalline film was measured using an X-ray diffractometer. Figure 14 shows the 2θ / ω results from the XRD diffraction. As is clear from Figure 14, the obtained crystalline film was a GeO2 single crystal film with a (002)-oriented tetragonal rutile structure. Figure 15 shows the ω scan results from the X-ray diffraction measurement. As shown in Figure 15, the rocking curve half-width at the 002 diffraction peak of r-GeO2 was 936 arcsec. The film thickness was 200 nm. These results indicate that a GeO2 crystalline film with good crystallinity was formed over the entire surface of the TiO2 (001) substrate with a rutile crystal structure.

[0048] Furthermore, when the surface of the obtained GeO2 crystal film was observed using an atomic force microscope (AFM), it was found that the surface roughness (RMS) based on JIS B0601 was 8.3 nm, as shown in Figure 16, indicating excellent surface smoothness.

[0049] The surface of the obtained GeO2 crystal film was observed using SEM. Figure 17 shows an SEM image. As is clear from Figure 17, GeO2 crystals with excellent surface smoothness and good crystallinity were formed. Furthermore, when the surface of the obtained crystal film was evaluated using EDS, it was found that the crystal film was formed over the entire surface to a depth of 100 mm, as shown in Figure 18. 2 It was found that the pores were formed over an area of ​​more than 100m.

[0050] The electrical properties of the obtained film were evaluated by Hall effect measurement using the van der Pauw method. The measurement environment was room temperature and the frequency of the applied magnetic field was 50 mHz. As a result, the carrier concentration was 1.05 × 10 20 (1 / cm 3 ) and the mobility is 12(cm 2 / V·s). The sheet resistance was 2.65×10 2 (Ω / □). The electrical resistivity was 5.29×10 ―3 The carrier type was "n".

[0051] An ohmic electrode was formed on the obtained crystal film using indium as shown in Figure 19, and ohmic measurements were performed. The results are shown in Figure 20. As is clear from Figure 20, it was found that the film had excellent ohmic characteristics.

[0052] Example 2 Film formation was carried out in the same manner as in Example 1, except that the concentration of antimony chloride was changed to 3 mol%. The obtained crystalline film was measured using an X-ray diffractometer. Figure 21 shows the XRD diffraction results. As is clear from Figure 21, the obtained crystalline film was a GeO2 single crystal film with a (002)-oriented tetragonal rutile structure. A GeO2 crystalline film with good crystallinity was formed over the entire surface of the TiO2 (001) substrate with a rutile-type crystal structure. The film thickness was 200 nm.

[0053] The electrical properties of the obtained film were evaluated by Hall effect measurement using the van der Pauw method. The measurement environment was room temperature and the frequency of the applied magnetic field was 50 mHz. As a result, the carrier concentration was 1.68 × 10 20 (1 / cm 3 ) and the mobility is 6 (cm 2 / V·s). The sheet resistance was 1.68×10 2 (Ω / □). The electrical resistivity was 5.76×10 ―3 The carrier type was "n".

[0054] Example 3 Film formation was performed in the same manner as in Example 1, except that the antimony chloride concentration was changed to 0.2 mol% and the substrate was changed to a TiO2 (001) substrate with a rutile structure, a square with sides of 15 mm, and an average thickness of 500 μm. The resulting crystalline film was measured using an X-ray diffractometer. Figure 22 shows the 2θ / ω results from the XRD diffraction analysis. As is clear from Figure 22, the resulting crystalline film was a GeO2 single crystal film with a (002)-oriented tetragonal rutile structure. A GeO2 crystalline film containing antimony and with good crystallinity was formed on the entire surface of the TiO2 (001) substrate with a rutile crystal structure. The film thickness was 770 nm. The ω scan results from the X-ray diffraction analysis are shown in Figure 33. From FIG. 33, it was found that the rocking curve half-width at the 002 diffraction peak was 410 arcsec, and a uniform r-GeO2(001) single crystal thin film was formed on the r-TiO2(001) substrate.

[0055] An ohmic electrode was formed on the obtained single crystal thin film using indium as shown in Figure 34, and ohmic measurements were performed. The results are shown in Figure 35. As is clear from Figure 35, it was found that the film had excellent ohmic characteristics.

[0056] The electrical properties of the obtained film were evaluated by Hall effect measurement using the van der Pauw method. The measurement environment was room temperature and the frequency of the applied magnetic field was 50 mHz. As a result, the carrier concentration was 6.17 × 10 18 (1 / cm 3 ) and the mobility is 57(cm 2 / V·s). The sheet resistance was 2.32×10 2 (Ω / □). The electrical resistivity was 1.78×10 ―3 The carrier type was "n".

[0057] Example 4 1. Formation of buffer layer Film formation was performed in the same manner as in Example 2, except that the substrate was changed to a Nb-doped r-TiO2 (001) substrate with a rutile structure. The resulting crystalline film was measured using an XRD diffractometer. Figure 23 shows the XRD analysis results. As shown in Figure 23, the resulting thin film was a tetragonally oriented GeO2 (002) single crystal film. Figure 24 shows the ω-scan results of the X-ray diffraction measurement. As shown in Figure 24, the rocking curve half-width at the 002 diffraction peak was 1171 arcsec, indicating that an antimony-containing r-GeO2 single crystal film with good crystallinity was formed on the Nb-doped TiO2 (001) substrate. The film thickness was 170 nm, and the sheet resistance was less than 300 Ω / □.

[0058] 2.n - Formation of the semiconductor layer An r-GeO2 single crystal film was fabricated on the Nb-doped TiO2 (001) substrate with the r-GeO2 single crystal film fabricated in the above 1. Buffer Layer Formation procedure, following the same procedure as in 1. Buffer Layer Formation, except for varying the amount of antimony chloride added to the atomization source solution 24a used in 1. Buffer Layer Formation. The resulting crystalline film was measured using an XRD diffractometer. Figure 25 shows the XRD analysis results. Figure 25 indicates that the resulting thin film was a tetragonally oriented GeO2 (002) single crystal film. Figure 26 shows the ω-scan results of the X-ray diffraction measurement. Figure 26 indicates that the rocking curve half-width at the 002 diffraction peak was 550 arcsec, indicating that an r-GeO2 single crystal film with good crystallinity had been formed on the Nb-doped TiO2 (001) substrate. The film thickness was 1.2 μm, and the sheet resistance was less than 300 Ω / □.

[0059] 3. Formation of Electrodes An SBD with the completely vertical structure shown in Figure 27 was fabricated. The electrodes were formed by EB evaporation. The electrode formation conditions are shown below. Figure 28 shows a surface image of a sample with electrodes formed on a crystalline film. EB evaporation, Ti 75 nm / Pt 75 nm (Reverse side), metal mask RTA, N2 550oC 60s EB evaporation, Ni 75 nm / Au 75 nm (Front side), metal mask

[0060] The SBD with the fully vertical structure obtained as described above was subjected to IV measurement. The results are shown in Figure 29. From Figure 29, the ON / OFF voltage at an applied voltage of ±5V was 3.065 × 10 7 The ON current value was 51 mA / cm when a forward voltage of 10 V was applied. 2 These results show that Example 1 is excellent in semiconductor properties and Schottky properties.

[0061] Furthermore, the n - The carrier concentration was calculated from the results of CV measurement of the type semiconductor layer. 17 ~4×10 17 cm -3 This shows that the carrier concentration can be easily controlled in the present invention. The relationship between the carrier concentration and the depth calculated from the results of the CV measurement in Example 1 is shown in FIG.

[0062] Example 5 The amount of antimony chloride added was 1 mol %, and the 2.n - Except for not forming the mold semiconductor layer, film formation was carried out in the same manner as in Example 4. The film thickness was 170 nm, and the sheet resistance was 300 Ω / □ or less. 1. Formation of electrodes An Sb-containing r-GeO2 single crystal film was prepared on a Nb-doped r-TiO2 (001) substrate with a square shape measuring 10 mm on a side and an average thickness of 500 μm, and then an electrode was formed on the substrate. A cross-sectional diagram is shown in Figure 31. The electrode was formed by EB deposition. The electrode formation conditions are as follows: EB evaporation, Ti 75 nm / Pt 75 nm (Reverse side), metal mask EB evaporation, Ti 75 nm / Pt 75 nm (Front side), metal mask RTA, N2 550oC 60s RTA, N2 600oC 60s (Additional)

[0063] The ohmic characteristics of the r-GeO2 single crystal film fabricated on the obtained Nb-doped r-TiO2(001) substrate were also measured by IV measurement. The results are shown in Figure 32. From Figure 32, it was confirmed that an ohmic contact was formed between the Nb-doped r-TiO2(001) substrate and the r-GeO2 single crystal film. [Industrial Applicability]

[0064] The crystal and layered structure of the present invention are suitable for use in, for example, semiconductor devices. [Explanation of symbols]

[0065] 19 Film forming equipment 20 Film sample 21 Sample stage 22a Carrier gas source 22b Dilution gas source 23a Flow control valve 23b Flow control valve 24 Raw material bulkhead 24a Raw material solution for atomization 24b Ultrasonic transparent base material 24c units 26 Ultrasonic vibrator 27 Film forming room 28 Heater 30 Atomization device 31 Guide bulkhead 33 Dilution gas supply pipe 34 Carrier gas supply pipe 35 Ultrasonic transmission fluid tank 36 Ultrasonic transmission fluid 37 Film forming room 101a n - Type semiconductor layer 101b n + Type semiconductor layer 102 p-type semiconductor layer 103 Metal layer 104 Insulator layer 105a Schottky electrode 105b Ohmic electrode 111a n -Type semiconductor layer 111b n + Type semiconductor layer 114 Semi-insulating layer 115a gate electrode 115b Source electrode 115c Drain electrode 118 Buffer layer 121a Wide bandgap n-type semiconductor layer 121b Narrow bandgap n-type semiconductor layer 121c n + Type semiconductor layer 123 p-type semiconductor layer 124 Semi-insulating layer 125a Gate electrode 125b Source electrode 125c drain electrode 128 Buffer layer 129 PCB 131a n - Type semiconductor layer 131b 1st n + Type semiconductor layer 131c second n + Type semiconductor layer 132 p-type semiconductor layer 134 Gate insulating film 135a gate electrode 135b Source electrode 135c Drain electrode 138 Buffer layer 139 Semi-insulating layer 141a n - Type semiconductor layer 141b 1st n + Type semiconductor layer 141c second n + Type semiconductor layer 142 p-type semiconductor layer 145a Gate electrode 145b Source electrode 145c Drain electrode 151 n-type semiconductor layer 151a n - Type semiconductor layer 151b n + Type semiconductor layer 152 p-type semiconductor layer 154 Gate insulating film 155a Gate electrode 155b Emitter electrode 155c Collector electrode 161 n-type semiconductor layer 162 p-type semiconductor layer 163 Light-emitting layer 165a first electrode 165b second electrode 167 Translucent electrode 169 PCB 1010a n - type semiconductor 1010b n + type semiconductor 1020 Ohmic electrode 1030 Schottky electrode 1030a metal layer 1030b metal layer 1030c metal layer 1060 Electrolytic relaxation region

Claims

1. A crystal containing germanium dioxide as a main component, characterized in that the crystal has a sheet resistance of 300 Ω / □ or less.

2. The crystal according to claim 1, which is in the form of a film.

3. The crystal of claim 1, which is a single crystal film.

4. The crystal of claim 1, which comprises a dopant.

5. 5. The crystal of claim 4, wherein the dopant comprises an element from Group 15 of the periodic table.

6. The crystal of claim 1 which is a semiconductor.

7. The crystal according to claim 1, which has a rutile crystal structure.

8. A laminated structure in which a crystalline film is laminated on a crystalline substrate directly or via another layer, the crystalline film being a crystalline film containing germanium dioxide as its main component, and the sheet resistance of the crystalline film being 300 Ω / □ or less.

9. 9. The laminated structure according to claim 8, wherein the crystalline substrate has a rutile crystalline structure.

10. 9. The laminated structure according to claim 8, wherein the crystalline film has a rutile crystal structure.

11. 9. A semiconductor device including a crystal or a laminated structure, wherein the crystal is the crystal according to claim 1, and the laminated structure is the laminated structure according to claim 8.

12. 12. The semiconductor device according to claim 11, wherein the crystal or the crystal film of the laminated structure is in contact with an ohmic electrode to form an ohmic contact.

13. 12. The semiconductor device according to claim 11, which is a power device.

14. 12. The semiconductor device according to claim 11, wherein the ON / OFF ratio is 1,000,000 or more.

15. The ON current value when a forward voltage of 10 V is applied is 10 mA / cm ２ 12. The semiconductor device according to claim 11.

16. 12. The semiconductor device according to claim 11, which is a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal semiconductor field effect transistor (MESFET), a static induction transistor (SIT), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), or a light emitting diode (LED).

17. 12. An electronic device including a semiconductor device, wherein the semiconductor device is the semiconductor device according to claim 11.

18. A system including an electronic device, wherein the electronic device is the electronic device according to claim 17.

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