Wiring board and method of manufacturing the same

Abstract

To provide a technique for suppressing undulation of the surface of a wiring board.SOLUTION: A plurality of conductive layers 20 and a plurality of insulating layers 21 which are alternately laminated, a plurality of connection conductors 30 which are via conductors 12 connecting the conductive layers 20 separated by two insulating layers 21, a first area R1 in which the plurality of connection conductors 30 are arranged relatively densely, and a second area R1 in which the plurality of connection conductors 30 are arranged more sparsely than in the first area R2, the plurality of connecting conductors 30 include the stacked via conductors 31 in which the via conductors 12 respectively formed in the two insulating layers 21 are stacked and the skip via conductors 32 that are continuous over the two insulating layers 21, the stacked via conductors 31 occupy more than the skip via conductors 32 in the plurality of connecting conductors 30 in the first region R1, and the skip via conductors 32 occupy more than the stacked via conductors 31 in the plurality of connecting conductors 30 in the second region R2.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a wiring board in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked, and a method for manufacturing the same. [Background technology]

[0002] In this type of wiring board, the conductive layer is generally formed by plating (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-212380 A (paragraph

[0029] , Figure 1) Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional wiring board structures, the thickness of the same conductive layer can vary depending on the location, which can result in large undulations on the surface of the wiring board. This application provides a technology for suppressing the undulations on the surface of the wiring board. [Means for solving the problem]

[0005] One aspect of the invention disclosed herein, made in consideration of the above problems, is a wiring board comprising: a plurality of conductive layers and a plurality of insulating layers stacked alternately; a plurality of connecting conductors which are via conductors connecting the conductive layers separated by two insulating layers; a first region in which the plurality of connecting conductors are arranged relatively densely; and a second region in which the plurality of connecting conductors are arranged more sparsely than in the first region, wherein the plurality of connecting conductors include stacked via conductors formed in each of the two insulating layers and skip via conductors which are continuous across the two insulating layers, and the stacked via conductors occupy more of the plurality of connecting conductors in the first region than the skip via conductors, and the plurality of connecting conductors in the second region are occupied by the skip via conductors more than the stacked via conductors. [Brief explanation of the drawings]

[0006] [Figure 1] Figure 1 shows a cross-sectional view of the wiring board. [Figure 2] Figure 2 is a cross-sectional side view of the wiring board. [Figure 3] FIG. 3A is a cross-sectional side view of a core substrate, FIG. 3B is a cross-sectional side view of a core substrate on which a conductive layer is laminated, and FIG. 3C is a cross-sectional side view of a core substrate on which an insulating layer is laminated. [Figure 4] FIG. 4A is an enlarged cross-sectional view of a core substrate in which stacked via conductors are formed, and FIG. 4B is an enlarged cross-sectional view of a core substrate in which stacked via holes and skip via holes are formed. DETAILED DESCRIPTION OF THE INVENTION

[0007] [First embodiment] A wiring board 10 according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 4. As shown in FIG. 2, the wiring board 10 of this embodiment includes, for example, a core substrate 11, three conductive layers 20 and two insulating layers 21 alternately stacked on both the front and back surfaces of the core substrate 11, and a solder resist layer (not shown) as the outermost layer. FIG. 2 shows only the front side of the wiring board 10 from the core substrate 11, and FIG. 1 shows a plan view of the front side of the wiring board 10 with the solder resist layer omitted. Hereinafter, when distinguishing between the conductive layers 20 on the front side of the core substrate 11, the conductive layers 20 will be referred to as a "first conductive layer 20A," a "second conductive layer 20B," and a "third conductive layer 20C" in order from the core substrate 11 side toward the top of FIG. 2. When distinguishing between the insulating layers 21, the insulating layers 21 will be referred to as a "first insulating layer 21A," a "second insulating layer 21B," and a "second insulating layer 21B" in order from the core substrate 11 side toward the top of FIG. 2.

[0008] Although the conductive layers 20 and insulating layers 21 alternately stacked in the wiring board 10 of this embodiment include three conductive layers 20 and two insulating layers 21, the wiring board 10 may include more conductive layers 20 and insulating layers 21 as long as it includes at least three conductive layers 20 and two insulating layers 21. Furthermore, although the wiring board 10 of this embodiment includes a core substrate 11, the wiring board 10 may not include a core substrate 11 and may instead have a structure in which a plurality of conductive layers 20 and a plurality of insulating layers 21 are stacked.

[0009] Core substrate 11 has a structure in which, for example, multiple prepregs are laminated, each prepreg being made of a core material such as a woven glass cloth and impregnated with resin, and insulating layer 21 has no core material and is made of a resin film made of a thermosetting resin containing an inorganic filler. The outermost layer, a solder resist layer (not shown), is an ultraviolet-curable photosensitive film made of, for example, an epoxy resin. Core substrate 11 may have a structure in which resin films are laminated, or insulating layer 21 may be made of a prepreg. Furthermore, the solder resist layer may be formed by curing a liquid material.

[0010] A plurality of through holes 15H are formed in core substrate 11, and the interiors of these through holes 15H are filled with through hole conductors 15. Conductive layers 20 on the front and back surfaces of core substrate 11 are connected to each other by the plurality of through hole conductors 15.

[0011] The plurality of conductive layers 20 are, for example, electrolytically plated to a predetermined thickness and arranged in the shape of a predetermined electrical circuit, and each conductive layer 20 is entirely covered with a respective insulating layer 21. A plurality of vias 12H are formed in each of the plurality of insulating layers 21, and via conductors 12 are filled therein. The electrical circuits of the plurality of conductive layers 20 are connected to each other by the plurality of via conductors 12 on both the front and back sides of the core substrate 11. Specifically, the vias 12H and the via conductors 12 form a cone shape whose diameter decreases toward the core substrate 11. The via conductors 12 are formed on lands 16 included in the conductive layer 20 below the insulating layer 21 that has the via conductors 12, and the lands 16 included in the conductive layer 20 above the insulating layer 21 that has the via conductors 12 are formed on the via conductors 12.

[0012] The front side of the core substrate 11 of the wiring board 10 is provided with a plurality of connecting conductors 30, which are via conductors that connect the first and third conductive layers 20A, 20C separated by the first and second insulating layers 21A, 21B.

[0013] The plurality of connecting conductors 30 also include stacked via conductors 31 having a two-stage structure in which via conductors 12 formed in each of the first and second insulating layers 21A and 21B are stacked, and skip via conductors 32 having a single stage structure that extends continuously across the first and second insulating layers 21A and 21B.

[0014] Specifically, the stacked via conductor 31 has a structure in which a via conductor 12 included in the first insulating layer 21A, a land 16 included in the second conductive layer 20B, and a via conductor 12 included in the second insulating layer 21B are stacked one on top of the other. The land 16 included in the first conductive layer 20A is connected to the lower end of the stacked via conductor 31, and the land 16 included in the third conductive layer 20C is connected to the upper end of the stacked via conductor 31. The via conductor 12 constituting the stacked via conductor 31 has substantially the same conical shape as a single via conductor 12 not included in the connecting conductor 30.

[0015] The skip via conductor 32 is disposed in a portion where the first insulating layer 21A and the second insulating layer 21B are in direct contact with each other without sandwiching the conductive layer 20 therebetween. The skip via conductor 32 has a conical shape that extends continuously across the first and second insulating layers 21A and 21B, and its lower end is connected to a land 16 included in the first conductive layer 20A, and its upper end is connected to a land 16 included in the third conductive layer 20C. The outer diameter of the upper end of the skip via conductor 32 is approximately the same as the outer diameter of the upper end of the via conductor 12 included in the stack via conductor 31, and the outer diameter of the lower end of the skip via conductor 32 is also approximately the same as the outer diameter of the lower end of the via conductor 12 included in the stack via conductor 31. That is, the skip via conductor 32 has a conical shape with a smaller taper than the via conductor 12 included in the stack via conductor 31.

[0016] One or both of the upper and lower ends of the skip via conductor 32 may be larger or smaller than the upper and lower ends of the via conductor 12 included in the stack via conductor 31 .

[0017] The middle land 16 and the lands 16 at the upper and lower ends of the stack via conductor 31, and the lands 16 at the upper and lower ends of the skip via conductor 32, are disk-shaped with an outer diameter slightly larger than the large diameter portion at the upper end of the via conductor 12. Some of the lands 16 also form part of the wiring portion included in the conductive layer 20. Some or all of the lands 16 of the stack via conductor 31 and the skip via conductor 32 are exposed through openings formed in a solder resist layer (not shown) and are used as pads to which electrical components are connected.

[0018] 1, the wiring board 10 includes a first region R1 in which the connection conductors 30 are densely arranged, and a second region R2 in which the connection conductors 30 are sparsely arranged. For example, all the connection conductors 30 included in the first region R1 are the stacked via conductors 31 described above, and all the connection conductors 30 included in the second region R2 are the skip via conductors 32 described above.

[0019] The first and second regions R1 and R2, which are the targets of density comparison of the connecting conductors 30, may be regions containing at least three or more connecting conductors 30, preferably six or more connecting conductors 30. The areas of the first and second regions R1 and R2 to be compared may be the same or different. The difference in density of the connecting conductors 30 may be determined by the difference in the average distance between the central axes of adjacent connecting conductors 30. For example, the average distance between the central axes of the connecting conductors 30 in the second region R2 is preferably 1.2 times or more, and more preferably 2 times or more, the average distance between the central axes of the connecting conductors 30 in the first region R1. In the example of FIG. 1, the average distance between the central axes of the connecting conductors 30 in the second region R2 is approximately twice the average distance between the central axes of the connecting conductors 30 in the first region R1.

[0020] This concludes the description of the structure of wiring board 10 of this embodiment. Next, a method for manufacturing wiring board 10 will be described. (1) As shown in FIG. 3A, a plurality of through holes 15H are formed by a laser in an insulating base material 11K prepared as a core substrate 11, and smears inside the through holes 15H are removed by a desmearing process.

[0021] (2) Next, as shown in Fig. 3B, for example, known subtractive processes such as electroless plating, electrolytic plating, and etching are performed to laminate first conductive layers 20A including lands 16 on both the front and back surfaces of insulating substrate 11K, and through-hole conductors 15 are filled into through-holes 15H. This completes core substrate 11. Note that through-hole conductors 15 may be made of a conductive paste or the like.

[0022] 3C, an insulating resin film is placed on the first conductive layer 20A and hot-pressed to form the first insulating layer 21A. Next, the first insulating layer 21A is irradiated with a laser to form the via 12H at a predetermined position in the first region R1, and then the smear inside the via 12H is removed by a desmearing process.

[0023] (4) Next, as shown in Fig. 4A, for example, a known semi-additive method is used to perform electroless plating, plating resist processing, and electrolytic plating processing, thereby laminating a second conductive layer 20B including lands 16 on the upper surface of the first insulating layer 21A, and forming via conductors 12 inside the vias 12H. These via conductors 12 are the lower via conductors included in the first insulating layer 21A among the stacked via conductors 31. Note that Fig. 4 shows only the front surface of the wiring board 10.

[0024] (5) Next, as shown in FIG. 4B, an insulating resin film is placed on second conductive layer 20B and hot-pressed to form second insulating layer 21B. Next, second insulating layer 21B is irradiated with a laser to form vias 12H in first region R1 at locations corresponding to the upper surfaces of lower via conductors 12 and at predetermined positions in second region R2. At this time, the laser is irradiated to the predetermined positions in second region R2 until it penetrates first insulating layer 21A and exposes first conductive layer 20A.

[0025] (6) Next, the vias 12H formed in the first region R1 and the second region R2 are subjected to a desmearing process to remove smears from inside the vias 12H. Next, the second insulating layer 21B is subjected to an electroless plating process, a plating resist process, and an electrolytic plating process. A third conductive layer 20C including lands 16 is laminated on the upper surface of the second insulating layer 21B, and a via conductor 12 is formed inside the vias 12H formed in the first region R1. This via conductor 12 is the upper via conductor 12 included in the second insulating layer 21B among the stacked via conductors 31. At the same time, a skip via conductor 32 is formed inside the vias 12H formed in the second region R2 (see FIG. 2).

[0026] After step (6), a solder resist layer may be laminated on the third conductive layer 20C, and further, a plurality of conductive layers 20 and a plurality of insulating layers 21 may be laminated.

[0027] This completes the description of the method for manufacturing wiring board 10 of this embodiment. The structure of wiring board 10 of this embodiment and wiring board 10 manufactured by the above-described manufacturing method have the effect of suppressing unevenness on the surface of wiring board 10, as will be described below.

[0028] That is, the wiring board 10 of this embodiment is provided with a plurality of connecting conductors 30 that connect the first and third conductive layers 20A, 20C that are separated by the first and second insulating layers 21A, 21B as described above (see FIG. 2). Also, as shown in FIG. 1, the plurality of connecting conductors 30 are densely arranged in the first region R1 and sparsely arranged in the second region R2.

[0029] Here, the plating solution has a substantially uniform metal concentration throughout the solution, and the amount of plating deposited per unit volume is substantially the same. Therefore, the amount of metal distributed per connecting conductor 30 is smaller in the first region R1, where multiple connecting conductors 30 are densely arranged, than in the second region R2, where multiple connecting conductors 30 are sparsely arranged. In addition, if the shapes of the connecting conductors 30 are the same, the formation of the connecting conductors 30 progresses faster in the second region R2 than in the first region R1. Therefore, a conventional wiring board in which the connecting conductors 30 are the same shape but simply have first and second regions R1 and R2 with different arrangement densities of the connecting conductors 30 results in large undulations on the surface.

[0030] 2, the plurality of connecting conductors 30 of the wiring board 10 of this embodiment include a stacked via conductor 31 having a two-stage structure in which via conductors 12 formed in each of two insulating layers 21 are stacked, and a single-stage skip via conductor 32 having a height equivalent to two stages and continuous across the two insulating layers 21. The via conductors 12 in each stage of the stacked via conductor 31 having a two-stage structure are formed earlier by plating than the skip via conductors 32 because they are lower than the skip via conductors 32. As a result, the third conductive layer 20C on the stacked via conductor 31 is thicker than the third conductive layer 20C on the skip via conductors 32.

[0031] In the wiring board 10 of this embodiment, the first region R1 where the connection conductors 30 are densely arranged is occupied by stacked via conductors 31, and the second region R2 where the connection conductors 30 are sparsely arranged is occupied by skip via conductors 32. This acts to cancel out the difference in thickness of the third conductive layer 20C on the connection conductors 30 due to the difference in shape of the connection conductors 30 (i.e., whether they are stacked via conductors 31 or skip via conductors 32) and the difference in thickness of the third conductive layer 20C on the connection conductors 30 due to the difference in arrangement density of the connection conductors 30 (i.e., the difference between the first and second regions R1 and R2). This reduces the difference in thickness depending on the location on the same third conductive layer 20C, and makes it possible to reduce unevenness on the surface of the wiring board 10.

[0032] In this embodiment, all of the connecting conductors 30 included in the first region R1 are stacked via conductors 31, and all of the connecting conductors 30 included in the second region R2 are skip via conductors 32, but as long as most of the connecting conductors 30 included in the first region R1 are occupied by stacked via conductors 31 and most of the connecting conductors 30 included in the second region R2 are occupied by skip via conductors 32, the first and second regions R1, R2 may each contain a mixture of stacked via conductors 31 and skip via conductors 32, or may contain a mixture of individual via conductors 12 that do not constitute connecting conductors 30. Even with such a configuration, the same effect as this embodiment can be achieved.

[0033] In addition, in this embodiment, the first and second regions R1, R2 are defined based on the density of the connecting conductors 30, but regardless of the distribution of the connecting conductors 30, the region where the stack via conductors 31 are arranged in a group may be defined as the first region R1, and the region where the skip via conductors 32 are arranged in a group may be defined as the second region R2.

[0034] Although the present specification and drawings disclose specific examples of the technology included in the scope of the claims, the technology described in the claims is not limited to these specific examples, but also includes various modifications and variations of the specific examples, and also includes parts of the specific examples taken out alone. [Explanation of symbols]

[0035] 10. Wiring board 12 Via conductor 20 Conductive layer 21 Insulating layer 30 Connecting conductor 31 Stacked via conductor 32 Skip via conductor R1 First Region R2 Second Region

Claims

1. a plurality of conductive layers and a plurality of insulating layers stacked alternately; a plurality of connection conductors, which are via conductors connecting conductive layers separated by two insulating layers; a first region in which the plurality of connecting conductors are arranged relatively densely; a second region in which the plurality of connection conductors are arranged more sparsely than in the first region, the plurality of connection conductors include stacked via conductors formed by stacking via conductors formed in each of the two insulating layers, and skip via conductors that are continuous across the two insulating layers; the plurality of connecting conductors in the first region are such that the stacked via conductors occupy more than the skip via conductors; In the plurality of connecting conductors in the second region, the skip via conductors occupy more than the stacked via conductors.

2. 2. The wiring board according to claim 1, The difference between the thickness of the conductive layer on the stacked via conductor in the first region and the thickness of the conductive layer on the skip via conductor in the second region is 1 μm or less.

3. 2. The wiring board according to claim 1, The recess in the top surface of the skip via conductor is 10 μm or less.

4. 3. The wiring board according to claim 1, The via diameter of the bottom end of the stack via conductor in the first region is approximately the same as the via diameter of the bottom end of the skip via conductor in the second region.

5. 3. The wiring board according to claim 1, The connection conductors in the first region are all the stacked via conductors, and the connection conductors in the second region are all the skip via conductors.

6. a plurality of conductive layers and a plurality of insulating layers stacked alternately; a plurality of connection conductors, which are via conductors connecting conductive layers separated by two insulating layers; a first region in which the plurality of connecting conductors are arranged relatively densely; a second region in which the plurality of connection conductors are arranged more sparsely than in the first region, forming stacked via conductors in the first region as the plurality of connection conductors, each of which is formed in one of the two insulating layers; and forming, in the second region, skip via conductors that are continuous across the two insulating layers as the plurality of connecting conductors.

7. 7. The method for manufacturing a wiring board according to claim 6, a first drilling step of drilling a lower layer via in a lower insulating layer of the two insulating layers in the first region to fill a lower via conductor of the stacked via conductor; a first plating step in which the lower layer vias are filled with via conductors and a conductive layer is laminated on the lower layer insulating layer in the first region; a second drilling step in which, in the first region, an upper layer via is drilled in an upper insulating layer of the two insulating layers to fill an upper side via conductor of the stacked via conductor, and in the second region, continuous vias are drilled continuously in the upper and lower layers of the two insulating layers to fill the skip via conductor; and a second plating process in which, in the first region and the second region, the upper layer vias are filled with the via conductors on the upper side of the stacked via conductors, the continuous vias are filled with the skip via conductors, and a conductive layer is stacked on the upper layer of the two insulating layers.

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