Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device with improved heat dissipation and bonding strength.SOLUTION: A semiconductor device according to an embodiment includes a substrate having a first main surface and a second main surface opposite to the first main surface, a first electrode provided on the first main surface, a second electrode provided on the second main surface, and a MOSFET provided on the substrate and having the first electrode as a drain electrode and the second electrode as a source electrode. The first electrode includes a layer region provided on the first major surface along the first major surface, and a first region extending from the first major surface into the substrate in a first direction from the first electrode toward the second electrode and adjacent to the layer region, and a lower surface of the first electrode protrudes in a direction opposite to the first direction in the first region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] The resistance of a vertical metal oxide semiconductor field effect transistor (MOSFET) used in a semiconductor device includes the resistance of the substrate and the resistance of the drain electrode, which also serves as a heat dissipation path for the semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 7381215 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device with improved heat dissipation and bonding strength. [Means for solving the problem]

[0005] The semiconductor device of the embodiment includes a substrate having a first main surface and a second main surface opposite the first main surface, a first electrode provided on the first main surface, a second electrode provided on the second main surface, and a MOSFET provided on the second main surface side of the substrate, with the first electrode as a drain electrode and the second electrode as a source electrode, wherein the first electrode has a layer region provided on the first main surface along the first main surface, and a first region extending from the first main surface into the substrate in a first direction from the first electrode to the second electrode and adjacent to the layer region, and the lower surface of the first electrode protrudes in the first region in a direction opposite to the first direction.

[0006] In another embodiment, a semiconductor device includes a substrate having a first main surface and a second main surface opposite the first main surface, a first electrode provided on the first main surface, a second electrode provided on the second main surface, and a MOSFET provided on the second main surface side of the substrate, the first electrode serving as a drain electrode and the second electrode as a source electrode, wherein the first electrode has a layer region provided on the first main surface along the first main surface, and a third region extending from the first main surface through the substrate in a first direction from the first electrode to the second electrode and adjacent to the layer region, and a lower surface of the first electrode is recessed in the third region toward the first direction. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 3] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. [Figure 4] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a second embodiment. [Figure 5] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a third embodiment. [Figure 6] FIG. 10 is a top view illustrating a semiconductor device according to a fourth embodiment. [Figure 7] FIG. 10 is a top view illustrating a semiconductor device according to a fourth embodiment. [Figure 8] FIG. 10 is a top view illustrating a semiconductor device according to a fourth embodiment. [Figure 9] FIG. 10 is a cross-sectional view taken along the XY plane, illustrating the semiconductor device according to the fifth embodiment. [Figure 10] FIG. 13 is a cross-sectional view taken along the XY plane, illustrating a first modified example of the semiconductor device according to the fifth embodiment. [Figure 11] FIG. 13 is a cross-sectional view taken along the XY plane, illustrating a second modified example of the semiconductor device according to the fifth embodiment. [Figure 12] FIG. 13 is a cross-sectional view illustrating a second modified example of the semiconductor device according to the fifth embodiment. [Figure 13] FIG. 10 is a cross-sectional view taken along the XY plane, illustrating a semiconductor device according to a sixth embodiment. [Figure 14A] 5A to 5C are cross-sectional views illustrating a step of providing a resist on the first main surface of the substrate. [Figure 14B] 10A to 10C are cross-sectional views illustrating a step of selectively digging the first main surface of the substrate. [Figure 14C] 10A to 10C are cross-sectional views illustrating a step of forming a first metal layer in the opening. [Figure 14D] 5A to 5C are cross-sectional views illustrating a step of forming a first electrode. [Figure 14E] 10A to 10C are cross-sectional views illustrating a step of forming a second metal layer. [Figure 14F] 10A to 10C are cross-sectional views showing a step of providing a chip on a conductive member. [Figure 14G] 10A to 10C are cross-sectional views illustrating a step of forming a bonding layer. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0009] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be different depending on the drawing.

[0010] For example, in the cross-sectional views shown in the present specification, some laminated structures are shown, but the thickness ratio of each layer in the laminated structure is not necessarily the same as that in reality. Even if one layer is shown thicker than another layer in the cross-sectional view, in reality, the thicknesses of one layer and the other layer may be approximately the same, or one layer may be thinner than the other layer. In other words, the dimensions such as thicknesses shown in the drawings in the present specification may differ from the actual dimensions.

[0011] The direction from the first electrode 11 to the second electrode 12 is defined as the Z direction (first direction). The direction perpendicular to the Z direction is defined as the X direction (second direction), and the direction intersecting the X and Z directions is defined as the Y direction (third direction). In this embodiment, the X direction, Y direction, and Z direction are shown as being orthogonal to each other, but they are not limited to being orthogonal as long as they intersect with each other.

[0012] For the sake of explanation, the positive direction in the Z direction is referred to as "up" and the negative direction in the Z direction is referred to as "down." However, the "up" and "down" directions are not limited to the direction of gravity or the direction when the semiconductor device is mounted. Furthermore, when referring to thickness, it refers to the length in the Z direction.

[0013] Facing each other via the first metal layer ML1 or the second metal layer ML2 may be referred to as contacting each other via the first metal layer ML1 or the second metal layer ML2, or simply contacting each other, or may be referred to as contacting each other.

[0014] In the following description, n + , n, n - and p + , p, p - The notation indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + shape, n - The shape is simply n-type, p-type + shape, p - The shape is sometimes simply referred to as p-shape.

[0015] In the present specification and the drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0016] (First embodiment) FIG. 1 is a cross-sectional view illustrating a semiconductor device 100 according to the first embodiment.

[0017] 1 is, for example, a MOSFET. The semiconductor device 100 includes a chip 10 having a first electrode 11, a substrate 20, a control region 40, an insulating layer 31, a second electrode 12, a plug 32, a bonding layer 50, and a conductive member 70. The first electrode 11 is, for example, a drain electrode of the MOSFET. The second electrode 12 is, for example, a source electrode of the MOSFET.

[0018] The substrate 20 has a first main surface 20a (lower surface) that intersects with the Z direction and a second main surface 20b (upper surface) located opposite the first main surface 20a. The first electrode 11 extends from the first main surface 20a through the substrate 20 in the positive direction of the Z direction. A first region 11a of the first electrode 11 extends through the substrate 20 in the Z direction. A layer region 11L of the first electrode 11 is provided along the first main surface 20a of the substrate 20. A first metal layer ML1 is interposed between the first electrode 11 and the substrate 20. The first electrode 11 contacts the bonding layer 50 on the lower surface via a second metal layer ML2. The control region 40 extends from the second main surface 20b through the substrate 20 in the negative direction of the Z direction.

[0019] The substrate 20 includes a first semiconductor region 21 (n + a drain region of a semiconductor layer), a second semiconductor region 22 (n ー a third semiconductor region 23 of the second conductivity type (a p-type base region), a fourth semiconductor region 24 of the first conductivity type (a n-type drift region), + a source region of the second conductivity type), a fifth semiconductor region 25 (p + a first conductivity type sixth semiconductor region 26 (n + It has a buffer area of ​​the shape.

[0020] The first semiconductor region 21 is provided on the first electrode 11 at a position closest to the first major surface 20a. The second semiconductor region 22 is provided on the first semiconductor region 21. It is desirable to provide a sixth semiconductor region 26 between the first semiconductor region 21 and the second semiconductor region 22. A third semiconductor region 23 is provided on the second semiconductor region 22. A fourth semiconductor region 24 is provided on the third semiconductor region 23.

[0021] The sixth semiconductor region 26 has a higher concentration of impurities of the first conductivity type than the second semiconductor region 22. The sixth semiconductor region 26 may have a higher concentration of impurities of the first conductivity type than the first semiconductor region 21.

[0022] The control region 40 has a first insulating film 41A in contact with the substrate 20, a conductive region 42 provided in the first insulating film 41A and facing the substrate 20 via the first insulating film 41A, and a gate electrode 43 provided above the conductive region 42 via a second insulating film 41B and facing the third semiconductor region 23 via a gate insulating film 41C. The conductive region 42 is a field plate connected to the second electrode 12, for example, by a structure not shown in FIG. 1. A plurality of control regions 40 are provided, and are arranged side by side in the X direction and extend in the Y direction, for example, as shown in FIG. 1. Alternatively, the control region 40 may be arranged in a lattice pattern in the XY plane.

[0023] An insulating layer 31 is provided to cover the control region 40. A second electrode 12 is provided on the insulating layer 31. A plug 32 extends through the insulating layer 31 and the fourth semiconductor region 24 of the first conductivity type and is electrically connected to the third semiconductor region 23 of the second conductivity type, and is electrically connected to the second electrode 12. The plug 32 is connected to the third semiconductor region 23 via the fifth semiconductor region 25.

[0024] The chip 10 is connected to the conductive member 70 via the bonding layer 50. The conductive member 70 and the first electrode 11 face each other via the bonding layer 50. A second metal layer ML2 may be interposed between the first electrode 11 and the bonding layer 50. The conductive member 70 is, for example, a die pad.

[0025] 1, a third electrode 13 is provided on the insulating layer 31 so as to be spaced apart from the second electrode 12. The third electrode 13 is, for example, a gate pad electrically connected to the gate electrode 43.

[0026] Furthermore, a conductive member (not shown in FIG. 1) may be provided on the second electrode 12 and the third electrode 13 via a bonding layer (not shown in FIG. 1). The conductive member is, for example, a metal plate such as a connector. The third electrode 13 may be provided with a bonding wire instead of a connector.

[0027] Next, an example of the material of each component will be described.

[0028] The first electrode 11 is made of a metal containing, for example, Cu. The second electrode 12 is made of a metal containing, for example, Cu or Al. The first metal layer ML1 contains at least one of Ti, Cu, Ta, N, TiCu, TiNCu, TiN, and TaN. The first metal layer ML1 desirably has a structure of at least two layers, in which a layer containing Ti and a layer containing Cu are stacked in the direction from the substrate 20 toward the first electrode 11.

[0029] The substrate 20 is a semiconductor containing at least one of, for example, C, Si, Ge, SiC, GaN, and AlN. The semiconductor layer of the first conductivity type is formed by implanting, for example, N, P, or As into the substrate 20 and then thermally diffusing the implanted ions. The semiconductor layer of the second conductivity type is formed by implanting, for example, B or Ga into the substrate 20 and then thermally diffusing the implanted ions.

[0030] The first insulating film 41A, the second insulating film 41B, and the gate insulating film 41C are, for example, oxide films containing silicon oxide such as SiO2. The conductive region 42 is, for example, conductive polysilicon containing impurities. The gate electrode 43 is, for example, conductive polysilicon containing impurities.

[0031] The insulating layer 31 is an oxide film containing silicon oxide such as SiO2, etc. The plug 32 is a metal containing Al or W, for example.

[0032] The bonding layer 50 is, for example, solder. The bonding layer 50 contains at least one metal element, for example, Sn, Pb, or Ag. The second metal layer ML2 contains at least one metal element, for example, Ti, Ni, Ag, or Au. The second metal layer ML2 contains Ti and Ni, and desirably contains Ag or Au, and further desirably has a three-layer structure in which Ti, Ni, and Ag are layered in this order from the first electrode 11 toward the bonding layer 50. The conductive member 70 contains, for example, Cu.

[0033] To summarize the thermal conductivity of each material, the thermal conductivity of the first electrode 11 is higher than that of the substrate 20. The thermal conductivity of the substrate 20 is higher than that of the bonding layer 50. The thermal conductivity of the first electrode 11 and that of the conductive member 70 are, for example, approximately the same. Specifically, the thermal conductivity of Cu is approximately 398 W / mK, the thermal conductivity of Si is approximately 160 W / mK, and the thermal conductivity of solder is approximately 49 W / mK.

[0034] Next, the structures of the first electrode 11 and the bonding layer 50 will be further described.

[0035] The first electrode 11 has a first region 11a extending through the substrate 20 in a direction from the first major surface 20a toward the second electrode 12, and a layer region 11L provided adjacent to the first region 11a along the first major surface 20a. The first region 11a faces the first semiconductor region 21 in the X direction. The first region 11a is located in the first semiconductor region 21 in the negative direction of the Z direction relative to the sixth semiconductor region 26.

[0036] At least a part of the first region 11a is located in the negative Z direction relative to the layer region 11L. The lower surface of the first electrode 11 protrudes in the negative Z direction in the first region 11a.

[0037] Here, the term "the surface of a certain region protrudes in the negative Z direction" means that the profile of the surface shape in the X direction is convex in the negative Z direction, and the absolute value of the step of the convex shape from the apex of the convex shape in the positive and negative X directions is equal to or greater than a predetermined length. Here, the predetermined length is, for example, 1.0 μm. The predetermined length may be 2.0 μm or 3.0 μm. Alternatively, the predetermined length may be 4.0 μm or 5.0 μm.

[0038] As will be described later, the term "the surface of a certain region is recessed in the positive Z direction" means that the surface shape profile in the X direction is recessed in the positive Z direction, and the absolute value of the step of the recess from the bottom of the recess in the positive and negative X directions is equal to or greater than a predetermined length. Here, the predetermined length is, for example, 5.0 μm. The predetermined length may also be 10.0 μm, 20.0 μm, or 30.0 μm.

[0039] Conversely, a flat surface is a structure that is neither protruding nor recessed, i.e., a flat surface that does not have a step of a predetermined length or more. Here, the predetermined length is, for example, 1.0 μm. The predetermined length may be 2.0 μm or 3.0 μm. Alternatively, the predetermined length may be 4.0 μm or 5.0 μm.

[0040] The lower surface of the first electrode 11 is covered with a second metal layer ML2. A bonding layer 50 is provided between the second metal layer ML2 and the conductive member 70. The upper surface of the conductive member 70 is, for example, flat. The first electrode 11 and the bonding layer 50 are in contact with each other via the second metal layer ML2.

[0041] The thickness of the bonding layer 50 in the Z direction is smaller in a region in contact with the first region 11a than in a region in contact with the layer region 11L. The thickness of the bonding layer 50 in the Z direction may be zero in a region in contact with the first region 11a. That is, the bonding layer 50 may not be present below the first region 11a, and a portion of the lower surface of the first electrode 11 below the first region 11a may be in contact with the conductive member 70 without being covered by the bonding layer 50. The bonding layer 50 may be interposed between the first region 11a and the conductive member 70, and the first region 11a and the conductive member 70 may be in contact with each other via the second metal layer ML2. Alternatively, the bonding layer 50 may not be interposed between the first region 11a and the conductive member 70, and the first region 11a and the conductive member 70 may be in contact with each other via the second metal layer ML2. From the viewpoint of heat dissipation, which will be described later, it is desirable to make the bonding layer 50 below the first region 11a thinner.

[0042] The operation of the semiconductor device 100 will now be described.

[0043] First, when a voltage is applied to the gate electrode 43 and exceeds the threshold voltage, a channel is formed in the third semiconductor region 23 facing the gate electrode 43 via the gate insulating film 41C. For example, an n-type channel is formed in the third semiconductor region 23, which is a p-type base region. In this way, the semiconductor device 100 is turned on.

[0044] Subsequently, when a positive voltage is applied to the first electrode 11 with the second electrode 12 as the reference, for example, a current flows from the first electrode 11 to the second electrode 12. The current flows to the second electrode 12 via the first electrode 11, the first semiconductor region 21, the sixth semiconductor region 26, the second semiconductor region 22, the channel formed in the third semiconductor region 23, the fourth semiconductor region 24, and the plug 32.

[0045] Next, when the voltage applied to the gate electrode 43 is made smaller than the threshold voltage, the channel of the third semiconductor region 23 disappears, and the semiconductor device 100 enters the OFF state.

[0046] When the semiconductor device 100 is switched to the OFF state, the electrons accumulated in the second semiconductor region 22 during the ON state are discharged from the first electrode 11, and the depletion layer expands.

[0047] The depletion layer spreads from the second electrode 12 toward the first electrode 11, but by controlling the potential of the conductive region 42 to be the same as the potential of the first electrode 11 or the second electrode 12, for example, the spread of the depletion layer is promoted and the electric field concentration is alleviated.

[0048] Furthermore, the sixth semiconductor region 26 has a higher impurity concentration than the second semiconductor region 22, and the expansion of the depletion layer can be reliably stopped in the sixth semiconductor region 26. The sixth semiconductor region 26 suppresses punch-through caused by contact between the depletion layer and the first electrode 11, and a stable turn-off operation can be achieved.

[0049] According to the semiconductor device 100 of this embodiment, the reliability of the semiconductor device can be improved by improving the heat dissipation from the chip 10 to the conductive member 70. At the same time, the bonding strength between the chip 10 and the conductive member 70 can be improved by increasing the thickness of the bonding layer 50 in the Z direction below the layer region 11L. Generally, uniformly reducing the thickness of the bonding layer 50 in the Z direction in order to improve heat dissipation may reduce the bonding strength. According to the semiconductor device of this embodiment, the trade-off between heat dissipation and bonding strength can be improved.

[0050] The first electrode 11, which has a higher thermal conductivity than the substrate 20 and the bonding layer 50, serves as a path for the heat flow, and the heat generated in the substrate 20 is efficiently released to the conductive member 70 through the first electrode 11. This prevents heat from accumulating in the substrate 20, improving the reliability of the semiconductor device.

[0051] The heat flow paths P1 and P2 shown in FIG. 1 will be compared for explanation. Path P1 runs from the substrate 20, through the first region 11a, and to the conductive member 70. The Z-direction thickness of the bonding layer 50 through which path P1 passes is smaller than that of path P2. On the other hand, the Z-direction thickness of the first electrode 11 through which path P1 passes is greater than that of path P2. Because the first electrode 11 has a higher thermal conductivity than the bonding layer 50 and the substrate 20, path P1 allows heat to flow more easily than path P2.

[0052] The path P2 passes through a portion of the substrate 20 that is located between the first regions 11a in the X direction. The substrate 20 has a lower thermal conductivity than the first electrode 11, and the path P2 has a smaller thermal conductance than the path P1.

[0053] According to the semiconductor device of this embodiment, the efficiency of heat dissipation from the chip 10 to the conductive member 70 can be improved by providing a heat dissipation path that passes through the path P1.

[0054] On the other hand, since the bonding layer 50 is thick in the Z direction at the portion where the layer region 11L and the second metal layer ML2 are in contact with each other, it is possible to maintain the bonding strength between the chip 10 and the conductive member 70. In particular, compared to an example in which the thickness of the entire bonding layer 50 in the Z direction is uniformly reduced to improve heat dissipation, this embodiment maintains the thickness in the Z direction at a portion of the bonding layer 50, thereby making it possible to increase the bonding strength between the chip 10 and the conductive member 70.

[0055] By forming the first region 11a so that the lower surface of the first electrode 11 has a step in the first region 11a that is equal to or greater than the thickness of the bonding layer 50 required to maintain the bonding strength between the chip 10 and the conductive member 70, it is possible to maintain the bonding strength between the chip 10 and the conductive member 70. By adjusting the shape of the first region 11a and the amount of material supplied that forms the bonding layer 50, it is possible to maintain the bonding strength.

[0056] The first metal layer ML1 contains, for example, Ti, and prevents atoms contained in the first electrode 11 from diffusing into the substrate 20, thereby maintaining the reliability of the semiconductor device 100. The second metal layer ML2 contains an element having a higher solder wettability than the first electrode 11. By providing the second metal layer ML2 between the first electrode 11 and the bonding layer 50, the bonding strength of the bonding layer 50 can be further increased. Furthermore, by providing the second metal layer ML2 between the first electrode 11 and the bonding layer 50, for example, when the first electrode 11 contains Cu and the bonding layer 50 contains solder, the first electrode 11 is prevented from being corroded by the bonding layer 50. If the bonding layer 50 corrodes the first electrode 11, the bonding layer 50 may come into contact with the substrate 20. It is also known that the adhesion between the bonding layer 50 and a substrate 20 containing, for example, Si, is lower than the adhesion between the bonding layer 50 and the first electrode 11. According to the semiconductor device of this embodiment, contact between the bonding layer 50 and the substrate 20 is suppressed, thereby suppressing a decrease in the bonding strength between the chip 10 and the conductive member 70, and improving the reliability of the semiconductor device.

[0057] (Modification of the first embodiment) 2 is a cross-sectional view of a semiconductor device 101 according to a modification of the first embodiment. Description of parts common to the semiconductor device 100 shown in FIG.

[0058] The first electrode 11 has a second region 11b that is separated from the first region 11a in the X direction and has a length in the X direction greater than that of the first region 11a. The second region 11b is adjacent to the layer region 11L. The second region 11b extends within the substrate 20 and faces the first semiconductor region 21 in the X direction.

[0059] The length of the second region 11b in the X direction is, for example, 1.5 times or more the length of the first region 11a in the X direction. The length of the second region 11b in the X direction may be two times or more, or may be three times or more the length of the first region 11a in the X direction. The length of the first region 11a in the X direction is, for example, 10 μm or more and less than 30 μm. The length of the second region 11b in the X direction is, for example, 30 μm or more and less than 60 μm.

[0060] The second region 11b does not need to be longer in the X direction than the first region 11a, and may be longer in the Y direction, or the lengths in the X direction do not necessarily have to be different and may extend to a position closer to the sixth semiconductor region 26 than the first region 11a. In order to suppress contact between the depletion layer and the first electrode 11 when the semiconductor device 100 is turned off, it is desirable that the first semiconductor region 21 be interposed between the second region 11b and the sixth semiconductor region 26. The distance in the Z direction between the first region 11a and the second region 11b and the second electrode 12 is longer than the distance in the Z direction between the first semiconductor region 21 and the second electrode 12.

[0061] For example, the sixth semiconductor region 26 is formed along the XY plane. Note that it is desirable from the viewpoint of manufacturing efficiency to have the distances between the first region 11a and the sixth semiconductor region 26 equal to the distances between the first region 11a and the second region 11b, because this allows the first region 11a and the second region 11b to be formed simultaneously.

[0062] The lower surface of the first electrode 11 is located in the positive Z direction in the second region 11b than in the first region 11a. The lower surface of the first electrode 11 is a flat surface parallel to the XY plane in the second region 11b, as shown in Fig. 2, for example. The lower surface of the first electrode 11 may protrude in the negative Z direction in the second region 11b by a step that is smaller than the step in the first region 11a.

[0063] The Z-direction thickness of the first electrode 11 in the second region 11b is greater than the Z-direction thickness of the layer region 11L. The Z-direction thickness of the first electrode 11 in the first region 11a is at least partially greater than the Z-direction thickness of the first electrode 11 in the second region 11b.

[0064] The semiconductor device 101 according to this modification can further improve the trade-off between heat dissipation and bonding strength. By providing the second region 11b that is wider in the X direction, the second region 11b, which has a higher thermal conductivity than the substrate 20, can serve as a heat dissipation path, improving heat dissipation. Meanwhile, below the second region 11b, the thickness of the bonding layer 50 in the Z direction is greater than that of the first region 11a, so that the bonding strength between the chip 10 and the conductive member 70 can be maintained strong.

[0065] For comparison, when improving heat dissipation by the first regions 11a, the area of ​​the region with a small thickness in the Z direction of the bonding layer 50 or the proportion of the area in the semiconductor device increases as the number or density of the first regions 11a increases. On the other hand, according to this modification, the heat dissipation is improved by the second regions 11b, which have a higher thermal conductivity than the substrate 20, and at the same time, the bonding layer 50 can be made thicker in the Z direction below the second regions 11b than below the first regions 11a. Therefore, it is possible to further improve the trade-off between heat dissipation and bonding strength.

[0066] (Second embodiment) 3 is a cross-sectional view of a semiconductor device 200 according to the second embodiment. Description of parts common to the semiconductor device 100 shown in FIG.

[0067] The first electrode 11 of the semiconductor device 200 has a third region 11c extending through the substrate 20 from the first main surface 20a toward the second electrode 12, and a layer region 11L provided adjacent to the third region 11c along the first main surface 20a of the substrate 20. The first electrode 11 has a lower surface that is recessed in the positive direction of the Z direction in the third region 11c, and a flat lower surface in the layer region 11L. The first electrode 11 is formed thicker in the Z direction in the third region 11c than in the layer region 11L.

[0068] The length of the third region 11c in the X direction is, for example, 60 μm or more and half or less of the length of the chip 10 in the X direction. If the length of the chip 10 in the X direction is, for example, 3 mm, the length of the third region 11c in the X direction is 1.5 mm or less. Furthermore, the length of the chip 10 in the Y direction may be, for example, equal to the length of the chip 10 in the X direction, and the length of the third region 11c in the X direction is half or less of the length of the chip 10 in the Y direction.

[0069] The bonding layer 50 is provided to be thicker below the third region 11c than below the layer region 11L. At least a part of the upper surface of the bonding layer 50 below the third region 11c is located in the positive Z direction relative to the upper surface of the bonding layer 50 below the layer region 11L.

[0070] According to the semiconductor device 200 of this embodiment, the trade-off between heat dissipation and bonding strength can be improved by providing a third region 11c having a higher thermal conductivity than the substrate 20 above the region where the bonding layer 50 is provided thickly in the Z direction.

[0071] By forming the bonding layer 50 thicker below the third region 11c, it is possible to improve the strength of the bond between the chip 10 and the conductive member 70. Furthermore, by controlling the shape of the depression in the lower surface of the first electrode 11 formed in the third region 11c and adjusting the amount of material supplied for the bonding layer 50, it is possible to control the thickness in the Z direction of the bonding layer 50 below the third region 11c. Therefore, it is possible to design a semiconductor device so as to achieve the required bonding strength.

[0072] By maintaining the bonding strength below the third region 11c, the bonding layer 50 below the layer region 11L can be formed thin in the Z direction. By thinning the bonding layer 50, which has a relatively low thermal conductivity, the thermal conductance of the path P3 of the heat flow from the layer region 11L through the bonding layer 50 to the conductive member 70 can be increased, thereby improving heat dissipation.

[0073] Furthermore, the third region 11c is located above the portion where the bonding layer 50 is thick, and the heat dissipation performance can be improved when the third region 11c has a higher thermal conductivity than the substrate 20. That is, for the path P4, while the bonding layer 50 is thick, a decrease in thermal conductance can be suppressed by passing through the third region 11c.

[0074] (Modification of the second embodiment) 4 is a cross-sectional view of a semiconductor device 201 according to the second embodiment. Description of parts common to the semiconductor device 200 shown in FIG.

[0075] The first electrode 11 has a second region 11b separated from the third region 11c in the X direction. The second region 11b is provided adjacent to the layer region 11L. In the second region 11b, at least a part of the lower surface of the first electrode 11 is located in the negative direction of the Z direction relative to the third region 11c. In the second region 11b, the lower surface of the first electrode 11 is, for example, a flat surface parallel to the XY plane. In the second region 11b, the lower surface of the first electrode 11 may have a step that is smaller than the step in the third region 11c and may have a structure that is recessed in the positive direction of the Z direction.

[0076] The length in the X direction of the second region 11b is smaller than the length in the X direction of the third region 11c. The length in the X direction of the third region 11c is, for example, 1.5 times or more the length in the X direction of the second region 11b. The length in the X direction of the third region 11c may be, for example, twice or more the length in the X direction of the second region 11b. The length in the X direction of the second region 11b is, for example, 30 μm or more and less than 60 μm. The length in the X direction of the third region 11c is, for example, 60 μm or more and half or less the length in the X direction of the chip 10.

[0077] The second region 11b does not need to have a smaller length in the X direction than the third region 11c, and may have a smaller length in the Y direction. Alternatively, the lengths in the X direction do not necessarily have to be different, and the second region 11b may be located farther away from the sixth semiconductor region 26 than the third region 11c. For example, the sixth semiconductor region 26 is formed along the XY plane. From the viewpoint of manufacturing efficiency, it is desirable that the distances between the second region 11b and the third region 11c and the sixth semiconductor region 26 are equal, since this allows the second region 11b and the third region 11c to be formed simultaneously.

[0078] The bonding layer 50 below the second region 11b is provided thinner in the Z direction than the bonding layer 50 below the third region 11c. The bonding layer 50 below the second region 11b may be provided thicker or thinner in the Z direction than the bonding layer 50 below the layer region 11L.

[0079] The semiconductor device 201 according to this modification can further improve heat dissipation. By forming the second region 11b from a material having a higher thermal conductivity than the substrate 20, the thermal conductance of the path of heat flow passing through the second region 11b can be increased compared to when the second region 11b is not provided.

[0080] On the other hand, the bonding layer 50, which has a relatively low thermal conductivity, is provided thinner in the Z direction below the second region 11b than below the third region 11c, which suppresses a decrease in thermal conductance, thereby improving the heat dissipation performance of the heat dissipation path passing through the second region 11b.

[0081] The bonding strength between the chip 10 and the conductive member 70 can be maintained by the bonding layer 50 that is provided thicker below the third region 11c. By controlling the size of the step that the lower surface of the first electrode 11 has in the third region 11c and by controlling the thickness in the Z direction of the bonding layer 50 below the layer region 11L, it is possible to determine the thickness in the Z direction of the bonding layer 50 below the third region 11c and maintain the bonding strength.

[0082] (Third embodiment) 5 is a cross-sectional view of a semiconductor device 300 according to the third embodiment. Descriptions of parts common to the semiconductor devices 100 and 200 shown in FIGS.

[0083] The semiconductor device 300 has a first region 11a and a third region 11c spaced apart from the first region 11a in the X direction. The semiconductor device 300 has a structure in which the underside of the first electrode 11 protrudes in the negative Z direction in the first region 11a and is recessed in the positive Z direction in the third region 11c. The length of the first region 11a in the X direction is shorter than the length of the third region 11c in the X direction.

[0084] The first region 11a does not need to have a smaller length in the X direction than the third region 11c, and may have a smaller length in the Y direction. Alternatively, the lengths of the first region 11a in the X direction do not necessarily have to be different, and the first region 11a may be located farther from the sixth semiconductor region 26 than the third region 11c. For example, the sixth semiconductor region 26 is formed along the XY plane. From the viewpoint of manufacturing efficiency, it is desirable that the distances between the first region 11a and the third region 11c and the sixth semiconductor region 26 are equal, since this allows the first region 11a and the third region 11c to be formed simultaneously.

[0085] The first electrode 11 further has a layer region 11L adjacent to the first region 11a and the third region 11c, and the thickness in the Z direction of the bonding layer 50 below the third region 11c is greater than the thickness in the Z direction of the bonding layer 50 below the layer region 11L. Also, the thickness in the Z direction of the bonding layer 50 below the layer region 11L is greater than the thickness in the Z direction of the bonding layer 50 below the first region 11a. The bonding layer 50 does not need to be provided over the entire upper surface of the conductive member 70, and the first region 11a may be in direct contact with the conductive member 70 via the second metal layer ML2.

[0086] The semiconductor device 300 according to this embodiment can improve heat dissipation and the bonding strength between the chip 10 and the conductive member 70. The heat dissipation is improved by improving the thermal conductance of the heat flow path passing through the first region 11a. The bonding strength between the chip 10 and the conductive member 70 is improved by forming the bonding layer 50 below the third region 11c thicker in the Z direction.

[0087] Compared to the semiconductor device 100 according to the first embodiment, the present embodiment can further improve heat dissipation by reducing the thickness in the Z direction of the bonding layer 50 below the layer region 11L. Even when the bonding layer 50 below the layer region 11L is thinned in the Z direction, the bonding strength between the chip 10 and the conductive member 70 can be maintained because the bonding layer 50 below the third region 11c is formed thick in the Z direction.

[0088] This allows for a wider range of selection of the thickness in the Z direction of the bonding layer 50 below the layer region 11L. Even if the thickness in the Z direction of the bonding layer 50 below the layer region 11L is approximately the same as the step of the structure protruding in the negative Z direction on the underside of the first electrode 11 in the first region 11a, the bonding strength between the chip 10 and the conductive member 70 can be maintained. Therefore, there is no need for the bonding layer 50 to be interposed between the first region 11a and the conductive member 70. The thermal conductance can be further improved by providing a heat flow path that does not involve the bonding layer 50.

[0089] Compared to the semiconductor device 200 according to the second embodiment, the present embodiment can improve heat dissipation by thinning the bonding layer 50 below the first region 11a. The thickness of the bonding layer 50 in the Z direction below the layer region 11L can be selected from a wide range between the present embodiment and the second embodiment. In the present embodiment, the first region 11a is further formed, so that the bonding layer 50 is formed thinner in the Z direction below the first region 11a than below the layer region 11L, thereby improving heat dissipation.

[0090] (Fourth embodiment) 6, 7, and 8 are top views showing a semiconductor device according to a fourth embodiment. The views show the chip 10 as viewed from the positive Z direction. A second electrode 12 provided on the top surface of the chip 10 and a third electrode 13 spaced apart from the second electrode 12 are shown. The second electrode 12 is, for example, a source electrode. The third electrode 13 is, for example, a gate pad. First, a description will be given with reference to FIG. 6.

[0091] 6 is an example in which a third electrode 13 is provided at one corner of a chip 10, and a second electrode 12 is provided at a distance in the X and Y directions from the third electrode 13. Note that the third electrode 13 is not limited to being provided at a corner of the chip, and may be located at an edge of the chip.

[0092] Here, we define a boundary region A where heat dissipation is generally likely to decrease. Boundary region A is defined on the XY plane of chip 10 and is a region that does not overlap with second electrode 12 and third electrode 13 in the Z direction. Since second electrode 12 and third electrode 13 are the main heat dissipation paths for heat flow on the top surface of chip 10, boundary region A is generally prone to heat dissipation.

[0093] The boundary region A includes an end region At located at the end of the chip 10, on the periphery of the second electrode 12, and an inter-electrode region Ags, which is the space between the second electrode 12 and the third electrode 13. The inter-electrode region Ags includes a first portion extending in the X direction and a second portion extending in the Y direction.

[0094] The semiconductor device 400 according to this embodiment has a structure that improves heat dissipation from the underside of the chip 10 at a position corresponding to the boundary region A. Taking the semiconductor device 100 as an example, a first region 11a of the first electrode 11 is formed on the underside of the chip 10 at a position corresponding to the boundary region A in the negative Z direction. In the boundary region A, the path P1 of the heat flow that passes through the first region 11a is a heat dissipation path with large thermal conductance.

[0095] The first regions 11a formed at positions corresponding to the boundary region A are provided so as to surround the second electrodes 12, for example, along the terminal region At. The first regions 11a may be formed in multiple rows, extending along the terminal region At so as to surround the second electrodes 12 in multiple layers. Also, in the inter-electrode region Ags, the first regions 11a are formed in multiple rows, for example, along the inter-electrode region Ags. The first regions 11a are not necessarily formed along the boundary region A, but it is desirable to form the first regions 11a along the boundary region A in order to provide a wider first region 11a at a position corresponding to the boundary region A.

[0096] 7, a plurality of second electrodes 12 may be formed. The boundary region A may further include an inter-electrode region Ass located between the second electrodes 12. The first regions 11a are provided in one or more rows, for example, extending along the inter-electrode region Ass.

[0097] Furthermore, as shown in the semiconductor device 402 of FIG. 8, the third electrode does not need to be located at the edge of the chip 10, but may be provided in the center of the chip 10. Here, the center of a certain area refers to the area located in the center of the area in the XY plane. The third electrode 13 is surrounded by the second electrode 12. The inter-electrode area Ags is located, for example, in a ring shape. The first area 11a is formed in multiple rows, for example, extending along the inter-electrode area Ags so as to surround the third electrode 13 in multiple rows.

[0098] The structure in which the first region 11a of the first electrode 11 is formed on the underside of the chip 10 at a position corresponding to the boundary region A in the negative Z direction is not limited to the semiconductor device 100, but can also be applied to the semiconductor device 101 having the second region 11b in addition to the first region 11a, or the semiconductor device 300 having the third region 11c in addition to the first region 11a. In the semiconductor device 101 or 300, the first region 11a of the first electrode 11 can be formed on the underside of the chip 10 at a position corresponding to the boundary region A.

[0099] 4 as an example, second regions 11b are formed at positions corresponding to boundary region A in the negative Z direction. The second regions 11b are formed in one or more rows, for example, extending along termination region At so as to surround second electrode 12. Also, in inter-electrode region Ags, second regions 11b are formed in multiple rows, for example, aligned along inter-electrode region Ags. In other words, it is not necessarily first region 11a that is provided at the position corresponding to boundary region A, but may be second region 11b.

[0100] According to the semiconductor device 400 of this embodiment, the reliability of the semiconductor device can be improved by improving the heat dissipation in the boundary region A. For example, by making the path P1 of the semiconductor device 100 a path for heat flow in the boundary region A, the thermal conductance is increased and the heat dissipation is improved. By improving the heat dissipation in the boundary region A, where heat dissipation is likely to be reduced due to the absence of electrodes on the top surface of the chip 10, localized heat accumulation in the chip 10 is suppressed, and thermal destruction is suppressed.

[0101] Taking the semiconductor device 100 as an example, by providing the first region 11a in the boundary region A, the heat dissipation performance of the boundary region A is improved, while in regions other than the boundary region A, for example, in the central portion of the chip 10, a layer region 11L can be provided with an area sufficient to maintain the bonding strength between the chip 10 and the conductive member 70. In the central portion of the chip 10, the bonding layer 50 below the layer region 11L maintains the bonding strength between the chip 10 and the conductive member 70.

[0102] Furthermore, in the semiconductor device 101, the first region 11a can be provided in the boundary region A, and the second region 11b can be provided in the central portion of the chip 10. Therefore, compared to the semiconductor device 100 having the first region 11a and the layer region 11L, the second region 11b, which has a larger thermal conductance than the layer region 11L, can be provided in the central portion of the chip 10, thereby improving the heat dissipation performance in the central portion of the chip 10. Furthermore, in the semiconductor device 300, the bonding strength in the central portion of the chip 10 can be further improved by providing the third region 11c in the central portion of the chip.

[0103] Taking semiconductor device 201 as an example, by providing second region 11b at a position corresponding to boundary region A, the thermal conductance is increased in the path of the heat flow passing through second region 11b, which contains a material with a higher thermal conductivity than substrate 20, thereby improving the heat dissipation performance of boundary region A. On the other hand, by providing third region 11c at a position corresponding to a region other than boundary region A, for example, at a position corresponding to the center of chip 10, the bonding strength between chip 10 and conductive member 70 can be maintained.

[0104] (Fifth embodiment) 9 is a cross-sectional view along the XY plane showing a semiconductor device 500 according to a fifth embodiment. The cross section in the XY plane taken along line P1-P2 shown in FIG. 5 is viewed from the negative Z direction. The first electrode 11 provided in the first semiconductor region 21 of the substrate 20 is shown. The second electrode 12 overlapping in the positive Z direction is shown as a region surrounded by a dotted line. While FIG. 9 shows an example in which the second electrode 12 is rectangular in the XY plane, the shape of the second electrode 12 is not limited to a rectangle.

[0105] 9 to 11 show a portion of the first semiconductor region 21 that overlaps with the second electrode 12 in the Z direction, and do not show a portion that overlaps with, for example, the third electrode 13 in the Z direction. However, a third electrode 13 (not shown) may be provided on the top surface of the chip 10, spaced apart from the second electrode 12 shown by the dotted line, and another second electrode 12 (not shown) may also be provided. That is, although not shown in FIG. 9, for example, inter-electrode regions Ags and Ass or a termination region At shown in FIG. 7 may be located around the second electrode 12.

[0106] A plurality of first regions 11a of the first electrode 11 are arranged in the X direction and extend in the Y direction. Although not shown in FIG. 9, a plurality of control regions 40 are arranged in the X direction on the upper surface of the substrate 20 and extend in the Y direction. The extension direction of the control regions 40 is indicated by an arrow along the Y direction in FIG. 9. The first regions 11a are provided so as to extend in the same direction as the extension of the control regions 40.

[0107] Note that the channels formed in the third semiconductor region 23 by the voltage applied to the gate electrode 43 are formed along the control region 40, and therefore are aligned in multiple locations in the X direction and extend in the Y direction. When the semiconductor device is in the on state, current mainly flows through the portion of the region that overlaps with the second electrode 12 in the Z direction and is surrounded by a dotted line, where the channels are formed. In other words, when the semiconductor device is in the on state, multiple portions through which current flows and heat is generated are aligned in the X direction and extend in the Y direction.

[0108] The first region 11a of the first electrode 11 is preferably provided in the X direction between control regions 40 adjacent to each other in the X direction on the upper surface of the substrate 20, and overlaps in the Z direction with the channel formed in the third semiconductor region 23. The greater the overlap in the Z direction between the channel formed in the third semiconductor region 23 and the first region 11a of the first region 11, the more improved the heat dissipation performance for heat generated from the channel.

[0109] 9 is not limited to having the first region 11a, but may also have a third region 11c. The third regions 11c are arranged side by side in the X direction and extend in the Y direction. In this case, the path P3 shown in FIG. 3 extends along the Y direction, which is the extension direction of the control region 40.

[0110] The semiconductor device 500 according to this embodiment can further improve the heat dissipation performance of the semiconductor device. The bonding layer 50 below the first region 11a is formed thinner than the other regions, and the path of heat flow passing through the first region 11a has high thermal conductance. By providing the first region 11a along the direction in which the channel is formed, heat generated mainly in the channel through which current flows can be efficiently dissipated to the conductive member 70.

[0111] When the semiconductor device is in an on-state, heat generated from the channel when a current flows through the channel is dissipated through the first region 11a, thereby making it possible to prevent thermal destruction of the semiconductor device.

[0112] According to the semiconductor device of this embodiment, the first region 11a extending in the Y direction can dissipate heat generated by the channel extending in the Y direction, thereby improving heat dissipation. At each position in the Y direction where heat is generated by the channel, the first region 11a extending in the Y direction serves as a heat dissipation path, preventing localized heat accumulation.

[0113] Furthermore, when the first electrode 11 has the third region 11c, as described with reference to Figure 3, path P3, which is a heat dissipation path with large thermal conductance, extends along the direction in which the channel extends, thereby improving the heat dissipation performance of the semiconductor device via path P3.

[0114] (First modified example of the fifth embodiment) 10 shows a cross-sectional view along the XY plane of a semiconductor device 501 according to a first modification of the fifth embodiment. As shown in Fig. 10, the first regions 11a may extend in a direction perpendicular to the extension direction of the control region 40. The first regions 11a extend in the X direction and are formed in multiple rows in the Y direction.

[0115] The length of one period of the periodically arranged structure is defined as the pitch. When referring to the pitch in the Y direction of the first regions 11a shown in FIG. 10, it refers to the length between the centers of adjacent first regions 11a in the Y direction. The pitch in the X direction of the control regions 40 arranged in the X direction and the pitch in the Y direction of the first regions 11a arranged in the Y direction may be different. For example, the pitch in the X direction of the control regions 40 is smaller than the pitch in the Y direction of the first regions 11a.

[0116] Furthermore, the extension direction of the first region 11a does not need to be perpendicular to the extension direction of the control region 40, but only needs to intersect with it. When the semiconductor device 501 is on, the channels that extend in the Y direction and are aligned in the X direction do not need to be perpendicular to the first region 11a, but only needs to intersect with it.

[0117] According to the semiconductor device 501 of this modification, even if the pitch of the control region 40 in the X direction and the pitch of the first region 11a in the Y direction are different, the heat generated in the channel when the semiconductor device is on can be efficiently dissipated by the first region 11a.

[0118] Each of the first regions 11a extending in the X direction overlaps in the Z direction with a plurality of channels extending in the Y direction and aligned in the X direction. That is, each of the first regions 11a extending in the X direction serves as a heat dissipation path from the plurality of channels.

[0119] Each of the multiple channels aligned in the X direction and the first region 11a extending in the X direction at least partially overlap in the Z direction. Therefore, a heat dissipation path is uniformly provided for each of the multiple channels aligned in the X direction. Even if the pitch of the control region 40 in the X direction is smaller than the pitch of the first region 11a, differences in heat dissipation performance among the multiple channels are suppressed.

[0120] 9, if the pitch of the control regions 40 in the X direction is smaller than the pitch of the first regions 11a in the semiconductor device 500 in the X direction, regions with high and low heat dissipation properties may be created in the XY plane. If multiple control regions 40 are provided between adjacent first regions 11a in the X direction, the heat dissipation properties of the channels near the middle of the adjacent first regions 11a in the X direction may be poorer than those of the portions closer to the first regions 11a. In other words, among the multiple channels lined up in the X direction, there may be locally some channels with high heat dissipation properties and some channels with poor heat dissipation properties.

[0121] On the other hand, according to the semiconductor device 501 of this modification, even if the pitch of the control regions 40 in the X direction is smaller than the pitch of the first regions 11a in the Y direction, the heat dissipation performance of each of the multiple channels aligned in the X direction can be improved more uniformly. This prevents localized areas with poor heat dissipation performance, thereby further improving the reliability of the semiconductor device.

[0122] 9, the heat dissipation performance of each of the channels extending in the Y direction is uniformly improved in the Y direction, thereby preventing localized areas with poor heat dissipation performance from occurring within a single channel that is continuous in the Y direction. Meanwhile, the semiconductor device 501 according to this modification prevents localized areas with poor heat dissipation performance from occurring among multiple channels aligned in the X direction. In either case, the occurrence of localized areas with poor heat dissipation performance can be prevented, thereby improving the reliability of the semiconductor device.

[0123] Furthermore, the semiconductor device 501 according to this modification can further improve the reliability of the semiconductor device by reducing warpage of the chip 10. Trenches are provided in the Z direction on each of the first main surface 20a and the second main surface 20b of the substrate 20 of the chip 10. The trenches provided on the first main surface 20a and the second main surface 20b intersect (preferably perpendicular to each other), thereby reducing warpage of the chip 10.

[0124] Generally, when a trench extending in one direction (e.g., the Y direction) is provided on the second main surface 20b of the substrate 20 and a material forming the control region 40 is embedded in the trench, the stress distribution acting on the substrate 20 differs between the direction along the trench (the Y direction) and the direction perpendicular to the trench (the X direction). The difference in stress distribution between the X direction and the Y direction can cause warping of the substrate 20 and, in turn, the chip 10. When the chip 10 warps, for example, an air layer with low thermal conductivity is formed in the bonding layer 50 containing solder, which can deteriorate the heat dissipation capability of the chip 10 and potentially lead to thermal breakdown.

[0125] In this modification, trenches are provided on the first main surface 20a of the substrate 20, extending in a direction intersecting (preferably perpendicular to) the trenches provided on the second main surface 20b, and a material for forming the first electrode 11 is embedded in the trenches. The intersecting trenches cause the stress distribution in the X and Y directions on the first main surface 20a of the substrate 20 to be oriented in a direction that alleviates the difference in the stress distribution in the X and Y directions on the second main surface 20b. Therefore, compared to a case where, for example, trenches are provided on the first main surface 20a that extend in the same direction as the trenches provided on the second main surface 20b, it is possible to suppress the imbalance in the stress distribution in the X and Y directions on the chip 10 and thereby suppress warpage of the chip 10. By suppressing warpage of the chip 10, it is possible to suppress the formation of an air layer with low thermal conductivity in the bonding layer 50, etc., thereby maintaining good heat dissipation and improving reliability.

[0126] (Second modified example of the fifth embodiment) 11 is a cross-sectional view along the XY plane of a semiconductor device 502 according to a second modification of the fifth embodiment. This is a view of the cross section in the XY plane along line P1-P2 shown in FIG. 5, viewed from the negative Z direction. Descriptions of parts common to the semiconductor device 500 will be omitted.

[0127] FIG. 11 shows an example in which the first region 11a of the first electrode 11 extends in the X and Y directions to form a grid. The Y-direction width of the portion of the first region 11a extending in the X direction may be different from the X-direction width of the portion of the first electrode 11 extending in the Y direction. The Y-direction pitch of the portions of the grid extending in the X direction and the X-direction pitch of the portions of the grid extending in the Y direction may be equal, for example, and will be referred to simply as the grid interval below. That is, the grid interval is defined in common for the X and Y directions and is the distance between the centers of adjacent portions of the grid extending in parallel. For example, the grid interval of the first region 11a of the first electrode 11 is the length GS shown in FIG. 11.

[0128] An example will be described in which the first region 11a extends in the X and Y directions and the first region 11a of the first electrode 11 is formed in a lattice pattern on the XY plane. That is, the heat dissipation path passing through the lattice-shaped first region 11a is a heat dissipation path with large thermal conductance.

[0129] On the upper surface of the substrate 20 (not shown in Fig. 11), the control region 40 is provided in a grid pattern, for example, extending in the X and Y directions. The control region 40 is not limited to a grid pattern, and may include at least a portion extending in the X direction and a portion extending in the Y direction. Furthermore, the control region 40 may include at least a portion extending in the Y direction, as shown in Fig. 9 or 10, for example. Furthermore, the control region 40 may include at least a portion extending in the X direction.

[0130] The lattice spacing of the first region 11a of the first electrode 11 and the lattice spacing of the control region 40 may be different, but it is desirable that the lattice spacing of the first region 11a of the first electrode 11 and the lattice spacing of the control region 40 are equal, as this further improves heat dissipation, as described below.

[0131] A semiconductor device 502 according to this modification has field plates FP arranged in a dot pattern spaced apart in the X and Y directions on the second main surface 20b side of the substrate 20. The cross-sectional shape of the field plates FP in the XY plane is, for example, circular. The cross-sectional shape of the field plates FP in the XY plane may also be rectangular.

[0132] Fig. 12 shows an XZ cross-sectional view taken along the line Q1-Q2 shown in Fig. 11. The structure of the second main surface 20b side of the substrate 20 is different from that of the semiconductor device 100.

[0133] The control region 40 has a gate electrode 45 and a gate insulating film 45i interposed between the gate electrode 45 and the substrate 20. An insulating layer 35 is interposed between the gate electrode 45 and the second electrode 12.

[0134] A field plate FP is provided at a distance from the control region 40 in the X direction, and an insulating portion FPi is interposed between the field plate FP and the substrate 20. The field plate FP is electrically connected to the second electrode 12.

[0135] Between the control region 40 and the insulating portion FPi in the X direction, there are a third semiconductor region 23 (p-type base region) and a fourth semiconductor region 24 (n + Although not shown in FIG. 12, a p + A contact region of the shape may be provided to connect to the second electrode 12 .

[0136] The field plate FP extends in the negative Z direction through the substrate 20 from the second main surface (upper surface) 20b of the substrate 20. The field plate FP is, for example, conductive polysilicon containing impurities, and the insulating portion FPi includes an insulator such as silicon oxide.

[0137] FIG. 12 shows an example in which the lattice spacing of the first region 11a of the first electrode 11 is equal to the lattice spacing of the control region 40. Although FIG. 12 shows an XZ cross section, the semiconductor device 501 may also have a similar structure in a YZ cross section. The first region 11a is provided at a position overlapping in the Z direction with each of the control regions 40 arranged in the X direction. The X-direction length of each of the control regions 40 and the X-direction length of each of the first regions 11a may be different. For example, the first region 11a may be formed longer in the X direction, and at least a portion of the third semiconductor region 23 and the fourth semiconductor region 24 adjacent to the control region 40 may overlap in the Z direction with the first region 11a. In other words, the portion where a channel is mainly formed when the semiconductor device 502 is on overlaps with the first region 11a in the Z direction.

[0138] The first region 11a may be provided at a position overlapping in the Z direction with each of the field plates FP aligned in the X direction. The lattice spacing of the first region 11a of the first electrode 11 and the lattice spacing of the control region 40 may be different.

[0139] The operation of the semiconductor device 502 will be described with reference to Figures 11 and 12. When a voltage is applied to the gate electrode 45 of the control region 40, a channel is formed in the third semiconductor region 23 adjacent to the control region 40. The channel has a portion that extends in the X direction and a portion that extends in the Y direction, following the lattice shape of the control region 40. The channel is formed, for example, between the lattice-shaped control regions 40, surrounding the field plate FP. When the semiconductor device 502 is off, a depletion layer extends from the insulating portion FPi of the field plate FP to the second semiconductor region 22, maintaining the breakdown voltage.

[0140] According to the semiconductor device 502 of this modification, when the control region 40 is arranged, for example, in a lattice pattern, heat generated by a current flowing through a channel including portions extending in the X direction and the Y direction can be efficiently dissipated by the first region 11a of the first electrode 11 arranged in a lattice pattern.

[0141] By providing the first regions 11a of the first electrode 11 in a lattice pattern, heat generated from the portions of the channels extending in the X direction is dissipated evenly in the X direction via the portions of the first regions 11a extending in the X direction. Furthermore, the heat dissipation of the multiple channels aligned in the Y direction is improved evenly via the portions of the first regions 11a of the first electrode 11 extending in the Y direction. Meanwhile, heat generated from the portions of the channels extending in the Y direction is dissipated evenly in the Y direction via the portions of the first regions 11a of the first electrode 11 extending in the Y direction, and the heat dissipation of the multiple channels aligned in the X direction is improved evenly via the portions of the first regions 11a of the first electrode 11 extending in the X direction. In other words, locally poor heat dissipation and heat accumulation can be suppressed, thereby improving the reliability of the semiconductor device.

[0142] When the lattice spacing of the first region 11a of the first electrode 11 is equal to the lattice spacing of the control region 40, the overlapping area in the Z direction between the channel formed around the control region 40 and the first region 11a of the first electrode 11 increases, thereby further improving heat dissipation.

[0143] It should be noted that heat dissipation can be improved even when the control region 40 is not lattice-shaped. For example, when the control region 40 extends in the Y direction and is aligned in the X direction, the first region 11 of the first electrode 11 provided in a lattice pattern has a portion that is aligned with the extension direction of the control region 40 and a portion that intersects with the extension direction of the control region 40. Therefore, as described for the semiconductor devices 500 and 501, it is possible to prevent the occurrence of locally poor heat dissipation portions in the channel formed along the extension direction of the control region 40, thereby improving the reliability of the semiconductor device.

[0144] For example, when the control region 40 extends in the Y direction and is aligned in the X direction, the first region 11 of the first electrode 11 arranged in a lattice pattern uniformly improves the heat dissipation performance in the Y direction for each of the channels extending in the Y direction, thereby preventing the occurrence of locally poor heat dissipation performance in a single channel continuous in the Y direction. Furthermore, it is possible to prevent the occurrence of locally poor heat dissipation performance among multiple channels aligned in the X direction.

[0145] (Sixth embodiment) 13 is a cross-sectional view along the XY plane showing a semiconductor device 600 according to a sixth embodiment. It is a view of the cross section in the XY plane along the P1-P2 line shown in FIG. 5, viewed from the negative Z direction. Portions common to the description of the semiconductor device 500 according to the fifth embodiment will be omitted.

[0146] 13 is a cross-sectional view of the entire chip 10. In FIG. 13, the second electrodes 12 and third electrodes 13 of the semiconductor device 400 shown in FIG. 6 are illustrated as regions surrounded by dotted lines. An example is shown in which one row of first regions 11a is provided at a position overlapping the boundary region A (the termination region At and the inter-electrode region Ags) in the Z direction. Note that multiple rows of first regions 11a may be formed. The center of the chip 10 in the XY plane is illustrated as center C.

[0147] In a portion of the first electrode 11 that is surrounded in the XY plane by a first region 11a that is provided along the boundary region A, a plurality of first regions 11a and a plurality of second regions 11b are provided in a dot pattern in the X and Y directions. First semiconductor regions 21 of the substrate 20 are interposed in a lattice pattern between the first regions 11a and the second regions 11b of the first electrode 11. A second region 11b is provided in a central portion of the second electrode 12, and dot-shaped first regions 11a are provided around at least one second region 11b, and further first regions 11a are provided along the boundary region A around the dot-shaped first regions 11a.

[0148] The second regions 11b each have a larger cross-sectional area in the XY plane than the first regions 11a arranged in a dot pattern. The second regions 11b may each have a larger length in the X direction or a larger length in the Y direction than the first regions 11a arranged in a dot pattern.

[0149] 13 shows an example in which the first electrode 11 has a first region 11a and a second region 11b as in FIG. 2. The second region 11b shown in FIG. 13 may be replaced with a third region 11c. Furthermore, the first electrode 11 may have the second region 11b and the third region 11c as in FIG. 4. In this case, for example, the third region 11c is provided in the center of the second electrode 12 indicated by the dotted line, and the second region 11b is provided so as to surround the third region 11c in the XY plane.

[0150] The central portion of the second electrode 12 overlaps, for example, the active region of the chip 10, and is the portion through which current mainly flows when the semiconductor device is in the on state. That is, when the semiconductor device is in the on state, the amount of heat generated is large in the central portion of the second electrode 12. On the other hand, in the portions that surround the central portion of the second electrode 12 and are closer to the inter-electrode regions Ags and Ass or the termination region At than the central portion of the second electrode 12, the magnitude of the current in the on state is smaller than that in the active region.

[0151] It is desirable that many of the dot-shaped first regions 11a, second regions 11b, and third regions 11c are provided symmetrically in the XY plane. Here, symmetry refers to point symmetry about a certain point. For example, it is desirable that many of the dot-shaped first regions 11a, second regions 11b, and third regions 11c are provided point symmetrically with respect to the center C of the chip 10 in the XY plane. In the example shown in FIG. 13, the first regions 11a are not provided near the corners of the chip 10 that overlap with the second electrodes 12, and the dot-shaped first regions 11a and second regions 11b are provided point symmetrically with respect to the center C (the first regions 11a that overlap with the boundary region A in the Z direction are not necessarily provided symmetrically). On the other hand, the first regions 11a may be provided in corners of the chip 10 where the third electrodes 13 are not provided, and the dot-shaped first regions 11a do not necessarily have to be point symmetric with respect to the center C.

[0152] According to the semiconductor device 600 of this embodiment, by providing dot-shaped first regions 11a surrounding the center of the second electrode 12, it is possible to improve the heat dissipation performance of regions of the chip 10 that have relatively poor heat dissipation performance. In addition to providing the first regions 11a in the inter-electrode regions Ags and Ass or the terminal region At as described in the fourth embodiment, dot-shaped first regions 11a are also provided in portions closer to the inter-electrode regions Ags and Ass or the terminal region At than to the center of the second electrode 12. In regions where no electrodes are provided on the top surface of the chip 10 and where heat dissipation performance is poor, the number of heat dissipation paths that reach the conductive member 70 via the first regions 11a is increased, thereby increasing thermal conductance.

[0153] On the other hand, the bonding strength between the chip 10 and the conductive member 70 can be improved by the bonding layer 50 (not shown in FIG. 13) below the second region 11b surrounded by the dot-shaped first region 11a. The bonding layer 50 located below the first electrode 11 is provided thicker in the Z direction below the second region 11b than below the first region 11a. The thick bonding layer 50 improves the bonding strength between the chip 10 and the conductive member 70. If the second region 11b shown in FIG. 13 is replaced with the third region 11c, the bonding layer 50 is provided thicker, further improving the bonding strength between the chip 10 and the conductive member 70.

[0154] Furthermore, in the semiconductor device 600 according to this embodiment, the first region 11a, the second region 11b, and the third region 11c are symmetrically arranged, thereby reducing stress applied to the substrate 20. In the areas where the first region 11a, the second region 11b, and the third region 11c are provided, the thickness of the first electrode 11 in the Z direction is greater than that of the layer region 11L. The thermal expansion coefficients of the first electrode 11 and the substrate 20 are different, and the distribution of stress applied to the substrate 20 due to thermal history depends on the layout of the first region 11a, the second region 11b, and the third region 11c. In the semiconductor device according to this embodiment, the first electrode 11 can be arranged point-symmetrically with respect to the center C of the chip, at least in areas other than the periphery of the third electrode 13. By providing many areas where the first region 11a, the second region 11b, and the third region 11c are symmetrically arranged, stress is distributed more isotropically in the XY plane, thereby suppressing warping of the substrate 20 due to stress. Suppressing warping of the substrate 20 improves the reliability of the semiconductor device. By providing the first electrodes 11 in a dot pattern, the area in which the first regions 11a are provided can be finely adjusted, and the first electrodes 11 can be arranged symmetrically, so that the semiconductor device 600 of this embodiment can be applied to various layouts of the second electrodes 12 and the third electrodes 13 in the XY plane.

[0155] According to the semiconductor device according to at least one embodiment described above, the heat dissipation performance can be improved by thinning the bonding layer 50 below the first region 11a. Alternatively, the bonding strength between the chip 10 and the conductive member 70 can be improved by increasing the thickness of the bonding layer 50 in the Z direction below the third region 11c. By arranging the first region 11a, the second region 11b, and the third region 11c in combination, a semiconductor device with improved heat dissipation performance and bonding strength can be provided.

[0156] 14A to 14F, an example of a method for manufacturing the semiconductor device 300 according to the third embodiment shown in Fig. 5 will be described. The semiconductor device 100 according to the first embodiment and the semiconductor device 200 according to the second embodiment can also be manufactured by, for example, a similar process.

[0157] The manufacturing process shown in Figures 14A to 14F is a process that is performed after forming the structure on the second electrode 12 side of the structure of chip 10 shown in Figure 1. Figures 14A to 14F illustrate the structure on the second electrode 12 side of the structure of chip 10 and the structure of substrate 20, omitting the structure. Also, the illustrations are upside down compared to Figure 1.

[0158] 14A shows a process of selectively forming a resist 80 as a mask on the first main surface 20a after, for example, forming a sixth semiconductor region 26 (not shown) on the substrate 20. The mask pattern of the resist 80 is formed by, for example, photolithography.

[0159] 14B shows a step of forming first openings Ha and second openings Hc by removing substrate 20 in areas where resist 80 was not formed. The first openings Ha have a smaller volume than the second openings Hc. For example, the first width Wa in the X direction of the first openings Ha is smaller than the second width Wc of the second openings Hc.

[0160] The first opening Ha and the second opening Hc are formed by, for example, etching. Etching includes isotropic etching or anisotropic etching. The first opening Ha and the second opening Hc may be formed by both isotropic etching and anisotropic etching. For example, isotropic etching, formation of a protective film, and partial removal of the protective film by anisotropic etching may be repeated.

[0161] 14C, after removing the resist 80, a first metal layer ML1 is formed on the first main surface 20a and the surfaces of the first opening Ha and second opening Hc. The first metal layer ML1 is formed by, for example, sputtering or CVD. The first metal layer ML1 includes at least one of Ti, Cu, Ta, N, TiCu, TiNCu, TiN, and TaN.

[0162] 14D, a first electrode 11 is formed in contact with the first metal layer ML1. The first electrode 11 is provided by, for example, a plating process. The first electrode 11 is formed by, for example, an electrolytic plating method so as to fill the first opening Ha and the second opening Hc. The first metal layer ML1 may be, for example, a seed layer for the plating process. The first electrode 11 includes, for example, Cu.

[0163] Furthermore, the first region 11a of the first electrode 11 formed in the first opening Ha is formed thicker in the Z direction than the third region 11c of the first electrode 11 formed in the second opening Hc. For example, by selecting a plating method, the smaller the volume of the opening, the greater the thickness of the deposited layer in the Z direction can be. The plating method can be, for example, electrolytic plating. Furthermore, depending on the plating method, the amount deposited in the first opening Ha and the second opening Hc can be made greater than the amount deposited as layer region 11L on the first main surface 20a. The layer region 11L is thinner in the Z direction than the first region 11a and the third region 11c, and is formed along the first main surface 20a.

[0164] 14E, a second metal layer ML2 is formed on the surface of the first electrode 11. The second metal layer ML2 is formed by, for example, sputtering. The second metal layer ML2 contains at least one metal element selected from the group consisting of Ti, Ni, Ag, and Au.

[0165] Furthermore, the chip 10 shown in Figures 14E through 14F is turned upside down, and as shown in Figure 14F, the chip 10 is mounted on the conductive member 70 so that the first electrode 11 and the conductive member 70 are in contact with each other via the bonding layer 50. The conductive member 72 is disposed on the second electrode 12 via the bonding layer 52. The bonding layers 50 and 52 are provided, for example, in a ball shape, and are not necessarily layered in the process of Figure 14E. The conductive member 72 is, for example, a connector containing Cu. The bonding layer 52 contains, for example, solder.

[0166] Finally, by heating the semiconductor device 300 while sandwiching the chip 10 between the conductive members 70 and 72, the bonding layers 50 and 52 melt and flow between the chip 10 and the conductive members 70 and 72, as shown in Fig. 14G, and then cooling the bonding layers to bond the chip and the conductive members 70 and 72. The conductive member 72 is, for example, a part of a metal plate connected to the source electrode of a MOSFET.

[0167] When the bonding layer 50 flows between the chip 10 and the conductive member 70, the material constituting the bonding layer 50 is pushed out below the first region 11a of the first electrode 11, and the material constituting the bonding layer 50 flows in below the third region 11c. Therefore, in the Z direction, the bonding layer 50 is thinner below the first region 11a, and the bonding layer 50 is thicker below the third region 11c.

[0168] In the above explanation, the first electrode 11 and the first and second metal layers ML1 and ML2 have been described as separate elements, but for example, the first electrode 11 may have multiple layers. In other words, the first metal layer ML1 and the second metal layer ML2 may also be considered to be included in the first electrode 11. For example, the layer region 11L of the first electrode 11 may include at least the first metal layer ML1 or the second metal layer ML2.

[0169] The embodiments have been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, designs that are appropriately modified by a person skilled in the art from these specific examples are also included within the scope of the embodiments as long as they have the characteristics of the embodiments. The elements, as well as their arrangement, materials, conditions, shapes, sizes, etc., of the above-mentioned specific examples are not limited to those exemplified and can be modified as appropriate.

[0170] Furthermore, the elements of each of the above-described embodiments can be combined to the extent technically possible, and combinations of these are also included within the scope of the embodiments as long as they include the features of the embodiments. In addition, within the scope of the concept of the embodiments, a person skilled in the art may conceive of various modifications and alterations, and it is understood that these modifications and alterations also fall within the scope of the embodiments.

[0171] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0172] 100, 101, 200, 201, 300, 400, 401, 402, 500, 600, 601... Semiconductor device 10 chips 11...1st electrode 11a...First area 11b...Second area 11c...Third area 11L...layer area 12...Second electrode 13...Third electrode 20... Substrate 21...First semiconductor region 22...Second semiconductor region 23. Third semiconductor region 24. Fourth semiconductor region 25. Fifth Semiconductor Region 26. Sixth Semiconductor Region 31. Insulating layer 40. Control Area 41A First insulating film 41B: Second insulating film 41C···Gate insulating film 42...conductive area 43 Gate electrode 50, 52...Joining layer ML1...1st metal layer ML2...Second metal layer 70, 72...Conductive members 80...Resist Ha...1st opening Hc...Second opening A...boundary area Ags, Ass... area between electrodes At...Terminal area FP Field Plate FPi...insulation part

Claims

1. a substrate having a first main surface and a second main surface opposite the first main surface; a first electrode provided on the first major surface; a second electrode provided on the second major surface; a MOSFET provided on the second main surface side of the substrate, the MOSFET having the first electrode as a drain electrode and the second electrode as a source electrode; Equipped with The first electrode is a layer region provided on the first major surface along the first major surface; a first region extending from the first main surface into the substrate in a first direction from the first electrode toward the second electrode and adjacent to the layer region; and a lower surface of the first electrode protruding in a direction opposite to the first direction in the first region; Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein the first electrode is spaced from the first region in a second direction intersecting the first direction, extends through the substrate from the first main surface toward the first direction, and further includes a second region adjacent to the layer region.

3. The length of the first region in the second direction is smaller than the length of the second region in the second direction. The semiconductor device according to claim 2 .

4. The semiconductor device according to claim 3 , wherein the lower surface of the first electrode has a flat surface parallel to the second direction in the second region.

5. a substrate having a first major surface and a second major surface opposite the first major surface; a first electrode provided on the first major surface; a second electrode provided on the second major surface; a MOSFET provided on the second main surface side of the substrate, the MOSFET having the first electrode as a drain electrode and the second electrode as a source electrode; Equipped with The first electrode is a layer region provided on the first major surface along the first major surface; a third region extending through the substrate from the first main surface in a first direction from the first electrode toward the second electrode and adjacent to the layer region; and a lower surface of the first electrode is recessed in the third region toward the first direction; Semiconductor device.

6. The semiconductor device further includes a first metal layer provided between the substrate and the first electrode, the first metal layer including at least one of Ti, Cu, Ta, N, TiCu, TiNCu, TiN, and TaN. The semiconductor device according to claim 1 .

7. The substrate is a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of the first conductivity type provided on the first semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region; a fourth semiconductor region of the first conductivity type provided on the third semiconductor region and connected to the second electrode; a buffer region of a first conductivity type provided between the first semiconductor region and the second semiconductor region and having a higher impurity concentration of the first conductivity type than the second semiconductor region; and a distance between the first region and the second electrode in the first direction is longer than a distance between the first semiconductor region and the second electrode in the first direction; The semiconductor device according to claim 1 .

8. a third electrode provided on the second main surface of the substrate and spaced apart from the second electrode; the second main surface has an inter-electrode region located between the second electrode and the third electrode; The first region is provided at a position overlapping the inter-electrode region in the first direction. The semiconductor device according to claim 1 .

9. a gate electrode of the MOSFET provided on the second main surface of the substrate extends in a third direction perpendicular to the first direction and the second direction, and a plurality of gate electrodes are formed along the second direction; The first region extends in the third direction and is formed in plurality along the second direction.

5. The semiconductor device according to claim 2.

10. A conductive member; A bonding layer; Furthermore, the first electrode is provided on the conductive member via the bonding layer and is electrically connected to the conductive member via the bonding layer; The semiconductor device according to claim 1 .

11. the conductive member contains Cu, The bonding layer includes solder. The semiconductor device according to claim 10.

12. a second metal layer provided on the lower surface of the first electrode and containing at least one of Ti, Ni, Ag, and Au; The semiconductor device according to claim 11.

13. 5. The method for manufacturing a semiconductor device according to claim 2, further comprising the steps of: a first opening having a first width in the second direction and a second opening having a second width in the second direction that is wider than the first width, the first opening being formed by electroplating, and a lower surface of the first electrode protruding in a direction opposite to the first direction in the first opening by selecting a predetermined width.

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