Semiconductor device

Abstract

To provide a semiconductor device capable of operating a content reference memory at a higher speed.SOLUTION: The semiconductor device 1 includes the memory array 4 including the master block 2 that stores the first portion of the bit string constituting the data entry and the slave block 3 that stores the remaining second portion of the bit string, and the searcher 21 that is included in the master block 2 and determines a match between the portion of the search data corresponding to the first portion and any of the first portions of the data entries. The master block 2 controls to activate the slave block 3 according to the start of the determination of the search unit 21, and controls to continue the activation of the slave block 3 or deactivate the slave block 3 according to the result of the determination of the search unit 21.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device having a content addressable memory that has a function of determining whether a plurality of data entries match search data. [Background technology]

[0002] A storage device called a search memory or content addressable memory (CAM) searches stored data words (also called data entries) for a match to a search word, and if a matching data word is found, outputs its address.

[0003] There are two types of CAM: BCAM (Binary CAM) and TCAM (Ternary CAM). Each memory cell in BCAM stores either "0" or "1". On the other hand, in the case of TCAM, each memory cell can store "Don't Care" information in addition to "0" and "1". "Don't Care" indicates that either "0" or "1" is acceptable.

[0004] TCAMs are widely used for address lookup and access control in routers for networks such as the Internet. To accommodate larger capacity, TCAMs typically have multiple memory arrays, and search operations are performed on each memory array simultaneously. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2023-114100 Summary of the Invention [Problem to be solved by the invention]

[0006] Patent Document 1 describes dividing a memory array into a plurality of parts in the bit direction, and stopping the search operation of the memory array in the subsequent stage when all entries in the memory array in the previous stage do not match.

[0007] However, in Patent Document 1, the search results of the preceding memory array are obtained before the search operation of the succeeding memory array is executed. Therefore, for example, if a plurality of succeeding memory arrays are provided, the delay time until the control signal indicating the execution of a search reaches the last memory array may limit the speed of the entire internal reference memory.

[0008] The embodiments described below have been made in consideration of the above, and other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] In one embodiment of a semiconductor device, a memory array of a content addressable memory includes a first block that stores a first portion of a bit string that constitutes a data entry, and a second block that stores a second portion of the bit string excluding the first portion, and the first block controls the second block to be activated in response to the start of a determination by a first search circuit that determines a match between any of a plurality of first portions and a portion of search data that corresponds to the first portion, and controls the first block to continue activation or to inactivate the second block in response to the result of the determination by the first search circuit. [Effects of the Invention]

[0010] According to the embodiment, the content addressable memory can be operated at a higher speed. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic diagram of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a diagram showing a basic operation of the semiconductor device of FIG. [Figure 3] FIG. 3 is a diagram showing a basic operation of the semiconductor device of FIG. [Figure 4] FIG. 4 is a diagram showing a basic operation of the semiconductor device of FIG. [Figure 5] FIG. 5 shows a case where the slave block is divided into eight parts. [Figure 6] FIG. 6 is a circuit diagram of the master block. [Figure 7] FIG. 7 is a circuit diagram of the timing generation circuit. [Figure 8] FIG. 8 is a circuit diagram of the SL driver. [Figure 9] FIG. 9 is a circuit diagram of the ML driver. [Figure 10] FIG. 10 is a circuit diagram of the All-Miss decision circuit. [Figure 11] FIG. 11 is a circuit diagram of the SLEN generation circuit. [Figure 12] FIG. 12 is a timing chart showing the operation of the SLEN generation circuit. [Figure 13] FIG. 13 is a timing chart showing the operation of the master block of FIG. [Figure 14] FIG. 14 is a schematic diagram of a semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a schematic diagram showing an application example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0013] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0014] Furthermore, the circuit elements constituting each functional block of the embodiments are formed on a semiconductor substrate such as single crystal silicon using integrated circuit technology such as known CMOS (complementary metal oxide semiconductor transistor). In the embodiments, a MOSFET (metal oxide semiconductor field effect transistor) (abbreviated as MOS transistor) is used as an example of a MISFET (metal insulator semiconductor field effect transistor), but this does not exclude non-oxide films as gate insulating films. In the embodiments, a p-channel MOSFET and an n-channel MOSFET are referred to as a pMOS transistor and an nMOS transistor, respectively.

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated description thereof will be omitted.

[0016] (First embodiment) A schematic diagram of a semiconductor device according to this embodiment is shown in Figure 1. This embodiment describes a content addressable memory divided into multiple memory blocks that sequentially perform search operations along the column direction on a memory array including multiple content addressable memory cells arranged in a matrix for storing data entries (hereinafter sometimes abbreviated as entries).

[0017] [Schematic configuration of this embodiment] A content addressable memory will be described as an example of a semiconductor device with reference to Figure 1. The semiconductor device 1 (content addressable memory) includes a master block 2, a slave block 3, a master FF (flip-flop) 5, and an AND circuit 6. The master block 2 and the slave block 3 form a memory array 4.

[0018] The master block 2 has a memory array configured with, for example, 256-entry, 64-bit TCAM cells (not shown in FIG. 1). The master block 2 stores 256 entries of 64-bit data among the data entries. In other words, the master block 2 functions as a first block that stores a first portion of the bit string that constitutes the data entry. The master block 2 also includes a search unit 21, an all-miss determination circuit 22, and a drive signal advance circuit 23.

[0019] The search unit 21 includes a timing generation circuit 211, an SL driver 212, an ML driver 213, etc. (See FIG. 6). The search unit 21 searches whether the bit string of the part of the search data input to the semiconductor device 1 (content addressable memory) that corresponds to the master block 2 matches each entry stored in the memory array 4, and outputs the search result. The search result (determination result) is output as MMLO[255:0]. That is, the search unit 21 functions as a first search circuit. The detailed circuitry and operation of the search unit 21 will be described later.

[0020] If the search unit 21 finds, as a result of the search, that at least one entry matches the search data, the all-miss determination circuit 22 continues to assert the slave drive signal (SLEN) output by the drive signal first output circuit 23, and if no entry matches the search data, the all-miss determination circuit 22 negates the slave drive signal output by the drive signal first output circuit 23. The detailed circuitry and operation of the all-miss determination circuit 22 will be described later.

[0021] When the master block 2 starts operating, the drive signal advance circuit 23 outputs a slave drive signal to the slave block 3 to activate the slave block 3. Also, under the control of the all-miss decision circuit 22, the drive signal advance circuit 23 outputs a slave drive signal to activate or deactivate the slave block 3 according to the search result of the search unit 21. In the configuration of FIG. 1, the slave drive signal is output in common (via the same signal line) to the slave blocks 3a and 3b. The detailed circuit and operation of the drive signal advance circuit 23 will be described later.

[0022] The slave block 3 has a memory array configured with, for example, 256 entries and 92-bit TCAM cells (not shown in FIG. 1). The slave block 3 stores 256 entries of data, excluding the first 64 bits of the data entry. In other words, the slave block 3 functions as a second block that stores the second part of the data entry, excluding the first part. The slave block 3 also has a search unit 31. In FIG. 1, the slave block 3 includes two slave blocks, 3a and 3b, and the slave blocks 3a and 3b have the same configuration.

[0023] The slave blocks 3a and 3b function as sub-blocks that store the third portions constituting the second portion of the data entry, respectively, and determine whether the third portions stored in the slave blocks 3a and 3b match the corresponding third portions of the search data.

[0024] The search unit 31 has the same basic configuration as the search unit 21. The search unit 31 searches whether the bit string of the portion of the search data input to the semiconductor device 1 (content addressable memory) corresponding to the slave block 3 matches an entry stored in the memory array, and outputs the determination result. The search result (determination result) of the slave block 3a is output as SL0MLO[255:0], and the search result of the slave block 3b is output as SL1MLO[255:0]. In other words, the search unit 31 functions as a second search circuit.

[0025] The master FF5 is a register for delaying MMLO[255:0], the search result of the master block 2, by one clock. The logical product circuit 6 outputs the logical product of MMLO[225:0] delayed by one clock, SL0MLO[255:0], and SL1MLO[255:0]. In other words, the logical product circuit 6 functions as a match detection circuit that determines whether the search data matches a data entry by the logical product of the determination result of the master block 2 and the determination results of the slave blocks 3a and 3b.

[0026] 1, the master block 2 first performs a search operation at the first clock, and then the slave block 3 performs a search operation at the second clock. Therefore, ALL MLO[255:0], which is the output of the AND circuit 6, is determined at the second clock.

[0027] [Basic operation of this embodiment] For example, in the circuit described in Patent Document 1, the slave drive signal for activating the slave block 3 is output based on the result from the master block 2. Therefore, it is necessary to wait for the slave drive signal to reach the slave block 3 at the end, which limits the speed of the entire content addressable memory. Therefore, in this embodiment, the slave drive signal is output first based on the output of the clock signal (CLK) to activate the slave block 3. Then, as soon as the search result from the master block 2 is known, the slave drive signal is stopped as needed to deactivate the slave block 3. Therefore, by the time search data is supplied to the slave block 3 and the search operation is initiated, the slave drive signal indicating activation has already reached all of the slave blocks 3, which allows the speed of the entire content addressable memory to be increased.

[0028] Next, the basic operation of this embodiment will be described with reference to FIGS. 2 to 4. FIG. 2 shows a case where the search results for both the master block 2 and the slave blocks 3a and 3b are a match (Hit). In FIG. 2, the search unit 21 starts a search operation, triggered, for example, by the rising edge of the clock signal CLK. In parallel with this search operation, the drive signal advance circuit 23 outputs the slave drive signal SLEN to the slave blocks 3a and 3b (asserts the slave drive signal SLEN). Then, SLEN0 of the slave block 3a and SLEN1 of the slave block 3b are asserted, activating the slave blocks 3a and 3b. Therefore, the slave blocks 3a and 3b are ready to start a search operation, triggered by the next rising edge of the clock signal CLK (thick line in FIG. 2).

[0029] Thereafter, the search unit 21 outputs a match (Hit) as the search result. Because the search result is a match, the all-miss decision circuit 22 controls the drive signal advance circuit 23 to continue asserting the slave drive signal SLEN. That is, the slave block 3 is kept activated. Therefore, the search operation of the slave blocks 3a and 3b is started at the next rising edge of the clock signal CLK. Therefore, the search unit 31 performs a search (decision).

[0030] 2, the search results for both the master block 2 and the slave blocks 3a and 3b are a match (Hit), so ALL MLO also outputs a match (Hit). In other words, the slave drive signal SLEN reaches the slave blocks 3a and 3b at the rising edge of the next clock, so the slave blocks 3a and 3b operate normally and output a match (Hit), and ALL MLO also outputs a match (Hit).

[0031] 3 shows a case where the search result of the master block 2 is a mismatch (Miss). In FIG. 3, the search unit 21 starts a search operation, triggered by, for example, the rising edge of the clock signal CLK. In parallel with this search operation, the drive signal advance circuit 23 asserts the slave drive signal SLEN. Then, SLEN0 of the slave block 3a and SLEN1 of the slave block 3b are asserted, activating the slave blocks 3a and 3b. Therefore, the search operation can be started at the next rising edge of the clock signal CLK.

[0032] Thereafter, the search unit 21 outputs a mismatch (Miss) as the search result. Because the search result is a mismatch, the All-Miss judgment circuit 22 controls the drive signal advance circuit 23 to negate the slave drive signal SLEN, thereby inactivating the slave block 3 (thick line in FIG. 3). As a result, SLEN0 of the slave block 3a and SLEN1 of the slave block 3b are negated, and no search operation is performed in the slave blocks 3a and 3b even when the next rising edge of the clock signal CLK arrives. Therefore, no search (judgment) is performed by the search unit 31.

[0033] In FIG. 3, the search result for the master block 2 is a mismatch (Miss), so regardless of the search results for the slave blocks 3a and 3b, the ALL MLO outputs a mismatch (Miss).

[0034] 4 shows a case where the search result of the master block 2 is a mismatch (Miss) and the change in the slave drive signal SLEN does not arrive in time for the slave block 3b at the end. In FIG. 4, the search unit 21 starts a search operation, triggered by, for example, the rising edge of the clock signal CLK. In parallel with this search operation, the drive signal advance circuit 23 asserts the slave drive signal SLEN. Then, SLEN0 of the slave block 3a and SLEN1 of the slave block 3b are asserted, activating the slave blocks 3a and 3b. Therefore, the search operation can be started at the next rising edge of the clock signal CLK.

[0035] Thereafter, a mismatch (Miss) is output as the search result of the search unit 21. Because the search result is a mismatch, the All-Miss decision circuit 22 controls the drive signal advance circuit 23 to negate the slave drive signal SLEN, thereby inactivating the slave block 3 (thick solid line in FIG. 4). As a result, SLEN0 of the slave block 3a is negated, and no search operation is performed in the slave block 3a even when the next rising edge of the clock signal CLK occurs.

[0036] On the other hand, SLEN1 of slave block 3b is not negated in time for the rising edge of the clock signal CLK, so slave block 3b performs a search operation (thick dashed line in Figure 4). However, since the search result of master block 2 has already determined a mismatch, the logical AND circuit 6 is determined to be low level (Lo) indicating a mismatch (Miss), and even if slave block 3b outputs a match (Hit), there is no effect on ALL MLO.

[0037] In FIG. 4, the search result for the master block 2 is a mismatch (Miss), so the ALL MLO outputs a mismatch (Miss) regardless of the search results for the slave blocks 3a and 3b.

[0038] 2 and the like, the slave block 3 is divided into two, but it may be divided into more parts (eight in FIG. 5) as shown in FIG. 5. In this case, it is more effective to send the slave drive signal SLEN first as in this embodiment, so that each slave block 3 is ready to operate during the first clock, and to control the slave drive signal SLEN in accordance with the search result of the master block 2.

[0039] As shown in Figure 5, if the slave block is divided into eight parts, for example, the RC delay of the slave drive signal SLEN may prevent it from reaching the last slave block 3g by cycle 2 (the dashed line in the bottom row of Figure 5). In this case, the slave block 3g will operate, but the other slave blocks 3a, 3b, ..., 3f will be stopped, so the number of stopped blocks will increase overall for the slave block 3, resulting in a significant power reduction effect. Also, because the slave block 3 is controlled to stop when the search result of the master block 2 is a mismatch, the mismatch of the master block 2 determines the overall result as a mismatch, and the slave drive signal SLEN is unlikely to be a constraint on increasing the speed of circuit operation.

[0040] [Circuit configuration example of this embodiment] An example of a circuit configuration of this embodiment will be described with reference to FIGS. 6 to 12. The circuits shown below are merely examples, and other circuit configurations may be used as long as they achieve the same functions. The logic levels indicating the assertion and negation of each signal may also be changed as appropriate. FIG. 6 shows the circuit of the master block 2. Of the components shown in FIG. 6, the components included in the search unit 21 are also included in the slave block 3. Therefore, while FIG. 6 also shows SLEN0 (SLEN1) as an input, in the master block 2, SLEN0 can simply be fixed to Hi. The SLEN generation circuit 23 shown in FIG. 6 has the same function as the drive signal advance circuit 23 shown in FIG. 1, etc. While the master FF 5 is shown external to the master block 2 in FIG. 1, etc., it may be included in the master block 2 as shown in FIG. 6.

[0041] 6, the search unit 21 includes a timing generation circuit 211, an SL driver 212, and an ML driver 213. The memory array is divided into entries (indicated by dashed lines), and each entry has a plurality of TCAM cells MC. Match lines ML are provided corresponding to a plurality of TCAM cells MC included in memory cell rows arranged along the column direction.

[0042] 7 is an example of a circuit diagram of the timing generation circuit 211. The timing generation circuit 211 includes flip-flops 301 and 302, AND circuits 303 and 304, inverters 305, 309, 319, 321, 322, 324, 326, and 327, pMOS transistors 306 and 313, nMOS transistors 307, 308, 314, and 315, capacitance elements 310 and 316, a delay circuit 311, NOR circuits 312 and 317, and NAND circuits 318, 320, 323, and 325.

[0043] The flip-flop 301 receives and outputs a control signal CEN based on the clock signal CLK. The control signal CEN controls whether the clock signal CLK is enabled or disabled. The flip-flop 302 receives and outputs a slave drive signal SLEN based on the clock signal CLK.

[0044] The AND circuit 303 receives the clock signal CLK and the inverted signal of the output of the flip-flop 301, and outputs the result of an AND logic operation. The AND circuit 304 receives the output of the AND circuit 303 and the inverted signal of the output of the inverter 319, and outputs the result of an AND logic operation.

[0045] The inverter 305 inverts the output of the AND circuit 304 and outputs it to the gate of a pMOS transistor 306 , the gate of an nMOS transistor 307 , and the gate of an nMOS transistor 308 .

[0046] The pMOS transistor 306 and the nMOS transistors 307 and 308 are connected in series between a power supply potential (voltage Vcc level) and a ground potential (voltage Vss level). A control signal is output from the connection node between the pMOS transistor 306 and the nMOS transistor 307.

[0047] The inverter 309 inverts the control signal output from the connection node between the pMOS transistor 306 and the nMOS transistor 307 and outputs the inverted signal.

[0048] The delay circuit 311 delays a control signal output from a connection node between the pMOS transistor 306 and the nMOS transistor 307 by a predetermined time and outputs the delayed signal. The delay circuit 311 can be configured, for example, with a multi-stage inverter. The input node of the delay circuit 311 is connected to a capacitive element 310 whose other electrode is connected to a ground potential (voltage Vss level).

[0049] The NOR circuit 312 inverts the output signal of the delay circuit 311 and outputs it to the gate of the pMOS transistor 313 , the gate of the nMOS transistor 314 , and the gate of the nMOS transistor 315 .

[0050] The pMOS transistor 313 and the nMOS transistors 314 and 315 are connected in series between a power supply potential and a ground potential. A control signal is output from the connection node between the pMOS transistor 313 and the nMOS transistor 314.

[0051] The NOR circuit 317 inverts a control signal output from a connection node between the pMOS transistor 313 and the nMOS transistor 314 and outputs the inverted signal to the NAND circuit 318. The input node of the NOR circuit 317 is connected to a capacitive element 316, the other electrode of which is connected to a ground potential.

[0052] The NAND circuit 318 receives the output signal of the NOR circuit 317 and the output signal of the inverter 309, and outputs the NAND logic operation result. The inverter 319 inverts the output signal of the NAND circuit 318 and outputs it.

[0053] The NAND circuit 320 receives the output signal of the AND circuit 304 and the output signal of the NAND circuit 318, and outputs the NAND logic operation result. The inverters 321 and 322 output the output of the NAND circuit 320 as the control signal PCE.

[0054] The NAND circuit 323 receives the output signal of the NAND circuit 320 and the output signal of the flip-flop 302, and outputs the NAND logic operation result. The inverter 324 inverts the output signal of the NAND circuit 323 and outputs it as the control signal SLE.

[0055] The NAND circuit 325 receives the output signal of the inverter 319 and the output signal of the flip-flop 302, and outputs the result of a NAND logic operation. The inverters 326 and 327 output the output of the NAND circuit 325 as the control signal MAE.

[0056] The timing generation circuit 211 is a circuit that generates the control signals PCE, MAE, and SLE in response to the clock signal CLK. The control signals PCE and SLE are asserted simultaneously with the input of the clock signal CLK, and are negated at the timing when they return after tracing back through the delay circuit 311. The control signal MAE is asserted at this negation timing, and the all-miss judgment input AMI and the match signal output line MLO (see FIG. 6) are established.

[0057] Fig. 8 shows an example of the circuit of the SL driver 212. The SL driver 212 includes a flip-flop 401, an inverter 402, and NOR circuits 403 and 404. Fig. 8 shows a circuit corresponding to one search line pair SL and SLB, and in practice, a plurality of circuits shown in Fig. 8 are provided according to the number of bits of the entry (search data).

[0058] The flip-flop 401 receives search data supplied to the data terminal D based on the clock signal CLK, and outputs the data to the NOR circuits 403 and 404. The inverter 402 inverts the control signal SLE and outputs it.

[0059] The NOR circuit 403 receives the output signal of the flip-flop 401 and the output signal of the inverter 402 as inputs, and outputs the NOR logical operation result as a search line SL. The NOR circuit 404 receives the inverted signal of the output of the flip-flop 401 and the output signal of the inverter 402 as inputs, and outputs the NOR logical operation result as a search line SLB.

[0060] The SL driver 212 is a circuit that asserts the search line pair SL, SLB to each TCAM cell MC. When the control signal SLE goes high, the SL driver 212 asserts the search data set in the data terminal D to the search line pair SL, SLB.

[0061] Fig. 9 shows an example of the circuit of the ML driver 213. Fig. 9 shows a circuit corresponding to one match line ML, and in reality, the circuit of Fig. 9 is provided according to the number of match lines ML (number of entries). The ML driver 213 includes inverters 501 and 502 and a pMOS transistor 503.

[0062] The inverters 501 and 502 output a control signal PCE to the gate of a pMOS transistor 503. The pMOS transistor 503 is connected between the power supply potential (voltage Vcc level) and the match line ML. The ML driver 213 is a circuit that drives the match line ML. When the control signal PCE is Lo, the match line ML is precharged, and when the control signal PCE is Hi, the precharge is cut off.

[0063] 9 also shows the circuit of the MLO latch 214. The MLO latch 214 includes inverters 504, 505, 506, 507, 508, 509, and 510.

[0064] When a control signal is input, the inverter 504 outputs an inverted signal of the match line ML. The inverter 505 outputs an inverted signal of the output signal of the inverter 504 or the inverter 506 as an all-miss decision input AMI.

[0065] When a control signal is input, inverter 506 outputs an inverted signal of the output signal of inverter 505. When a signal is output from inverter 504, inverter 507 outputs an inverted signal of the output signal of inverter 504 to the match signal output line MLO. When a signal is output from inverter 506, inverter 507 outputs an inverted signal of the output signal of inverter 506 to the match signal output line MLO. Inverters 508, 509, and 510 output a control signal MAE and an inverted signal of the control signal MAE as control signals for inverters 504 and 506.

[0066] At the timing when the match line ML is determined, the control signal MAE is asserted, and the MLO latch 214 transmits the data of the match line ML to the match signal output line MLO and the all-miss decision input AMI.

[0067] More specifically, when the control signal MAE is asserted, the inverter 504 opens and outputs an inverted signal of the match line ML. On the other hand, the inverter 506 closes and does not output a signal. Therefore, when the control signal MAE is asserted, the data of the match line ML is transmitted to the match signal output line MLO and the all-miss judgment input AMI. When the control signal MAE is negated, the inverter 504 closes and does not output a signal. On the other hand, the inverter 506 opens and inverts the output signal of the inverter 505, returns it to the inverter 505, and also outputs it to the inverter 507. Therefore, when the control signal MAE is negated, the signal levels of the match signal output line MLO and the all-miss judgment input AMI are maintained at their previous values.

[0068] 10 shows an example of the all-miss decision circuit 22. The all-miss decision circuit 22 is a circuit that determines whether all the all-miss decision inputs AMI[255:0] indicate a mismatch (Miss). In other words, it determines whether all the match lines ML indicate a mismatch. At this time, if all the entries in the block are Lo (all mismatch), the all-miss generation signal AMO outputs Lo. If even one entry is a match (Hit), the all-miss generation signal AMO outputs Hi. While FIG. 10 shows an example configured with multiple stages of NOR-NAND circuits, other circuit configurations may be used as long as they can achieve the above function.

[0069] 11 shows an example of the SLEN generation circuit 23. The SLEN generation circuit 23 includes inverters 601, 602, 603, 604, 610, 611, 612, 617, 620, 622, and 627, an OR circuit 605, NAND circuits 606, 607, 618, and 619, delay circuits 608 and 609, pMOS transistors 613, 614, 623, and 624, and nMOS transistors 615, 616, 621, 625, and 626.

[0070] Inverter 601 inverts the signal level of the control signal PCE and outputs it. Inverter 602 inverts the signal level of the control signal PCE and outputs it. Inverter 603 inverts the output signal level of inverter 602 and outputs it. Inverter 604 inverts the output signal level of inverter 604 and outputs it.

[0071] An OR circuit 605 receives the output signal of the inverter 601 and the output signal of the inverter 604, and outputs the OR logical operation result. A NAND circuit 606 receives the output signal of the OR circuit 605 and the output signal of the NAND circuit 607, and outputs the NAND logical operation result as a control signal CK1AM. A NAND circuit 607 receives the control signal CK1AM and the output signal of the delay circuit 609, and outputs the NAND logical operation result.

[0072] The delay circuit 608 delays the control signal CK1AM by a predetermined time and outputs it as the control signal BACKDOWN. The delay circuit 609 delays the control signal BACKDOWN by a predetermined time and outputs it. The delay time of the delay circuit 608 is preferably a time that is long enough for the all-miss generation signal AMO to be determined, as shown in FIG. 12, for example.

[0073] Inverter 610 inverts the signal level of the control signal BACKDOWN and outputs it. Inverter 611 inverts the signal level of inverter 610 and outputs it as the control signal AMSE. Inverter 612 inverts the signal level of the control signal AMSE and outputs it.

[0074] The pMOS transistors 613 and 614 and the nMOS transistors 615 and 616 are connected in series between a power supply potential (voltage Vcc level) and a ground potential (voltage Vss level). A control signal is output from a connection node between the pMOS transistor 614 and the nMOS transistor 615. An all-miss generation signal AMO is input to the gates of the pMOS transistor 613 and the nMOS transistor 616, an inverted signal of the control signal AMSE is input to the gate of the pMOS transistor 614, and the control signal AMSE is input to the gate of the nMOS transistor 615.

[0075] The inverter 617 inverts the signal level of the control signal BACKDOWN and outputs it. The NAND circuit 618 receives the output signal of the inverter 617 and the output signal of the NAND circuit 619 as inputs, and outputs the NAND logical operation result. The NAND circuit 619 receives the output signal of the inverter 617 and the control signal CK1AM as inputs, and outputs the NAND logical operation result. The inverter 620 inverts the output signal of the NAND circuit 619 and outputs it as the control signal AMSRST.

[0076] The nMOS transistor 621 is connected between the power supply potential and the ground potential. The gate of the nMOS transistor 621 receives a control signal AMSRST.

[0077] The inverter 622 inverts the signal level of the control signal output from the connection node between the pMOS transistor 614 and the nMOS transistor 615 and outputs the inverted signal.

[0078] The pMOS transistors 623 and 624 and the nMOS transistors 625 and 626 are connected in series between a power supply potential and a ground potential. A control signal is output from the connection node between the pMOS transistor 624 and the nMOS transistor 625. The output signal of the inverter 622 is input to the gates of the pMOS transistor 623 and the nMOS transistor 626, the output signal of the NAND circuit 618 is input to the gate of the pMOS transistor 624, and the output signal of the inverter 617 is input to the gate of the nMOS transistor 625.

[0079] The inverter 627 inverts the signal level of the control signal output from the connection node between the pMOS transistor 624 and the nMOS transistor 625 and outputs it as the slave drive signal SLEN.

[0080] Here, the operation of the SLEN generation circuit 23 will be described with reference to the timing chart of Fig. 12. The names of the signals shown in Fig. 12 are the control signals described above. The SLEN generation circuit 23 shown in Fig. 11 is a circuit that generates the slave drive signal SLEN. This circuit sets the slave drive signal SLEN to Hi based on the Hi (asserted) state of the control signal PCE generated by the timing generation circuit 211.

[0081] When the control signal PCE is asserted Hi, the control signal AMSRST goes Hi, which turns on the nMOS transistor 621 and forcibly sets the slave drive signal SLEN to Hi. On the other hand, the control signal AMSE is Lo, so the all-miss generation signal AMO is not output as the slave drive signal SLEN. At the timing when the control signal BACKDOWN goes Hi, the all-miss generation signal AMO is transmitted to the slave drive signal SLEN via the delay circuit 608. When the control signal PCE is negated, the control signal AMSRST goes Lo, and because the control signal AMSE is Hi, the all-miss generation signal AMO is output as the slave drive signal SLEN.

[0082] The circuit shown in FIG. 11 realizes the advance of setting the slave drive signal SLEN to a high level (activation), and after the search unit 21 determines whether or not there is a match, the result is transmitted to the slave drive signal SLEN.

[0083] As described above, the SLEN generation circuit 23 functions as a drive control circuit that controls the slave block 3 to be activated or inactivated by outputting the slave drive signal SLEN to the slave block 3.

[0084] [Operation of the Circuit of this Embodiment] Next, the operation of the master block 2 configured as described above will be described with reference to the timing chart in Fig. 13. At the rising edge of the clock signal CLK, the timing generation circuit 211 asserts the control signals PCE and SLE. When the control signal PCE is asserted, the precharge of the match line ML by the ML driver 213 is released. At the same time, the SL driver 212 propagates the input (search data) from the data terminal D to the TCAM cell MC via the search line pair SL and SLB.

[0085] After precharge is released and search data is asserted to the search line pair SL and SLB, the match line ML is held high if there is a match (Hit), and pulled low if there is a mismatch (Miss). When the match line ML is pulled low enough, the timing generation circuit 211 asserts the control signal MAE, and the MLO latch 214 latches the output of the match line ML onto the match signal output line MLO. At the same time as latching onto the match signal output line MLO, the all-miss decision circuit 22 decides whether or not the search results are all mismatches.

[0086] When the control signal PCE is asserted, the control signal CK1AM is asserted in the SLEN generation circuit 23, and the slave drive signal SLEN is asserted to Hi. Therefore, the slave drive signal SLEN can be set to Hi even when the match signal output line MLO is not yet output. In other words, the slave block 3 can be activated. After that, the control signal BACKDOWN goes Hi from the control signal CK1AM via the delay circuit 608. Then, the control signal AMSRST is set to Lo to release the reset, and the all-miss generation signal AMO is propagated to the slave drive signal SLEN. This determines whether the slave drive signal SLEN will be set to Lo. The slave drive signal SLEN, which has been determined to be set to Lo, is input to SLEN0 and SLEN1 of the slave block 3, and it is determined whether the slave block 3 will operate.

[0087] According to the above configuration, the semiconductor device 1 has a memory array 4 including a master block 2 that stores a first portion of a bit string that constitutes a data entry, and a slave block 3 that stores the remaining second portion excluding the first portion. The semiconductor device 1 further has a search unit 21 included in the master block 2 and that determines whether any of the portions (plurality of first portions) of the data entry stored in the master block 2 matches a portion of the search data that corresponds to the first portion. The master block 2 controls the slave block 3 to be activated in response to the start of determination by the search unit 21, and controls the slave block 3 to continue activation or to be inactivated in response to the result of the determination by the search unit 21.

[0088] Therefore, in the case of a circuit configuration in which whether or not to halt the slave block 3 is determined based on the search results of the master block 2, the slave block 3 can be made operational in accordance with the operation of the master block 2. Therefore, since there is no need to wait for the search results of the master block 2, the content addressable memory can operate at higher speed.

[0089] A smaller bit width of the master block 2 reduces the load capacitance of the match line ML, allowing it to operate at a higher speed. On the other hand, if the bit width of the master block 2 is small, the master block 2 is more likely to match, increasing the frequency with which the slave block 3 operates and reducing the power reduction effect. According to the configuration of this embodiment, it is possible to ensure the bit width of the master block 2 and reduce the frequency with which the slave block 3 operates. Therefore, it is possible to achieve both higher speed and reduced power consumption.

[0090] The master block 2 also has a SLEN generation circuit 23 that outputs a slave drive signal SLEN to the slave block 3 to control the slave block so that it is activated or deactivated. Therefore, the slave block 3 can be controlled by the slave drive signal SLEN in accordance with the operation of the master block 2.

[0091] The slave block 3 also has multiple slave blocks 3a and 3b that store multiple third portions that make up the second portion. For example, the slave block 3a determines whether any of the third portions stored therein matches the portion of the search data that corresponds to the slave block 3a. The SLEN generation circuit 23 outputs a slave drive signal SLEN to both the slave blocks 3a and 3b. Therefore, even if the number of bits in an entry is large, the number of bits in the master block can be reduced while optimizing the number of bits in each slave block. This allows the master block 2 to operate at a higher speed.

[0092] The block also includes a logical product circuit 6 that determines whether the search data matches a data entry by performing a logical product of the determination result of the master block 2 and the determination results of the slave blocks 3 a and 3 b. This makes it possible to output a match signal (match or mismatch) for all of the data entries divided between the master block 2 and the slave block 3.

[0093] The slave block 3 also includes a search unit 31 that determines whether any of the portions (plurality of second portions) of the data entry stored in the slave block 3 matches a portion of the search data corresponding to the second portion, depending on the determination by the master block 2. The search unit 31 makes a determination when the slave block 3 is activated by the master block 2, but does not make a determination when the slave block 3 is deactivated. Therefore, the operation of the search unit 31 is determined by whether the slave block 3 is activated or not.

[0094] (Second embodiment) Next, a second embodiment will be described. In the following, explanations of parts that overlap with the above-described embodiment will be omitted in principle.

[0095] [Configuration of this embodiment] 14 is a schematic diagram of a semiconductor device according to this embodiment. A semiconductor device 1A according to this embodiment is similar to the first embodiment in that it sequentially performs a search operation along the column direction on a memory array including a plurality of content addressable memory cells arranged in a matrix for storing data entries. This embodiment differs from the first embodiment in that the memory array is divided into a plurality of memory blocks in the row direction.

[0096] The content addressable memory of this embodiment will be described with reference to Fig. 14. The semiconductor device 1A (content addressable memory) includes a master block 7 and a slave block 8. The master block 7 and the slave block 8 form a memory array 9.

[0097] The master block 7 has a memory array configured with, for example, 64-entry, 64-bit TCAM cells. The master block 7 also includes a slave drive signal generation circuit 71 and a master FF 72.

[0098] The memory array of the master block 7 includes a circuit (search unit) having the same function as the search unit 21 described in the first embodiment. The master block 7 stores 64 entries out of the entries stored in the memory array 9. That is, the master block 7 includes a search circuit that determines whether search data matches any of the entries in a first entry set, which is a set of entries stored in the master block 7. The master block 7 is configured to store data that is frequently searched (high priority).

[0099] If all search results in the master block 7 are mismatches (misses), the slave drive signal generation circuit 71 outputs a slave drive signal to activate a search operation in the slave block 8. As in the first embodiment, the slave drive signal generation circuit 71 enables the slave block 8 to operate in synchronization with the start of operation of the master block 7, but in this embodiment, the slave drive signal generation circuit 71 stops the slave block 8 when a match is obtained in the master block 7.

[0100] In other words, the slave drive signal generation circuit 71 controls the slave block 8 to be activated in response to the start of operation of the master block 7, and controls the slave block 8 to continue being activated or to be deactivated in response to the result of the judgment of the search circuit in the master block 7.

[0101] The master FF 72 is a register for delaying the search result of the master block 7 by one clock, as in the first embodiment.

[0102] The slave block 8 has a memory array configured with, for example, 64-entry, 64-bit TCAM cells. In Fig. 14, the slave block 8 is provided with three slave blocks 8a, 8b, and 8c, all of which have the same configuration. The slave block 8 stores a second entry set, which is a portion of the data entries stored in the memory array 9 excluding the 64 entries of the first entry set.

[0103] According to the above configuration, the semiconductor device 1A has a memory array 9. The memory array 9 has a master block 7 that stores a first set of entries, which is a set of some of the multiple data entries. It also has a slave block 8 that stores a second set of entries, which is a set of the remaining multiple data entries excluding the first set of entries. The master block 7 has a search circuit that determines whether any of the entries in the first set of entries matches search data. The master block 7 controls the slave block 8 to be activated in response to the start of the search circuit's determination, and controls the slave block 8 to continue being activated or to be inactivated in response to the result of the search circuit's determination.

[0104] Therefore, as in the first embodiment, in the case of a circuit configuration in which whether or not to stop the slave block 3 is determined based on the search result of the master block 7, by enabling the slave block 3 to operate in accordance with the operation of the master block 7, it is not necessary to wait for the search result of the master block, and therefore the content addressable memory can operate faster.

[0105] Furthermore, by storing data that is frequently searched in the master block 7, the frequency with which the slave block 8 is stopped can be increased, thereby reducing power consumption.

[0106] In the case of content addressable memory, whether a slave block can be stopped depends on how often the master block matches (hits). By dividing the data in the entry direction, as in this embodiment, data that is likely to be hit can be stored in the master block. Therefore, by using the configuration of this embodiment, it is possible to increase the frequency with which slave blocks can be stopped.

[0107] (Application example) Finally, an application example of the above-mentioned embodiment will be described. The semiconductor device 1 or 1A (content addressable memory) shown in Fig. 1 or 14 can be used for address search and access control in a router for a network such as the Internet. An example of an address search system in a router using the semiconductor device 1 or 1A is shown in Fig. 15.

[0108] The address search system 150 shown in FIG. 15 includes the semiconductor device 1 or 1A, a PLL 101, a central control unit 102, a data input block 103, and an output processing block 104.

[0109] PLL 101 is a well-known phase-locked loop circuit that outputs a clock signal CLK to semiconductor device 1 or 1A. Central control device 102 outputs a search request signal to semiconductor device 1 or 1A. Central control device 102 also outputs search data to the data input block. Data input block 103 outputs the search data input from central control device 102 to semiconductor device 1 or 1A. Based on the search results output from semiconductor device 1 or 1A, the output processing block outputs a matching (hit) address to central control device 102.

[0110] 15 has network data such as IP addresses stored in advance. After starting a search operation, the central control device 102 inputs a search request signal to the semiconductor device 1 or 1A, and simultaneously inputs the data to be searched from the data input block 103 to the semiconductor device 1 or 1A. The semiconductor device 1 or 1A compares the data stored in the memory array with the data to be searched, and passes all matching addresses to the output processing block 104. The output processing block 104 outputs the corresponding address with the highest priority to the central control device 102. The priority may be determined by address, for example, by arranging high-priority information in the lower addresses of the memory array, or may be determined by providing a priority encoder or the like.

[0111] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0112] 1. Semiconductor device 2 Master Block (1st Block) 3 Slave block (second block) 4 Memory Array 7 Master Block (1st Block) 8 Slave Block (Second Block) 9 Memory Array 21 Search section (first search circuit) 22 All-Miss judgment circuit 23 SLEN generation circuit (drive control circuit) 31 Search section (second search circuit) 71 Slave drive signal generation circuit (drive control circuit)

Claims

1. a memory array included in a content addressable memory having a function of determining whether a plurality of data entries stored therein match at least a portion of externally input search data, the memory array comprising: a first block for storing a first portion of a bit string constituting the data entry; and a second block for storing a second portion of the bit string excluding the first portion; a first search circuit included in the first block for determining whether any of the plurality of first portions matches a portion of the search data corresponding to the first portion; the first block controls the second block to be activated in response to the start of determination by the first search circuit, and controls the second block to continue the activation or to be inactivated in response to a result of the determination by the first search circuit; Semiconductor device.

2. 2. The semiconductor device according to claim 1, the first block has a drive control circuit that outputs a drive signal to the second block to control the second block to be activated or inactivated; Semiconductor device.

3. 3. The semiconductor device according to claim 2, the second block has a plurality of sub-blocks that store the plurality of third portions that make up the second portion, the sub-block determines whether any of the plurality of third portions matches a portion of the search data corresponding to the third portion; the drive control circuit outputs the drive signals to the plurality of sub-blocks to control the sub-blocks to be activated or inactivated; Semiconductor device.

4. 4. The semiconductor device according to claim 3, a match detection circuit that determines whether the search data matches the data entry by performing a logical product of a determination result of the first block and a determination result of the plurality of sub-blocks; Semiconductor device.

5. 2. The semiconductor device according to claim 1, a second search circuit included in the second block, which determines whether any of the second portions matches a portion of the search data corresponding to the second portion in accordance with the determination in the first block; the second search circuit performs the determination when the second block is activated by the first block, and does not perform the determination when the second block is deactivated by the first block; Semiconductor device.

6. a memory array included in a content addressable memory having a function of determining whether a plurality of data entries stored therein match at least a portion of externally input search data, the memory array comprising: a first block for storing a first set of entries which is a set of some of the plurality of data entries; and a second block for storing a second set of entries which is the plurality of data entries excluding the first set of entries; a first search circuit included in the first block for determining whether any of the first entry set matches the search data; the first block controls the second block to be activated in response to the start of determination by the first search circuit, and controls the second block to continue the activation or to be inactivated in response to a result of the determination by the first search circuit; Semiconductor device.

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