Storage device

Abstract

To provide a highly reliable storage device.SOLUTION: A first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are sequentially provided on a side surface of a first conductor extending in a first direction when viewed from the first conductor side. The first conductor includes a first region overlapping with the second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with the third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween. A fourth conductor is provided between the first insulator and the first semiconductor in the second region.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. , process, machine, manufacture, or composition of matter (This is related to the above.)

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. It refers to semiconductor elements such as transistors and diodes, as well as semiconductor devices. The circuit is a semiconductor device. Also, the circuit is applicable to display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, etc. Devices, imaging devices, communication devices, and electronic equipment may contain semiconductor elements and semiconductor circuits. In addition, the present invention is applicable to display devices, light-emitting devices, lighting devices, electro-optical devices, storage devices, imaging devices, communication devices, etc. Devices and electronic devices may also be called semiconductor devices. [Background technology]

[0004] In recent years, with the increase in the amount of data handled, there has been a demand for semiconductor devices with larger storage capacities. To increase the storage capacity per unit area, memory cells are stacked. It is effective to form the memory cells in a stacked structure (see Patent Documents 1 and 2). This makes it possible to increase the storage capacity per unit area in accordance with the number of stacked memory cells. Patent Documents 3 and 4 disclose memory devices using oxide semiconductors. Patent Document 5 discloses a semiconductor memory using an oxide semiconductor as a charge storage layer. are. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Publication No. 2011 / 0065270A1 [Patent Document 2] U.S. Patent Publication No. 9634097B2 [Patent Document 3] Patent Publication No. 2018-207038 [Patent Document 4] Patent Publication No. 2019-8862 [Patent Document 5] Patent Publication No. 2018-157205 Summary of the Invention [Problem to be solved by the invention]

[0006] In Patent Document 1 and Patent Document 2, a plurality of memory elements (also called memory cells) are stacked. These are connected in series to form a three-dimensional memory cell array (memory stack). (also called a ring).

[0007] In Patent Document 1, a semiconductor provided in a columnar shape is in contact with an insulator having a charge storage layer. In Patent Document 2, a semiconductor provided in a pillar shape functions as a tunnel dielectric. Both Patent Document 1 and Patent Document 2 describe the writing of information to a memory cell. The charge is extracted and injected through the insulator. In some cases, trap centers are formed at the interface between a semiconductor and an insulator. The centers can trap electrons and cause the threshold voltage of the transistor to change. This may adversely affect the reliability of the storage device.

[0008] An object of one embodiment of the present invention is to provide a highly reliable memory device. An object of one embodiment of the present invention is to provide a storage device with a large storage capacity. An object of one embodiment of the present invention is to provide a memory device that occupies a small area. An object of one embodiment of the present invention is to provide a memory device with low manufacturing costs. An object of one embodiment of the present invention is to provide a highly reliable semiconductor device. An object of one embodiment of the present invention is to provide a semiconductor device that can be manufactured at low cost. An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0009] The description of these problems does not preclude the existence of other problems. The embodiment does not necessarily solve all of these problems. Problems other than these may be solved by the description. The above is self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other issues. [Means for solving the problem]

[0010] In one aspect of the present invention, a first conductor is provided on a side surface of the first conductor extending in a first direction, the first conductor being provided with a first A first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order. The semiconductor device has a first conductor, a first insulator, a first semiconductor, a second insulator, and a second semiconductor. a first region overlapping the second conductor through a third insulator; a first insulator; a first semiconductor; a second region overlapping the third conductor through a second insulator, a second semiconductor, and a third insulator; In the second region, a fourth conductor is provided between the second insulator and the second semiconductor.

[0011] Another aspect of the present invention is a semiconductor device including a first conductor, a second conductor, a third conductor, a fourth conductor, and a fourth conductor. A first insulator, a second insulator, a third insulator, a first semiconductor, a second semiconductor, and a first transistor. the first conductor extends in a first direction, and a side surface of the first conductor extending in the first direction In the above, the first insulator is provided adjacent to the first conductor, and the first semiconductor is provided adjacent to the first insulator. a second insulator is disposed adjacent to the first semiconductor, and the second semiconductor is disposed adjacent to the second insulator; a third insulator disposed adjacent to the second semiconductor; and a first conductor disposed adjacent to the first region. a first region and a second region, and in the first region, a second conductor is provided adjacent to a third insulator. In the second region, a third conductor is provided adjacent to the third insulator, and in the second region, The fourth conductor is provided between the second insulator and the second semiconductor, and the first semiconductor and the second semiconductor is a memory device electrically connected to one of the source and drain of the first transistor, be.

[0012] In the first region, a first insulator, a second insulator, a third insulator, a first semiconductor, and a second semiconductor Preferably, the first insulating body is provided concentrically in the second region. The first semiconductor, the second insulator, the third insulator, the first semiconductor, the second semiconductor, and the fourth conductor are arranged concentrically. It is preferable that a stator is provided.

[0013] The first region can function as a second transistor. The second region can function as a third transistor. The first semiconductor is preferably an oxide semiconductor. The second semiconductor is preferably an oxide semiconductor. Preferably, the material is a nitride semiconductor.

[0014] The carrier concentration of the first semiconductor is 4×10 17 / cm3 Over 1.4 x 10 18 / cm 3 below The sheet resistance of the first semiconductor is preferably 3×10 5 Ω / □ or more 1×10 6 Ω / □ or less preferable. [Effects of the Invention]

[0015] According to one embodiment of the present invention, a highly reliable memory device can be provided. According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. Therefore, a memory device with a small area can be provided. It is possible to provide a memory device with low manufacturing costs. Furthermore, according to one embodiment of the present invention, a semiconductor device with high manufacturing cost can be provided. Furthermore, according to one embodiment of the present invention, a novel semiconductor An apparatus can be provided.

[0016] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0017] [Figure 1] FIG. 1 is a perspective view of a storage device. [Figure 2] FIG. 2 is a cross-sectional view of the storage device. [Figure 3] FIG. 3 is a cross-sectional view of a memory string. [Figure 4]FIG. 4 is a cross-sectional view of a memory string. [Figure 5] 5A and 5B are cross-sectional views of a memory string. [Figure 6] 6A and 6B are cross-sectional views of a memory string. [Figure 7] 7A and 7B are cross-sectional and perspective views of a memory element. [Figure 8] 8A and 8B are cross-sectional views of a memory string. [Figure 9] 9A and 9B are cross-sectional views of a memory string. [Figure 10] 10A to 10F are cross-sectional views of a memory string. [Figure 11] Figure 11A is a diagram explaining the classification of IGZO crystal structures, Figure 11B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 11C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 12] 12A to 12C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A to 13C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A to 14C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A to 15C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A to 16C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A to 17D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A and 18B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 19]19A to 19C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A to 20C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A to 21C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 22] 22A to 22C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 23] 23A to 23C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 24] 24A to 24C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 25] 25A to 25C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 26] 26A to 26C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 27 is a diagram illustrating an example of the configuration of an MOCVD apparatus. [Figure 28] Fig. 28A is a schematic diagram of a multi-chamber film forming apparatus, and Fig. 28B is a cross-sectional view of a film forming chamber. [Figure 29] FIG. 29 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 30] FIG. 30 is an equivalent circuit diagram of the memory element MC. [Figure 31] FIG. 31 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 32] FIG. 32 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 33] FIG. 33 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 34] FIG. 34 is a timing chart illustrating an example of a write operation of a memory string. [Figure 35] 35A and 35B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 36] 36A and 36B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 37] 37A and 37B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 38] 38A and 38B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 39] 39A and 39B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 40] 40A and 40B are timing charts illustrating an example of a read operation of a memory string. [Figure 41] 41A and 41B are circuit diagrams illustrating an example of a read operation of a memory string. [Figure 42] 42A and 42B are circuit diagrams illustrating an example of a read operation of a memory string. [Figure 43] 43A and 43B are diagrams illustrating the Id-Vg characteristics of a transistor. [Figure 44] FIG. 44 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 45] FIG. 45 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 46] FIG. 46 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 47] FIG. 47 is a perspective view of a storage device. [Figure 48] FIG. 48 is a cross-sectional view of a storage device. [Figure 49] FIG. 49 is a cross-sectional view of a memory string. [Figure 50] FIG. 50 is a cross-sectional view of a memory string. [Figure 51]51A to 51C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 52] 52A to 52C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 53] 53A to 53C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 54] 54A to 54C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 55] 55A to 55C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 56] 56A to 56D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 57] 57A to 57C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 58] 58A to 58C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 59] 59A to 59C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 60] 60A to 60C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 61] 61A to 61C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 62] 62A to 62C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 63] 63A to 63C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 64] 64A to 64C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 65]65A to 65C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 66] 66A to 66C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 67] 67A to 67C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 68] FIG. 68 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 69] FIG. 69 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 70] 70A to 70C are perspective views illustrating configuration examples of a semiconductor device. [Figure 71] FIG. 71 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 72] FIG. 72 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 73] Fig. 73A is a schematic diagram of a semiconductor device, and Fig. 73B is a perspective view of the semiconductor device. [Figure 74] 74A to 74E are diagrams for explaining an example of a storage device. [Figure 75] 75A to 75G are diagrams for explaining an example of an electronic device. [Figure 76] 76A and 76B are diagrams showing the two-dimensional structure of a memory string. [Figure 77] FIG. 77 is an equivalent circuit diagram of a memory string. [Figure 78] 78A to 78H are diagrams for explaining the calculation results of the read operation. [Figure 79] FIG. 79 is a diagram for explaining the calculation results of the read operation. DETAILED DESCRIPTION OF THE INVENTION

[0018] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. Therefore, the present invention is based on the following embodiments. It should be noted that the following description of the invention is not intended to be limiting. In this case, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. The explanation will be omitted here.

[0019] In addition, the position, size, range, etc. of each component shown in the drawings are for the purpose of facilitating understanding of the invention. Therefore, the actual location, size, range, etc. may not be shown. The invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings. In the actual manufacturing process, resist masks, etc., may be unintentionally damaged by etching or other processes. However, this may not be reflected in the diagram to make it easier to understand.

[0020] In addition, in the drawings, etc., some components are omitted to make the explanation easier to understand. This may occur.

[0021] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0022] In this specification, a "terminal" in an electric circuit is a terminal that can be used to input or output a current, It refers to the part where pressure is input or output, or where a signal is received or transmitted. In some cases, a part of the wiring or electrode functions as a terminal.

[0023] In this specification, the terms "above" and "below" refer to the positional relationship of components directly above or below each other. For example, "electrode on insulating layer A" is not limited to being below and in direct contact with the insulating layer A. If the expression is "B", electrode B does not need to be formed directly on insulating layer A, The inclusion of other components between the edge layer A and the electrode B is not excluded.

[0024] The source and drain functions may also be different when using transistors with different polarities or when using circuits When the direction of the current changes during circuit operation, they are interchanged depending on the operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. In this specification, the terms source and drain may be used interchangeably. Let's say.

[0025] In this specification, "electrically connected" refers to a direct connection and a connection made by some means. This includes cases where the device is connected via "something that has an electrical effect." "Something that has an electrical effect" means something that allows the transmission and reception of electrical signals between connected objects. Therefore, even if it is expressed as "electrically connecting," In real circuits, there may be no physical connections, just wires running along the circuit. .

[0026] In this specification, "parallel" means that two lines are at an angle of -10° to 10°. This refers to the state in which the object is arranged at an angle between -5° and 5°. Also, "perpendicular" and "orthogonal" mean, for example, that two straight lines are at an angle of 80° or more and 100° or less. This refers to a state in which the object is arranged at an angle between 85° and 95°.

[0027] In this specification and elsewhere, the counting values ​​and the measurement values, or the counting values ​​or the measurement values, "identical," "same," "equal" with respect to things, methods, and events that can be converted into quantitative values Or when we say "uniform", unless otherwise specified, it is within the range of plus or minus 20%. This includes errors.

[0028] In addition, in this specification, the terms "adjacent" and "nearby" mean that components are in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" means that It is not necessary for the insulating layer A and the electrode B to be formed in direct contact with each other, and no other structure is required between the insulating layer A and the electrode B. This does not exclude those that include compositional elements.

[0029] Voltage is the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and the like, unless otherwise specified, voltage and potential can be interchangeable. It shall be.

[0030] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be written as "insulator." Therefore, it is possible to use "semiconductor" instead of "insulator." In this case, the boundary between "semiconductor" and "insulator" is vague, and it is difficult to make a strict distinction between the two. Therefore, the terms "semiconductor" and "insulator" used in this specification can be interpreted interchangeably. This may be possible.

[0031] Also, even if a material is written as a "semiconductor," if the material has a sufficiently high conductivity, it may be written as a "conductor." Therefore, it is possible to use "semiconductor" instead of "conductor." In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to make a strict distinction between the two. Therefore, the terms "semiconductor" and "conductor" in this specification can be interpreted interchangeably. This may be possible.

[0032] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It does not indicate any order or ranking such as the order of processes or stacking. In addition, even if a term is not accompanied by an ordinal number in this specification, etc., it is possible to avoid confusion of the constituent elements. In order to avoid this, ordinal numbers may be used in the claims. Even if a term has an ordinal number in In addition, even if a term is accompanied by an ordinal number in this specification, Ordinal numbers may be omitted in patent claims, etc.

[0033] In this specification, the "on state" of a transistor means that the source and This refers to a state in which the drain is considered to be electrically short-circuited (also called a "conducting state"). The "off state" of a transistor means that the source and drain of the transistor are electrically isolated. This refers to a state in which the conduction state can be considered to be non-conductive (also called a "non-conductive state").

[0034] In this specification, the term "on-state current" refers to the current flowing between the source and the transistor when the transistor is in the on state. The term "off-state current" may refer to the current that flows between the drain and the transistor. It can also refer to the current that flows between the source and drain when the device is in an open state.

[0035] In addition, in this specification and the like, a high power supply potential VDD (hereinafter simply referred to as "VDD", "H potential", or or "H") is the low power supply potential VSS (hereinafter simply referred to as "VSS", "L potential", or VSS refers to the power supply potential that is higher than VDD. It also refers to the power supply potential, which is the lowest potential. For example, VDD can be used as the ground potential. In the case of a potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than ground potential.

[0036] In addition, unless otherwise specified, the transistors shown in this specification and the like are enhancement transistors. The transistor is a normally-off n-channel field effect transistor. The threshold voltage (also called "Vth") is greater than 0V. Except in the case where "H potential is supplied to the gate of a transistor" means "to Unless otherwise specified, the term "transistor" is sometimes used interchangeably with "transistor on." "To supply an L potential to the gate of a transistor" is equivalent to "to turn off the transistor." There are cases where...

[0037] In this specification, the term "gate" refers to a gate electrode and a part or all of a gate wiring. The gate wiring is a wiring that connects the gate electrode of at least one transistor and another This refers to wiring that electrically connects electrodes or other wiring.

[0038] In this specification, the source includes a source region, a source electrode, and a source wiring. The source region is a semiconductor layer with a resistivity below a certain value. The source electrode is the conductive layer connected to the source region. The source wiring is a wiring that connects the source electrode of at least one transistor with another electrode or wiring. This refers to the wiring that electrically connects the

[0039] In this specification, the term "drain" refers to a drain region, a drain electrode, and a drain electrode. The drain region is a part or all of the wiring. The drain electrode is the conductive layer connected to the drain region. The drain wiring is a wiring that is connected to the drain electrode of at least one transistor. This refers to wiring that electrically connects electrodes or other wiring.

[0040] In addition, in drawings, etc., the potentials of the wiring and electrodes are shown in order to make them easier to understand. "H" indicating high potential or "L" indicating low potential may be added next to the electrode. In addition, wiring and electrodes where a potential change occurs are marked with "H" or "L" in a circle. When a transistor is in an off state, the transistor is An "x" symbol may be added.

[0041] Generally, a "capacitance" has a structure in which two electrodes face each other through an insulator (dielectric). In this specification and the like, the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, a "capacitance element" refers to a capacitor having two electrodes facing each other with an insulator interposed therebetween. a structure in which two wires face each other through an insulator; This includes cases where two wires are arranged with an insulator between them.

[0042] In addition, in this specification and the like, when the same reference numeral is used for a plurality of elements, it is not necessary to particularly distinguish between them. When necessary, use symbols such as "[1]", "[2]", "[n]", "[m,n]", etc. For example, the second wiring GL is written as wiring GL[2 ] may be written as follows.

[0043] (Embodiment 1) FIG. 1 shows a perspective view of a storage device 100 according to one embodiment of the present invention. FIG. 2 shows the memory device having the original stacked structure of the area A1-A2 shown by the dashed line in FIG. 1 and other figures, arrows indicating the X, Y, and Z directions are provided. The X, Y, and Z directions are perpendicular to each other. In this specification and elsewhere, one of the X direction, Y direction, and Z direction is referred to as the "first direction" or the "first The other one is sometimes called the "second direction" or "second direction." The remaining one is sometimes called the "third direction" or "third direction."

[0044] Figure 2 shows a cross section of the XZ plane. Therefore, some of the components may be omitted in Figures 1 and 2, etc.

[0045] <Storage device configuration example> A memory device 100 according to one embodiment of the present invention includes a memory cell array 110. The array 110 has a plurality of memory strings 120. The memory strings 120 are arranged in the Z direction. They extend in both directions and are arranged in a matrix on the XY plane.

[0046] FIG. 3 shows an example of a cross-sectional structure of a memory string 120 according to one embodiment of the present invention. The ring 120 has a structure in which a plurality of storage elements MC (also called "memory cells") are connected in series. In this embodiment, five memory elements MC are connected in series. However, the number of memory elements MC included in the memory string 120 is not limited to five. If the number of memory elements MC included in the memory string 120 is n, n is an integer of 2 or more. That's fine.

[0047] The memory string 120 also includes a plurality of conductors WWL, a plurality of conductors RWL, and a conductor In the memory cell array 110, the conductors WWL, RWL, and the conductor SG extends in the X direction. The plurality of conductors WWL and the plurality of conductors RWL are The conductors SG are alternately stacked with the insulators 123 interposed therebetween. It is provided in a layer below L and the plurality of conductors RWL.

[0048] In FIG. 3, the five storage elements MC are shown as storage elements MC[1] to MC[5]. In addition, when explaining matters common to the storage elements MC[1] to MC[5], the following will be simply explained. The memory element MC is shown in FIG. 1. The other elements, such as the conductor WWL, the conductor RWL, and the insulator 123, are The same applies to the components of

[0049] The memory string 120 includes a transistor STr 1 and a transistor STr2 electrically connected to the memory element MC[5].

[0050] The gate of the transistor STr2 is electrically connected to the conductor SEL. can function as the gate electrode of transistor STr2. Alternatively, one of the drains is electrically connected to the conductor BL.

[0051] The conductors WWL, RWL, and SG extend beyond the memory cell array 110. The conductor WWL, the conductor RWL, and the conductor SG are regions where the memory They are stacked in a stepped manner outside the cell array 110 (see FIGS. 1 and 2).

[0052] FIG. 5A shows a cross section of the portion B1-B2 indicated by the dashed line in FIG. 3 as seen from the Z direction. A cross section of the area C1-C2 indicated by the dashed line in the Z direction is shown in Figure 5B. An enlarged view of the indicated region 105 is shown in Figure 7A. Figure 7A corresponds to a cross-sectional view of the memory element MC. .

[0053] The memory string 120 has a conductor 122 on a substrate 121. The substrate 121 is For example, an insulator may be used. A substrate, which will be described later, may also be used as the base 121. On the conductor 122, there is an insulator 123[1], a conductor SG, an insulator 123[2], and a conductor RWL. [1], insulator 123[3], conductor WWL[1], insulator 123[4], conductor RWL [2], insulator 123[5], conductor WWL[2], insulator 123[6], conductor RWL [3], insulator 123[7], conductor WWL[3], insulator 123[8], conductor RWL [4], insulator 123[9], conductor WWL[4], insulator 123

[10] , conductor RW L[5], insulator 123

[11] , conductor WWL[5], and insulator 123

[12] (See Figure 3).

[0054] The memory string 120 includes an insulator 123[1], a conductor SG, and an insulator 123[2 ], conductor RWL[1], insulator 123[3], conductor WWL[1], insulator 123[4 ], conductor RWL[2], insulator 123[5], conductor WWL[2], insulator 123[6 ], conductor RWL[3], insulator 123[7], conductor WWL[3], insulator 123[8 ], conductor RWL[4], insulator 123[9], conductor WWL[4], insulator 123

[0010] , conductor RWL[5], insulator 123

[11] , conductor WWL[5], and insulator 123

[12] , each of which has a partially removed opening 141 (see FIG. 4). To make it easier to recognize 41, some of the components are shown with dashed lines in FIG.

[0055] The opening 141 extends in the Z direction and reaches the conductor 122. The diameter of the region 142 overlapping with the conductor RWL is larger than the diameter of the region 143 overlapping with the conductor WWL. Therefore, the side surface of the opening 141 has an uneven shape.

[0056] An insulator 124 and a semiconductor 125 are provided along the side of the opening 141. (See FIGS. 3, 5A, and 5B.) The semiconductor 125 is formed in the opening 141 through the insulator 124. It has an area that overlaps with the side.

[0057] The memory string 120 also has a conductor 130 extending in the Z direction. 0 is electrically connected to the conductor BG. The conductor 130 is located at or near the center of the opening 141. In addition, the insulator 129 is provided in the area where the conductor 130 overlaps the side surface of the opening 141. , a semiconductor 127, and an insulator 126. The semiconductor 127 is connected to the insulator 129. The insulator 126 has an area overlapping the side of the conductor 130 via the insulator 129. and a region overlapping with the side surface of the conductor 130 via the semiconductor 127. At the bottom of 41, semiconductor 127 has an area that is in electrical contact with conductor 122. In addition, the semiconductor 125 is electrically connected to the conductor 122 via the semiconductor 127. At the bottom of the opening 141, the conductor 130 is connected to the insulator 129 and the semiconductor 127. The conductor 130 has an overlapping area with the conductor 122. The conductor 130 has an overlapping area with the conductor RWL. In the semiconductor device, a conductor 128 is provided between a semiconductor 125 and an insulator 126 .

[0058] Between the conductor WWL and the conductor 130, an insulator 124 and a semiconductor 1 25, an insulator 126, a semiconductor 127, and an insulator 129 are provided in this order (see FIG. 5A). Between the conductor RWL and the conductor 130, an insulator 124, a semiconductor 12 5, a conductor 128, an insulator 126, a semiconductor 127, and an insulator 129 are provided in this order. (See Figure 5B).

[0059] 5A and 5B show a cross section (XY cross section) of one memory string 120. 6A and 6B show an example in which a plurality of memory strings 120 are provided. The memory strings 120 may be arranged side by side in the X-axis direction or in the Y-axis direction. They may be arranged side by side or in a matrix.

[0060] The memory element MC includes a transistor WTr and a transistor RTr (see FIG. 7A). The region where the conductor WWL and the conductor 130 overlap functions as the transistor WTr. When this is done, the intersection of the conductor WWL and the conductor 130 functions as a transistor WTr. At the intersection of the body WWL and the conductor 130, the insulator 129 is adjacent to the conductor 130, and the semiconductor The semiconductor 127 is adjacent to the insulator 129. The insulator 126 is adjacent to the semiconductor 127. The semiconductor 125 is adjacent to the insulator 126. Also, the insulator 124 is adjacent to the semiconductor 125.

[0061] The conductor WWL functions as the gate electrode of the transistor WTr, and the conductor 130 functions as the gate electrode of the transistor WTr. A part of the semiconductor 125 functions as a back gate electrode of the transistor WTr. It functions as a semiconductor layer in which the channel of the transistor WTr is formed. The semiconductor layer in which the panel is formed is connected to the gate electrode (conductor WWL) through a part of the insulator 124. In this embodiment and the like, a part of the conductor WWL functions as a gate electrode. In this example, the gate electrode and the conductor WWL are provided independently and connected to each other by an electric current. They may also be electrically connected.

[0062] The region where the conductor RWL and the conductor 130 overlap functions as the transistor RTr. In other words, the intersection of the conductor RWL and the conductor 130 functions as a transistor RTr. Furthermore, a conductor 128 is provided at the intersection of the conductor RWL and the conductor 130. At the intersection of the conductor WWL and the conductor 130, as well as at the intersection of the conductor RWL and the conductor 130, In this example, the insulator 129, the semiconductor 127, the insulator 126, the semiconductor 125, and the insulator 1 24 have overlapping areas in the direction perpendicular to the Z direction. At the intersection of the conductor RWL and the conductor 130, the conductor 12 is formed between the insulator 126 and the semiconductor 125. 8, which is different from the intersection of the conductor WWL and the conductor 130.

[0063] The conductor RWL functions as the gate electrode of the transistor RTr. A part of the semiconductor 127 functions as a back gate electrode of the transistor RTr. It functions as a semiconductor layer in which the channel of the transistor RTr is formed. The semiconductor layer in which the channel is formed is made up of an insulator 126, a conductor 128, a semiconductor 125, and an insulator 126. The gate electrode (conductor RWL) overlaps with a part of each of the insulators 124. The semiconductor layer in which the channel of the RTr is formed is connected to the back gate electrode via a part of the insulator 129. In this embodiment, a part of the conductor RWL overlaps with the back electrode (conductor 130). Although an example is shown in which the gate electrode functions as a back gate electrode, Alternatively, they may be provided independently and electrically connected to each other.

[0064] One of the source and drain of the transistor STr1 is connected to the semiconductor of the transistor WTr. The conductor 125 is electrically connected to the semiconductor 127 of the transistor RTr. , one of the source and drain of the transistor STr2 is connected to the The semiconductor 125 and the semiconductor 127 of the transistor RTr are electrically connected.

[0065] Here, we will explain the back gate. The gate and back gate are The back gate functions similarly to the gate. In addition, by changing the potential of the back gate, the threshold voltage of the transistor can be The gate or back gate can be set as the "first gate" or or "first gate" and the other is called "second gate" or "second gate" There is.

[0066] The gate and back gate are formed from conductive layers or semiconductor layers with low resistivity, The electric field generated outside the transistor does not affect the semiconductor layer where the channel is formed. In other words, it has the function of shielding against external factors such as static electricity. This makes it possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of the electric field.

[0067] In addition, the threshold voltage of the transistor can be controlled by controlling the potential of the back gate. The back gate potential can be set to the same potential as the gate, or to the ground potential (GND It may be a potential) or any other potential.

[0068] The semiconductor layer in which the channels of the transistors WTr and RTr are formed is a single-crystal crystalline semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, amorphous semiconductor, etc., either alone or in combination. Examples of semiconductor materials include silicon and germanium. Also usable are silicon germanium, silicon carbide, and gallium arsenide. Alternatively, a compound semiconductor such as an oxide semiconductor or a nitride semiconductor may be used. 1 and transistor STr2 in the same manner.

[0069] Note that the semiconductor layers used in the transistor may be stacked. Semiconductors having different crystal states may be used for each of the layers, or different semiconductor materials may be used for each of the layers. It's fine.

[0070] Transistor WTr, transistor RTr, transistor STr1, and transistor The semiconductor layer used in STr2 is preferably an oxide semiconductor containing a metal oxide. A transistor that uses metal oxide for the semiconductor layer is similar to a transistor that uses amorphous silicon for the semiconductor layer. Compared to transistors using polycrystalline silicon, it has a high field effect mobility. In a transistor using a conductor layer, there is a risk of grain boundaries occurring in the semiconductor layer. carriers are trapped, which causes a decrease in the on-state current of the transistor and a decrease in the field-effect mobility. On the other hand, as will be explained in detail later, oxide semiconductors have no clear grain boundaries. It is possible to realize a crystal structure in which no grain boundaries are observed or in which there are very few grain boundaries. The use of such an oxide semiconductor for the semiconductor layer results in a high on-state current and a high field-effect transition. This is preferable because it allows realization of a transistor having good electrical properties such as mobility.

[0071] In addition, oxide semiconductors, especially crystalline oxide semiconductors such as CAAC-IGZO, Nanoclusters of a few nm (e.g., 1 to 3 nm) whose c-axis is oriented in the direction perpendicular to the surface on which they are formed. Therefore, even in an opening extending in the Z direction, It is possible to form a crystal structure in which no clear crystal grain boundaries are observed.

[0072] In particular, the transistor WTr has a semiconductor layer in which the channel is formed, which is a type of metal oxide. A transistor including an oxide semiconductor (also referred to as an "OS transistor") is preferably used. Since oxide semiconductors have a band gap of 2 eV or more, the off-state current is significantly small. If an OS transistor is used for the transistor WTr, the data written to the node ND (described later) will The transistors that make up the memory element MC are OS transistors. When a transistor is used, the memory element MC can be called an "OS memory." The memory string 120 including the memory element MC can also be called an "OS memory." The storage device 100 can also be called "OS memory."

[0073] OS memory can be written for more than one year, or even more than ten years, even if the power supply is cut off. Therefore, the OS memory can be considered non-volatile memory. It is also possible.

[0074] In addition, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory is binary ( It is possible to store not only 1 bit but also multi-value (multi-bit) information.

[0075] In addition, since OS memory uses a method of writing charge to a node via a transistor, This eliminates the need for the high voltage required for conventional flash memory, and also enables high-speed write operations. In addition, the erase operation before rewriting data that is performed in flash memory is performed in OS memory. In addition, charge injection and extraction into the floating gate or charge trapping layer are unnecessary. Since the OS memory can be written to and read from virtually unlimited times, OS memory is less susceptible to deterioration and is more reliable than conventional flash memory. Sex is obtained.

[0076] In addition, the OS memory is magnetoresistive memory (MRAM) or resistive random access memory (ReRAM) ) does not involve structural changes at the atomic level. Therefore, OS memory is a magnetoresistive memory. It has better rewrite endurance than memory and resistive change memory.

[0077] Furthermore, the off-state current of OS transistors hardly increases even in high-temperature environments. The off-state current hardly increases even in ambient temperatures above 200°C and below. The on-state current is unlikely to decrease even in high-temperature environments. In addition, the OS transistor has a stable insulation between the source and drain. By using OS transistors as transistors in a semiconductor device, This makes it possible to realize a semiconductor device that operates stably even in a high-temperature environment and has good reliability.

[0078] The semiconductor 127 is preferably an n-type semiconductor. The region overlapping with the transistor is preferably an i-type or substantially i-type semiconductor. The WTr is an enhancement type (normally off) transistor. The transistor RTr is a depletion type (normally on type) transistor.

[0079] The semiconductor 125 and the semiconductor 127 may be made of the same material or different materials. For example, the semiconductor 125 and the semiconductor 127 may each be an oxide semiconductor. The semiconductor 125 and the semiconductor 127 may each be a semiconductor containing silicon. Alternatively, the semiconductor 125 may be an oxide semiconductor and the semiconductor 127 may be a semiconductor containing silicon. Alternatively, the semiconductor 125 may be a semiconductor containing silicon, and the semiconductor 127 may be a semiconductor containing silicon. may be an oxide semiconductor.

[0080] 7B shows a perspective cross-sectional view of the memory element MC. Therefore, the insulator 123 is not shown in FIG. 7B.

[0081] 5A corresponds to the XY plane at or near the center of the transistor WTr, and B corresponds to the XY plane at or near the center of the transistor RTr. In FIG. 5B, when the cross-sectional shape of the conductor 130 is circular, the insulator 129 is 0 and the semiconductor 127 is provided concentrically outside the insulator 129. The insulator 126 is provided concentrically around the semiconductor 127, and the semiconductor 125 is provided around the insulator 127. The insulator 124 is provided concentrically around the semiconductor 125. The conductor 128 is concentrically disposed between the insulator 126 and the semiconductor 125. It is being done.

[0082] Furthermore, the cross-sectional shape of the conductor 130 is not limited to a circle. The cross-sectional shape may be rectangular, or as shown in FIG. 8B, the cross-sectional shape of the conductor 130 may be triangular. 8A and 8B show the area B1-B2 indicated by the dashed line in FIG. 3 in the Z direction. It corresponds to a cross section seen from the front.

[0083] In addition, by dividing the memory string 120 along the Z-axis direction, This is preferable because it increases the number of memory cells that can be stored in the memory string 120. When dividing along the axial direction, the conductor WWL and the conductor RWL may also be divided.

[0084] FIG. 9A shows a semiconductor device in which the conductors WWL and the memory strings 120 are provided along the XZ plane. 9B shows the conductor RWL and memory The string 120 is divided by an insulator 153 provided along the XZ plane. In Figure 9 and other figures, the symbols of the divided components are suffixed with "a" or "b." .

[0085] As shown in FIG. 9A, the region where the conductor WWLa and the conductor 130a overlap is the transistor WT The transistor WTra functions as a conductor WWLa, an insulator 124a, and a semiconductor body 125a, insulator 126a, semiconductor 127a, insulator 129a, and conductor 130a The conductor WWLa functions as the gate electrode of the transistor WTra, and the conductor 1 The semiconductor 125 functions as a back gate electrode of the transistor WTra. A part of a functions as a semiconductor layer in which the channel of the transistor WTra is formed. The semiconductor layer in which the channel of the transistor WTra is formed is connected to the insulator 124a through a part of the insulator 124a. It overlaps with the gate electrode (conductor WWLa).

[0086] In addition, the region where the conductor WWLb and the conductor 130b overlap functions as the transistor WTrb. The transistor WTrb is made up of a conductor WWLb, an insulator 124b, a semiconductor 125b, and an insulator 126b. It has an insulating material 126b, a semiconductor material 127b, an insulator material 129b, and a conductor material 130b. Conductor WWLb serves as the gate electrode of transistor WTrb, and conductor 130b serves as the gate electrode of transistor WTrb. A part of the semiconductor 125b functions as a back gate electrode of the transistor WTrb. This functions as a semiconductor layer in which the channel of the transistor WTrb is formed. The semiconductor layer in which the channel of rb is formed is connected to the gate electrode (conductor) through a part of the insulator 124b. It overlaps with the electric field WWLb.

[0087] As shown in FIG. 9B, the conductor 128a, the conductor RWLa, and the conductor 130a overlap. The region functions as a transistor RTra. The transistor RTra is connected to RWLa, an insulating body 124a, semiconductor 125a, conductor 128a, insulator 126a, semiconductor 127a, insulation The conductor RWLa has a conductor 129a and a conductor 130a. The conductor 130a functions as a gate electrode. A part of the semiconductor 127a functions as a channel electrode of the transistor RTra. This functions as a semiconductor layer in which the channel of the transistor RTra is formed. The layers are insulator 126a, conductor 128a, semiconductor 125a, and insulator 124a, respectively. The gate electrode (conductor RWLa) overlaps with a part of the gate electrode. The semiconductor layer on which the panel is formed is connected to the back gate electrode (conductor) through a part of the insulator 129a. 130a).

[0088] In addition, the area where the conductor 128b, the conductor RWLb, and the conductor 130b overlap is a transistor. The transistor RTrb functions as a transistor RTrb. Conductor 125b, conductor 128b, insulator 126b, semiconductor 127b, insulator 129b, and and a conductor 130b. The conductor RWLb serves as the gate electrode of the transistor RTrb. In addition, the conductor 130b functions as a back gate electrode of the transistor RTrb. A part of the semiconductor 127b is a semiconductor in which the channel of the transistor RTrb is formed. The semiconductor layer in which the channel of the transistor RTrb is formed is an insulator 1 26b, the conductor 128b, the semiconductor 125b, and the insulator 124b. The channel of the transistor RTrb is formed. The semiconductor layer overlaps the back gate electrode (conductor 130b) via a part of the insulator 129b. become.

[0089] As described above, the conductor WWL, the conductor RWL, and the memory string 120 are divided. This allows the number of memory cells provided in the opening 141 to be doubled. The division method of the memory string 120 is not limited to the above. The strings 120 are divided by insulators 153 extending in the X-axis direction. 10B, the insulator 153 may extend in a direction different from the X-axis direction. As shown in Figure 10B, the memory string 120 may be divided into three or more. 10D show an example of a memory string 120 divided into three parts, and FIG. 10E and 10F shows an example of a memory string 120 divided into four. The number of memory cells provided in the opening 141 can be increased by three times and four times, respectively.

[0090] 10A to 10F, the insulator 153 is a conductor WWL and a conductor RWL. It is preferable to arrange them so as not to interfere with conduction in the X-axis direction.

[0091] The memory string 120 can be called a storage device, and the storage element MC can be called a storage device. It can also be called a placement.

[0092] [Constituent materials of semiconductor device] Next, constituent materials that can be used for the storage device 100 will be described.

[0093] [substrate] The memory device 100 can be provided on a substrate. The substrate can be, for example, an insulating substrate, a semiconductor substrate, or the like. A conductive substrate or an electrically conductive substrate may be used. An insulating substrate may be, for example, a glass substrate. , quartz substrate, sapphire substrate, stabilized zirconia substrate (yttria stabilized zirconia substrate As for semiconductor substrates, for example, silicon, germanium, Semiconductor substrates made of silicon, silicon carbide, silicon germanium, or gallium arsenide Examples include compound semiconductor substrates made of silicon, indium phosphide, zinc oxide, and gallium oxide. Furthermore, the semiconductor substrate having an insulating region inside the semiconductor substrate, for example, SOI (S Silicon-on-insulator (Si-on-insulator) substrates are available. Conductive substrates include graphite. Substrates include metal substrates, alloy substrates, conductive resin substrates, etc. Or, metal nitride substrates There are also substrates with conductive or semiconducting layers on insulating substrates. a substrate having a semiconductor substrate with a conductor or insulator provided thereon; a substrate having a semiconductor substrate with a conductor or insulator provided thereon; There are substrates on which semiconductors or insulators are provided, or elements are provided on these substrates. The elements provided on the substrate may include a capacitor element, a resistor element, a switch element, and the like. These include transistors, light-emitting elements, and memory elements.

[0094] [Insulator] The insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. , metal oxide nitrides, metal nitride oxides, etc.

[0095] In this specification, the term "oxynitride" refers to a material that contains more oxygen than nitrogen. For example, "silicon oxynitride" refers to a silicon material that contains more oxygen than nitrogen. In this specification and the like, the term "nitride oxide" refers to a material containing more nitrogen than oxygen. "Aluminum oxide nitride" refers to a material that contains more nitrogen than oxygen. Indicates aluminum material.

[0096] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. , leakage current and other problems may occur. By using igh-k materials, the voltage required for transistor operation can be reduced while maintaining the physical film thickness. On the other hand, the insulator that functions as the interlayer film should be made of a material with a low dielectric constant. Therefore, depending on the function of the insulator, the parasitic capacitance between the wiring can be reduced. It is advisable to select materials accordingly.

[0097] Insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. oxides containing aluminum, aluminum and hafnium, oxides containing aluminum and hafnium oxides with silicon and hafnium, oxides with silicon and hafnium or nitrides with silicon and hafnium.

[0098] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with added hydrogen and nitrogen, silicon oxide with pores, or resin. do.

[0099] In addition, OS transistors have the function of suppressing the permeation of impurities such as hydrogen and oxygen. By surrounding it with an insulator, the electrical characteristics of the transistor can be stabilized. Examples of insulators that have the function of suppressing the permeation of impurities and oxygen include boron, Carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, Silicon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, halide An insulator containing fluorine or tantalum may be used in a single layer or a multilayer. The oxide film is an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, Zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. Metal oxides, metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride are used. You can be there.

[0100] In addition, when an oxide semiconductor is used for the semiconductor 125 and / or the semiconductor 127, the gate insulating layer The insulator that functions as an insulator is an insulator that has a region containing oxygen that is desorbed by heating. For example, silicon oxide having a region containing oxygen that is desorbed by heating or The silicon oxynitride is in contact with the semiconductor 125 and / or the semiconductor 127. This can compensate for oxygen vacancies in the semiconductor 125 and / or the semiconductor 127. .

[0101] [conductor] Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Niobium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sodium, zirconium, beryllium, indium, ruthenium, iridium, strontium a metal element selected from the group consisting of ruthenium, lanthanum, etc., or an alloy containing the above-mentioned metal element; It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride , titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxides, ruthenium nitrides, strontium and ruthenium It is preferable to use oxides containing lanthanum and nickel, or oxides containing lanthanum and nickel. titanium nitride, titanium and aluminum nitride, tantalum and aluminum nitride Ruthenium nitrides, ruthenium oxides, ruthenium nitrides, oxides containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. It is preferable because it is a material that maintains conductivity even after the addition of impurity elements such as phosphorus. Highly conductive semiconductors, such as polycrystalline silicon, and silicon silicides, such as nickel silicide, A reside may also be used.

[0102] Alternatively, a plurality of conductive layers made of the above materials may be stacked. Alternatively, a laminated structure may be used in which a material containing a metal element and a conductive material containing oxygen are combined. In addition, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen is also available. Also, the material containing the metal element, the conductive material containing oxygen, and the nitrogen A laminated structure in which a conductive material containing the above is combined may also be used.

[0103] Note that an oxide semiconductor, which is a type of metal oxide, is used for a channel formation region of a transistor. In this case, the conductor functioning as the gate electrode includes a material containing the above-mentioned metal element, It is preferable to use a laminated structure in which a conductive material containing oxygen is combined. Preferably, the conductive material containing oxygen is provided on the channel formation region side. By providing the conductive material on the channel formation region side, oxygen released from the conductive material is transferred to the channel formation region. This will make it easier for the supply to the region.

[0104] In particular, the oxide semiconductor in which the channel is formed is used as a conductor that functions as a gate electrode. It is preferable to use a conductive material containing a metal element and oxygen. Conductive materials containing metal elements and nitrogen may also be used. For example, titanium nitride, tantalum nitride, etc. Alternatively, a conductive material containing nitrogen, such as indium tin oxide or tungsten oxide, may be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Indium tin oxide or silicon-doped indium tin oxide may also be used. The use of such a material allows the channel to be formed. In some cases, hydrogen contained in the oxide semiconductor formed on the surface of the oxide film can be captured. In some cases, it may be possible to capture hydrogen that is mixed in from insulators, etc.

[0105] [Oxide semiconductor] As the semiconductor 125 and the semiconductor 127, metal oxides that function as semiconductors (oxide semiconductors) In the following, it is preferable to use a semiconductor 125 and a semiconductor 127. The oxide semiconductor will be described.

[0106] The oxide semiconductor preferably contains at least indium or zinc. It is preferable that the alloy contains aluminum and zinc. It is preferable that the alloy contains boron, titanium, iron, nickel, or the like. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, One selected from aluminum, tantalum, tungsten, magnesium, cobalt, etc. Or, multiple types may be included.

[0107] Here, the oxide semiconductor is an In-M-Zn oxide having indium, element M, and zinc. The element M is aluminum, gallium, yttrium, and The element M can be one or more selected from the group consisting of tin, tin, and tin. Boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, Cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. However, there are cases where the element M may be a combination of multiple elements mentioned above. .

[0108] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides. Nitrogen-containing metal oxides are also called metal oxynitrides (met). It may also be called hydroxybenzoxanthate (hydroxybenzoxanthate).

[0109] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to FIG. 11A. FIG. 11A shows an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn). FIG. 1 is a diagram illustrating the classification of crystal structures of metals (oxides).

[0110] As shown in FIG. 11A, oxide semiconductors can be broadly divided into "amorphous" and ", "Crystalline" and "Crystal" Also, "Amorphous" includes completely amorp Also, "Crystalline" includes CAAC (c-ax is-aligned crystalline), nc(nanocrystalli ne), and CAC (cloud-aligned composite) ( excluding single crystal and poly crystal l). The classification of "Crystalline" includes single crystal, Polycrystalline and completely amorphous materials are excluded. Also, "Crystal" includes single crystal and poly Contains crystals.

[0111] The structures enclosed in the bold frame in Figure 11A are classified into "Amorphous" and "Cry It is an intermediate state between "crystal" and "new crystal" This structure belongs to the line phase. It is completely different from the stable "Amorphous" and "Crystal" This can be rephrased as a structure.

[0112] The crystal structure of the film or substrate can be determined by X-ray diffraction (XRD). It can be evaluated using the "Crystalline" spectrum. CAAC-IGZO films classified as The XRD spectrum obtained by the GIXD measurement is shown in Figure 11B. This is also called the Seemann-Bohlin method. The XRD spectrum obtained by the method shown in FIG. The composition of the AAC-IGZO film is approximately In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in FIG. 11B is 500 nm.

[0113] As shown in Figure 11B, the XRD spectrum of the CAAC-IGZO film shows clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows the following peaks: A peak indicating the c-axis orientation is detected near 2θ=31°. The peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0114] The crystal structure of the film or substrate was also analyzed by nanobeam electron diffraction (NBED). Diffraction patterns observed by electron diffraction (microelectron It can be evaluated by the diffraction pattern of the CAAC-IGZO film. The pattern is shown in Figure 11C. Figure 11C shows the pattern obtained by NBE, in which the electron beam is incident parallel to the substrate. The diffraction pattern observed by the CAAC-IGZO film shown in Figure 11C is The composition is In:Ga:Zn=4:2:3 [atomic ratio]. In the diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0115] As shown in Figure 11C, the diffraction pattern of the CAAC-IGZO film shows multiple c-axis orientations. spots are observed.

[0116] [Oxide semiconductor structure] When focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in FIG. 11A. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors and pseudo-non-crystalline oxide semiconductors. amorphous-like oxide semiconductor (a-like OS) semiconductor), amorphous oxide semiconductor, etc.

[0117] Next, for details on the above-mentioned CAAC-OS, nc-OS, and a-like OS, Give an explanation.

[0118] [CAAC-OS] The CAAC-OS has multiple crystalline regions, each of which has its c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film. The direction normal to the surface on which the CAAC-OS film is formed or the direction normal to the surface of the CAAC-OS film. The crystalline region is a region in which the atomic arrangement has periodicity. When viewed as an arrangement, the crystalline region is also a region with a uniform lattice arrangement. S has a region where multiple crystalline regions are connected in the ab-plane direction, and this region has strain. The distortion is a distortion of the lattice arrangement in the region where multiple crystal regions are connected. A place where the orientation of the lattice arrangement changes between a uniform area and a uniform area with a different lattice arrangement. In other words, the CAAC-OS has a c-axis orientation and no clear orientation in the ab-plane direction. It is an oxide semiconductor that does not contain

[0119] Each of the plurality of crystalline regions is made up of one or more minute crystals (maximum diameter 10n If a crystalline region is made up of a single microcrystal, The maximum diameter of the crystalline region is less than 10 nm. When the crystallized region is formed, the size of the crystallized region may be approximately several tens of nanometers.

[0120] In the In-M-Zn oxide, CAAC-OS is a compound containing indium (In) and oxide. A layer containing element M (hereinafter referred to as In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as They tend to have a layered crystal structure (also called a layered structure) in which the (M, Zn) layer is stacked. Indium and element M can be substituted for each other. Therefore, in the (M, Zn) layer, Indium may be contained. The In layer may contain the element M. The In layer may contain Zn. This layered structure can be seen, for example, in high-resolution TEM images. In this case, it is observed as a lattice image.

[0121] For example, when the structure of the CAAC-OS film is analyzed using an XRD device, the θ / 2θ shift In the out-of-plane XRD measurement using a tuner, the peak indicating the c-axis orientation was = 31° or its vicinity. The position of the peak indicating the c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0122] In addition, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots (spots) ) is observed. Note that one spot and another spot are the result of the incident electron beam passing through the sample. The spot (also called the direct spot) is the center of symmetry, and the observed positions are point-symmetric. do.

[0123] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is a hexagonal lattice. The unit cell is not necessarily a regular hexagon, but may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. In the OS, clear grain boundaries were confirmed even near the strain. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the arrangement of oxygen atoms in the CAAC-OS is dense in the ab-plane direction. The metal atoms are replaced by other atoms, which changes the bond distance between the atoms. This is thought to be because distortion can be tolerated.

[0124] The crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, trapping carriers and forming transistor on-states. Therefore, it is highly likely that this will cause a decrease in the on-state current and a decrease in the field-effect mobility. CAAC-OS, which has no visible grain boundaries, has a crystal structure suitable for the semiconductor layer of a transistor. It is one of the crystalline oxides that can be used to form CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferable. This is preferable because it can suppress the occurrence of grain boundaries more effectively than the material.

[0125] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to the decrease in electron mobility caused by the grain boundaries. In addition, the crystallinity of oxide semiconductors may be reduced due to the inclusion of impurities or the generation of defects. Therefore, CAAC-OS is similar to oxide semiconductors with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having a CAAC-OS are stable. Therefore, oxide semiconductors having CAAC-OS are heat-resistant and highly reliable. -OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process Therefore, using CAAC-OS for OS transistors will increase the flexibility of the manufacturing process. This makes it possible to

[0126] [nc-OS] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). In other words, nc-OS has a periodic atomic arrangement in the region of microscopic The size of the minute crystals is, for example, 1 nm or more and 10 nm or less. In particular, since the size of these tiny crystals is between 1 nm and 3 nm, they are also called nanocrystals. In nc-OS, there is no regularity in the crystal orientation between different nanocrystals. Therefore, depending on the analytical method, nc-OS may be classified as a-like In some cases, it is difficult to distinguish between an OS and an amorphous oxide semiconductor. For example, in the case of an nc-OS film, Structural analysis was performed using an XRD device. Out-of-place analysis using θ / 2θ scan In the XRD measurement, no peaks indicating crystallinity were detected. Electron diffraction using an electron beam with a probe diameter larger than that of nanocrystals (e.g., 50 nm or larger) When performing selected area electron diffraction (also known as selected area electron diffraction), a halo-like diffraction pattern is observed. On the other hand, for the nc-OS film, particles with sizes close to or smaller than the nanocrystals were observed. Electron beam diffraction (nanobeam electron diffraction) using an electron beam with a lobe diameter (for example, 1 nm to 30 nm) When direct beam diffraction is performed, multiple beams are generated within a ring-shaped area centered on the direct spot. An electron diffraction pattern may be obtained in which several spots are observed.

[0127] [a-like OS] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. Conductive. A-like OS has voids or low density regions. The OS has lower crystallinity than the nc-OS and CAAC-OS. The OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0128] [Oxide semiconductor composition] Next, the details of the CAC-OS will be explained. Regarding.

[0129] [CAC-OS] CAC-OS is, for example, a metal oxide in which the elements constituting the metal oxide are 0.5 nm or more and 10 nm or less. Preferably, a material unevenly distributed in a size of 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, it is assumed that one or more metal elements are unevenly distributed in a metal oxide, and the The region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm. A state where the mixture is at or near this size is also called a mosaic or patch state.

[0130] Furthermore, CAC-OS is a mosaic structure in which the material is separated into a first region and a second region. The first region is in a cloud-like shape, and the first region is distributed throughout the film (hereinafter also referred to as a cloud-like shape). In other words, the CAC-OS is a mixture of the first and second regions. It is a composite metal oxide having the following structure.

[0131] Here, the ratio of In to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide is The atomic ratios of In, Ga, and Zn are expressed as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is In this region, [In] is larger than [In] in the composition of the CAC-OS film. The second region is where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region has [In] higher than the [In] in the second region. The first region is larger than the second region, and [Ga] is smaller than [Ga] in the first region. In the second region, [Ga] is larger than [Ga] in the first region, and [In ] is a region smaller than [In] in the first region.

[0132] Specifically, the first region is mainly composed of indium oxide, indium zinc oxide, etc. The second region is a region in which the gallium oxide, gallium zinc oxide, etc. In other words, the first region is called a region where In is the main component. The second region can be rephrased as a region containing Ga as the main component. This can be done.

[0133] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0134] For example, in the case of CAC-OS, an In-Ga-Zn oxide, energy dispersive X-ray spectroscopy Law(EDX:Energy Dispersive X-ray spectrosco The EDX mapping obtained using the py) identified the region containing In as the main component (first region ) and a region (second region) mainly composed of Ga are unevenly distributed and mixed. It can be confirmed that:

[0135] When CAC-OS is used in a transistor, the conductivity due to the first region and the conductivity due to the second region are The insulating properties caused by the above work complementary to each other, resulting in a switching function (On / Off). In other words, CAC-OS is , a part of the material has a conductive function and a part of the material has an insulating function, and the whole of the material has a The material functions as a semiconductor. By separating the conductive function from the insulating function, Therefore, when using CAC-OS in transistors, This allows for a high on-state current (I on ), high field-effect mobility (μ), and good switching This allows for realizing a locking operation.

[0136] Oxide semiconductors have a variety of structures, each of which has different characteristics. Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and CA Two or more of C-OS, nc-OS, and CAAC-OS may be included.

[0137] [Transistor Having an Oxide Semiconductor] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0138] By using the oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized.

[0139] An oxide semiconductor with a low carrier concentration can be used for the channel formation region of a transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is preferably 1×10 18 c m -3 Preferably, it is 1×10 or less. 17 cm -3 It is more preferable that it is less than , 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 Less than More preferably, 1×10 12 cm -3 It is more preferable that it is less than . In addition, when the carrier concentration of the oxide semiconductor film is reduced, impurities in the oxide semiconductor film In this specification and the like, the impurity concentration is low, and the defect level density is low. A low density of defect states is called high purity intrinsic or substantially high purity intrinsic. An oxide semiconductor with a low concentration of arsenic is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. In addition, high purity authenticity or substantially high purity authenticity may be referred to as type i or substantially This is sometimes called type i.

[0140] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Therefore, the trap level density may also be low.

[0141] In addition, it takes a long time for the charges trapped in the trap levels of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. There are cases where this happens.

[0142] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is also preferable to reduce the impurity concentration in the film in contact with the film. Potassium metal, alkaline earth metal, iron, nickel, silicon, etc.

[0143] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0144] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, oxide Defect levels are formed in the semiconductor. The concentration of silicon and carbon in the oxide semiconductor and the silicon near the interface with the channel formation region of the oxide semiconductor and carbon concentration (Secondary Ion Mass Spectrometry (SIMS) The concentration obtained by spectrometry is calculated as 2 x 10 18 atoms / c m 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0145] In addition, when an alkali metal or an alkaline earth metal is contained in an oxide semiconductor, a defect level is formed. Therefore, alkali metals or alkaline earth metals are not included. A transistor using an oxide semiconductor that has been used in the past tends to be normally on. Therefore, the alkali metal or aluminum in the channel formation region of the oxide semiconductor obtained by SIMS The concentration of potassium earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0146] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers As a result, the concentration of nitrogen in the oxide semiconductor increases, making it easier to convert it into an n-type semiconductor. The transistor using the oxide semiconductor is likely to be normally on. If nitrogen is contained, trap levels may be formed. The electrical properties may become unstable. The nitrogen concentration in the channel formation region is set to 5×10 19 atoms / cm 3 Less than 5, preferably x10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Below Lower, more preferably 5 × 10 17 atoms / cm 3 Do the following:

[0147] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electrons acting as carriers are released. In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, it is necessary to use an oxide semiconductor containing hydrogen. Therefore, the transistor tends to be normally on. It is preferable that the hydrogen in the formation region is reduced as much as possible. In the channel formation region of the nitride semiconductor, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 Less than, better Preferably 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atom s / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0148] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor This allows stable electrical properties to be imparted.

[0149] [Other semiconductor materials] The semiconductor materials that can be used for the semiconductor 125 and the semiconductor 127 include the above-mentioned oxide semiconductors. The semiconductor 125 and the semiconductor 127 are not limited to semiconductors having a band gap. A semiconductor material (a semiconductor material that is not a zero-gap semiconductor) may be used. For example, silicon Semiconductors of any element, compound semiconductors such as gallium arsenide, layered materials that function as semiconductors Materials (also called atomic layer materials, two-dimensional materials, etc.) may be used as semiconductor materials. A layered substance that functions as a semiconductor is preferably used as the semiconductor material.

[0150] In this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The crystal structure of the material is such that layers formed by covalent and ionic bonds are held together by van der Waals forces. It is a layered structure formed through bonds weaker than covalent or ionic bonds. The quality is high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material with high two-dimensional electrical conductivity in the channel formation region, It is possible to provide a transistor with a large on-current.

[0151] Layered materials include graphene, silicene, and chalcogenides. Chalcogen is a general term for elements belonging to Group 16. They contain oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0152] The semiconductor 125 and the semiconductor 127 may be, for example, a transition metal chalcogenide that functions as a semiconductor. It is preferable to use genides. As transition metal chalcogenides, specifically, molybdenum sulfide (typically MoS2), Molybdenum telluride (typically MoSe2), molybdenum telluride (typically MoTe2 ), tungsten sulfide (typically WS2), tungsten selenide (typically WSe 2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS 2), hafnium selenide (typically HfSe2), zirconium sulfide (typically Z rS2), zirconium selenide (typically ZrSe2), etc.

[0153] <Example of how to make a memory device>

[0154] Next, an example of a method for manufacturing a memory device according to the present invention will be described with reference to FIGS. 12A to 26C. 12A to 26C, A is a top view seen from the Z direction, and B is a 26A to 26C are cross-sectional views of the area indicated by the dashed line A1-A2 in FIG. In each figure, C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in A. 17D is an enlarged cross-sectional view of the part surrounded by the dashed line in FIG. In the manufacturing method, one memory strip having two (also referred to as "two stages") memory elements MC is formed. However, the present embodiment is not limited to this example. The memory string 20 may have three or more stages of memory elements MC. For example, is 32 stages or more, preferably 64 stages or more, more preferably 128 stages or more, and even more preferably It is preferable that the memory cell array has 256 or more stages of memory elements MC.

[0155] First, a conductor 122 is formed on a substrate 121 having an insulating surface, and the following is formed around the conductor 122: An insulator 132 is formed (see Figures 12A to 12C).

[0156] Specifically, a conductive film is formed, and the conductive film is processed using a lithography method to form a conductor 12. Next, an insulating film is formed on the substrate 121 so as to cover the conductor 122. It is preferable to perform planarization treatment on the insulating film. It is preferable to polish the insulating film until the surface is exposed. However, the method for forming the conductor 122 and the insulator 132 is different from this. However, the present invention is not limited to this. An insulator 132 is formed on the base 121, and unnecessary portions of the insulator 132 are removed. By this, grooves and openings are formed, and the conductor 122 is formed so as to be embedded in the grooves and openings. Such a method for forming a conductor may be a damascene method (single damascene method, dual damascene method, etc.). By the above method, the conductor 12 shown in FIGS. 12A to 12C is formed. 2 and the insulator 132 can be obtained.

[0157] The conductor 122 and the insulator 132 can be formed by a sputtering method, a CVD method, a molecular beam epitaxy method, or the like. MBE (Molecular Beam Epitaxy) method, pulsed laser deposition (PLD: Pulsed Laser Deposition) method or ALD method, etc. This can be done using

[0158] The CVD method is a plasma CVD (PECVD) method that uses plasma. enhanced CVD method, thermal CVD (TCVD) D) method, and photo-CVD (Photo CVD) method, which uses light. Depending on the source gas, metal CVD (MCVD) and metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0159] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the processed object because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device These may become charged up by receiving electric charges from the plasma. The accumulated charge can destroy the wiring, electrodes, elements, etc. contained in the semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage does not occur. In addition, the thermal CVD method does not require the use of a metal oxide film, which increases the yield of semiconductor devices. Since no plasma damage occurs inside the film, a film with few defects can be obtained.

[0160] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with fewer defects can be produced. Obtained.

[0161] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less affected by the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of thin films with high aspect ratios. It is suitable for coating the surface of high openings. However, the ALD method has a relatively low film formation rate. Because the deposition rate is slow, it cannot be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases, this is preferable.

[0162] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having a composition. By changing the flow rate ratio of the source gases while When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film by hand, the time required for film formation is shortened by the time required for transport and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0163] In the lithography method, first, the resist is exposed to light through a photomask. The exposed areas are removed or left behind using a developer to form a resist mask. By etching the resist mask, a conductor, a semiconductor, or an insulator can be formed. For example, KrF excimer laser light, ArF excimer laser light, etc. can be processed into the desired shape. Using laser light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the resist. An immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the light source for exposure. Instead of light, an electron beam or an ion beam may be used. When using a photomask, a photomask is not required. Dry etching such as polishing is performed, wet etching is performed, and dry etching is performed. wet etching after etching, or wet etching after dry etching. A dry etching process can be performed.

[0164] Moreover, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When a hard mask is used, an insulating film or a conductive film that will be the hard mask material is formed on the conductive film. A resist mask is formed thereon, and the hard mask material is etched to form a desired shape. A hard mask having a shape can be formed.

[0165] The above processing can be performed by dry etching or wet etching. Etching is suitable for microfabrication.

[0166] The dry etching equipment is a capacitively coupled plasma (CCP) with parallel plate electrodes. Capacitively Coupled Plasma etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the electrodes. A configuration in which a plurality of different high frequency power supplies are applied to the electrodes may also be used. Alternatively, a high frequency power supply of the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a high-frequency power supply having a high-density plasma source may be used. Dry etching equipment with a high density plasma source can be used. The device may be, for example, an inductively coupled plasma (ICP) d Plasma etching equipment or the like can be used.

[0167] When a hard mask is used for etching the conductive film, the etching process is performed using the hard mask. This may be done after removing the resist mask used for forming the In the latter case, the resist mask may disappear during etching. After etching the conductive film, the hard mask may be removed by etching. If the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not necessarily hard There is no need to remove the hard mask.

[0168] The conductive film that becomes the conductor 122 is formed by forming a conductive film containing a metal element by a sputtering method. It is also possible to form it by using a CVD method.

[0169] The surface of the insulator 132 is preferably subjected to a planarization process as necessary. Chemical mechanical polishing (CMP) or reflow may be used for the chemical treatment.

[0170] An insulating film 123A, a conductive film 134A, and a conductive film 134B are formed on the conductor 122 and the insulator 132. In this embodiment, the insulating film 123A is formed on the insulator 132. Then, a conductive film 134A is formed on the insulating film 123A, and the insulating film 123A is formed on the conductive film 134A. 12A to 12C show an example in which a conductive film 136A is formed on the insulating film 123A. The conductive film 134A, the conductive film 136A, and the insulating film 123A are formed by CVD. Alternatively, a sputtering method may be used.

[0171] The conductor 122, the conductive film 134A, and the conductive film 136A are made of silicon doped with impurities. The conductive film 136A can be formed of a conductive material such as a silicon or metal. In this process, it is necessary to selectively etch the conductor 122 and the conductive film 134A. Therefore, it is preferable that the material is different from that of the conductor 122 and the conductive film 134A. On the other hand, the conductor 122 and the conductive film 134A may be made of the same material or different materials. The conductor 122, the conductive film 134A, or the conductive film 136A may be made of silicon. When using silicon, amorphous silicon or polysilicon can be used. To make silicon conductive, p-type impurities or n-type impurities may be added. As the conductive material containing titanium, cobalt, or nickel, silicide is used. The conductive film 134A can be used as the conductive body 122, the conductive film 134A, or the conductive film 136A. When a metal material is used for the conductor 122, the conductive film 134A, or the conductive film 136A, aluminum Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten Stainless steel, hafnium, vanadium, niobium, manganese, magnesium, zirconium, Using materials containing one or more metal elements selected from lithium, indium, ruthenium, etc. It is possible.

[0172] The insulator 132 and the insulating film 123A may be made of an insulating oxide, nitride, or oxynitride. Examples of usable oxides include nitrides, metal oxides, metal oxide nitrides, and metal nitride oxides. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen silicon oxide or resin with voids, aluminum oxide, gallium oxide, hafnium oxide oxides containing tungsten, zirconium oxide, aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, Oxynitride with silicon and hafnium or nitride with silicon and hafnium Compounds such as nitroxides can be used.

[0173] In this embodiment, the insulating film 123A is formed in six layers, the conductive film 134A is formed in three layers, and the conductive film Although an example in which two layers of 136A are formed has been shown, the number of layers is not limited to this. The number of layers of the conductive film 134A can be adjusted depending on the performance of the device. m (m is an integer of 2 or more), the number of layers of the insulating film 123A is 2×m, and the number of layers of the conductive film 136A is 1×m. The number of layers is m-1. For example, m is 33 or more, preferably 65 or more, and more preferably It can be set to preferably 129 or more, and more preferably 257 or more.

[0174] Next, a mask is formed on the insulating film 123A, and the insulating film 123A, the conductive film 134A, and the conductive film 134B are The conductive film 136A is processed by lithography to expose the first conductive material 122. An opening is formed (see FIGS. 13A to 13C).

[0175] Next, the conductive film 136A is subjected to isotropic etching to remove the conductive film 136A in the first opening. The side surfaces of the insulating film 123A and the conductive film 134A are recessed from the side surfaces of the insulating film 123A and the conductive film 134A (FIGS. 14A to 14C). (See FIG. 14C.) By this process, the diameter of the first opening overlapping the conductive film 136A becomes The diameter of the first opening overlapping with the conductive film 123A and the diameter of the first opening overlapping with the conductive film 134A Therefore, unevenness is formed on the side surface of the first opening. Isotropic etching by dry etching using gas, radicals, plasma, etc. Isotropic etching by wet etching using a liquid can be used. The liquid used in dry etching is sometimes called an etchant. When performing isotropic etching, a gas containing at least one of chlorine, bromine, and fluorine, Isotropic etching can be used to form the first opening. It is preferable to perform this process without removing the mask used. The first opening obtained by the above process is This corresponds to the opening 141 shown in FIG.

[0176] Next, an insulating film 124A and a semiconductor film 125A are deposited on the insulating film 123A and inside the first opening. , and a conductive film 128A is formed (see FIGS. 15A to 15C). However, the insulating film 124A may have a laminated structure. It can be formed by using the LD method. In particular, by using the ALD method, it is possible to This is preferable because it allows a film of uniform thickness to be formed even in large grooves or openings. Alternatively, the insulating film 124A may be formed by a combination of the ALD method and the CVD method. When 124A has a laminated structure, each insulating film may be formed in the same film forming apparatus or in different apparatuses. The film may be formed using a film forming apparatus.

[0177] The insulating film 124A formed by the above method has good coverage and conforms to the uneven shape of the side surface of the first opening. In other words, the insulating film 123A and the conductive film 124A can be formed on the insulating film 123A. 34A and the side surfaces of the conductive film 136A, as well as a part of the upper surface of the insulating film 123A, The insulating film 124A can be formed so as to contact a part of the lower surface as well.

[0178] The semiconductor film 125A can be formed by using a CVD method or an ALD method. By using the VD method, it is possible to form a film with a uniform thickness even for grooves and openings with a large aspect ratio. Alternatively, a semiconductor can be formed by combining the ALD method and the CVD method. A conductive film 125A may be formed.

[0179] The semiconductor film 125A is preferably an oxide semiconductor having a CAAC structure. When the film 125A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 125A is , and is oriented in the normal direction of the surface on which the insulating film 124A is formed inside the first opening. The semiconductors located on the side surfaces of the insulating film 123A, the conductive film 134A, and the conductive film 136A are The c-axis of the conductive film 125A extends from the surface on which it is formed toward the axis 182 shown in FIGS. 15B and 15C. The axis 182 can be called the central axis of the first opening. The c-axis of the semiconductor 125 located above is oriented toward the axis 182 from the surface on which it is formed.

[0180] The conductive film 128A is conductive through at least the insulating film 124A and the semiconductor film 125A. It is sufficient that the conductive film 136A is formed to fill the recessed portion of the conductive film 136A, and it is not necessary that the entire inside of the first opening is filled. The conductive film 128A can be formed by using a CVD method or an ALD method. In particular, the ALD method allows for the formation of a film with a uniform thickness even in grooves and openings. Alternatively, the ALD method and the CVD method can be combined to form a conductive film. A film 128A may be formed.

[0181] Next, the conductive film 128A is processed to form the conductor 128 (see FIGS. 16A to 16C). The conductive film 128A is processed by isotropic etching or anisotropic etching. In forming the conductive film 128A, as shown in FIGS. 15A to 15C, If the conductive film 128A fills the recess and the first opening is not completely filled, the conductive film 12 It is preferable to use isotropic etching for processing 8A. When the conductive film 128A is formed so as to fill the opening, anisotropic etching is used. By the above-described processing, the conductor 128 is formed inside the recess. can be done.

[0182] Next, an insulating film 126A is formed inside the first opening (see FIGS. 17A to 17D).

[0183] The insulating film 126A can be formed by using a CVD method or an ALD method. This is preferable because it allows a film of uniform thickness to be formed even in grooves and openings. Alternatively, the insulating film 126A may be formed by combining the ALD method and the CVD method.

[0184] Next, the conductor 128 is used as a mask to increase the resistance of a part of the semiconductor film 125A, forming a high-resistance region. As a method for forming the high resistance region, the semiconductor film 125A is heated by microwaves. 144 to remove hydrogen contained in the semiconductor film 125A. When the irradiation of 144 is performed in an atmosphere containing oxygen, oxygen is supplied to the semiconductor film 125A. In this embodiment, the semiconductor film 1 is formed in an atmosphere containing oxygen and argon. A part of the semiconductor film 125A is irradiated with microwaves 144 to make a region 146 of the semiconductor film 125A highly resistive. (See FIGS. 17A to 17D.)

[0185] Here, heat treatment may be performed. The heat treatment is performed in a nitrogen-containing atmosphere at a temperature of 200° C. or higher and 50° C. or higher. The heat treatment is preferably carried out at 0°C or lower, more preferably at 300°C or higher and 400°C or lower. The atmosphere in which the treatment is carried out is not limited to the above, and may be an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere. This may also be done.

[0186] The heat treatment reduces the resistance of the semiconductor film 125A in contact with the conductor 128, and the region 148 A resistive region (N-type region) can be formed. The semiconductor film 125A and the conductor 128 are connected. By performing heat treatment in this state, a conductive layer is formed at the interface between the conductor 128 and the semiconductor film 125A. A metal compound layer containing the metal element of the body 128 and the component of the semiconductor film 125A is formed. By forming the metal compound layer, in the region in contact with the conductor 128, This is preferable because it reduces the resistance of the semiconductor film 125A. The conductor 128 may absorb oxygen. By performing heat treatment in this state, the resistance of the semiconductor film 125A becomes lower. The region 148, which has been made low-resistance by the heat treatment, may be conductive. Since the body 128 is covered with the microwave 144, it is not affected by the microwave 144 and remains low even after microwave treatment. A low resistance value can be maintained.

[0187] The carrier concentration of the region 146 after the microwave treatment and heat treatment is 1×10 18 / cm 3 Less than 1 x 10, preferably 17 / cm 3 or less, more preferably 1×10 16 / cm 3 The carrier concentration of the region 148 is preferably 1×10 18 / cm 3 More than 1×10 19 / cm 3 More preferably, 1×10 20 / cm 3 It is preferable that this is equal to or greater than this.

[0188] 17A to 17D, the resistance increasing process of the semiconductor film 125A is performed by the insulating film 126A. 18A, the insulating layer 18 is formed on the insulating film 18. However, the present embodiment is not limited to this. A resistance increasing process may be carried out before the formation of the insulating film 126A.

[0189] 17A to 17D, the conductor 128 is used as a mask to form a high-level semiconductor film 125A. Although an example of the resistance treatment has been shown, the present embodiment is not limited to this. The semiconductor film 125A is formed on the conductor 12 provided between the semiconductor film 125A and the insulating film 124A. 8, the semiconductor film 125A may be subjected to a high resistance treatment. The region 148 is subjected to a high resistance treatment such as microwave irradiation. Since the region 148 is in contact with the conductor 128, the reaction or interaction between the region 148 and the conductor 128 The interaction allows the region 148 to maintain a low resistance. In this case, it may be possible to make the region 148 have a lower resistance than the region 146 .

[0190] In order to provide the conductor 128 between the semiconductor film 125A and the insulating film 124A, After forming the semiconductor film 4A, the conductive film 128A is formed before forming the semiconductor film 125A. Then, the semiconductor film 125A is formed after forming the conductor 128, and then a high resistance treatment is performed. good.

[0191] Next, the insulating film 124A, the semiconductor film 125A, and the insulating film 125B formed on the bottom of the first opening are 26A is removed to obtain the insulator 124, the semiconductor 125, and the insulator 126. Anisotropic etching is used to remove 4A, semiconductor film 125A, and insulating film 126A. At this time, it is preferable that the insulating film 124A, the semiconductor film 125A, and the insulating film 123A are The insulating film 126A and the insulating film 124 are also removed, so that the insulator 124, the semiconductor 125, and the insulator 126B are removed. 6 is provided only on the side wall of the first opening (see FIGS. 19A to 19C). The insulating film 124A, the semiconductor film 125A, and the insulating film 126A at the bottom are removed to form the conductive film. The conductive material 122 is exposed.

[0192] Next, a semiconductor film 127A is formed inside the first opening so that a part of the semiconductor film 127A is in contact with the conductor 122. (See FIGS. 20A to 20C.) The semiconductor film 127A is partially connected to the semiconductor 125. In the storage device 100 exemplified in this embodiment, The conductor film 127A is connected to the semiconductor 125 at the bottom and the top of the first opening. It is possible.

[0193] The semiconductor film 127A is preferably an oxide semiconductor having a CAAC structure. When the semiconductor film 127A is an oxide semiconductor having a CAAC structure, The c-axis is oriented in the normal direction of the surface to be formed inside the first opening. The c-axis of the semiconductor film 127A located on the side of the opening is oriented from the surface to be formed toward the axis 182. As a result, the c-axis of the semiconductor 127 located above is oriented from the surface to be formed toward the axis 182. and orients.

[0194] Subsequently, an insulating film 129A is formed on the semiconductor film 127A, and a conductive film is formed on the insulating film 129A. The semiconductor film 127A, the insulating film 129A, and the conductive film 130A are The CVD method or the ALD method can be used to form the film. This allows the formation of a film with a uniform thickness even on grooves and openings with a large aspect ratio. Alternatively, the ALD method and the CVD method may be combined to form the film. For example, different film forming methods and film forming apparatuses may be used for the semiconductor film 12. The MOCVD method is preferably used to form 7A.

[0195] Here, the semiconductor film 127A is subjected to a high resistance treatment similar to that performed on the semiconductor film 125A. When the semiconductor film 127A is subjected to a high resistance treatment, the high resistance treatment may be performed by It is preferable to perform this step before forming the conductive film 130A or before forming the insulating film 129A. By performing a high resistance treatment on the conductive film 127A, the high resistance of the region 146 of the semiconductor film 125A is increased. If resistance can also be increased, the previous step of increasing resistance may be omitted.

[0196] Next, a heat treatment is performed in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C. Preferably, the heat treatment is carried out at a temperature of 300° C. or higher and 400° C. or lower. The method is not limited to the above, and may be carried out in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere. .

[0197] Next, the conductive film 130A is removed by a CMP method or the like until the surface of the insulating film 129A is exposed. The conductor 130 is obtained (see FIGS. 21A to 21C). This may be done after the conductor 130 is formed.

[0198] Next, the semiconductor film 127A and the insulating film 129A are processed to form the semiconductor film 127B and the insulating film 129A. The insulating film 129B is obtained (see FIGS. 21A to 21C). A wet etching method can be used.

[0199] Next, the insulating film 123A, the conductive film 134A, and the conductive film 136A are processed to form the insulating film 123A shown in FIG. 22B. Such a stepped insulator 123B, conductor 134B, and conductor 136B are formed ( (See FIGS. 22A to 22C.) The insulating film 123A, the conductive film 134A, and the conductive film 136 In the processing of A, the insulating film 123A, the conductive film 134A, and the conductive film 136A are etched. By alternately performing mask slimming and mask slimming, a stepped insulator 123B and a conductor 134 B and conductor 136B can be formed. and the end of the conductor 136B, the insulating film 123A is removed to expose the conductor 134B and the conductor 136B. The top surface of the conductive body 136B is exposed.

[0200] Next, the insulator 150 is formed (see FIGS. 22A to 22C). The insulator 150 is made of CV The insulator 150 can be formed by using a CMP method, a reflow method, or the like. It is preferable that the surface is subjected to a flattening treatment.

[0201] Next, the semiconductor film 127B, the insulating film 129B, the insulator 150, the insulator 123B, and the conductor 13 4B and the conductor 136B are processed to form the semiconductor 127, the insulator 129, the insulator 123, the conductor The conductive material 134 and the conductive material 136 are obtained (see FIGS. 23A to 23C). In this way, a semiconductor 127 electrically connected to the semiconductor 125 can be formed. 27 can be connected to the semiconductor 125 at the bottom of the first opening and at the top of the first opening. Cut.

[0202] Next, an insulator 152 is formed so as to fill the portion removed by the above processing (FIG. 23 (See FIGS. 23A to 23C.) The insulator 152 can be formed using a CVD method or an ALD method. Alternatively, the insulator 152 may be formed by combining the ALD method and the CVD method. The insulator 152 is preferably planarized using a CMP method, a reflow method, or the like. 23A and 23C, one memory cell is disposed between the insulators 152. However, the present embodiment is not limited to this. A plurality of memory strings may be provided in the Y direction between the plurality of memory strings. The memory strings share conductors 134, conductors 136, semiconductors 127, etc.

[0203] Next, the conductor 154 is formed so as to overlap a part of the semiconductor 127 with the insulator 129 interposed therebetween. (See FIGS. 24A to 24C.) The conductor 154 is made of the insulator 129, the insulator 150, and A conductive film is formed on the insulator 152 and processed by lithography. In FIG. 24A, the conductor 154 is located on the dashed line A1-A2. Although not shown, in FIG. 24B, the conductor 154 is shown by a dashed line.

[0204] The conductor 154 functions as the gate of the transistor STr2. The region overlapping with the conductor 154 functions as a channel forming region of the transistor STr2. Therefore, the conductor 154 is provided between the first opening and the conductor BL described later. On the other hand, it is preferable to connect the semiconductor 127 to the memory string 120 adjacent in the Y direction. If it has, between the first opening and the conductor BL of the adjacent memory string 120 ( In FIG. 24C, it is preferable that a conductor 154 is also provided on the A4 side from the first opening. stomach.

[0205] Next, an insulating layer is placed over the conductor 154, the insulator 129, the insulator 150, and the insulator 152. The insulator 156 is formed (see FIGS. 25A to 25C). The film can be formed by using an LD method, a sputtering method, or the like.

[0206] Next, the insulator 156, the insulator 129, and the insulator 150 are formed by lithography. The conductor 134, the conductor 136, the conductor 130, the conductor 154, and the semiconductor 12 The second opening is formed so that the conductor 17 is exposed. 34 and conductor 136, respectively (see FIGS. 25A to 25C).

[0207] Next, a conductor 161 electrically connected to the conductor 134 is embedded in the second opening. Conductor 162 electrically connected to conductor 136, and conductor 130 electrically connected to conductor 162. 63, a conductor 164 electrically connected to the conductor 154, and a semiconductor 127 electrically connected to the conductor 164 Conductor 165 is formed (see FIGS. 26A to 26C). Conductor 161, Conductor 162 The conductors 163, 164, and 165 are formed using a CVD method or an ALD method. Alternatively, the conductor can be formed by combining the ALD method and the CVD method. In addition, the conductor 161, the conductor 162, the conductor 163, the conductor 164, and the conductor The conductor 165 may have a laminated structure made up of multiple layers. 62, conductor 163, conductor 164, and conductor 165 are disposed on insulator 156 and A conductive film is formed inside the opening of 2, and unnecessary conductive film is removed using CMP or the like. It can be achieved.

[0208] Next, a conductor 171 electrically connected to the conductor 161 and a conductor 172 electrically connected to the conductor 162 are connected to the conductor 171. Conductor 172 is electrically connected to conductor 163, and conductor 173 is electrically connected to conductor 164. Forming a connecting conductor 174 and a conductor 175 electrically connecting with the conductor 165 (See Figures 26A to 26C.) Conductor 171, conductor 172, conductor 173, conductor The conductor 174 and the conductor 175 are formed by forming a conductive film on the insulator 156 and then forming the conductive film by lithography. It can be formed by processing it using

[0209] The conductor 171, the conductor 161, and the conductor 134 are connected to the conductor SG or the conductor WWL. The conductor 172, the conductor 162, and the conductor 136 function as the conductor RWL. The conductor 173, the conductor 163, and the conductor 130 function as the conductor BG. The conductor 174, the conductor 164, and the conductor 154 function as the conductor SEL. The conductor 175 and the conductor 165 function as the conductor BL. A semiconductor 127 that functions as a channel forming region and a conductor 134 that functions as a gate. a transistor STr1 having a semiconductor 127 functioning as a channel forming region, and a gate a transistor STr2 having a conductor 154 functioning as a channel forming region; A transistor having a semiconductor 125 functioning as a gate and a conductor 134 functioning as a gate. The semiconductor 127 functions as a WTr, a channel forming region, and a gate. The conductor 136, the conductor 130 that functions as a back gate, the semiconductor 127, and the conductor 1 36 and the conductor 128 between them. A memory device having transistor STr1, transistor STr2, transistor WTr, and transistor RTr can be fabricated.

[0210] <MOCVD Apparatus and Film Deposition Method Using MOCVD Method>

[0211] An MOCVD apparatus that can be used for forming oxides and the like, and a film deposition method using the MOCVD method will be described using FIGS. 27 and 28.

[0212] In the MOCVD method, a liquid raw material (also called a precursor, a precurser, or a metal precursor) is vaporized using a vaporizer and introduced into a chamber to form a film. The liquid precursor is held in a cylinder 1041 (cylinders 1041A to 1041D) for each precursor. Gas 1042 is supplied into the cylinder 1041 holding the precursor used for film deposition. As the gas 1042, an inert gas such as helium, argon, or nitrogen can be used. The supply of the gas 1042 can be controlled by a valve 1043, and the inside of a desired cylinder 1041 can be pressurized. By pressurizing the inside of the cylinder 1041, the liquid precursor can be supplied to the vaporizer 1044. The supply of the gas 1042 may be performed for one cylinder 1041 or simultaneously for two or more cylinders 1041. Also, FIG. 27 shows an example in which four cylinders 1041 are connected to the MOCVD apparatus, but the present embodiment is not limited to this. The cylinder 1041 may be one or more.

[0213] By forming a film using a plurality of precursors, films having different compositions can be formed. For example, a precursor containing indium is held in the cylinder 1041A, and the cylinder 1041 Cylinder B holds a precursor containing gallium, and cylinder 1041C holds a precursor containing zinc. and simultaneously supplying gas 1042 to cylinders 1041A to 1041C. A film containing indium, gallium, and zinc can be formed by the method described below. As will be described later, the vaporized precursor is mixed with a reaction gas containing oxygen, and then the mixture is poured into the film-forming chamber 1008. or 1009, the wafer held in the film-forming chamber 1008 or 1009 An oxide containing indium, gallium, and zinc can be formed on 1012.

[0214] The precursor supplied to the vaporizer 1044 is first supplied to the dispersion section 1045. When precursors are used for film formation, these precursors are mixed in the dispersion section 1045. At this time, it is preferable that gas 1046 is supplied to the dispersion section. The gas 1046 is sometimes called the primary carrier gas. It is used to supply the precursor from the dispersion section 1045 to the vaporization section 1048. As 046, an inert gas such as helium, argon, or nitrogen can be used.

[0215] The precursor or the mixture of precursors is heated and vaporized in the vaporizer 1048 . The vaporized precursor is supplied by gas 1047 toward valve 1049. Gas 1047 is sometimes called a secondary carrier gas. An inert gas such as benzene or nitrogen can be used.

[0216] The vaporized precursor and the secondary carrier gas are kept in the tank until the supply is stable. The secondary carrier gas is preferably not supplied to the deposition chamber 1008 or 1009 but is instead exhausted. At this time, by closing the valve 1049a and opening the valve 1049b, the pre-mixed The nozzle, the nozzle, and the secondary carrier gas can be vented.

[0217] Once the vaporized precursor and secondary carrier gas supplies are stable, close valve 1049a. The precursor and the secondary carrier gas are introduced into the deposition chamber 10. 1008 or 1009 to form a desired film on the wafer 1012. can be done.

[0218] As described above, the precursor and the secondary carrier gas are evacuated before they become stable. A desired amount of precursor or a desired mixture ratio of precursors is introduced into the film-forming chamber 1008 or 1009. The precursor and secondary carrier gas can be exhausted before they stabilize. By vaporizing the film, a film of desired quality or thickness can be formed on the wafer 1012. In addition, the uniformity of the film formed is improved, which is preferable.

[0219] Also, the precursor and secondary carrier gases passed through valve 1049a are supplied with gas 105 The gas 1050 may be a reactive gas such as an oxidizing gas or a nitriding gas. As the oxidizing gas, oxygen, ozone, etc. can be used. Nitrogen, nitrous oxide, nitrogen dioxide, ammonia, etc. are used as nitriding gases. The supply of gas 1050 can be controlled by a valve 1051. In addition, a mass flow controller or the like may be provided as appropriate to control the supply amount of the gas 1050 .

[0220] Here, the precursor vaporized by the vaporization unit 1048 is liquefied or solidified due to a temperature change. For example, solidification may produce powder of the components contained in the precursor. Therefore, the piping from the vaporizing section 1048 to the film forming chamber 1008 or 1009, It is preferable to heat the film chamber 1008, the film forming chamber 1009, and the exhaust piping. The heating temperature of the exhaust pipe is preferably equal to or higher than the heating temperature of the vaporizer. The heating temperature of the film forming chamber 1008 and the film forming chamber 1009 is determined based on the film quality, film uniformity, and film forming speed. The implementer can make an appropriate decision taking into consideration the above.

[0221] As described above, the film thickness and film quality can be improved by the film formation method using vaporized precursors. It is possible to form a highly uniform film. In addition, it has a high surface coverage rate even on uneven surfaces. In particular, in apertures with a large aspect ratio, the It is possible to form films with high quality and thickness uniformity.

[0222] Here, as an example of an apparatus capable of forming a film using the MOCVD method, a film forming apparatus 100 An example of the configuration of 0 will be described with reference to FIGS. 28A and 28B. 28A is a schematic diagram of a chamber-type film forming apparatus 1000, and FIG. 28B is a cross-sectional view of a film forming chamber 1008. .

[0223] <Configuration example of film formation equipment> The film forming apparatus 1000 includes a cassette chamber 1002, an alignment chamber 1004, and a transfer chamber 1005. 6, a film forming chamber 1008, a film forming chamber 1009, a cooling chamber 1010, and a transfer arm 10 The transfer arm 1014 can transfer the wafer 1012. Here, the cassette chamber 1002, the alignment chamber 1004, the film forming chamber 1008, the film forming chamber 10 09, the cooling chamber 1010 is connected to the transfer chamber 1006. 1008 and the film forming chamber 1009, continuous film formation can be performed without exposing the film to the atmosphere. This prevents impurities from being mixed into the film. Contamination at the interface is reduced, resulting in a clean interface.

[0224] A cassette having a plurality of wafers 1012 can be placed in the cassette chamber 1002. One or more cassettes can be placed. After the wafer 1012 is removed from the cassette chamber 1002 and processed by film deposition, it is returned to its original position in the cassette chamber 1002. It is returned to the cassette of hope.

[0225] In the alignment chamber 1004, the position of the wafer 1012 on the transfer arm 1014 is adjusted. The wafer 1012 taken out from the cassette chamber 1002 is transferred to the film forming chamber 1008 or It is preferable to adjust the position before transporting the wafer to the cassette 009. Before returning the wafer 1012 to the chamber 1002, alignment may be performed.

[0226] In the film-forming chamber 1008 and the film-forming chamber 1009, a film is formed on the wafer 1012.

[0227] In the cooling chamber 1010, the wafers processed in the film forming chamber 1008 or the film forming chamber 1009 are cooled. The temperature of the film forming chamber 1008 or the film forming chamber 1009 is adjusted. If the process is performed in a heated atmosphere, the wafer 1012 is cooled rapidly. After temperature adjustment in the cooling chamber 1010, it is preferable to carry out the wafer into the cassette chamber 1002. Yes.

[0228] In addition, the cassette chamber 1002, the alignment chamber 1004, the transfer chamber 1006, and the film forming chambers 1008 , the film forming chamber 1009, and the cooling chamber 1010 are preferably filled with an inert gas (such as nitrogen gas) whose dew point is controlled to prevent adhesion of moisture, etc., and it is desirable to maintain a reduced pressure.

[0229] Also, an MOCVD apparatus can be used in the film forming chamber 1008 and the film forming chamber 1009. Further, a configuration using a film forming apparatus other than the MOCVD apparatus may be adopted in either the film forming chamber 1008 or the film forming chamber 1009. Examples of the film forming apparatus used in the film forming chamber 1008 and the film forming chamber 1009 include, for example, a sputtering apparatus, a PECVD apparatus, a TCVD apparatus, an ALD apparatus, etc.

[0230] Also, the film forming apparatus 1000 is configured to include a cassette chamber 1002, an alignment chamber 1004, a transfer chamber 10 06, a film forming chamber 1008, a film forming chamber 1009, and a cooling chamber 1010, but the present invention is not limited thereto. The film forming apparatus 1000 may have three or more film forming chambers, or may be configured to include an additional processing chamber for performing heat treatment or plasma treatment. Further, the film forming apparatus 1000 may be a single wafer type or a batch type for simultaneously forming films on a plurality of substrates.

[0231] <MOCVD apparatus> Next, the configuration when an MOCVD apparatus is used as the film forming chamber 1008 will be described using FIG. 28B. The film forming chamber 1008 has a bottom outer wall 1021, a side outer wall 1022, and an upper outer wall 1023. The upper outer wall 1023 has a raw material inlet 1025 and a shower plate 10 The outer side wall 1022 is provided with a gate for loading and unloading the wafer 1012. The bottom outer wall 1021 is provided with an exhaust portion 1026, an exhaust valve 1028, and a 027, and a stage 1029 are provided. A heater for controlling the temperature during film formation may be provided on the upper outer wall 1023. It is preferable that the bottom outer wall 1021, the side outer wall 1022, and the top outer wall 1023 are For example, the bottom outer wall 1021, the side outer wall 1022, and The bottom outer wall 1021 and the side wall 1023 may be integrally formed. A lower outer wall 1022 is integrally formed, and an upper outer wall 1023 may function as a lid.

[0232] The gas containing the precursor vaporized by the vaporizer 1048 is introduced into the film forming chamber through the raw material inlet 1025. 1008, and the wafer 10 on the stage 1029 is introduced through the shower plate 1024. The supplied gas is deposited on the wafer 1012 to form a film. The gas that was not used in forming the film and the excess gas are discharged from the exhaust section 1026 to the outside of the film forming chamber 1008. The exhaust is then released to the

[0233] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0234] (Embodiment 2) In this embodiment, the circuit configuration and operation of a memory string 120, which is a storage device, will be described. FIG. 29 shows an example of the circuit configuration of the memory string 120. The equivalent circuit diagram of the MC is shown below.

[0235] <Memory string circuit configuration example> FIG. 29 shows an example of the circuit configuration of a memory string 120 having five memory elements MC. The memory element MC has a transistor WTr and a transistor RTr. The transistor WTr included in the memory element MC[1] is represented as transistor WTr[1]. The transistor RTr included in the memory element MC[1] is represented as transistor RTr[1]. Therefore, the memory string 120 shown in FIG. to transistor WTr[5], and transistor RTr[1] to transistor RT r[5]. The memory string 120 shown in FIG. The memory string 120 includes a NAND type memory It is a device.

[0236] NAND type storage devices that include OS memory are referred to as "OS NAND type" or "OS NAND It is also called "OS type storage device." It is also called "OS type storage device" which has a configuration in which multiple OS memories are stacked in the Z direction. S NAND type storage devices are referred to as "3D OS NAND type" or "3D OS NAND It is also called a "type of storage device."

[0237] In the equivalent circuit diagram, etc., it is clearly indicated that the transistor is an OS transistor. For this reason, the circuit symbol for a transistor may have the letter "OS" added to it. The transistor is a Si transistor (a transistor that uses silicon in the semiconductor layer where the channel is formed). In order to clearly indicate that the transistor is a silicon-based device, the symbol "Si" may be added to the circuit symbol of the transistor. In FIG. 29, the transistors WTr and RTr are OS transistors. This indicates that

[0238] The transistor WTr is preferably a normally-off transistor, and the transistor RTr As described in the above embodiment, a normally-on transistor is preferable. The transistor RTr has a conductor 128 between the gate and the semiconductor layer. , can function as the floating gate of the transistor RTr. For example, The conductor 128 included in RTr[1] is called conductor 128[1].

[0239] In addition, the conductor 128 is electrically connected to either the source or the drain of the transistor WTr. The node connecting the conductor 128[1] and the transistor WTr[ The node to which either the source or drain of ND[1] is electrically connected is called node ND[1].

[0240] Either the source or drain of transistor RTr[1] is connected to the source of transistor STr1. The other is electrically connected to the source or drain of the transistor RTr[2]. The gate of the transistor RTr[1] is electrically connected to either the source or the drain. The back gate of the transistor RTr[1] is electrically connected to the conductor RWL[1]. The source or drain of the transistor WTr[1] is electrically connected to the body BG. One is electrically connected to the conductor 128[1], and the other is electrically connected to the conductor 128[2]. The gate of the transistor WTr[1] is electrically connected to the conductor WWL[1]. The other of the source and drain of the transistor STr1 is electrically connected to the conductor 122. The gate is electrically connected to the conductor SG.

[0241] Here, as shown in FIG. 30, the transistor RTr is placed in the capacitor Cs and the transistor Tr. The gate of the transistor Tr is connected to the conductor RW via the capacitance Cs. Electrically connected to L.

[0242] In addition, one of the source and drain of the transistor RTr[5] is connected to the transistor RTr [4] is electrically connected to the other of the source or drain of transistor STr2 The gate of the transistor RTr[5] is electrically connected to either the source or the drain of the transistor RTr[6]. The back gate of the transistor RTr[5] is electrically connected to the conductor RWL[5]. The gate is electrically connected to the conductor BG. The source or drain of the transistor WTr[5] One of the inputs is electrically connected to the conductor 128[5], and the other is connected to the The gate of the transistor WTr[5] is electrically connected to either the source or the drain. is electrically connected to the conductor WWL [5]. The other end of the drain is electrically connected to the conductor BL, and the gate is electrically connected to the conductor SEL. To be continued.

[0243] When the memory string 120 includes n memory elements MC (n is an integer of 1 or more), the first The i-th (i is an integer between 1 and n) memory element MC[i ], one of the source and drain of the transistor RTr[i] is a transistor It is electrically connected to the other of the source or drain of RTr[i-1], and the other is the transistor The transistor RTr[i+1] is electrically connected to either the source or the drain of the transistor RTr[i+1]. The gate of the transistor RTr[i] is electrically connected to the conductor RWL[i]. The back gate of transistor r[i] is electrically connected to the conductor BG. One of the source and drain of the conductor 128[i] is electrically connected to the conductor 128[i], and the other is electrically connected to the conductor 128[i]. The gate of transistor WTr[i] is electrically connected to the conductive body 128[i+1]. It is electrically connected to WWL[i].

[0244] The transistors STr1 and STr2 are, for example, OS transistors. The transistor STr1 and the transistor STr2 may be Si transistors. One of the transistors STr2 may be an OS transistor and the other may be a Si transistor. When both the transistors WTr and RTr are formed of OS transistors, In this case, the transistors STr1 and STr2 are also formed of OS transistors. It is preferable that the productivity of semiconductor devices is improved by preparing semiconductor materials for transistors. can be increased.

[0245] In addition, an OS transistor is used for the transistor WTr, and a Si transistor is used for the transistor RTr. An OS transistor may be used as the transistor WTr. The equivalent circuit diagram of the memory string 120 when Si transistors are used as the RTr is shown below. This is shown in FIG. 31. In FIG. 31, the transistors STr1 and STr2 are Si transistors. An example using a transistor is shown.

[0246] When the transistor RTr is formed of a Si transistor, the semiconductor 125 is formed of, for example, a polycrystalline When the transistor WTr is formed as an OS transistor, The conductor 127 may be made of, for example, CAAC-IGZO.

[0247] As shown in FIG. 32, depending on the purpose or application, the transistor WTr may be A Si transistor may be used, and an OS transistor may be used as the transistor RTr. In FIG. 32, OS transistors are used for the transistors STr1 and STr2. An example is shown.

[0248] Also, as shown in FIG. 33, depending on the purpose or application, the transistors WTr and Both the transistors WTr and RTr may be Si transistors. When Si transistors are used for both the transistor STr1 and the transistor RTr, It is also preferable to use a Si transistor for the transistor STr2.

[0249] <Memory string operation example> Next, an example of the operation of the memory string 120 shown in FIG. 29 will be described.

[0250] [Write operation] In this embodiment, an H potential is written to the storage element MC[1] and the storage element MC[3]. An example of an operation when writing an L potential to another memory element MC will be described. 35A to 39B are timing charts for explaining a write operation. FIG.

[0251] In the initial state, an L potential is written to the memory elements MC[1] to MC[5]. In addition, Conductor WWL[1] to Conductor WWL[5], Conductor RWL[1] Conductor RWL[5], Conductor SEL, Conductor BG, Conductor BL, Conductor SG, and It is assumed that the L potential is supplied to the conductor 122. The conductor BG is a transistor The threshold voltage of the RTr can be controlled. The potential supplied to the conductor BG may be adjusted appropriately so that the conductor BG functions as a transistor.

[0252] [Period T1] In the period T1, the conductors WWL[1] to WWL[5], the conductor BL, and the conductor An H potential is applied to the electrode SEL (see FIG. 35A). The potential of the node ND[5] becomes H potential.

[0253] [Period T2] In the period T2, the L potential is supplied to the conductor WWL[1] (see FIG. 35B). , the transistor WTr[1] is turned off, and the charge written to the node ND[1] Here, a charge equivalent to the H potential is held in the node ND[1].

[0254] [Period T3] In the period T3, the L potential is applied to the conductor BL (see FIG. 36A). The potentials of the nodes ND[2] to ND[5] become L potential. At this time, the conductor 128[2] The conductor 128 [5] also becomes the L potential, but the transistor RTr is a normally-on transistor. Since the transistors RTr[2] to RTr[5] are in the off state, It's not ok.

[0255] [Period T4] In the period T4, the L potential is supplied to the conductor WWL[2] (see FIG. 36B). , the transistor WTr[2] is turned off, and the charge written to the node ND[2] Here, a charge equivalent to the L potential is held at the node ND[2].

[0256] [Period T5] In the period T5, the conductor BL is supplied with a high potential (see FIG. 37A). The potentials of nodes [3] to [5] become H potential.

[0257] [Period T6] In period T6, the L potential is supplied to the conductor WWL[3] (see FIG. 37B). , the transistor WTr[3] is turned off, and the charge written to the node ND[3] Here, a charge equivalent to the H potential is held in the node ND[3].

[0258] [Period T7] In the period T7, the L potential is applied to the conductor BL (see FIG. 38A). The potentials of the nodes ND[4] and ND[5] become L potential.

[0259] [Period T8] In period T8, the L potential is supplied to the conductor WWL[4] (see FIG. 38B). , the transistor WTr[4] is turned off, and the charge written to the node ND[4] Here, a charge equivalent to the L potential is held at the node ND[4].

[0260] [Period T9] In the period T9, the conductor BL remains at the L potential (see FIG. 39A). The potential of the node ND[5] also remains at the L potential.

[0261] [Period T10] In the period T10, the conductor WWL[5] is supplied with an L potential (see FIG. 39B). Then, the transistor WTr[5] is turned off, and the charge written to the node ND[5] Here, a charge equivalent to the L potential is held at the node ND[5]. , an L potential is supplied to the conductor SEL.

[0262] In this way, information can be written to the memory element MC.

[0263] It should be noted that, among the multiple storage elements MC, information is written to the i-th storage element MC (excluding i=1). When the write operation is performed, the write operation of information to the first (i-1)th memory element MC is omitted. For example, if you want to write information to memory element MC[4], you can write ] to the memory element MC[3]. In this case, the write operation from the period T1 to the period T6 shown in this embodiment mode can be omitted. This reduces the time and power consumption required for the write operation of the storage device.

[0264] [Read operation] An example of a read operation of the memory string 120 having the above circuit configuration will be described. It is assumed that the H potential is held in the memory element MC[1] and the memory element MC[3]. Conductor WWL[1] to Conductor WWL[5], Conductor RWL[1] to Conductor RWL[5] [5], conductor SEL, conductor BG, conductor BL, conductor SG, and conductor 122 are connected to L. 40A and 40B are timing charts for explaining the read operation. 41A to 42B are circuit diagrams for explaining the read operation. is.

[0265] <When the holding potential is H potential> First, the read operation of the memory element MC[3] in which the H potential is held will be described.

[0266] [Period T11] In the period T11, the conductors RWL[1] to RWL[5] and the conductor SEL (See FIG. 41A.) Then, the transistor STr2 is turned on. In this state, the semiconductor 127 of the transistor RTr is electrically connected to the conductor BL. The conductor BL and the semiconductor 127 are precharged with an H potential, and both are set in a floating state.

[0267] Here, the Id-Vg characteristics of the transistor will be explained. 43A and 43B are diagrams illustrating the Id-Vg characteristics of a transistor. The vertical axis indicates the gate voltage (Vg), and the vertical axis indicates the drain current (Id). Figure 43B shows the Id-Vg characteristics of a normally-off transistor, and Figure 43B shows the Id-Vg characteristics of a normally-on transistor. Figure 1 shows the Id-Vg characteristics of the capacitor.

[0268] The H potential is a higher potential than the L potential. If the L potential is 0V, the H potential is a positive voltage. In a normally-off transistor, the channel resistance (socket) when Vg is at the L potential (0V) is The resistance between the source and drain is extremely large, so Id hardly flows. At this point, the channel resistance value decreases and Id increases (see FIG. 43A).

[0269] In a normally-on transistor, the channel resistance is small even when Vg is at the L potential. Compared to a transistor with a gate-off function, a large amount of Id flows. Also, Vg becomes a high potential. As a result, the channel resistance value further decreases, and Id further increases (see FIG. 43B).

[0270] Since the transistor RTr is a normally-on transistor, the potential of the conductor RWL Even if the potential of the semiconductor 127 is low, the semiconductor 127 can be precharged. By supplying a high potential to RWL, the on-resistance of the transistor RTr decreases, This reduces the time and power consumption required for charging.

[0271] [Period T12] In the period T12, the conductor RWL[3] is supplied with an L potential (see FIG. 41B). Since the H potential is maintained in the ND[3], the potential of the conductor RWL[3] becomes the L potential. However, the channel resistance of the transistor RTr[3] becomes smaller.

[0272] [Period T13] During the period T13, the H potential is supplied to the conductor SG to turn on the transistor STr1. (See FIG. 42A.) Then, the conductor BL and the conductor 122 are electrically connected. Body RWL[1], Conductor RWL[2], Conductor RWL[4], and Conductor RWL[5] Since an H potential is supplied to transistor RTr[1], transistor RTr[2] , the channel resistance of transistor RTr[4] and transistor RTr[5] is The potential of the conductor RWL[3] is supplied with L potential. However, since the node ND[3] is held at a high potential, the transistor RTr[3 ] also has a small channel resistance. The potential of L changes suddenly from H potential to L potential (see FIG. 40A).

[0273] [T14 period] In a period T14, an L potential is supplied to the conductor SEL, the conductor RWL, and the conductor SG. (See Figure 42B.)

[0274] <When the holding potential is L potential> Next, the read operation of the memory element MC[2] in which the L potential is held will be described. When reading out the information (potential) stored in the memory element MC[2], during the period T12, The potential of the conductor RWL[2] is set to the L potential (see FIG. 40B). Since the L potential is maintained in transistor RTr[2], the channel resistance of transistor RTr[2] is large. It remains as it is.

[0275] Subsequently, in a period T13, a high potential is supplied to the conductor SG, and the conductors BL and 122 are At this time, the channel resistance of the transistor RTr[2] is large, so the conductor The potential change from H potential to L potential of BL becomes gradual.

[0276] In this way, during the period T12 and the period T13, By setting the potential of the conductor RWL corresponding to the memory element MC to the L potential, the information stored in the memory element MC is You can find out.

[0277] <Modification> FIG. 44 shows the circuit configuration of a memory string 120A, which is a modification of the memory string 120. For example, the memory string 120A includes a transistor STr It has a circuit configuration with 3 added.

[0278] In the memory string 120A shown in FIG. 44, the source or The other drain is not the source or drain of the transistor STr2, but the The source and drain of the transistor STr3 are electrically connected to each other. The other of the source and drain of STr3 is electrically connected to the conductor BL. The gate of the transistor STr2 is electrically connected to the conductor RSEL. The gate of 3 is electrically connected to the conductive WSEL.

[0279] During a write operation, the transistor STr3 is turned on and the transistor STr2 is turned off. During a read operation, the transistor STr3 is turned off, and the transistor STr When writing or reading information through the conductor BL, The information transmission path can be switched by a dedicated transistor for each memory. This stabilizes the operation of the device and improves the reliability of the storage device.

[0280] As shown in FIG. 45, the other of the source and drain of the transistor STr2 is connected to a conductive RBL and the other of the source and drain of the transistor STr3. During a write operation, information is written via the conductor WBL. During a read operation, information is read out via the conductor RBL. By providing dedicated conductors BL for both write and read operations, the operation of the memory device is stabilized. This can improve the reliability of the storage device.

[0281] The memory string 120B shown in FIG. 46 includes a transistor S The circuit configuration includes an additional transistor Tr4. One is electrically connected to either the source or drain of the transistor WTr[1], and the other The gate of transistor STr4 is electrically connected to the conductor WBL[2]. It is electrically connected to WSEL[2].

[0282] In the memory string 120B, the gate of the transistor STr3 is connected to the conductor WSEL [1], and the other of the source and drain of the transistor STr3 is conductive. As shown in FIG. 44, the transistor ST The circuit may be configured so that the transistor STr2 and the transistor STr3 are electrically connected to the conductor BL. .

[0283] The memory string 120B writes information to the conductors WBL[1] and WBL [2] can be done both ways. Therefore, the writing speed of information can be increased. Furthermore, the charge corresponding to the information to be written can be supplied more reliably.

[0284] When writing information to the i-th memory element MC, if i is close to n, the conductor WBL[ By writing information from the [1] side, the information of the 1st to i-1th memory elements MC is written. In addition, when i is close to 1, the write operation can be omitted. By writing information from the (i+1)th memory element to the nth memory element, the information writing operation is completed. In the memory string 120B, the time required for the write operation can be reduced. , power consumption can be further reduced.

[0285] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0286] (Embodiment 3) In this embodiment, a storage device 100A, which is a modified example of the storage device 100, will be described. FIG. 47 is a perspective view of a memory device 100A according to one embodiment of the present invention. It is to be noted that the present embodiment does not explain the following points. For this, other embodiments can be referred to.

[0287] <Storage device configuration example> The memory device 100A includes a memory string 120s. The configuration of the transistor STr2 is different from that of the memory string 120. 1 shows an example of a cross-sectional configuration of the memory string 120s. A conductor SEL, which functions as the gate electrode of Tr2, is provided on the insulator 123

[12] . An insulator 138 is provided on the conductor SEL. It functions as the back gate electrode of the transistor STr2.

[0288] Similar to the storage device 100 shown in the above embodiment, the storage device 100A shown in this embodiment This figure also shows a case where five memory elements MC are connected in series, but a memory string 120 is provided. The number of memory elements MC that can be used is not limited to five.

[0289] The memory string 120s has a conductor 122 on a base 121. 2, insulator 123[1], conductor SG, insulator 123[2], conductor RWL[1], insulator Insulator 123[3], Conductor WWL[1], Insulator 123[4], Conductor RWL[2], Insulator Insulator 123[5], Conductor WWL[2], Insulator 123[6], Conductor RWL[3], Insulator Insulator 123[7], Conductor WWL[3], Insulator 123[8], Conductor RWL[4], Insulator Insulator 123[9], Conductor WWL[4], Insulator 123

[10] , Conductor RWL[5], Insulator 123

[11] , Conductor WWL[5], Insulator 123

[12] , Conductor SEL, and and an insulator 138 (see FIG. 49).

[0290] The memory string 120s also includes an insulator 123[1], a conductor SG, and an insulator 123[ 2], conductor RWL[1], insulator 123[3], conductor WWL[1], insulator 123[ 4], conductor RWL[2], insulator 123[5], conductor WWL[2], insulator 123[ 6], conductor RWL[3], insulator 123[7], conductor WWL[3], insulator 123[ 8], Conductor RWL[4], Insulator 123[9], Conductor WWL[4], Insulator 123

[0010] , Conductor RWL[5], Insulator 123

[11] , Conductor WWL[5], Insulator 12 3

[12] , the conductor SEL, and the insulator 138 are partially removed to form an opening 14 1 (see FIG. 50). In order to make it easier to recognize the opening 141, the components in FIG. A portion is shown by a dashed line.

[0291] <Example of how to make a memory device>

[0292] Next, another example of a method for manufacturing the memory device 100A will be described with reference to Figures 51 to 67. 51 to 67, A is a top view seen from the Z direction, and B is a view of A. 51 to 67. 5C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in A. 6B is an enlarged cross-sectional view of the part surrounded by the dashed line. 1, one memory string 120s having two stages of memory elements MC is illustrated. The memory string 120s may have three or more stages of memory elements MC. For example, the memory string 120s may have 32 or more stages, preferably 64 or more stages. More preferably, the memory device has 128 or more stages, and even more preferably, 256 or more stages. It is preferable that

[0293] First, in the same manner as in the example of the manufacturing method of the memory device 100, a conductor 1 is formed on a substrate 121 having an insulating surface. 22 is formed, and an insulator 132 is formed around the conductor 122 (FIGS. 51A to 51C reference.).

[0294] Subsequently, a conductive film 137A is formed on the uppermost insulating film 123A, and an insulating film is formed on the conductive film 137A. The conductive film 138A is formed by the same method as the conductive film 134A. The insulating film 138A can be formed using the same method as the insulating film 123A. and may be made of similar materials.

[0295] Next, a mask (not shown) is formed on the insulating film 138A, and the insulating film 138A and the conductive film 137 A, an insulating film 123A, a conductive film 134A, and a conductive film 136A are formed by using a lithography method. 52A to 52C, and a first opening is formed to expose the conductor 122. See C. ).

[0296] Next, the conductive film 136A is subjected to isotropic etching to remove the conductive film 136A in the first opening. The side surfaces of the insulating film 123A, the conductive film 134A, the conductive film 137A, and the insulating film 138A are The conductive film 136 is recessed from the side surface (see FIGS. 53A to 53C). The diameter of the first opening overlapping with A is the same as that of the insulating film 123A, the conductive film 134A, the conductive film 137A, and the The diameter of each of the first openings overlapping with insulating film 138A is larger than the diameter of each of the first openings. Irregularities form on the sides of the mouth.

[0297] Next, an insulating film 124A is formed on the insulating film 138A and inside the first opening (FIG. 54 As described in the above embodiment, the insulating film 124A is a laminated film. As shown in the above embodiment, the insulating film 124A may be formed by a CVD method. In particular, the ALD method allows for the formation of grooves and openings. Even if the thickness is small, it is possible to form a film with a uniform thickness, which is preferable.

[0298] Next, the conductive film 128A is processed to form the conductor 128 (see FIGS. 55A to 55C). The conductive film 128A is processed by isotropic etching or anisotropic etching. That's fine.

[0299] Next, an insulating film 126A is formed inside the first opening (see FIGS. 56A to 56D). Subsequently, microwaves 144 are irradiated to increase the resistance of a region 146 of the semiconductor film 125A. As explained in the above embodiment, a heat treatment may be carried out thereafter. The semiconductor film 125A in contact with the conductor 128 has a low resistance, forming a low resistance region in the region 148. It is possible.

[0300] In addition, in FIG. 56, the resistance increasing process of the semiconductor film 125A is performed after the formation of the insulating film 126A. However, the present embodiment is not limited to this. A resistance increasing treatment may be carried out before forming 26A.

[0301] Next, the insulating film 124A, the semiconductor film 125A, and the insulating film 125B formed on the bottom of the first opening are 26A is removed to obtain insulator 124, semiconductor 125B, and insulator 126B. The insulating film 124A, the semiconductor film 125A, and the insulating film 126A on the insulating film 138A are also removed. As the insulating material 124, the semiconductor 125B, and the insulating material 126B are removed, the insulating material 124, the semiconductor 125B, and the insulating material 126B are removed from the first opening. The insulating film 124 is formed only on the sidewall (see FIGS. 57A to 57C). A, the semiconductor film 125A, and the insulating film 126A are removed, and the conductor 122 is exposed again. Put out.

[0302] Next, in the XY plane shown in FIGS. 58A to 58C, the semiconductor layer overlapping the conductive film 137A is The semiconductor 125B and the insulator 126B are removed. To remove B, first, a material 180 (sacrificial layer) that can be easily removed in a subsequent process is placed inside the first opening. ) to fill the first opening to a desired depth. Then, the remaining material 1 is removed by etching or the like (see Figures 58A to 58C). 80 as a mask, the semiconductor 125B and the insulator 125C exposed by the etching are 26B are sequentially removed to obtain a semiconductor 125 and an insulator 126 (FIGS. 59A to 59C). After removing the semiconductor 125B and the insulator 126B, the material 180 is removed (see FIG. See Figures 60A to 60C.

[0303] It should be noted that even if a part of the semiconductor 125B and the insulator 126B is not removed, the transistors can be removed in the corresponding regions. When the transistor STr2 can be constructed, the semiconductor 125B using the material 180 and the insulator The removal step of 126B can be omitted. At this time, the insulating layer 126B is formed between the conductor 137 and the semiconductor 127. A transistor STr is provided with a semiconductor 125 via an insulator 124 and an insulator 126. 2 is formed.

[0304] Next, a semiconductor film 127A is formed inside the first opening so that a part of the semiconductor film 127A is in contact with the conductor 122. At this time, the semiconductor film 127A is partially covered with the semiconductor 12 5. In the storage device 100A exemplified in this embodiment, The semiconductor film 127A is in contact with the semiconductor 125 at the bottom and top of the first opening. can be connected.

[0305] As shown in the above embodiment, the semiconductor film 127A is an oxide film having a CAAC structure. As described above, the semiconductor film 127A has a CAAC structure. In the case where the semiconductor film 127A is an oxide semiconductor, the c-axis of the semiconductor film 127A is aligned along the axial direction of the first opening. At this time, the semiconductor film 127A positioned on the side surface of the first opening is oriented in the normal direction of the grown surface. The c-axis is oriented from the surface to be formed toward axis 182 shown in Figures 61A to 61C. The c-axis of the semiconductor 127 located above is oriented toward the axis 182 from the surface on which it is formed.

[0306] Subsequently, an insulating film 129A is formed on the semiconductor film 127A, and a conductive film is formed on the insulating film 129A. The conductive film 130A is formed.

[0307] As described in the above embodiment, the semiconductor film 127A may be subjected to a resistance increasing treatment. The resistance increasing treatment is performed before forming the conductive film 130A or before forming the insulating film 129A. It is preferable that the semiconductor film 127A is subjected to a resistance increasing treatment to increase the resistance of the semiconductor film 125A. If the resistance of the region 146 can also be increased, the resistance increase process in the previous step may be omitted.

[0308] Next, a heat treatment is performed in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C. Preferably, the heat treatment is carried out at a temperature of 300° C. or higher and 400° C. or lower. The method is not limited to the above, and may be carried out in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere. .

[0309] Next, the conductive film 130A is removed by a CMP method or the like until the surface of the insulating film 129A is exposed. The conductor 130 is obtained (see FIGS. 62A to 62C). This may be done after the formation of 130.

[0310] Next, the semiconductor film 127A and the insulating film 129A are processed to form the semiconductor 127 and the insulating film 129A. 129 is obtained (see Figures 63A to 63C).

[0311] Next, the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive The film 136A is processed to form a stepped insulator 138B, a conductor 137B, and a An insulator 123B, a conductor 134B, and a conductor 136B are formed (FIGS. 64A to 6 4C.) The insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and In the processing of the conductive film 136A, the insulating film 138A, the conductive film 137A, and the insulating film 123A , etching of the conductive film 134A and the conductive film 136A and slimming of the mask are alternately performed. By doing so, the stepped insulator 138B, the conductor 137B, the insulator 123B, and the conductor 134 B, and conductor 136B can be formed.

[0312] Next, the insulator 150 is formed. As shown in the above embodiment, the insulator 150 is made of CV The insulator 150 can be formed by using the D method. The insulator 150 can also be formed by using the CMP method, the reflow method, etc. It is preferable that the surface is flattened using a polishing agent or the like.

[0313] Next, the insulator 150, the insulator 138B, the conductor 137B, the insulator 123B, and the conductor 134 B, and the conductor 136B are processed, and the insulator 138, the conductor 137, the insulator 123, the conductor The conductive body 134 and the conductive body 136 are obtained (see FIGS. 65A to 65C). As shown in FIGS. 9A to 10F, when dividing the memory string 120, the conductor 130 , insulator 129, semiconductor 127, insulator 126, conductor 128, semiconductor 125, and insulator The edge 124 may be processed.

[0314] Subsequently, an insulator 152 is formed so as to fill in the portion removed by the above processing. The insulator 152 may be planarized by using a CMP method, a reflow method, or the like. In addition, when processing to divide the memory string 120 is performed, the shape of the insulator 152 is Insulator 153 is formed simultaneously with the formation of the insulating layer 152 and / or in a manner similar to the formation of insulating layer 152. In addition, in FIG. 65A and FIG. 65C, one insulating material 152 may be formed between two insulating materials 152. Although an example in which two memory strings are provided is shown, the present embodiment is not limited to this. A plurality of memory strings may be provided in the Y direction between the two insulators 152 . At this time, the plurality of memory strings are made up of conductors 134, 136, and 137. Furthermore, at this time, the semiconductor 127 has independent wiring BL for electrical connection. Preferably, the two are electrically connected.

[0315] Next, an insulating layer is applied to cover the conductor 130, the insulator 129, the insulator 150, and the insulator 152. The edge 156 is formed (see Figures 66A to 66C).

[0316] Subsequently, the insulators 156, 129, 138, and 150 are lithographically The conductors 134, 136, 130, 137, and 138 are processed using the Fee method. A second opening is formed to expose the semiconductor 127. The second opening has a stepped shape. The conductive layers 134 and 136 are formed at positions overlapping the conductive layers 134 and 136 (FIG. 66A). See also Figure 66C.

[0317] Next, a conductor 161 electrically connected to the conductor 134 is embedded in the second opening. Conductor 162 electrically connected to conductor 136, and conductor 130 electrically connected to conductor 162. 63, a conductor 164 electrically connected to the conductor 137, and a semiconductor 127 electrically connected to the conductor 164 Conductors 165 are formed (see Figures 67A to 67C).

[0318] Next, a conductor 171 electrically connected to the conductor 161 and a conductor 172 electrically connected to the conductor 162 are a conductor 172 electrically connected to the conductor 163; a conductor 173 electrically connected to the conductor 164; and a conductor 175 electrically connected to the conductor 165. do.

[0319] As in the storage device 100 shown in the above embodiment, the storage device 100A also has a conductor 171, conductor 161, and conductor 134 are referred to as conductor SG or conductor WWL. Similarly, conductor 172, conductor 162, and conductor 136 function as conductor RWL. Similarly, conductor 173, conductor 163, and conductor 130 function as conductor B. G. Conductor 174, conductor 164, and conductor 137 are connected to conductor SEL The conductor 175 and the conductor 165 function as the conductor BL. By this process, a semiconductor 127 that functions as a channel forming region and a conductive layer that functions as a gate are formed. The transistor STr1 has a semiconductor 12 serving as a channel forming region. 7 and a conductor 137 serving as a gate, a transistor STr2, a channel type The transistor has a semiconductor 125 that functions as a gate and a conductor 134 that functions as a gate. The transistor WTr and the semiconductor 127 functioning as a channel forming region and the gate The conductor 136 functions as a gate electrode, the conductor 130 functions as a back gate, and the semiconductor 127 and conductor 136. In addition, the transistor STr1, the transistor STr2, the transistor WTr, and A memory device having a transistor RTr can be fabricated.

[0320] <Memory string circuit configuration example> An example of the circuit configuration of the memory string 120s is shown in FIG. Compared to the circuit configuration example shown in 29, the orientation of the transistor STr2 is different, and the conductor SEL However, the positions of the wiring BL and the memory string 120 shown in FIG. The circuit configuration shown in FIG. 68 is substantially the same as the circuit configuration example shown in FIG. The memory string 120s can operate in the same manner as the memory string 120. The same modifications as those for the memory string 120 can also be used for s.

[0321] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0322] (Fourth embodiment) In this embodiment, a configuration example of a semiconductor device 400 including a memory device 100 will be described. The storage device 100 may be replaced by a storage device 100A.

[0323] FIG. 69 is a block diagram illustrating a configuration example of a semiconductor device 400 according to one embodiment of the present invention. The semiconductor device 400 shown in FIG. 69 includes a driver circuit 410 and a memory array 420 . The memory array 420 includes one or more memory devices 100. In FIG. 20 shows an example in which a plurality of storage devices 100 are arranged in a matrix.

[0324] The drive circuit 410 includes a PSW 441 (power switch), a PSW 442, and a peripheral circuit 4 The peripheral circuit 415 includes a peripheral circuit 411, a control circuit 412 (Cont control circuit), and a voltage generation circuit 428.

[0325] In the semiconductor device 400, each circuit, each signal, and each voltage may be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. CE, signal GW, signal CLK, signal WAKE, signal ADDR, signal WDA, signal PON1 The signal PON2 is an input signal from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0326] The signals BW, CE, and GW are control signals. signal GW is the global write enable signal, signal BW is the bypass signal. The signal ADDR is an address signal. The signal WDA is a write enable signal. The signals PON1 and PON2 are write data and the signal RDA is read data. These are signals for power gating control. Note that the signals PON1 and PON2 are used for control It may be generated by the control circuit 412.

[0327] The control circuit 412 is a logic circuit having a function of controlling the overall operation of the semiconductor device 400. For example, the control circuit may be a logic circuit that converts the signals CE, GW, and BW into logic signals. The operation mode (for example, write operation, read operation) of the semiconductor device 400 is determined by calculation. Alternatively, the control circuit 412 may set the peripherals to perform this mode of operation. Generates a control signal for circuit 411.

[0328] The voltage generating circuit 428 has a function of generating a negative voltage. For example, the signal WAKE has a function of controlling the input to the voltage generating circuit 428. When the signal of the line is given, the signal CLK is input to the voltage generating circuit 428, and the voltage generating circuit 4 28 generates a negative voltage.

[0329] The peripheral circuit 411 is used to write and read data to and from the storage device 100. The peripheral circuit 411 includes a row decoder 421, a column decoder 422, and a Column Decoder 422, Row Driver 423 er), a column driver 424, an input circuit 425 t Cir.), an output circuit 426 (Output Cir.), a sense amplifier 427 (s It has a ense amplifier.

[0330] The row decoder 421 and the column decoder 422 have the function of decoding the signal ADDR. The row decoder 421 is a circuit for specifying the row to be accessed, and the column decoder 422 is a circuit for specifying a column to be accessed. The column driver 424 has a function of selecting the wiring WL designated by the column driver 424. A function for writing data to the storage device 100, a function for reading data from the storage device 100, and a function for storing the read data. It has functions such as holding.

[0331] The input circuit 425 has a function of holding the signal WDA. The output data of the input circuit 425 is output to the column driver 424. The data (Din) that the column driver 424 reads from the memory device 100 is written to the The data (Dout) is output to the output circuit 426. The output circuit 426 stores the Dout. The output circuit 426 outputs Dout to the outside of the semiconductor device 400. The data output from the output circuit 426 is the signal RDA.

[0332] PSW441 is the V to the peripheral circuit 415 DD It has the function of controlling the supply of PSW442. is the V to row driver 423 HM Here, the semiconductor device has a function of controlling the supply of High power supply voltage of 400 V DD and the low power supply voltage is GND (ground potential). HM is the high supply voltage used to drive the word line high, and V DD Higher than The signal PON1 controls the on / off of the PSW441, and the signal PON2 controls the In FIG. 69, in the peripheral circuit 415, V DD Although the number of power domains to which the power is supplied is set to 1, it is also possible to have multiple power domains. A power switch may be provided for each power domain.

[0333] The drive circuit 410 and the memory array 420 may be provided on the same plane. As shown in FIG. 1, the driving circuit 410 and the memory array 420 may be provided overlapping each other. By overlapping the memory array 420, the signal propagation distance can be shortened. As shown in FIG. 70B, a plurality of memory arrays 420 are stacked on the driving circuit 410. That's fine.

[0334] As shown in FIG. 70C, memory arrays 420 are provided above and below the drive circuit 410. In FIG. 70C, one memory layer may be provided above and one memory layer may be provided below the driving circuit 410. In this example, a plurality of memory arrays 420 are provided. By placing them in a sandwiched position, the signal propagation distance can be further shortened. The memory array 420 is stacked on the upper layer of the drive circuit 410, and the memory array 420 is stacked on the lower layer of the drive circuit 410. The number of layers of the memory array 420 may be one or more. The number of stacked memory arrays 420 and the memory arrays stacked below the drive circuit 410 Preferably, the numbers 420 are equal.

[0335] <Example of Cross-Sectional Configuration of Semiconductor Device 400> 71 shows a cross-sectional configuration example of the semiconductor device 400 shown in FIG. 4 shows a portion of a semiconductor device 400.

[0336] In FIG. 71, the transistors 301, 302, and The transistor 301 and the transistor 303 are shown. 302 functions as a part of the sense amplifier 427. Also, transistor 303 is a column selector. Specifically, the conductor BL included in the memory array 420 The transistor 301 is electrically connected to one of the source and drain of the transistor 30 The gate of the transistor 301 is electrically connected to one of the source and drain of the transistor 302. The gate of transistor 302 is electrically connected to the other of the source and drain of transistor 301. Also, one of the source and drain of the transistor 301 and the transistor The other of the source and drain of the transistor 302 is connected to a transistor that functions as a column selection switch. This electrically connects the source and drain of the semiconductor device 40 0 layout area can be reduced. In this example, seven memory elements MC are provided per memory string. The number of memory elements MC provided in one memory string is not limited to this. The number of storage elements MC may be 32, 64, 128, or 200 or more.

[0337] The conductors BL of the memory array 420 are embedded in the insulators 726 and 722, etc. Conductor 752, conductor 705, conductor 714, and conductor 715 are formed so as to be and through which the sense amplifier 427 and the transistor 30 functioning as a column selection switch are connected. 3. Note that the circuits and transistors included in the driver circuit 410 are, for example, The present invention is not limited to the circuit configuration or transistor structure. The configuration of the semiconductor device 400, including the row decoder, row driver, source line driver, input / output circuit, etc. Also, appropriate circuits and transistors can be provided depending on the driving method.

[0338] The transistor 301, the transistor 302, and the transistor 303 are formed on a substrate 311. conductor 316, insulator 315, and semiconductor made up of a part of substrate 311, respectively. region 313, and low resistance regions 314a and 314b which function as source or drain regions. As shown in FIG. 71, one low resistance region is The source or drain region of one of the transistors 301 and 302, In some cases, one of the two regions may be shared as the source region or drain region of the other.

[0339] The transistor 301, the transistor 302, and the transistor 303 have a channel formed The semiconductor region 313 (part of the substrate 311) formed thereon has a convex shape. The side and top surfaces of the heat sink 13 are covered with a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. The transistor 301, the transistor 302, and the transistor 303 utilize the protruding portion of the semiconductor substrate. It is also called a FIN type transistor because it uses a The insulating layer may have an insulating material that functions as a mask for forming the semiconductor portion. Although the case where a convex portion is formed by processing a part of a conductor substrate has been shown, it is also possible to process an SOI substrate to form a convex shape. Alternatively, a semiconductor film having the following structure may be formed.

[0340] The transistor 301, the transistor 302, and the transistor 303 are p-channel transistors. The transistor 301 and the transistor 302 may be either a n-channel or n-channel type. The transistors 302 are preferably transistors each having a different polarity.

[0341] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are the drain region, silicon is It preferably contains a semiconductor such as a silicon-based semiconductor, and preferably contains single crystal silicon. Or Ge (germanium), SiGe (silicon germanium), GaAs (gallium It may be formed of a material containing gallium aluminum arsenide (GaAlAs), GaAlAs (Gallium Aluminum Arsenide), etc. By applying stress to the crystal lattice and changing the lattice spacing, we can control the effective mass of silicon. Alternatively, GaAs and GaAlAs may be used to form a transistor. The transistor 301, the transistor 302, and the transistor 303 are HEMT (High Electrical MEMS) It may also be called a power transistor mobility transistor.

[0342] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the body material, elements that impart n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. The element imparting electrical conductivity is included.

[0343] The insulator 315 separates the transistors 301, 302, and 303. It functions as a gate insulating film.

[0344] The conductor 316 that functions as the gate electrode is made of an element that gives n-type conductivity, such as arsenic or phosphorus. Semiconductor materials such as silicon that contain elements that impart p-type conductivity, such as silicon or boron A conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0345] Since the work function is determined by the conductor material, the threshold can be adjusted by changing the conductor material. Specifically, titanium nitride, tantalum nitride, etc. are used as the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use a material such as It is preferable to use metal materials such as tungsten and aluminum as the lamination material, and particularly tungsten. It is preferable to use tin in terms of heat resistance.

[0346] An insulator 317 is provided above the conductor 316 to function as an etching stopper. In addition, it is preferable that the side of the insulator 315 is provided with an insulating layer that functions as a spacer. It is preferable that an insulator 318 is provided. As a result, the low resistance region 314a and the low resistance region 314b are electrically connected to the conductor 328. Therefore, the low resistance region 314a and the low resistance region 314b can be determined in a self-aligned manner. Misalignment occurred when forming the opening to expose a portion of the resist region 314b. In this way, an opening can be formed to expose the intended area. A conductor 328 is formed in the opening, forming a low resistance region 314a and a low resistance A good contact with reduced contact resistance is obtained between region 314b and conductor 328. The low resistance region 314a and the low resistance region 314b formed in this way are electrically conductive. The contact with the insulator 328 is sometimes called a self-aligned contact. 317, and a conductor electrically connected to the conductor 316 so as to be embedded in the insulator 322. An electrical current 329 may be provided.

[0347] The transistors 301, 302, and 303 are covered with an insulator. 320, insulator 322, insulator 324, insulator 326, and insulator 327 are stacked in this order. It is set up as follows.

[0348] As insulator 320, insulator 322, insulator 324, insulator 326, and insulator 327 For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide Aluminum, aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, etc. That's good enough.

[0349] The insulator 322 smooths out the steps caused by the transistor 301 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process such as chemical mechanical polishing (CMP). It's fine.

[0350] The insulator 324 is also provided with a substrate 311 or a transistor 301, etc., for example, to separate the memory array. A film having a barrier property that prevents hydrogen and impurities from diffusing is used in the area where the electrode 420 is provided. It is preferable that

[0351] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, a semiconductor element having an oxide semiconductor such as a memory element MC can be The diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. It is preferable to use a film that suppresses hydrogen diffusion between the MC and the transistor 301, etc. Specifically, a film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0352] The amount of desorbed hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorption from the insulator 324 can be measured by TDS analysis when the surface temperature of the film is 5 In the range of 0°C to 500°C, the amount of desorption converted to hydrogen atoms is Converted to 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 at oms / cm 2 The following is fine.

[0353] It is preferable that the insulators 326 and 327 have a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 and the insulator 327 is preferably less than 4, and more preferably 3. For example, the relative dielectric constant of the insulator 326 and the insulator 327 is preferably less than 1000 . The dielectric constant is preferably 0.7 times or less, more preferably 0.6 times or less, of the dielectric constant of the insulating body 324. By using a material with a low resistance as the interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0354] Also, insulator 320, insulator 322, insulator 324, insulator 326, and insulator 327 The memory array 420 includes a conductor 328, a conductor 329, and a conductor The conductors 328, 329, and 330 are embedded. has a function as a plug or wiring. In some cases, multiple structures of the conductor may be collectively given the same symbol. In the above, the wiring and the plug electrically connected to the wiring may be integrated. That is, when a part of the conductor functions as a wiring, and when a part of the conductor functions as a plug, In some cases, this may be the case.

[0355] The materials of each plug and wiring (conductor 328, conductor 329, conductor 330, etc.) Examples of the conductive material include metals, alloys, metal nitrides, and metal oxides. Tungsten and other materials that have both heat resistance and electrical conductivity can be used as single layers or laminated layers. It is preferable to use a high melting point material such as molybdenum, and it is more preferable to use tungsten. Alternatively, it is preferable to form the wiring board from a low-resistance conductive material such as aluminum or copper. By using a resistive conductive material, the wiring resistance can be reduced.

[0356] A wiring layer may be provided on the insulator 327 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring. The conductors 328, 329, and 330 can be formed using the same materials. Cut.

[0357] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. In addition, the conductor 356 has a barrier property against hydrogen. It is preferable that the insulating material 350 contains a conductor. In particular, the insulating material 350 has a barrier property against hydrogen. In the opening, a conductor having a barrier property against hydrogen is formed. The transistor 301 and the like can be separated from the memory element MC by a barrier layer. This can suppress the diffusion of hydrogen from the resistor 301 and the like to the memory element MC.

[0358] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, It is possible to suppress the diffusion of hydrogen from the transistor 301 and the like while maintaining the conductivity of the transistor. In this case, the tantalum nitride layer, which has a barrier property against hydrogen, acts as a barrier against hydrogen. It is preferable that the insulating material 350 has a structure in which the insulating material 350 is in contact with the insulating material 350.

[0359] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductors 328, 329, and 330 can be formed using the same materials. Cut.

[0360] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. The conductor 366 has a barrier property against hydrogen. It is preferable that the insulating material 360 contains a conductor. In particular, the insulating material 360 has a barrier property against hydrogen. In the opening, a conductor having a barrier property against hydrogen is formed. The transistor 301 and the like can be separated from the storage element MC by a barrier layer.

[0361] An insulator 722 is provided on the insulator 364 and the conductor 366. The memory array 420 is provided above the insulator 364 and the insulator 722. A barrier film made of a material similar to that of the insulator 324 may be provided.

[0362] 72 shows a semiconductor device 400 using a memory device 100A instead of the memory device 100. An example of a cross-sectional configuration is shown.

[0363] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0364] (Embodiment 5) In this embodiment, a semiconductor device on which the memory device of the present invention is mounted will be described with reference to FIGS. 73A and 73B. An example of a chip 1200, which is a type of semiconductor device, is shown. The chip 1200 includes multiple circuits ( In this way, multiple circuits (systems) are integrated into a single chip. The technology that integrates these components is called System on Chip (SoC). There is a match.

[0365] As shown in FIG. 73A, the chip 1200 includes a CPU 1211, a GPU 1212, and one or more A plurality of analog arithmetic units 1213, one or more memory controllers 1214, one or more It has a plurality of interfaces 1215, one or more network circuits 1216, etc. .

[0366] The chip 1200 is provided with bumps (not shown), and as shown in FIG. 73B, The first surface of the printed circuit board (PCB) 1201 and In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201. and connects to the motherboard 1203.

[0367] The motherboard 1203 includes storage devices such as a DRAM 1221 and a flash memory 1222. The flash memory 1222 may be the semiconductor memory shown in the above embodiment. It is preferable to use the semiconductor device shown in the above embodiment as a flash memory 1. 222, the storage capacity of the flash memory 1222 can be increased. .

[0368] The CPU 1211 preferably has multiple CPU cores. It is preferable to have multiple GPU cores. Each of the CPUs 12 may have a memory for temporarily storing data. Even if a memory common to the GPU 1211 and the GPU 1212 is provided on the chip 1200, In addition, the GPU1212 is suitable for parallel calculation of large amounts of data, and is suitable for image processing and multiplication and accumulation. It can be used for calculations. The GPU 1212 is equipped with an image processing circuit and a multiply-and-accumulate circuit. This makes it possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0369] In addition, the CPU 1211 and GPU 1212 are mounted on the same chip, The wiring between PU1211 and GPU1212 can be shortened, and Data transfer to the GPU 1212, the memory of the CPU 1211 and the GPU 1212 After the data transfer between GPU1212 and the calculation in GPU1212, The calculation results can be transferred to 1 at high speed.

[0370] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital The analog calculation unit 1213 has one or both of a digital / analog conversion circuit. The above-mentioned product-sum calculation circuit may be provided.

[0371] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. and a circuit that functions as an interface with the flash memory 1222.

[0372] The interface 1215 includes a display device, a speaker, a microphone, a camera, a controller, and The controller has an interface circuit with external devices such as a mouse. Such interfaces include devices such as keyboards, game controllers, etc. , USB (Universal Serial Bus), HDMI (registered trademark) gh-Definition Multimedia Interface) It is possible.

[0373] The network circuit 1216 is connected to a LAN (Local Area Network) or the like. It has a network circuit for connecting to the network, and also has a circuit for network security. may have

[0374] The above circuits (systems) can be formed on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, the manufacturing process can be increased. This eliminates the need for a ferroelectric capacitor, allowing chip 1200 to be manufactured at low cost.

[0375] A PCB 1201 on which a chip 1200 having a GPU 1212 is mounted, a DRAM 1221 The motherboard 1203 provided with the GPU module 1222 and the flash memory 1222 It can be called Rule 1204.

[0376] The GPU module 1204 has a chip 1200 that uses SoC technology. In addition, because it has excellent image processing capabilities, it can be used on smartphones. Mobile devices such as smartphones, tablets, laptops, and portable (portable) game consoles It is suitable for use in mobile electronic devices. Deep neural networks (DNNs) and convolutional neural networks ( CNN), recurrent neural network (RNN), autoencoder, deep Boltzmann It can implement techniques such as deep belief networks (DBM) and deep belief networks (DBN). Therefore, the chip 1200 is an AI chip, or the GPU module 1204 is an AI system module. It can be used as a tool.

[0377] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. This can be done.

[0378] (Embodiment 6) In this embodiment, an application example of a semiconductor device using the memory device described in the above embodiment will be described. The storage device shown in the above embodiment is a memory card (for example, an SD card), a U Various removable storage devices such as USB memory and SSD (Solid State Drive) 74A to 74E show some configurations of removable storage devices. For example, the semiconductor device shown in the above embodiment is packaged. It is processed into memory chips and used in various storage devices and removable memory.

[0379] FIG. 74A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a carrier The board 1104 includes a chip 1102, a USB connector 1103, and a circuit board 1104. It is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 1105, The controller chip 1106 is attached to the memory chip 1105. The memory device or semiconductor device shown in the above embodiment can be incorporated.

[0380] FIG. 74B is a schematic diagram of the external appearance of an SD card, and FIG. 74C is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a board 1113. The substrate 1113 is housed in a housing 1111. For example, the substrate 1113 has: A memory chip 1114 and a controller chip 1115 are attached to the board 111. By providing a memory chip 1114 on the back side of the SD card 1110, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. This allows the memory chip to communicate wirelessly between the host device and the SD card 1110. The data in the memory chip 1114 can be read and written. The memory device or semiconductor device described in the embodiment can be incorporated into the semiconductor device.

[0381] FIG. 74D is a schematic diagram of the external appearance of an SSD, and FIG. 74E is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The board 1153 is housed in the housing 1151. For example, the board 1153 may include a memory chip. 1154, memory chip 1155, and controller chip 1156 are attached. The memory chip 1155 is a working memory for the controller chip 1156, and A memory chip 1154 is also provided on the back side of the substrate 1153. By doing so, the capacity of the SSD 1150 can be increased. The memory device or semiconductor device described in the above embodiment can be incorporated into the semiconductor device.

[0382] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0383] (Embodiment 7) 75A to 75G show examples of memory devices or semiconductor devices according to one embodiment of the present invention. Specific examples of child devices are shown below.

[0384] <Electronic devices and systems> The memory device or semiconductor device according to one embodiment of the present invention can be incorporated into various electronic devices. Examples of electronic devices include information terminals, computers, smartphones, and Book terminals, television equipment, digital signage Electronic signs), large game machines such as pachinko machines, digital cameras, digital video cameras, Digital photo frames, mobile phones, portable game consoles, recording and playback devices, navigation systems The computer here includes a tablet, a computer system, a sound reproducing device, etc. In addition to laptop computers, notebook computers, and desktop computers, This includes large computers such as server systems.

[0385] The electronic device according to one embodiment of the present invention may include an antenna. This allows the display of images, information, etc. on the display unit. In the case where the device has a secondary battery, the antenna may be used for contactless power transmission.

[0386] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, etc.). , distance, light, liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared radiation) It may be possible.

[0387] The electronic device according to one embodiment of the present invention can have various functions. Still images, videos, text images, etc.) on the display, touch panel function, calendar It has the functions of displaying the date, time, etc., and running various software (programs). functions, wireless communication functions, and functions to read programs or data recorded on recording media. They may have abilities, etc.

[0388] [Information terminal] The memory device or the semiconductor device according to one embodiment of the present invention is used to program a microcontroller. Therefore, according to one aspect of the present invention, a memory device for holding a gram can be formed. The microcontroller chip can be made smaller.

[0389] FIG. 75A shows a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102, and an input interface. As a face, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101. According to one aspect of the present invention, a miniaturized microcontroller is used. This allows for effective use of the limited space inside the mobile phone. A storage device according to one embodiment of the present invention may be used for the storage. This allows for a larger storage capacity per unit area.

[0390] FIG. 75B illustrates a notebook type information terminal 5200. The information terminal includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203. According to one aspect of the present invention, a miniaturized microcontroller is used to This allows for effective use of the limited space inside the information terminal. A storage device according to one embodiment of the present invention may be used for the storage. This allows for a larger storage capacity per unit area of ​​the memory.

[0391] In the above, a smartphone and a notebook type information terminal are used as examples of electronic devices. As shown in Figures 75A and 75B, the devices are not limited to smartphones and notebook-type information terminals. Other information terminals can be applied. Examples of information terminals include PDAs (Personal Digital Assistants) ant), desktop information terminals, and workstations.

[0392] [Game consoles] FIG. 75C shows a portable game machine 5300, which is an example of a game machine. 300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 530 5, operation keys 5306, etc. The housing 5302 and the housing 5303 are The connection part 5305 provided on the housing 5301 can be removed from another housing. By attaching it to the body (not shown), the image output on the display unit 5304 can be displayed on another video device. (not shown). At this time, the housings 5302 and 5303 Each of these can function as an operation unit. This allows multiple players to play at the same time. The boards of the housings 5301, 5302, and 5303 are A memory device or a semiconductor device according to one embodiment of the present invention is incorporated into a chip or the like. You can put it in.

[0393] FIG. 75D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire. do.

[0394] One embodiment of the present invention is applied to game machines such as a portable game machine 5300 and a stationary game machine 5400. By using such a miniaturized microcontroller, it is possible to reduce the space inside the game console. In addition, the storage of the portable game machine can be effectively utilized. Such a storage device or semiconductor device may be used. The storage capacity per area can be increased.

[0395] 75C and 75D show examples of game machines, such as a portable game machine and a stationary game machine. Although the microcontroller of one aspect of the present invention is illustrated in the figure, this is not a game machine. The microcontroller of one embodiment of the present invention can be applied to a game machine such as: For example, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), Examples include pitching machines for batting practice installed at sports facilities.

[0396] [Mainframe Computer] A memory device or a semiconductor device according to one embodiment of the present invention can be applied to a large-scale computer. can.

[0397] FIG. 75E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 75F shows a rack-mounted computer 5500 included in the supercomputer 5500. 502.

[0398] The Supercomputer 5500 consists of a rack 5501 and multiple rack-mounted computers. The computers 5502 are stored in a rack 5501. The computer 5502 is provided with a plurality of substrates 5504, on which the The microcontroller according to one aspect of the present invention can be mounted on the By using a microcontroller with a built-in microcontroller, the limited space of a large computer can be effectively utilized. In addition, the present invention can be applied to the storage of a large-scale computer. Such a storage device or semiconductor device may be used. The storage capacity per area can be increased.

[0399] In Figures 75E and 75F, a supercomputer is shown as an example of a large computer. However, a large scale computer to which a microcontroller according to one aspect of the present invention is applied is The present invention is not limited to the above. Examples of such data include computers that provide services (servers), large general-purpose computers, Examples include computers (mainframes).

[0400] [electric appliances] FIG. 75G shows an electric refrigerator-freezer 5800, which is an example of an electric appliance. The cabinet 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0401] The memory device or semiconductor device according to one embodiment of the present invention is applied to an electric refrigerator-freezer 5800. For example, the miniaturized refrigerator-freezer 5800 according to one embodiment of the present invention may be used. By applying a microcontroller with It can be used for.

[0402] We have explained the electric refrigerator-freezer as an example of an electrical appliance, but other electrical appliances include: For example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water heaters, etc. Servers, heating and cooling appliances including air conditioners, washing machines, dryers, audiovisual equipment Examples include personal equipment.

[0403] The electronic devices described in the present embodiment, their functions, effects, etc. may be used in conjunction with other electronic devices. This can be combined as appropriate with the description of

[0404] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible. [Example]

[0405] Optimal carriers for semiconductors 127 used in memory strings 120 according to one embodiment of the present invention The concentration range was investigated using device simulation.

[0406] The device simulation was performed using Synopsys TCAD Sentaurus. The device simulation was performed on a memory device having three memory elements MC (memory cells). The simulation was carried out assuming restoring. FIG. 76B shows a two-dimensional structure of the memory string 900. 1 is an enlarged view of one of the memory elements MC.

[0407] As shown in FIGS. 76A and 76B, the memory string 900 is made of a conductor W WL, conductor RWL, insulator P_Ins (insulator 123), insulator T_Ins (insulator 1 24), oxide semiconductor OS1 (semiconductor 125), insulator M_Ins (insulator 126), acid Semiconductor OS2 (Semiconductor 127), Conductor FG (Conductor 128), Insulator B_Ins ( A configuration including an insulator 129) and a conductor BG (conductor 130) was assumed.

[0408] Table 1 shows the setting parameters for the insulator and conductor. In Table 1, the insulator T_Ins , the film thickness of the insulator M_Ins, the insulator B_Ins, and the conductor BG is the insulator T_In s, the length of the insulator M_Ins, the insulator B_Ins, and the conductor BG in the X direction. In the insulator T_Ins, the length in the direction perpendicular to the side and top surfaces of the conductor FG is also The film thickness of the insulator P_Ins, conductor WWL, and conductor RWL is referred to as the insulating thickness. The lengths of the insulator P_Ins, the conductor WWL, and the conductor RWL in the Z direction. The length of the conductor FG in the Z direction was set to 60 nm, and the length of the conductor FG in the X direction was set to 50 nm.

[0409] [Table 1]

[0410] Table 2 shows the semiconductor setting parameters. The film thickness of the oxide semiconductor OS2 is the length in the X direction of the oxide semiconductor OS1 and the oxide semiconductor OS2. In the oxide semiconductor OS1, the conductor FG is perpendicular to the side and top surfaces. The length in the direction is also called the film thickness.

[0411] [Table 2]

[0412] The device simulation was performed by dividing the two-dimensional structure shown in Figure 76A into 36 The experiment was carried out assuming a memory string 900 with a cylindrical structure rotated by 0°.

[0413] When the node ND[3] is held at “0” (L potential), and when the node ND[3] is held at “1 For each case where the "H potential" is maintained, the oxide semiconductor The voltage change of OS2 was calculated. In this simulation, the L potential was 0 V and the H potential was It was set to 1.5V.

[0414] FIG. 77 shows an equivalent circuit diagram of the memory string 900. In FIG. 77, The conductor WBL, the conductor RBL, and the terminal 995 are not shown. The conductor RBL is electrically connected to one end of the oxide semiconductor OS1. The terminal 995 is electrically connected to the other end of the oxide semiconductor OS2. can be.

[0415] Next, the read operation performed in the device simulation will be explained (see FIG. 77). During the read operation, the voltage of the conductor BG is set to 0V, and the voltage of the conductors WWL[1] to WW The voltage of L[3] was set to -1V.

[0416] First, a high potential is applied to the conductor RBL, and 0 V is applied to the terminal 995. Next, Supply 3.3V to L[1] and conductor RWL[2], and 0V to conductor RWL[3]. Then, the transistors RTr[1] and RTr[2] are turned on. The transistor RTr[3] is turned on and off depending on the voltage of the node ND[3]. The state is determined.

[0417] Next, the voltage supply to the conductor RBL is stopped, and the conductor RBL is put into a floating state. Then, the voltage of the conductor RBL changes according to the voltage of the node ND[3]. By detecting this, the information held in node ND[3] can be known.

[0418] In the device simulation, the voltage change of the conductor RBL during the read operation is calculated by the oxide semiconductor Calculations were made for each carrier concentration of the conductor OS2.

[0419] The calculation results are shown in Figures 78A to 78H. The horizontal axis of Figures 78A to 78H represents the elapsed time (ti me), and the vertical axis represents the voltage (V_BL) of the oxide semiconductor OS2. After 2 μs from the start, the conductor RBL was set to a floating state. Therefore, profile 999[0] is V_ This shows the change in BL. Also, profile 999[1] has a value of “1” at node ND[3]. This shows the change in V_BL when

[0420] FIG. 78A shows the carrier concentration (Nd) of the oxide semiconductor OS2 at 3×10 17 / cm 3 and Figure 78B shows the calculation results when Nd is 4 × 10 17 / cm 3 Calculation result when Figure 78C shows Nd at 6 × 10 17 / cm 3 This is the calculation result when Figure 78 D is Nd 1×10 18 / cm 3 Figure 78E shows the calculation results when Nd is 1 .4×10 18 / cm 3 Figure 78F shows the calculation results when Nd is 1.6 × 10 18 / cm 3 Figure 78G shows the calculation results when Nd is 1.8 × 10 18 / cm 3 Figure 78H shows the calculation results when Nd is 2 × 10 18 / cm 3 In the case of This is the calculation result.

[0421] Figure 79 shows the profile of Nd of the oxide semiconductor OS2 and the profile 12 μs after the start of the read operation. A graph showing the relationship between the voltage difference (dV_BL) between profile 999[0] and profile 999[1] In FIG. 79, the horizontal axis represents Nd of the oxide semiconductor OS2, and the vertical axis represents dV_BL. If V_BL is 1V or higher, it is "read OK", and if it is less than 1V, it is "read NG". Then, Nd becomes 4×10 17 / cm 3 Over 1.4 x 10 18 / cm 3 Node ND when: It can be seen that the information stored in [3] can be read.

[0422] By using Formulas 1 and 2, the oxide semiconductor film thickness and carrier concentration can be calculated. The sheet resistance of the semiconductor can be determined.

[0423]

number

[0424]

number

[0425] R sheet is the sheet resistance, ρ OS is the resistivity of the oxide semiconductor, t OS is an oxide semiconductor film Thickness, n OS is the carrier concentration in the oxide semiconductor, μ OS is the electron mobility of the oxide semiconductor, and q is It is the elementary charge.

[0426] μ OS 10cm 2 / Vs, q = 1.6022 × 10 -19 Oxide when Coulomb Table 3 shows the conversion table of carrier concentration and sheet resistance for each semiconductor film thickness.

[0427] [Table 3]

[0428] From Table 3, when the oxide semiconductor film thickness is 15 nm, the carrier concentration is 4 × 10 17 / cm 3 is and the sheet resistance is 1×10 6 Ω / □. Also, the carrier concentration is 1.4×1 0 18 / cm 3 Then the sheet resistance is 3×10 5 We can see that it becomes Ω / □.

[0429] Device simulations have shown that the carrier concentration of semiconductor 127 is 4×10 17 / cm 3 Over 1.4 x 10 18 / cm 3 The following was found to be preferable. Sheet resistance is 3×10 5 Ω / □ or more 1×10 6 It was found that Ω / □ or less is preferable.

[0430] This embodiment can be implemented by appropriately combining with the configurations described in other embodiments. is. [Explanation of symbols]

[0431] 100: storage device, 105: area, 110: memory cell array, 120: memory string 121: substrate, 122: conductor, 123: insulator, 124: insulator, 125: semiconductor , 126: insulator, 127: semiconductor, 128: conductor, 129: insulator, 130: conductor , 132: insulator, 134: conductor, 136: conductor

Claims

[Claim 1] a first conductor, a second conductor, a third conductor, and a fourth conductor; a first insulator, a second insulator, and a third insulator; a first semiconductor and a second semiconductor; a first transistor; and the first conductor extends in a first direction; On a side surface of the first conductor extending in the first direction, the first insulator is disposed adjacent to the first conductor; the first semiconductor is disposed adjacent to the first insulator; the second insulator is disposed adjacent to the first semiconductor; the second semiconductor is disposed adjacent to the second insulator; the third insulator is disposed adjacent to the second semiconductor; the first conductor has a first region and a second region; In the first region, the second conductor is provided adjacent to the third insulator, In the second region, the third conductor is provided adjacent to the third insulator, In the second region, the fourth conductor is provided between the second insulator and the second semiconductor; The first semiconductor and the second semiconductor are electrically connected to one of the source and the drain of the first transistor.

Images