Switching device

Abstract

To provide a switching device having a novel configuration.SOLUTION: The switching device includes the island separately provided in the resin package, the conductive member is connected to the source terminal and the source electrode, is interposed in the current path between the single sense source terminal and the source electrode, and does not directly connect the single sense source terminal and the source electrode, but the single sense source terminal and the source electrode are electrically connected via the island as the conductor and the relay point, and the switching device does not have a wire that directly connects the single sense source terminal and the SiC switching element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to switching devices. [Background technology]

[0002] Switching devices used in electronic circuits such as inverter circuits and converter circuits generally consist of multiple switching elements connected in parallel to increase current capacity. In addition to Si switching elements, SiC switching elements are also known. Examples of SiC switching elements include SiC-MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), SiC-Bipolar Transistors, SiC-JFETs (Junction Field Effect Transistors), and SiC-IGBTs (Insulated Gate Bipolar Transistors). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-137072 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide a switching device with a novel configuration. [Means for solving the problem]

[0005] One embodiment of the present disclosure provides a switching device including: a SiC switching element having a gate electrode, a source electrode, and a drain electrode; a source terminal electrically connected to the source electrode and outputting a current that flows in response to an on-control; a single sense-source terminal electrically connected to the source electrode; a conductive member having a resistance; a resin package that seals the SiC switching element, the single sense-source terminal, and the conductive member; and an island separately provided within the resin package, wherein the conductive member is connected to the source terminal and the source electrode and is interposed in a current path between the single sense-source terminal and the source electrode; the single sense-source terminal and the source electrode are not directly connected to each other, but the single sense-source terminal and the source electrode are electrically connected via a conductor and the island as a relay point; and no wire is provided that directly connects the single sense-source terminal and the SiC switching element.

[0006] In one embodiment of the present disclosure, the semiconductor device includes a gate terminal electrically connected to the gate electrode and a drain terminal electrically connected to the drain electrode, and a portion of a terminal portion of the source terminal, a portion of the single sense source terminal, a portion of the gate terminal, and a portion of a terminal portion of the drain terminal are each exposed from the resin package.

[0007] In one embodiment of the present disclosure, the conductor includes a bonding wire.

[0008] In one embodiment of the present disclosure, the single sense source terminal and the source electrode are connected by at least two wires, with the island as a relay point.

[0009] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1]FIG. 1 is a schematic diagram of a switching device according to one embodiment of the present invention. [Figure 2] FIG. 2 is an electrical circuit diagram of the switching device of FIG. [Figure 3] FIG. 3 is an electrical circuit diagram of an inverter circuit according to one embodiment of the present invention. [Figure 4] FIG. 4 is an electric circuit diagram showing the electrical configuration of a module on which a plurality of switching devices shown in FIG. 1 are mounted. [Figure 5] FIG. 5 is an electric circuit diagram showing the electrical configuration of the gate drive circuit. [Figure 6] FIG. 6 is a graph showing the relationship between the gate-source voltage and the short-circuit withstand capability of the switching device of FIG. [Figure 7] FIG. 7 is a plan view for explaining the configuration of the semiconductor module. [Figure 8] FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is an electric circuit diagram of the semiconductor module shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0012] Fig. 1 is a schematic diagram of a switching device 1 according to one embodiment of the present invention. Fig. 2 is an electrical circuit diagram of the switching device 1 of Fig. 1. In Fig. 1, one corner (a region hatched with a dashed line) of a semiconductor chip 11 is shown in perspective to clarify the configuration of the switching device 1.

[0013] The switching device 1 includes a flat rectangular resin package 2, a source terminal 3 (S) as an example of an output terminal of the present invention sealed in the resin package 2, a sense source terminal 4 (SS) as an example of a driving terminal of the present invention, a gate terminal 5 (G), and a drain terminal 6 (D).

[0014] The four terminals 3 to 6 are each made of a metal plate formed into a predetermined shape, and are arranged in order from one side surface of the resin package 2 to the opposite side surface.

[0015] In this embodiment, the source terminal 3 and the drain terminal 6 are each formed to have a shape including rectangular islands 7 and 8 and elongated rectangular terminal portions 9 and 10 extending linearly from one side of the islands 7 and 8. The sense source terminal 4 and the gate terminal 5 are also formed to have an elongated rectangular shape, similar to the terminal portions 9 and 10. The terminal portion 9 of the source terminal 3, and the terminal portions 10 of the sense source terminal 4, gate terminal 5 and drain terminal 6 are arranged parallel to one another.

[0016] A semiconductor chip 11, which is an example of a SiC switching element of the present invention, is mounted on the drain terminal 6 (at the center of the island 8). A drain pad 12, which is an example of a third electrode of the present invention, is formed over almost the entire back surface of the semiconductor chip 11, and this drain pad 12 is bonded to the island 8. This electrically connects the drain pad 12 of the semiconductor chip 11 to the drain terminal 6. A source pad 13, which is an example of a second electrode of the present invention, and a gate pad 14, which is an example of a first electrode of the present invention, are formed on the front surface of the semiconductor chip 11.

[0017] The source pad 13 has a generally square shape in plan view, and is formed to cover almost the entire surface of the semiconductor chip 11. A removal region 15 is formed in the source pad 13 near the center of one side. The removal region 15 is an area where the source pad 13 is not formed. The gate pad 14 is disposed in the removal region 15. A gap is provided between the gate pad 14 and the source pad 13, and they are insulated from each other.

[0018] A plurality of source wires 16 (bonding wires), which are an example of the conductive member of the present invention, are stretched between the source pad 13 and the source terminal 3, and the source pad 13 and the source terminal 3 are electrically connected by the source wires 16. In this embodiment, four source wires 16 of the same length are provided parallel to one another. Therefore, the resistance of each source wire 16 can be unified to a constant value. In addition, a sense source wire 17 (bonding wire) is stretched between the source terminal 3 (island 7) and the sense source terminal 4. As a result, the sense source terminal 4 is electrically connected to the source pad 13 via a current path including the sense source wires 17 and the source wires 16.

[0019] 1, one end of the sense source wire 17 is separated from the source pad 13 and connected to the source terminal 3. This makes it possible to connect an external resistor 22 having a resistance value r according to the constituent material, length, wire diameter, etc. of the source wire 16 in series between the sense source terminal 4 and the source pad 13, as shown in FIG. 2. In other words, in the switching device 1 according to this embodiment, the position of the sense source is separated from the source end (source pad 13) of the semiconductor chip 11, and a wire, wiring, etc. is interposed therebetween, thereby providing an external gate resistor (external resistor 22) that becomes a parasitic resistance when a gate-source voltage is applied to the semiconductor chip 11.

[0020] A gate wire 18 (bonding wire) is stretched between the gate pad 14 and the gate terminal 5, and the gate pad 14 and the gate terminal 5 are electrically connected by the gate wire 18.

[0021] In this embodiment, as shown in FIG. 2, the semiconductor chip 11 includes a MOSFET 19 (SiC-MOSFET) using SiC and a body diode 20. The source, drain, and gate of the MOSFET 19 are electrically connected to a source pad 13, a drain pad 12, and a gate pad 14, respectively. The switching element formed in the semiconductor chip 11 may be an element other than a MOSFET. For example, the switching element may be a SiC-IGBT, a SiC-bipolar transistor, a SiC-JFET, or the like. When the switching element is a SiC-IGBT, the source pad 13, the drain pad 12, the gate pad 14, and the sense-source terminal 4 correspond to the emitter pad, collector pad, gate pad, and sense-emitter terminal of the SiC-IGBT, respectively. When the switching element is a SiC-bipolar transistor, the source pad 13, the drain pad 12, the gate pad 14, and the sense-source terminal 4 correspond to the emitter pad, collector pad, base pad, and sense-emitter terminal of the SiC-bipolar transistor, respectively.

[0022] Resin package 2 encapsulates semiconductor chip 11, the entire wires 16 to 18, the entire island 7 and part of terminal portion 9 of source terminal 3, parts of sense source terminal 4 and gate terminal 5, and the entire island 8 and part of terminal portion 10 of drain terminal 6. From the side surface of resin package 2, parts of terminal portion 9 of source terminal 3, sense source terminal 4, gate terminal 5, and terminal portion 10 of drain terminal 6 are exposed.

[0023] Fig. 3 is an electrical circuit diagram of an inverter circuit 31 according to one embodiment of the present invention. Fig. 4 is an electrical circuit diagram showing the electrical configuration of a switching module 43 on which a plurality of switching devices 1 of Fig. 1 are mounted.

[0024] An inverter circuit 31 as an example of an electronic circuit of the present invention includes first to fourth switching devices 32 to 35, first to fourth gate drive circuits 36 to 39, and a control unit 40.

[0025] The first to fourth switching devices 32 to 35 are each configured with the above-mentioned switching device 1. Note that Fig. 3 selectively shows those circuit elements shown in Fig. 2 that are necessary for explaining Fig. 3. Furthermore, the first to fourth switching devices 32 to 35 may be incorporated into the inverter circuit 31 as a switching module 43 configured by connecting a plurality of switching devices 1 in parallel, as shown in Fig. 4, for example, with the first switching device 32 as a representative example.

[0026] The drain terminal 6 of the first switching device 32 is connected to the positive terminal of the power supply 41. The source terminal 3 of the first switching device 32 is connected to the drain terminal 6 of the second switching device 33. The gate terminal 5 of the first switching device 32 and the sense source terminal 4 of the first switching device 32 are connected to the first gate drive circuit 36.

[0027] The source terminal 3 of the second switching device 33 is connected to the negative terminal of the power supply 41. The gate terminal 5 of the second switching device 33 and the sense source terminal 4 of the second switching device 33 are connected to a second gate drive circuit 37.

[0028] The drain terminal 6 of the third switching device 34 is connected to the positive terminal of the power supply 41. The source terminal 3 of the third switching device 34 is connected to the drain terminal 6 of the fourth switching device 35. The gate terminal 5 of the third switching device 34 and the sense source terminal 4 of the third switching device 34 are connected to a third gate drive circuit 38.

[0029] The source terminal 3 of the fourth switching device 35 is connected to the negative terminal of a power supply 41. The gate terminal 5 of the fourth switching device 35 and the sense source terminal 4 of the fourth switching device 35 are connected to a fourth gate drive circuit 39. A load 42 is connected between the connection point between the first switching device 32 and the second switching device 33 and the connection point between the third switching device 34 and the fourth switching device 35.

[0030] The control unit 40 is made up of a microcomputer including a CPU and memories (ROM, RAM, etc.) that store its programs, etc. The control unit 40 generates a first gate control signal CG1 for the MOSFET 19 of the first switching device 32, a second gate control signal CG2 for the MOSFET 19 of the second switching device 33, a third gate control signal CG3 for the MOSFET 19 of the third switching device 34, and a fourth gate control signal CG4 for the MOSFET 19 of the fourth switching device 35, and provides these signals to the first to fourth gate drive circuits 36 to 39, respectively.

[0031] The gate drive circuits 36, 37, 38, 39 generate and output gate drive signals DG1, DG2, DG3, DG4 for the first switching device 32, the second switching device 33, the third switching device 34, and the fourth switching device 35, respectively, based on gate control signals CG1, CG2, CG3, CG4 provided by the control unit 40. This controls the driving of the first to fourth switching devices 32 to 35.

[0032] In such an inverter circuit 31, for example, the first switching device 32 and the fourth switching device 35 are turned on. Thereafter, these switching devices 32 and 35 are turned off, thereby turning all of the switching devices 32 to 35 into the off state. After a predetermined dead time period has elapsed, the second switching device 33 and the third switching device 34 are turned on. Thereafter, these switching devices 33 and 34 are turned off, thereby turning all of the switching devices 32 to 35 into the off state. After a predetermined dead time period has elapsed, the first switching device 32 and the fourth switching device 35 are turned on again. By repeating such operations, the load 42 is AC driven.

[0033] Each gate drive circuit 36, 37, 38, 39 has an overcurrent protection function for protecting the corresponding switching device 32, 33, 34, 35 when a short circuit occurs, causing the voltage of the power supply 41 to be directly applied to the corresponding switching device 32, 33, 34, 35. Examples of situations in which a short circuit occurs, causing the voltage of the power supply 41 to be directly applied to the switching device 32, 33, 34, 35, include when the load 42 is shorted, when two switching devices (32, 33; 34, 35) connected in series between the positive and negative terminals of the power supply 41 are simultaneously turned on, or when one of the two switching devices (32, 33; 34, 35) connected in series between the positive and negative terminals of the power supply 41 experiences a short-circuit failure. Because each gate drive circuit 36, 37, 38, 39 has the same configuration, the overcurrent protection function of the first gate drive circuit 36 ​​will be described in detail below.

[0034] FIG. 5 is an electrical circuit diagram showing the electrical configuration of the gate drive circuit 36.

[0035] The first gate drive circuit 36 ​​includes an amplifier circuit 51 , a first switching circuit 52 , a gate resistor 53 , a second switching circuit 54 , a current blocking resistor 55 , and an overcurrent detection circuit 56 .

[0036] A gate control signal CG1 from the control unit 40 is input to an input terminal of the amplifier circuit 51. The amplifier circuit 51 amplifies the gate control signal CG1 to generate a gate drive signal DG1. The output terminal of the amplifier circuit 51 is connected to one input terminal a of a first switching circuit 52. The first switching circuit 52 has two input terminals a and b and one output terminal c, and selects either one of the input terminals a and b to connect to the output terminal c. The other input terminal b of the first switching circuit 52 is in an open state. The output terminal c of the first switching circuit 52 is connected to the gate terminal 5 of the first switching device 32 via a gate resistor 53. The first switching circuit 52 is controlled by the output of an overcurrent detection circuit 56.

[0037] The second switching circuit 54 has one input terminal d and two output terminals e and f, and selects one of the output terminals e and f to connect the input terminal d to the selected output terminal. The input terminal d is connected to the connection point between the gate resistor 53 and the gate terminal 5 of the first switching device 32 via a current interruption resistor 55. One output terminal e is in an open state. The other output terminal f is grounded. The second switching circuit 54 is controlled by the output of an overcurrent detection circuit 56. The resistance value of the gate resistor 53 is r1, and the resistance value of the current interruption resistor 55 is r2. As will be described later, r2 is set to a value greater than r1.

[0038] The overcurrent detection circuit 56 includes a current detection resistor 57 and a comparison circuit 58. One end of the current detection resistor 57 is connected to the sense source terminal 4 of the first switching device 32, and the other end of the current detection resistor 57 is grounded. The voltage (voltage drop) across the current detection resistor 57 is calculated based on the current I flowing through the MOSFET 19 of the first switching device 32. DThe voltage across the current detection resistor 57 is applied to a comparison circuit 58. The comparison circuit 58 compares the voltage across the current detection resistor 57 with a reference voltage to determine whether or not an overcurrent state exists, and outputs a determination signal representing the determination result. Specifically, the comparison circuit 58 determines that an overcurrent state exists (detects an overcurrent) when the voltage across the current detection resistor 57 is greater than the reference voltage.

[0039] When no overcurrent is detected by the overcurrent detection circuit 56 (normal operation), the second switching circuit 54 selects the first output terminal e and connects the input terminal d to the first output terminal e. As a result, the input terminal d of the second switching circuit 54 is in a high impedance state. Furthermore, the first switching circuit 52 selects the first input terminal a and connects the first input terminal a to the output terminal c. As a result, the gate drive signal DG1 generated by the amplifier circuit 51 is applied to the gate terminal 5 of the first switching device 32 via the gate resistor 53. The MOSFET 19 of the first switching device 32 is driven and controlled by this gate drive signal DG1.

[0040] When an overcurrent is detected by the overcurrent detection circuit 56, the first switching circuit 52 selects the second input terminal b and connects the output terminal c to the second input terminal b. As a result, the output terminal c of the first switching circuit 52 goes into a high impedance state. Furthermore, the second switching circuit 54 selects the second output terminal f and connects the input terminal d to the second output terminal f. As a result, the input terminal d of the second switching circuit 54 is grounded.

[0041] That is, the gate terminal 5 of the first switching device 32 is grounded via the current blocking resistor 55. As a result, the gate-source voltage Vgs of the first switching device 32 is reduced, and the drain current I flowing through the MOSFET 19 of the first switching device 32 is reduced. DThe short-circuit current (short-circuit current) is interrupted. The interruption speed of the short-circuit current varies depending on the resistance value r2 of the current interruption resistor 55. The larger the resistance value r2 of the current interruption resistor 55, the slower the interruption speed of the short-circuit current. The resistance value r2 of the current interruption resistor 55 is greater than the resistance value r1 of the gate resistor 53. In this embodiment, the resistance value r1 of the gate resistor 53 is, for example, 3.9 [Ω], and the resistance value r2 of the current interruption resistor 55 is, for example, 33 [Ω].

[0042] The short-circuit current is interrupted by grounding the gate terminal 5 of the first switching device 32, but it takes a certain amount of time for the interruption. For example, it takes about 10 μsec (microseconds) after the overcurrent is detected. However, if the first switching device 32 cannot be interrupted within the short-circuit withstand voltage tsc, the short-circuit current I D The first switching device 32 may be thermally destroyed due to thermal runaway caused by the above.

[0043] Therefore, in this embodiment, as described above, an external resistor 22 having a resistance value r according to the constituent material, length, wire diameter, etc. of the source wire 16 (see FIG. 2) is connected in series between the source end of the MOSFET 19 and the sense source terminal 4.

[0044] Therefore, compared to when the sense source terminal 4 is directly connected to the source end of the MOSFET 19 as in the conventional wire 21 shown by the dashed line in FIG. 5, an overcurrent I D The gate-source voltage Vgs when D ·r) can be reduced.

[0045] Fig. 6 is a graph showing the relationship between the gate-source voltage Vgs and the short-circuit capability tsc of the switching device 1 of Fig. 1. Specifically, two types of device samples having a structure similar to that of the switching device 1 shown in Fig. 1 were fabricated, and one MOSFET 19 was formed as a DMOS (Double-Diffused MOSFET) and the other MOSFET 19 was formed as a TMOS (Trench MOSFET), and the results of a short-circuit test were shown.

[0046] As shown in Figure 6, in both the DMOS and TMOS cases, the short-circuit capability tsc improves as the gate-source voltage Vgs decreases. Therefore, as shown in Figure 5, the overcurrent I D When the voltage Vgs between the gate and source flows, the voltage drop (-I D r), the short-circuit resistance of the first switching device 32 can be improved. As a result, the short-circuit current I D can be blocked.

[0047] Furthermore, by appropriately adjusting the constituent material, length, wire diameter, etc. of the source wire 16 (see FIG. 2) and determining the resistance value of the external resistor 22, the drain current I D When the drain current I is relatively small or at a rated value, the voltage drop across the external resistor 22 can be reduced. D When is relatively low, the gate-source voltage Vgs is about 18.5V, and the drain current I D When is the rated value, the gate-source voltage Vgs is about 18.0V, and the drain current I D When is 4 to 5 times the rated value, the resistance value r of the external resistor 22 is set to I so that the gate-source voltage Vgs is about 16.5V. D ×1 / 100mΩ~5×I D × 1 / 100mΩ. This allows the drain current I DWhen is relatively small or at the rated value, the decrease in the gate-source voltage Vgs can be suppressed, and a drive voltage sufficient for switching operation can be applied to the MOSFET 19. In other words, the impact on the switching performance of the MOSFET 19 is small.

[0048] Furthermore, in this embodiment, the source wire 16 for current output of the switching device 1 is used as the external resistor 22, so that the effect of improving the short-circuit resistance described above can be achieved at low cost without increasing the number of components.

[0049] Furthermore, in this embodiment, since the external resistor 22 is sealed in the resin package 2, the switching device 1 can be mounted in a conventional layout.

[0050] Although one embodiment of the present invention has been described above, the present invention can also be embodied in other forms.

[0051] For example, in the above-described embodiment, one current interruption resistor 55 is used to interrupt the short-circuit current, but multiple current interruption resistors may be used to change the interruption speed in stages when interrupting the current.

[0052] For example, a case will be described in which, in Fig. 5, gate resistor 53 is used as a first current blocking resistor and current blocking resistor 55 is used as a second current blocking resistor when detecting an overcurrent. The resistance value r2 of the second current blocking resistor (current blocking resistor 55) is set to be larger than the resistance value r1 of the first current blocking resistor (gate resistor 53). For example, the resistance value r1 is 3.9 [Ω] and the resistance value r2 is 33 [Ω].

[0053] In this case, the first switching circuit 52 has a third input terminal g, as shown by the dashed line in Fig. 5. The third input terminal g is grounded. The gate drive circuit 36 ​​also includes a voltage monitoring unit 59 that monitors the gate-source voltage Vgs of the first switching device 32, as shown by the dashed line in Fig. 5.

[0054] When an overcurrent is detected by the overcurrent detection circuit 56, the first switching circuit 52 selects the second input terminal b and connects the output terminal c to the second input terminal b. As a result, the output terminal c of the first switching circuit 52 goes into a high impedance state. Furthermore, the second switching circuit 54 selects the second output terminal f and connects the input terminal d to the second output terminal f. As a result, the input terminal d of the second switching circuit 54 is grounded.

[0055] That is, the gate terminal 5 of the first switching device 32 is grounded via the second current blocking resistor 55. As a result, the gate-source voltage Vgs of the first switching device 32 is reduced. In this case, the resistance value of the second current blocking resistor 55 is set larger than the resistance value of the first current blocking resistor 33, so the current blocking speed is slower than when the gate terminal 5 of the first switching device 32 is grounded via the first current blocking resistor 33. When the gate-source voltage Vgs decreases and reaches a voltage value (10 V in this example) at which the temperature characteristic of the on-resistance of the first switching device 32 becomes negative, the voltage monitoring unit 59 outputs a resistance switching signal to the first switching circuit 52 and the second switching circuit 54.

[0056] When the first switching circuit 52 receives a resistance switching signal from the voltage monitoring unit 59, it selects the third input terminal g and connects the output terminal c to the third input terminal g. When the second switching circuit 54 receives a resistance switching signal from the voltage monitoring unit 59, it selects the first output terminal e and connects the input terminal d to the first output terminal e. As a result, the gate terminal 5 of the first switching device 32 is grounded via the first current blocking resistor 33, and the gate-source voltage Vgs is reduced. Because the resistance value of the first current blocking resistor 33 is smaller than the resistance value of the second current blocking resistor 55, the current blocking speed is increased.

[0057] In addition, in the above-described embodiment, the source wire 16 is used as the external resistor 22 in order to avoid increasing the number of components. However, for example, an island made of a metal plate or the like may be provided separately within the resin package 2, and the sense source terminal 4 and the source pad 13 may be connected by at least two wires using the island as a relay point.

[0058] Furthermore, in the above embodiment, the present invention is applied to an inverter circuit, but the present invention can also be applied to electronic circuits other than inverter circuits, such as a converter circuit.

[0059] 7 to 10 show a semiconductor module to which a switching device according to an embodiment of the present invention is applied.

[0060] Fig. 7 is a plan view for explaining the configuration of the semiconductor module, showing a state in which the top plate has been removed. Fig. 8 is a schematic cross-sectional view taken along line VIII-VIII in Fig. 7. Fig. 9 is a schematic cross-sectional view taken along line IX-IX in Fig. 7.

[0061] The semiconductor module 61 includes a heat sink 62, a case 63, and a plurality of terminals assembled to the case 63. The plurality of terminals include a first power supply terminal (in this example, a positive power supply terminal) P, a second power supply terminal (in this example, a negative power supply terminal) N, a first output terminal OUT1, and a second output terminal OUT2. The plurality of terminals further includes a first source sense terminal SS1, a first gate terminal G1, a second source sense terminal SS2, and a second gate terminal G2. The first output terminal OUT1 and the second output terminal OUT2 will be collectively referred to as "output terminals OUT."

[0062] For ease of explanation, the following may refer to the +X direction, −X direction, +Y direction, and −Y direction shown in FIG. 7 and the +Z direction and −Z direction shown in FIG. 8. The +X direction and −X direction are two directions along the long sides of the case 63 (heat sink 62), which is generally rectangular in plan view, and are collectively referred to simply as the “X direction.” The +Y direction and −Y direction are two directions along the short sides of the case 63, and are collectively referred to simply as the “Y direction.” The +Z direction and −Z direction are two directions along the normal to the heat sink 62, and are collectively referred to simply as the “Z direction.” When the heat sink 62 is placed on a horizontal plane, the X direction and the Y direction are two horizontal directions (first horizontal direction and second horizontal direction) along two horizontal lines (X axis and Y axis) that are orthogonal to each other, and the Z direction is a vertical direction (height direction) along a vertical line (Z axis).

[0063] The heat sink 62 is a rectangular plate-like body of uniform thickness in a plan view, and is made of a material with high thermal conductivity. More specifically, the heat sink 62 may be a copper plate made of copper. This copper plate may have a nickel-plated layer formed on its surface. A heat sink or other cooling means is attached to the surface of the heat sink 62 on the -Z direction side, as needed.

[0064] The case 63 is formed in a substantially rectangular parallelepiped shape and is made of a resin material. It is particularly preferable to use a heat-resistant resin such as PPS (polyphenylene sulfide). The case 63 is rectangular in plan view and has approximately the same size as the heat sink 62. It includes a frame 64 fixed to one surface (the surface facing the +Z direction) of the heat sink 62 and a top plate (not shown) fixed to the frame 64. The top plate closes one side (the +Z direction) of the frame 64 and faces one surface of the heat sink 62, which closes the other side (the -Z direction) of the frame 64. Thus, the heat sink 62, the frame 64, and the top plate define a circuit-accommodating space within the case 63. In this embodiment, the frame 64 and the terminals are formed by simultaneous molding.

[0065] The frame 64 includes a pair of side walls 66, 67 and a pair of end walls 68, 69 connecting the ends of the pair of side walls 66, 67. Outwardly opening recesses 70 are formed at the four corners of the surface of the frame 64 on the +Z direction side. The wall opposite the outward opening of each recess 70 is curved to protrude inward. Mounting through-holes 71 are formed in the bottom wall of each recess 70, penetrating the bottom wall. Cylindrical metal members 72 are fitted and fixed in the mounting through-holes 71. Mounting through-holes (not shown) communicating with the mounting through-holes 71 are formed in the heat sink 62. The semiconductor module 61 is fixed to a predetermined position on the mounting target by bolts (not shown) inserted through the mounting through-holes 71 in the case 63 and the heat sink 62. Cooling means such as the heat sink described above may be attached using these mounting through-holes 71.

[0066] A terminal block 73 for the first power supply terminal P and a terminal block 74 for the second power supply terminal N are formed on the outer surface of the end wall 69. In a plan view, the terminal block 73 is disposed on the +Y side of the longitudinal center of the end wall 69, and the terminal block 74 is disposed on the −Y side of the longitudinal center of the end wall 69. These terminal blocks 73, 74 are formed integrally with the end wall 69.

[0067] A terminal block 75 for the first output terminal OUT1 and a terminal block 76 for the second output terminal OUT2 are formed on the outer surface of the end wall 68. In a plan view, terminal block 75 is disposed on the +Y direction side of the longitudinal center of the end wall 68, and terminal block 76 is disposed on the −Y direction side of the longitudinal center of the end wall 68. These terminal blocks 75, 76 are formed integrally with the end wall 68. A nut (not shown) is embedded in each of the terminal blocks 73, 74, 75, 76 with the central axis of its screw hole aligned in the Z direction.

[0068] A first power supply terminal P is arranged on the surface (surface facing the +Z direction) of terminal block 73. A second power supply terminal N is arranged on the surface (surface facing the +Z direction) of terminal block 74. A first output terminal OUT1 is arranged on the surface (surface facing the +Z direction) of terminal block 75. A second output terminal OUT2 is arranged on the surface (surface facing the +Z direction) of terminal block 76.

[0069] The first power supply terminal P, the second power supply terminal N, the first output terminal OUT1, and the second output terminal OUT2 are each made by cutting a metal plate (for example, a nickel-plated copper plate) into a predetermined shape and bending it, and are electrically connected to the circuit inside the case 63. The tips of the first power supply terminal P, the second power supply terminal N, the first output terminal OUT1, and the second output terminal OUT2 are extended onto the terminal blocks 73, 74, 75, and 76, respectively. The tips of the first power supply terminal P, the second power supply terminal N, the first output terminal OUT1, and the second output terminal OUT2 are formed to fit along the surfaces of the terminal blocks 73, 74, 75, and 76, respectively. Insertion holes 83d, 84d, 85d, and 86d are formed in the tips of the first power supply terminal P, the second power supply terminal N, the first output terminal OUT1, and the second output terminal OUT2, respectively. By using bolts that are inserted through these insertion holes 83d, 84d, 85d, 86d and screwed into the nuts, the terminals P, N, OUT1, OUT2 can be connected to bus bars provided on the mounting side of the semiconductor module 61.

[0070] A first source sense terminal SS1, a first gate terminal G1, etc. are attached to one side wall 67. The tips of these terminals SS1, G1 protrude outward (in the +Z direction) from the surface (surface on the +Z direction side) of the side wall 67 toward the outside of the case 63 (in the +Z direction). The first source sense terminal SS1 and the first gate terminal G1 are arranged at an interval in the X direction between the -X direction end of the side wall 67 and the center in the length direction (X direction).

[0071] A second gate terminal G2 and a second source sense terminal SS2 are attached to the other side wall 66. The tips of these terminals G2 and SS2 protrude outward (in the +Z direction) from the surface of the side wall 66 (the surface on the +Z direction side) of the case 63. The second gate terminal G2 and the second source sense terminal SS2 are arranged at intervals in the X direction between the center of the length direction (X direction) of the side wall 66 and the end on the +X direction side. The source sense terminals SS1 and SS2 and the gate terminals G1 and G2 are each made by bending a metal rod (for example, a nickel-plated copper rod) with a rectangular cross section, and are electrically connected to a circuit inside the case 63.

[0072] The first power terminal P includes a tip portion 83a that extends along the surface of the terminal block 73, a base portion 83b that is disposed parallel to the tip portion 83a on the -Z direction side of the tip portion 83a, and a rising portion that connects the tip portion 83a to the base portion 83b. The rising portion connects the -Y direction edge of the base portion 83b to the -Y direction edge of the tip portion 83a. Most of the base portion 83b and the rising portion of the first power terminal P are embedded within the end wall 69 and the terminal block 73. A comb-shaped terminal 83c that protrudes toward the inside of the case 63 is formed on the -X direction end of the base portion 83b.

[0073] The second power supply terminal N includes a tip portion 84a that extends along the surface of the terminal block 74, a base portion 84b that is disposed parallel to the tip portion 84a on the −Z direction side of the tip portion 84a, and a rising portion that connects the tip portion 84a to the base portion 84b. The rising portion connects the +Y direction edge of the base portion 84b to the +Y direction edge of the tip portion 84a. Most of the base portion 84b and the rising portion of the second power supply terminal N are embedded within the end wall 69 and the terminal block 74. A comb-shaped terminal 84c that protrudes toward the inside of the case 63 is formed on the −X direction end of the base portion 84b.

[0074] The first output terminal OUT1 includes a tip portion 85a that extends along the surface of the terminal block 75, a base portion 85b that is disposed parallel to the tip portion 85a on the −Z direction side of the tip portion 85a, and a rising portion that connects the tip portion 85a to the base portion 85b. The rising portion connects the −Y direction edge of the base portion 85b to the −Y direction edge of the tip portion 85a. Most of the base portion 85b of the first output terminal OUT1 and the rising portion are embedded within the end wall 68 and the terminal block 75. A comb-shaped terminal 85c that protrudes toward the inside of the case 63 is formed on the end portion of the base portion 85b on the +X direction side.

[0075] The second output terminal OUT2 includes a tip portion 86a that extends along the surface of the terminal block 76, a base portion 86b that is disposed parallel to the tip portion 86a on the −Z direction side of the tip portion 86a, and a rising portion that connects the tip portion 86a to the base portion 86b. The rising portion connects the +Y direction edge of the base portion 86b to the +Y direction edge of the tip portion 86a. Most of the base portion 86b of the second output terminal OUT2 and the rising portion are embedded within the end wall 68 and the terminal block 76. A comb-shaped terminal 86c that protrudes toward the inside of the case 63 is formed on the +X direction end of the base portion 86b.

[0076] The first source sense terminal SS1 is crank-shaped when viewed from the X direction, and its middle portion is embedded in the side wall 67. The base end of the first source sense terminal SS1 is disposed inside the case 63. The tip end of the first source sense terminal SS1 protrudes from the surface of the side wall 67 in the +Z direction.

[0077] The first gate terminals G1 are crank-shaped when viewed from the X direction, and their middle portions are embedded in the side walls 67. The base ends of the first gate terminals G1 are disposed inside the case 63. The tip ends of the first gate terminals G1 protrude from the surfaces of the side walls 67 in the +Z direction.

[0078] The second source sense terminals SS2 are crank-shaped when viewed from the X direction, and their middle portions are embedded in the side wall 66. The base ends of the second source sense terminals SS2 are disposed inside the case 63. The tip ends of the second source sense terminals SS2 protrude from the surface of the side wall 66 in the +Z direction.

[0079] The second gate terminals G2 are crank-shaped when viewed from the X direction, and their middle portions are embedded in the side wall 66. The base ends of the second gate terminals G2 are disposed inside the case 63. The tip ends of the second gate terminals G2 protrude from the surface of the side wall 66 in the +Z direction.

[0080] In the area surrounded by the frame portion 4 on the surface (+Z direction surface) of the heat sink 62, the first assembly 100 and the second assembly 200 are arranged side by side in the X direction. The first assembly 100 is arranged on the power supply terminals P and N side, and the second assembly 200 is arranged on the output terminal OUT side. The first assembly 100 constitutes half of the upper arm (high side) circuit and half of the lower arm (low side) circuit. The second assembly 200 constitutes the other half of the upper arm circuit and the other half of the lower arm circuit.

[0081] The first assembly 100 includes a first insulating substrate 101, a plurality of first switching elements Tr1, a plurality of first diode elements Di1, a plurality of second switching elements Tr2, and a plurality of second diode elements Di2.

[0082] The first insulating substrate 101 has a substantially rectangular shape in a plan view, and is bonded to the surface of the heat sink 62 with its four sides parallel to the four sides of the heat sink 62. A first bonding conductor layer 102 (see FIG. 8 ) is formed on the surface of the first insulating substrate 101 facing the heat sink 62 (the surface on the −Z direction side). The first bonding conductor layer 102 is bonded to the heat sink 62 via a solder layer 131.

[0083] A plurality of conductor layers for an upper arm circuit and a plurality of conductor layers for a lower arm circuit are formed on the surface (+Z direction surface) of the first insulating substrate 101 opposite to the heat sink 62. The plurality of conductor layers for the upper arm circuit include a first element junction conductor layer 103, a first gate terminal conductor layer 104, and a first source sense terminal conductor layer 105. The plurality of conductor layers for the lower arm circuit include a second element junction conductor layer 106, an N-terminal conductor layer 107, a second gate terminal conductor layer 108, and a second source sense terminal conductor layer 109.

[0084] In this embodiment, the first insulating substrate 101 is made of AlN. For example, a substrate in which copper foil is directly bonded to both sides of a ceramic (DBC: Direct Bonding Copper) can be used as the first insulating substrate 101. When a DBC substrate is used as the first insulating substrate 101, the conductor layers 102 to 109 can be formed from the copper foil.

[0085] The first element bonding conductor layer 103 is disposed near the side on the +Y direction side of the surface of the first insulating substrate 101, and has a rectangular shape that is long in the X direction in a planar view. The first element bonding conductor layer 103 has a protrusion that extends in the -Y direction at its +X direction end. The N-terminal conductor layer 107 is disposed near the side on the -Y direction side of the surface of the first insulating substrate 101, and has a rectangular shape that is long in the X direction in a planar view. The N-terminal conductor layer 107 has a protrusion that extends toward the protrusion of the first element bonding conductor layer 103 at its +X direction end. The second element bonding conductor layer 106 is disposed in a region surrounded by the first element bonding conductor layer 103, the N-terminal conductor layer 107, and the side on the -X direction side of the first insulating substrate 101 in a planar view, and has a rectangular shape that is long in the X direction in a planar view.

[0086] The first gate terminal conductor layer 104 is disposed between the first element bonding conductor layer 103 and the side of the first insulating substrate 101 on the +Y direction side, and has a rectangular shape that is elongated in the X direction in plan view. The first source sense terminal conductor layer 105 is disposed between the first gate terminal conductor layer 104 and the side of the first insulating substrate 101 on the +Y direction side, and has a rectangular shape that is elongated in the X direction in plan view.

[0087] The second gate terminal conductor layer 108 is disposed between the N-terminal conductor layer 107 and the side of the first insulating substrate 101 on the -Y direction side, and has a rectangular shape that is elongated in the X direction in plan view. The second source sense terminal conductor layer 109 is disposed between the second gate terminal conductor layer 108 and the side of the first insulating substrate 101 on the -Y direction side, and has a rectangular shape that is elongated in the X direction in plan view.

[0088] The comb-tooth-shaped terminal 83c of the first power supply terminal P is bonded to an end portion of the surface of the first element bonding conductor layer 103 on the +X direction side. The comb-tooth-shaped terminal 84c of the second power supply terminal N is bonded to an end portion of the surface of the N-terminal conductor layer 107 on the +X direction side. Because the terminal of the first power supply terminal P has a comb-tooth shape like the comb-tooth-shaped terminal 83c, when bonding the first power supply terminal P to the first element bonding conductor layer 103, for example, an ultrasonic bonding head can be pressed against the tip of the comb-tooth-shaped terminal 83c to easily ultrasonically bond the comb-tooth-shaped terminal 83c to the first element bonding conductor layer 103. Furthermore, because the terminal of the second power supply terminal N has a comb-tooth shape like the comb-tooth-shaped terminal 84c, when bonding the second power supply terminal N to the N-terminal conductor layer 107, for example, an ultrasonic bonding head can be pressed against the tip of the comb-tooth-shaped terminal 84c to easily ultrasonically bond the comb-tooth-shaped terminal 84c to the N-terminal conductor layer 107. A base end of the second gate terminal G2 is bonded to the second gate terminal conductor layer 108. A base end of the second source sense terminal SS2 is bonded to the second source sense terminal conductor layer 109. These bonds may be made by ultrasonic welding.

[0089] Drain electrodes of a plurality of first switching elements Tr1 are bonded to the surface of the first element bonding conductor layer 103 via a solder layer 132 (see FIG. 8 ), and cathode electrodes of a plurality of first diode elements Di1 are bonded to the surface of the first element bonding conductor layer 103 via a solder layer 133. Each first switching element Tr1 has a source electrode and a gate electrode on the surface opposite to the surface bonded to the first element bonding conductor layer 103. Each first diode element Di1 has an anode electrode on the surface opposite to the surface bonded to the first element bonding conductor layer 103.

[0090] Five first diode elements Di1 are arranged side by side at intervals in the X direction near the side on the +Y direction side of the surface of the first element bonding conductor layer 103. Furthermore, five first switching elements Tr1 are arranged side by side at intervals in the X direction between the side on the -Y direction side of the first element bonding conductor layer 93 and the five first diode elements Di1. The five first switching elements Tr1 are aligned with the five first diode elements Di1 in the Y direction.

[0091] The first switching element Tr1 and the first diode element Di1, which are aligned in the Y direction, are connected to the second element bonding conductor layer 106 by a first connecting metal member 110 extending substantially in the Y direction in a plan view. The first connecting metal member 110 has a base end joined to the second element bonding conductor layer 106 via solder 134 and a block-shaped rising portion whose tip extends in the +Z direction, and a plate-shaped horizontal portion extending from the tip of the rising portion in the +Y direction and disposed above the first switching element Tr1 and the first diode element Di1. The tip of the horizontal portion is joined to the anode electrode of the first diode element Di1 via solder 135, and an intermediate portion of the horizontal portion is joined to the source electrode of the first switching element Tr1 via solder 136. The width (length in the X direction) of the first connecting metal member 110 is shorter than the width (length in the X direction) of the first switching element Tr1. In plan view, the horizontal portion of the first connection metal member 110 passes through the middle of the width of the first switching element Tr1.

[0092] The gate electrode of each first switching element Tr1 is connected to the first gate terminal conductor layer 104 by a wire 111. Each first connecting metal member 110 is connected to the first source sense terminal conductor layer 105 by a wire 112. That is, the source electrode of each first switching element Tr1 is connected to the first source sense terminal conductor layer 105 via the solder 136, the first connecting metal member 110, and the wire 112.

[0093] Drain electrodes of multiple second switching elements Tr2 are bonded to the surface of the second element bonding conductor layer 106 via a solder layer 137 (see FIG. 8), and cathode electrodes of multiple second diode elements Di2 are bonded to the surface of the second element bonding conductor layer 106 via a solder layer 138. Each second switching element Tr2 has a source electrode and a gate electrode on the surface opposite to the surface bonded to the second element bonding conductor layer 106. Each second diode element Di2 has an anode electrode on the surface opposite to the surface bonded to the second element bonding conductor layer 106.

[0094] Five second switching elements Tr2 are arranged side by side at intervals in the X direction near the edge on the -Y direction side of the surface of the second element bonding conductor layer 106. Five second diode elements Di2 are arranged side by side at intervals in the X direction between the edge on the +Y direction side of the second element bonding conductor layer 106 and the five second switching elements Tr2. The five second diode elements Di2 are aligned with the five second switching elements Tr2 in the Y direction. The five second diode elements Di2 are also aligned with the five first switching elements Tr1 in the Y direction.

[0095] The second switching element Tr2 and the second diode element Di2, which are aligned in the Y direction, are connected to the N-terminal conductor layer 107 by a second connection metal member 120 extending substantially in the Y direction in plan view. The second connection metal member 120 has a base end joined to the N-terminal conductor layer 107 via solder 139, a block-shaped rising portion whose tip extends in the +Z direction, and a plate-shaped horizontal portion extending from the tip of the rising portion in the +Y direction and disposed above the second switching element Tr2 and the second diode element Di2. The tip of the horizontal portion is joined to the anode electrode of the second diode element Di2 via solder 140, and an intermediate portion of the horizontal portion is joined to the source electrode of the second switching element Tr2 via solder 141. The width (length in the X direction) of the second connection metal member 120 is shorter than the width (length in the X direction) of the second switching element Tr2. In plan view, the horizontal portion of the second connection metal member 120 passes through the middle portion of the width of the second switching element Tr2.

[0096] The gate electrode of each second switching element Tr2 is connected to the second gate terminal conductor layer 108 by a wire 121. The N-terminal conductor layer 107 is connected to the second source sense terminal conductor layer 109 by a wire 122. That is, the source electrode of each second switching element Tr2 is connected to the second source sense terminal conductor layer 109 via the solder 141, the second connecting metal member 120, the N-terminal conductor layer 107, and the wire 122.

[0097] The second assembly 200 includes a second insulating substrate 201, a plurality of third switching elements Tr3, a plurality of third diode elements Di3, a plurality of fourth switching elements Tr4, and a plurality of fourth diode elements Di4.

[0098] The second insulating substrate 201 has a substantially rectangular shape in a plan view, and is bonded to the surface of the heat sink 62 with its four sides parallel to the four sides of the heat sink 62. A second bonding conductor layer 202 (see FIG. 9) is formed on the surface of the second insulating substrate 201 facing the heat sink 62 (the surface on the -Z direction side). This second bonding conductor layer is bonded to the heat sink 62 via a solder layer 231.

[0099] A plurality of conductor layers for an upper arm circuit and a plurality of conductor layers for a lower arm circuit are formed on the surface (+Z direction surface) of second insulating substrate 201 opposite heat sink 62. The plurality of conductor layers for the upper arm circuit include a third element junction conductor layer 203, a third gate terminal conductor layer 204, and a third source sense terminal conductor layer 205. The plurality of conductor layers for the lower arm circuit include a fourth element junction conductor layer 206, a source conductor layer 207, a fourth gate terminal conductor layer 208, and a fourth source sense terminal conductor layer 209.

[0100] In this embodiment, second insulating substrate 201 is made of AlN. For example, a substrate in which copper foil is directly bonded to both sides of a ceramic (DBC: Direct Bonding Copper) can be used as second insulating substrate 201. When a DBC substrate is used as second insulating substrate 201, each of conductor layers 202 to 209 can be formed from the copper foil.

[0101] The third element bonding conductor layer 203 is disposed near the +Y side of the surface of the second insulating substrate 201 and has a rectangular shape elongated in the X direction in plan view. The third element bonding conductor layer 203 has a protrusion extending in the +Y direction at its -X side end. The source conductor layer 207 is disposed near the -Y side of the surface of the second insulating substrate 201 and has a rectangular shape elongated in the X direction in plan view. The fourth element bonding conductor layer 206 is T-shaped in plan view and is disposed between the third element bonding conductor layer 203 and the source conductor layer 207. The fourth element bonding conductor layer 206 includes a rectangular element bonding portion 206a elongated in the X direction in plan view and an output terminal bonding portion 206b extending along the -X side of the second insulating substrate 201. The -X side end of the element bonding portion 206a is connected to the longitudinal center of the output terminal bonding portion 206b.

[0102] The third gate terminal conductor layer 204 is disposed between the third element bonding conductor layer 203 and the side of the second insulating substrate 201 on the +Y direction side, and has a rectangular shape that is elongated in the X direction in plan view. The third source sense terminal conductor layer 205 is disposed between the third gate terminal conductor layer 204 and the side of the second insulating substrate 201 on the +Y direction side, and has a rectangular shape that is elongated in the X direction in plan view.

[0103] The fourth gate terminal conductor layer 208 is disposed between the source conductor layer 207 and the side of the second insulating substrate 201 on the -Y direction side, and has a rectangular shape that is elongated in the X direction in plan view. The fourth source sense terminal conductor layer 209 is disposed between the fourth gate terminal conductor layer 208 and the side of the second insulating substrate 201 on the -Y direction side, and has a rectangular shape that is elongated in the X direction in plan view.

[0104] The comb-tooth-shaped terminal 85c of the first output terminal OUT1 and the comb-tooth-shaped terminal 86c of the second output terminal OUT2 are bonded to the surface of the output terminal bond portion 206b of the fourth element bonding conductor layer 206. Because the terminal of the first output terminal OUT1 has a comb-tooth shape like the comb-tooth-shaped terminal 85c, when bonding the first output terminal OUT1 to the output terminal bond portion 206b, for example, an ultrasonic bonding head can be pressed against the tip of the comb-tooth-shaped terminal 85c to easily ultrasonically bond the comb-tooth-shaped terminal 85c to the output terminal bond portion 206b. Also, because the terminal of the second output terminal OUT2 has a comb-tooth shape like the comb-tooth-shaped terminal 86c, when bonding the second output terminal OUT2 to the output terminal bond portion 206b, for example, an ultrasonic bonding head can be pressed against the tip of the comb-tooth-shaped terminal 86c to easily ultrasonically bond the comb-tooth-shaped terminal 86c to the output terminal bond portion 206b. A base end of the first gate terminal G1 is bonded to the third gate terminal conductor layer 204. A base end of the first source sense terminal SS1 is bonded to the third source sense terminal conductor layer 205. These bonds may be made by ultrasonic welding.

[0105] Drain electrodes of multiple third switching elements Tr3 are bonded to the surface of the third element bonding conductor layer 203 via a solder layer 232 (see FIG. 9 ), and cathode electrodes of multiple third diode elements Di3 are bonded to the surface of the third element bonding conductor layer 203 via a solder layer 233. Each third switching element Tr3 has a source electrode and a gate electrode on the surface opposite to the surface bonded to the third element bonding conductor layer 203. Each third diode element Di3 has an anode electrode on the surface opposite to the surface bonded to the third element bonding conductor layer 203.

[0106] Five third diode elements Di3 are arranged side by side at intervals in the X direction near the side on the +Y direction side of the surface of the third element bonding conductor layer 203. Furthermore, five third switching elements Tr3 are arranged side by side at intervals in the X direction between the side on the -Y direction side of the third element bonding conductor layer 203 and the five third diode elements Di3. The five third switching elements Tr3 are aligned with the five third diode elements Di3 in the Y direction.

[0107] The third switching element Tr3 and the third diode element Di3, which are aligned in the Y direction, are connected to the fourth element bonding conductor layer 206 by a third connection metal member 210 extending substantially in the Y direction in plan view. The third connection metal member 210 has a base end joined to the fourth element bonding conductor layer 206 via solder 234 and a block-shaped rising portion whose tip extends in the +Z direction, and a plate-shaped horizontal portion extending from the tip of the rising portion in the +Y direction and positioned above the third switching element Tr3 and the third diode element Di3. The tip of the horizontal portion is joined to the anode electrode of the third diode element Di3 via solder 235, and an intermediate portion of the horizontal portion is joined to the source electrode of the third switching element Tr3 via solder 236. The width (length in the X direction) of the third connection metal member 210 is shorter than the width (length in the X direction) of the third switching element Tr3. In plan view, the horizontal portion of the third connection metal member 210 passes through the middle of the width of the third switching element Tr3.

[0108] The gate electrode of each third switching element Tr3 is connected to the third gate terminal conductor layer 204 by a wire 211. Each third connecting metal member 210 is connected to the third source sense terminal conductor layer 205 by a wire 212. That is, the source electrode of each third switching element Tr3 is connected to the third source sense terminal conductor layer 205 via the solder 236, the third connecting metal member 210, and the wire 212.

[0109] Drain electrodes of a plurality of fourth switching elements Tr4 are bonded to the surface of the fourth element bonding conductor layer 206 via a solder layer 237 (see FIG. 9 ), and cathode electrodes of a plurality of fourth diode elements Di4 are bonded to the surface of the fourth element bonding conductor layer 206 via a solder layer 238. Each fourth switching element Tr4 has a source electrode and a gate electrode on the surface opposite to the surface bonded to the fourth element bonding conductor layer 206. Each fourth diode element Di4 has an anode electrode on the surface opposite to the surface bonded to the fourth element bonding conductor layer 206.

[0110] Five fourth switching elements Tr4 are arranged side by side at intervals in the X direction near the edge on the -Y direction side of the surface of the fourth element bonding conductor layer 206. Five fourth diode elements Di4 are arranged side by side at intervals in the X direction between the edge on the +Y direction side of the fourth element bonding conductor layer 206 and the five fourth switching elements Tr4. The five fourth diode elements Di4 are aligned with the five fourth switching elements Tr4 in the Y direction. The five fourth diode elements Di4 are also aligned with the five third switching elements Tr3 in the Y direction.

[0111] The fourth switching element Tr4 and the fourth diode element Di4, which are aligned in the Y direction, are connected to the source conductor layer 207 by a fourth connection metal member 220 extending substantially in the Y direction in plan view. The fourth connection metal member 220 has a base end joined to the source conductor layer 207 via solder 239 and a block-shaped rising portion whose tip extends in the +Z direction, and a plate-shaped horizontal portion extending from the tip of the rising portion in the +Y direction and disposed above the fourth switching element Tr4 and the fourth diode element Di4. The tip of the horizontal portion is joined to the anode electrode of the fourth diode element Di4 via solder 240, and an intermediate portion of the horizontal portion is joined to the source electrode of the fourth switching element Tr4 via solder 241. The width (length in the X direction) of the fourth connection metal member 220 is shorter than the width (length in the X direction) of the fourth switching element Tr4. In plan view, the horizontal portion of the fourth connection metal member 220 passes through the middle portion of the width of the fourth switching element Tr4.

[0112] The gate electrode of each fourth switching element Tr4 is connected to the fourth gate terminal conductor layer 208 by a wire 221.

[0113] The third element bonding conductor layer 203 of the second assembly 200 is connected to the first element bonding conductor layer 103 of the first assembly 100 by a first conductor layer connecting member 91. The first conductor layer connecting member 91 is made of an H-shaped plate-like body in a plan view, and is composed of a pair of rectangular portions that straddle the third element bonding conductor layer 203 and the first element bonding conductor layer 103, and a connecting portion that connects the centers of these rectangular portions. Since the first element bonding conductor layer 103 and the third element bonding conductor layer 203 are connected by the first conductor layer connecting member 91, lower inductance can be achieved compared to, for example, connection by wire. Furthermore, since the first conductor layer connecting member 91 is H-shaped in a plan view and has comb-teeth-shaped terminals, for example, when joining the first conductor layer connecting member 91 to the first element joining conductor layer 103, an ultrasonic joining head can be pressed against the tip of the first conductor layer connecting member 91, and the first conductor layer connecting member 91 can be easily ultrasonically joined to the first element joining conductor layer 103.

[0114] The fourth element bonding conductor layer 206 of the second assembly 200 is connected to the second element bonding conductor layer 106 of the first assembly 100 by a second conductor layer connecting member 92. The second conductor layer connecting member 92 is made of an H-shaped plate-like body in a plan view, and is composed of a pair of rectangular portions that straddle the fourth element bonding conductor layer 206 and the second element bonding conductor layer 106, and a connecting portion that connects the centers of these rectangular portions. Because the second element bonding conductor layer 106 and the fourth element bonding conductor layer 206 are connected by the second conductor layer connecting member 92, lower inductance can be achieved compared to, for example, connection by wire. Furthermore, since the second conductor layer connecting member 92 is H-shaped in a plan view and has comb-teeth-shaped terminals, for example, when joining the second conductor layer connecting member 92 to the second element joining conductor layer 106, an ultrasonic joining head can be pressed against the tip of the second conductor layer connecting member 92, and the second conductor layer connecting member 92 can be easily ultrasonically joined to the second element joining conductor layer 106.

[0115] The source conductor layer 207 of the second assembly 200 is connected to the N-terminal conductor layer 107 of the first assembly 100 by a third conductor layer connecting member 93. The third conductor layer connecting member 93 is a plate-like body that is H-shaped in plan view and is composed of a pair of rectangular portions that straddle the source conductor layer 207 and the N-terminal conductor layer 107, and a connecting portion that connects the centers of these rectangular portions. Because the N-terminal conductor layer 107 and the source conductor layer 207 are connected by the third conductor layer connecting member 93, lower inductance can be achieved compared to, for example, connection by wire. Furthermore, because the third conductor layer connecting member 93 is H-shaped in plan view and has comb-shaped terminals, for example, when joining the third conductor layer connecting member 93 to the N-terminal conductor layer 107, the third conductor layer connecting member 93 can be easily ultrasonically joined to the N-terminal conductor layer 107 by pressing an ultrasonic bonding head against the tip of the third conductor layer connecting member 93.

[0116] The third gate terminal conductor layer 204 of the second assembly 200 is connected to the first gate terminal conductor layer 104 of the first assembly 100 via a wire 94. The third source sense terminal conductor layer 205 of the second assembly 200 is connected to the first source sense terminal conductor layer 105 of the first assembly 100 via a wire 95.

[0117] The fourth gate terminal conductor layer 208 of the second assembly 200 is connected to the second gate terminal conductor layer 108 of the first assembly 100 via a wire 96 .

[0118] Fig. 10 is an electric circuit diagram for explaining the electrical configuration of the semiconductor module 61. In Fig. 10, two output terminals OUT1 and OUT2 are shown as one output terminal OUT.

[0119] The plurality of first switching elements Tr1 and the plurality of first diode elements Di1 provided in the first assembly 100 and the plurality of third switching elements Tr3 and the plurality of third diode elements Di3 provided in the second assembly 200 are connected in parallel between the first power supply terminal P and the output terminal OUT to form an upper arm circuit (high side circuit) 301. The plurality of second switching elements Tr2 and the plurality of second diode elements Di2 provided in the first assembly 100 and the plurality of fourth switching elements Tr4 and the plurality of fourth diode elements Di4 provided in the second assembly 200 are connected between the output terminal OUT and the second power supply terminal N to form a lower arm circuit (low side circuit) 302.

[0120] The upper arm circuit 301 and the lower arm circuit 302 are connected in series between the first power supply terminal P and the second power supply terminal N, and an output terminal OUT is connected to a connection point 303 between the upper arm circuit 301 and the lower arm circuit 302. A half-bridge circuit is configured in this manner. This half-bridge circuit can be used as a single-phase bridge circuit. Furthermore, by connecting multiple (e.g., three) half-bridge circuits (semiconductor modules 1) in parallel to a power supply, a multi-phase (e.g., three-phase) bridge circuit can be configured.

[0121] In this embodiment, the first to fourth switching elements Tr1 to Tr4 are configured by N-channel type DMOS (Double-Diffused Metal Oxide Semiconductor) field effect transistors. In particular, in this embodiment, the first to fourth switching elements Tr1 to Tr4 are high-speed switching MOSFETs (SiC-DMOS) configured by SiC semiconductor devices.

[0122] In this embodiment, the first to fourth diode elements Di1 to Di4 are configured by Schottky barrier diodes (SBDs). Particularly, in this embodiment, the first to fourth diode elements Di1 to Di4 are configured by SiC semiconductor devices (SiC-SBDs).

[0123] A first diode element Di1 is connected in parallel to each first switching element Tr1. A third diode element Di3 is connected in parallel to each third switching element Tr3. The drains of each first switching element Tr1 and each third switching element Tr3 and the cathodes of each first diode element Di1 and each third diode element Di3 are connected to a first power supply terminal P.

[0124] The anodes of the first diode elements Di1 are connected to the sources of the corresponding first switching elements Tr1, and the sources of the first switching elements Tr1 are connected to the output terminal OUT. Similarly, the anodes of the third diode elements Di3 are connected to the sources of the corresponding third switching elements Tr3, and the sources of the third switching elements Tr3 are connected to the output terminal OUT.

[0125] The gates of the plurality of first diode elements Di1 and the plurality of third diode elements Di3 are connected to the first gate terminal G1, and the sources of the plurality of first switching elements Tr1 and the plurality of third switching elements Tr3 are also connected to the first source sense terminal SS1.

[0126] The source of the first switching element Tr1 is connected to the first source sense terminal SS1 via solder 136, the first connecting metal member 110, the wire 112, the first source sense terminal conductor layer 105, the wire 95, and the third source sense terminal conductor layer 205. Therefore, between the source of the first switching element Tr1 and the first source sense terminal SS1, there is a wiring resistance including a resistance (external resistance) R1 that is parasitic on the current path formed by the solder 136 and the first connecting metal member 110. In this embodiment, the wiring resistance between the source of the first switching element Tr1 and the first source sense terminal SS1 is larger by the amount of the external resistance R1 than when one end of the wire 112 is directly connected to the source of the first switching element Tr1.

[0127] Furthermore, the source of the third switching element Tr3 is connected to the first source sense terminal SS1 via the solder 236, the third connecting metal member 210, the wire 212, and the third source sense terminal conductor layer 205. Therefore, between the source of the third switching element Tr3 and the first source sense terminal SS1, there is a wiring resistance including a resistance (external resistance) R3 that is parasitic on the current path formed by the solder 236 and the third connecting metal member 210. In this embodiment, the wiring resistance between the source of the third switching element Tr3 and the first source sense terminal SS1 is larger by the amount of the external resistance R3 than when one end of the wire 212 is directly connected to the source of the third switching element Tr3.

[0128] A second diode element Di2 is connected in parallel to each second switching element Tr2. A fourth diode element Di4 is connected in parallel to each fourth switching element Tr4. The drains of each second switching element Tr2 and each fourth switching element Tr4 and the cathodes of each second diode element Di2 and each fourth diode element Di4 are connected to the output terminal OUT.

[0129] The anodes of the plurality of second diode elements Di2 are connected to the sources of the corresponding second switching elements Tr2, and the sources of the second switching elements Tr2 are connected to the second power supply terminal N. Similarly, the anodes of the plurality of fourth diode elements Di4 are connected to the sources of the corresponding fourth switching elements Tr4, and the sources of the fourth switching elements Tr4 are connected to the second power supply terminal N.

[0130] The gates of the second diode elements Di2 and the fourth diode elements Di4 are connected to the second gate terminal G2. The sources of the second switching elements Tr2 and the fourth switching elements Tr4 are also connected to the second source sense terminal SS2.

[0131] The source of the second switching element Tr2 is connected to the second source sense terminal SS2 via solder 141, the second connecting metal member 120, the N-terminal conductor layer 107, the wire 122, and the second source sense terminal conductor layer 109. Therefore, between the source of the second switching element Tr2 and the second source sense terminal SS2, there is a wiring resistance including a resistance (external resistance) R2 that is parasitic on the current path formed by the solder 141, the second connecting metal member 120, and the N-terminal conductor layer 107. In this embodiment, the wiring resistance between the source of the second switching element Tr2 and the second source sense terminal SS2 is larger by the amount of the external resistance R2 than when one end of the wire 212 is directly connected to the source of the second switching element Tr2.

[0132] The source of the fourth switching element Tr4 is connected to the second source sense terminal SS2 via solder 241, the fourth connecting metal member 220, the source conductor layer 207, the third conductor layer connecting member 93, the N-terminal conductor layer 107, the wire 122, and the second source sense terminal conductor layer 109. Therefore, between the source of the fourth switching element Tr4 and the fourth source sense terminal SS2, there is a wiring resistance including a resistance (external resistance) R4 that is parasitic on the current path formed by the solder 241, the fourth connecting metal member 220, the third conductor layer connecting member 93, and the N-terminal conductor layer 107. In this embodiment, the wiring resistance between the source of the fourth switching element Tr4 and the second source sense terminal SS2 is larger by the amount of the external resistance R4 than when the source of the fourth switching element Tr4 and the second source sense terminal conductor layer 109 are directly connected by a wire.

[0133] Instead of connecting the N-terminal conductor layer 107 to the second source sense terminal conductor layer 109 by the wire 122, each second connecting metal member 120 may be connected to the second source sense terminal conductor layer 109 by a wire 122A, as shown by the two-dot chain line in Fig. 8. In this case, each fourth connecting metal member 220 may be connected to the fourth source sense terminal conductor layer 209 by a wire 122B, and the fourth source sense terminal conductor layer 209 may be connected to the second source sense terminal conductor layer 109 by a wire (not shown), as shown by the two-dot chain line in Fig. 9.

[0134] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited only by the appended claims.

[0135] This application corresponds to Patent Application No. 2013-240105 filed with the Japan Patent Office on November 20, 2013, the entire disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0136] 1. Switching Devices 2. Resin package 3 Source terminal 4 Sense source terminal 5 Gate terminal 6 Drain terminal 11 Semiconductor chips 12 Drain Pad 13 Saucepad 14 Gate Pad 16 Source wires 17 Sense source wire 19 MOSFET 22, R1~R4 external resistors 31 Inverter circuit 32 First Switching Device 33 Second Switching Device 34 Third Switching Device 35 The Fourth Switching Device 40 Control Unit 41 Power supply 42 Load 51 Amplification circuit 52 First switching circuit 53 Gate resistor 54 Second switching circuit 55 Current interruption resistance 56 Overcurrent detection circuit 57 Current detection resistor 58 Comparison circuit 59 Voltage monitoring unit 61 Semiconductor Module Tr1~Tr4 switching elements Di1~Di4 Di1~Di4

Claims

1. a SiC switching element having a gate electrode, a source electrode, and a drain electrode; a source terminal electrically connected to the source electrode and outputting a current that flows when the source electrode is turned on; a single sense source terminal electrically connected to the source electrode; a conductive member having a resistance; a resin package that seals the SiC switching element, the single sense / source terminal, and the conductive member; an island separately provided within the resin package, the conductive member is connected to the source terminal and the source electrode, and is interposed in a current path between the single sense source terminal and the source electrode; the single sense-source terminal and the source electrode are not directly connected to each other, but the single sense-source terminal and the source electrode are electrically connected to each other via a conductor and the island as a relay point; A switching device having no wire directly connecting the single sense source terminal and the SiC switching element.

2. a gate terminal electrically connected to the gate electrode; a drain terminal electrically connected to the drain electrode; 2. The switching device according to claim 1, wherein a portion of a terminal portion of the source terminal, a portion of the single sense source terminal, a portion of the gate terminal, and a portion of a terminal portion of the drain terminal are each exposed from the resin package.

3. The switching device of claim 1 , wherein the conductor comprises a bond wire.

4. The switching device according to claim 3 , wherein the single sense source terminal and the source electrode are connected by at least two wires, with the island as a relay point.

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