Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing an increase in chip area due to an increase in the width of a conductor located in the uppermost layer of a seal ring.SOLUTION: The semiconductor device includes a semiconductor substrate and a seal ring. The seal ring is formed on the outer peripheral portion of the semiconductor substrate in plan view. The seal ring includes a plurality of conductors stacked on each other. Each of the plurality of conductors has an inner peripheral edge and an outer peripheral edge. An inner peripheral edge of a first conductor located in an uppermost layer among the plurality of conductors is located inside all inner peripheral edges of a plurality of second conductors located in a layer lower than the first conductor among the plurality of conductors in a plan view.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] The semiconductor device described in JP 2019-114673 A (Patent Document 1) has a semiconductor substrate, a seal ring formed on the outer periphery of the semiconductor substrate, a passivation film, and a polyimide film. The seal ring has a plurality of conductors and a plurality of plugs. The plurality of conductors are stacked. Each of the plurality of plugs connects two adjacent conductors. However, one of the plurality of plugs connects the conductor located in the bottom layer to the semiconductor substrate. The passivation film covers the conductor located in the top layer. The polyimide film is formed on the passivation film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-114673 Summary of the Invention [Problem to be solved by the invention]

[0004] As the thickness of the conductor located in the top layer increases, the adhesion of the polyimide film decreases. Therefore, when increasing the thickness of the conductor located in the top layer, it is necessary to increase the width of the conductor located in the top layer to ensure adhesion of the polyimide film. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a semiconductor substrate and a seal ring. The seal ring is formed on the outer periphery of the semiconductor substrate in a plan view. The seal ring has a plurality of conductors stacked on top of one another. Each of the plurality of conductors has an inner peripheral edge and an outer peripheral edge. In a plan view, the inner peripheral edge of a first conductor located in the uppermost layer of the plurality of conductors is located inside any of the inner peripheral edges of a plurality of second conductors located in a layer below the first conductor. [Effects of the Invention]

[0006] According to the semiconductor device of the present disclosure, it is possible to prevent the chip area from increasing as the width of the first conductor increases. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a plan view of the semiconductor device DEV1. [Figure 2] FIG. 2 is a cross-sectional view of the semiconductor device DEV1 taken along line II-II in FIG. [Figure 3] 10A to 10C are manufacturing process diagrams of the semiconductor device DEV1. [Figure 4] FIG. 10 is a cross-sectional view illustrating an ion implantation step S2. [Figure 5] FIG. 10 is a cross-sectional view illustrating an element isolation film forming step S3. [Figure 6] FIG. 10 is a cross-sectional view illustrating a gate insulating film forming step S4. [Figure 7] FIG. 10 is a cross-sectional view illustrating a gate electrode forming step S5. [Figure 8] FIG. 10 is a cross-sectional view illustrating an ion implantation step S6. [Figure 9] FIG. 10 is a cross-sectional view illustrating a sidewall spacer forming step S7. [Figure 10] FIG. 10 is a cross-sectional view illustrating an ion implantation step S8. [Figure 11] FIG. 10 is a cross-sectional view illustrating an interlayer insulating film forming step S9. [Figure 12] FIG. 10 is a cross-sectional view illustrating a plug forming step S10. [Figure 13]FIG. 10 is a cross-sectional view illustrating a wiring formation step S11. [Figure 14] FIG. 10 is a cross-sectional view illustrating a passivation film forming step S12. [Figure 15] FIG. 10 is a cross-sectional view illustrating a polyimide film forming step S13. [Figure 16] FIG. 10 is a cross-sectional view illustrating a wiring formation step S14. [Figure 17] FIG. 10 is a cross-sectional view of a semiconductor device DEV1 according to a first modification. [Figure 18] FIG. 10 is a cross-sectional view of a semiconductor device DEV1 according to a second modification. [Figure 19] FIG. 11 is a plan view of a semiconductor device DEV1 according to a third modification. [Figure 20] 20 is a cross-sectional view of the semiconductor device DEV1 according to Modification 3 taken along the line XX-XX in FIG. 19. [Figure 21] FIG. 21 is a cross-sectional view of the semiconductor device DEV1 according to Modification 3 taken along the line XXI-XXI in FIG. 20. [Figure 22] FIG. 2 is a cross-sectional view of the semiconductor device DEV2. [Figure 23] 23 is a cross-sectional view of the semiconductor device DEV2 taken along the line XXIII-XXIII in FIG. 22. [Figure 24] FIG. 10 is a cross-sectional view of a semiconductor device DEV2 according to a modified example. [Figure 25] FIG. 25 is a cross-sectional view of a semiconductor device DEV2 according to a modified example taken along the line XXV-XXV in FIG. 24. DETAILED DESCRIPTION OF THE INVENTION

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present disclosure will be described with reference to the accompanying drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant descriptions will not be repeated.

[0009] (First embodiment) The semiconductor device DEV1 according to the first embodiment will be described.

[0010] <Configuration of semiconductor device DEV1> 1 and 2, the semiconductor device DEV1 has a semiconductor substrate SUB. The semiconductor substrate SUB has a peripheral portion PER in a plan view. The semiconductor substrate SUB has an upper surface F1 and a lower surface F2 located on the opposite side of the upper surface F1. The semiconductor substrate SUB is formed of, for example, single crystal silicon.

[0011] A source layer SL, a drain layer DL, and a well layer WE are formed in the semiconductor substrate SUB. The source layer SL and the drain layer DL are located on a top surface F1 with a gap between them. The well layer WE is located on the top surface F1 so as to surround the source layer SL and the drain layer DL. The conductivity type of the source layer SL and the drain layer DL is opposite to the conductivity type of the well layer WE. For example, the conductivity type of the source layer SL and the drain layer DL is n-type, and the conductivity type of the well layer WE is p-type.

[0012] The source layer SL has a first portion SL1 and a second portion SL2. The first portion SL1 is located between the second portion SL2 and the drain layer DL. The drain layer DL has a first portion DL1 and a second portion DL2. The first portion DL1 is located between the second portion DL2 and the source layer SL. The dopant concentration in the first portion SL1 is lower than the dopant concentration in the second portion SL2, and the dopant concentration in the first portion DL1 is lower than the dopant concentration in the second portion DL2. That is, the source layer SL and the drain layer DL have an LDD (Lightly Doped Diffusion) structure.

[0013] The semiconductor device DEV1 further has a gate insulating film GI. The gate insulating film GI is formed on an upper surface F1 located between the source layer SL and the drain layer DL. The gate insulating film GI is made of, for example, silicon oxide. The semiconductor device DEV1 further has a gate electrode GE. The gate electrode GE is formed on the gate insulating film GI. The gate electrode GE is made of, for example, polycrystalline silicon containing a dopant. The source layer SL, the drain layer DL, the well layer WE, the gate insulating film GI, and the gate electrode GE constitute a transistor.

[0014] The semiconductor device DEV1 further includes sidewall spacers SWS. The sidewall spacers SWS are formed on the first portions SL1 and DL1 so as to contact the side surfaces of the gate insulating film GI and the gate electrode GE. The sidewall spacers SWS are made of, for example, silicon nitride.

[0015] A trench TR is formed in the upper surface F1. The trench TR extends from the upper surface F1 toward the lower surface F2. The trench TR surrounds the transistor in a plan view. The semiconductor device DEV1 further has an element isolation film ISL. The element isolation film ISL is formed in the trench TR. This electrically isolates the transistor from other elements. The element isolation film ISL is formed of, for example, silicon oxide.

[0016] The semiconductor device DEV1 further has an interlayer insulating film ILD1. The interlayer insulating film ILD1 is formed on the upper surface F1 so as to cover the gate electrode GE, the sidewall spacers SWS, and the element isolation film ISL. The interlayer insulating film ILD1 is made of, for example, silicon oxide. The semiconductor device DEV1 further has an interlayer insulating film ILD2 and an interlayer insulating film ILD3. The interlayer insulating film ILD2 is formed on the interlayer insulating film ILD1, and the interlayer insulating film ILD3 is formed on the interlayer insulating film ILD2. The interlayer insulating films ILD2 and ILD3 are made of, for example, silicon oxide.

[0017] The semiconductor device DEV1 further includes interconnects WL1a, WL1b, and WL1c. The interconnects WL1a, WL1b, and WL1c are formed on an interlayer insulating film ILD1 and covered with an interlayer insulating film ILD2. The interconnects WL1a, WL1b, and WL1c are made of, for example, aluminum or an aluminum alloy. The semiconductor device DEV2 further includes plugs PG1a, PG1b, and PG1c. The plugs PG1a, PG1b, and PG1c are formed in the interlayer insulating film ILD1. The plug PG1a electrically connects the interconnect WL1a to the source layer SL. The plug PG1b electrically connects the interconnect WL1b to the drain layer DL. The plug PG1c electrically connects the interconnect WL1c to the gate electrode GE. The plugs PG1a, PG1b, and PG1c are made of, for example, tungsten.

[0018] The semiconductor device DEV1 further includes a wiring WL2a. The wiring WL2a is formed on an interlayer insulating film ILD2 and covered with an interlayer insulating film ILD3. The wiring WL2a is made of, for example, aluminum or an aluminum alloy. The semiconductor device DEV1 further includes a plug PG2a. The plug PG2a is formed in the interlayer insulating film ILD2. The plug PG2a electrically connects the wiring WL2a and the wiring WL1c. The plug PG2a is made of, for example, tungsten.

[0019] The semiconductor device DEV1 further includes a wiring WL3a. The wiring WL3a is formed on an interlayer insulating film ILD3. The wiring WL3a is made of, for example, aluminum or an aluminum alloy. The semiconductor device DEV1 further includes a plug PG3a. The plug PG3a is formed in the interlayer insulating film ILD3. The plug PG3a electrically connects the wiring WL3a and the wiring WL2a. The plug PG3a is made of, for example, tungsten.

[0020] The semiconductor device DEV1 further includes a seal ring SR. The seal ring SR is formed on an outer periphery portion PER. The seal ring SR is formed around the entire periphery of the outer periphery portion PER in a plan view. The seal ring SR includes a conductor CN1, a conductor CN2, a conductor CN3, and a plug PG1d, a plug PG2b, and a plug PG3b.

[0021] The conductor CN1 is formed on the interlayer insulating film ILD1 and is covered with the interlayer insulating film ILD2. The conductor CN2 is formed on the interlayer insulating film ILD2 and is covered with the interlayer insulating film ILD3. The conductor CN3 is formed on the interlayer insulating film ILD3. From another perspective, the conductor CN1 is formed in the same layer as the wiring WL1a, wiring WL1b, and wiring WL1c, the conductor CN2 is formed in the same layer as the wiring WL2a, and the conductor CN3 is formed in the same layer as the wiring WL3a. The conductors CN1, CN2, and CN3 are formed of, for example, aluminum or an aluminum alloy.

[0022] The plug PG1d is formed in the interlayer insulating film ILD1 and connects the conductor CN1 to the upper surface F1. The plug PG2b is formed in the interlayer insulating film ILD2 and connects the conductor CN2 to the conductor CN1. The plug PG3b is formed in the interlayer insulating film ILD3 and connects the conductor CN3 to the conductor CN2. The plugs PG1d, PG2b, and PG3b are made of, for example, tungsten.

[0023] The inner peripheral edge of the conductor CN3 is located inside both the inner peripheral edge of the conductor CN2 and the inner peripheral edge of the conductor CN1 in a planar view. The outer peripheral edge of the conductor CN3 overlaps both the outer peripheral edge of the conductor CN2 and the outer peripheral edge of the conductor CN1 in a planar view, for example. The source layer SL, the gate insulating film GI, and the gate electrode GE overlap with the conductor CN3 in a planar view. That is, it is sufficient that at least a portion of the above-mentioned transistor overlaps with the conductor CN3 in a planar view.

[0024] The thickness of the conductor CN3 is defined as thickness T. The width of the conductor CN3, i.e., the distance between the inner peripheral edge of the conductor CN3 and the outer peripheral edge of the conductor CN3, is defined as width W. The thickness T is, for example, 3 μm or more. The thickness T is, for example, 5 μm or less. The width W is, for example, 10 μm or more. The width W is, for example, 20 μm or less.

[0025] The semiconductor device DEV1 further includes a passivation film PV. The passivation film PV is formed on the interlayer insulating film ILD3 so as to cover the wiring WL3a and the conductor CN3. The passivation film PV is made of, for example, silicon nitride.

[0026] The semiconductor device DEV1 further includes a polyimide film PID1. The polyimide film PID1 is formed on the passivation film PV. An end (outer periphery) of the polyimide film PID1 overlaps the conductor CN3 in plan view. The end of the polyimide film PID1 is located inside the outer periphery of the conductor CN3 in plan view. The semiconductor device DEV1 includes a wiring WL4a. The wiring WL4a is formed on the polyimide film PID1. An opening OP is formed in the polyimide film PID1 and the passivation film PV. The wiring WL3a is exposed from the opening OP. The wiring WL4a is also formed in the opening OP. This electrically connects the wiring WL4a and the wiring WL3a. The wiring WL4a is made of, for example, copper or a copper alloy. The semiconductor device DEV1 further includes a polyimide film PID2. The polyimide film PID2 is formed on the polyimide film PID1 so as to cover the wiring WL4a.

[0027] <Method of Manufacturing Semiconductor Device DEV1> 3, the method for manufacturing the semiconductor device DEV1 includes a preparation step S1, an ion implantation step S2, an element isolation film formation step S3, a gate insulating film formation step S4, a gate electrode formation step S5, an ion implantation step S6, a sidewall spacer formation step S7, and an ion implantation step S8. The method for manufacturing the semiconductor device DEV1 further includes an interlayer insulating film formation step S9, a plug formation step S10, a wiring formation step S11, a passivation film formation step S12, a polyimide film formation step S13, a wiring formation step S14, a polyimide film formation step S15, and a dicing step S16.

[0028] In the preparation step S1, a semiconductor substrate SUB is prepared. As shown in Fig. 4, in the ion implantation step S2, ions are implanted to form a well layer WE in the semiconductor substrate SUB.

[0029] As shown in FIG. 5, in the element isolation film forming step S3, a trench TR and an element isolation film ISL are formed. In the element isolation film forming step S3, first, a hard mask is formed on the upper surface F1. Second, the upper surface F1 is etched using the hard mask to form the trench TR. Third, by, for example, a CVD (Chemical Vapor Deposition) method, a constituent material of the element isolation film ISL is embedded in the trench TR and formed on the upper surface F1. Fourth, the constituent material of the element isolation film ISL formed outside the trench TR is removed by, for example, a CMP method or etch-back. As a result, the element isolation film ISL is formed in the TR.

[0030] As shown in Fig. 6, in the gate insulating film forming step S4, a gate insulating film GI is formed on the upper surface F1 by, for example, thermal oxidation. As shown in Fig. 7, in the gate electrode forming step S5, a gate electrode GE is formed on the gate insulating film GI. In the gate electrode forming step S5, first, a constituent material of the gate electrode GE is formed on the gate insulating film GI by, for example, a CVD method. Second, a resist pattern is formed on the constituent material of the gate electrode GE. Third, the constituent material of the gate electrode GE is patterned using the resist pattern, thereby forming the gate electrode GE.

[0031] As shown in Fig. 8, in the ion implantation step S6, ion implantation is performed to form first portions SL1 and DL1 in the semiconductor substrate SUB. As shown in Fig. 9, in the sidewall spacer formation step S7, sidewall spacers SWS are formed on the upper surface F1 so as to contact the side surfaces of the gate insulating film GI and the gate electrode GE. In the sidewall spacer formation step S7, first, a constituent material of the sidewall spacers SWS is formed on the upper surface F1 by, for example, a CVD method so as to cover the gate insulating film GI, the gate electrode GE, and the element isolation film ISL. Second, the constituent material of the sidewall spacers SWS is etched back. In this manner, the sidewall spacers SWS are formed.

[0032] 10, in the ion implantation step S8, ion implantation is performed to form second portions SL2 and DL2 in the semiconductor substrate SUB. As shown in FIG. 11, in the interlayer insulating film formation step S9, an interlayer insulating film ILD1 is formed on the upper surface F1 so as to cover the sidewall spacers SWS, the element isolation film ISL, and the gate electrode GE. In the interlayer insulating film formation step S9, first, the interlayer insulating film ILD1 is formed on the upper surface F1 by, for example, a CVD method so as to cover the sidewall spacers SWS, the element isolation film ISL, and the gate electrode GE. Second, the upper surface of the interlayer insulating film ILD1 is planarized by, for example, a CMP method.

[0033] As shown in FIG. 12, in the plug formation step S10, plugs PG1a, PG1b, PG1c, and PG1d are formed in the interlayer insulating film ILD1. In the plug formation step S10, first, a resist pattern is formed on the interlayer insulating film ILD1. Second, the interlayer insulating film ILD1 is etched using the resist pattern to form a plurality of through holes in the interlayer insulating film ILD1. Third, by, for example, a CVD method, constituent materials such as the plugs PG1a are embedded in each of the plurality of through holes formed in the interlayer insulating film ILD and are formed on the interlayer insulating film ILD1. Fourth, constituent materials such as the plugs PG1a formed outside the plurality of through holes formed in the interlayer insulating film ILD are removed by, for example, a CMP method. As a result of the above, the plugs PG1a, PG1b, PG1c, and PG1d are formed in the interlayer insulating film ILD1.

[0034] 13, in the interconnect formation step S11, interconnects WL1a, WL1b, WL1c, and a conductor CN1 are formed on the interlayer insulating film ILD1. In the interconnect formation step S11, first, constituent materials for the interconnect WL1a and the like are formed on the interlayer insulating film ILD1 by, for example, sputtering. Second, a resist pattern is formed on the constituent materials for the interconnect WL1a and the like. Third, the constituent materials for the interconnect WL1a and the like are etched using the resist pattern, thereby patterning the constituent materials for the interconnect WL1a and the like to form WL1a, the interconnect WL1b, the interconnect WL1c, and the conductor CN1. Thereafter, steps similar to the interlayer insulating film formation step S9, the plug formation step S10, and the interconnect formation step S11 are sequentially repeated to form the interlayer insulating film ILD2, the plugs PG2a, PG2b, the interconnect WL2a, the conductor CN2, the interlayer insulating film ILD3, the plugs PG3a, PG3b, the interconnect WL3a, and the conductor CN3.

[0035] 14, in the passivation film formation step S12, a material for the passivation film PV is formed on the interlayer insulating film ILD3 so as to cover the wiring WL3a and the conductor CN3. In the passivation film formation step S12, first, a material for the passivation film PV is formed on the interlayer insulating film ILD3 by, for example, a CVD method so as to cover the wiring WL3a and the conductor CN3. Second, a resist pattern is formed on the passivation film PV. Third, the material for the passivation film PV is etched using the resist pattern, thereby patterning the material for the passivation film PV and forming the passivation film PV.

[0036] 15, in the polyimide film formation step S13, a polyimide film PID1 is formed on the passivation film PV. In the polyimide film formation step S13, a constituent material of the polyimide film PID1 is applied onto the passivation film PV. Secondly, the constituent material of the polyimide film PID1 is exposed to light and developed, thereby patterning the constituent material of the polyimide film PID1 and forming the polyimide film PID1.

[0037] As shown in FIG. 16, in the wiring formation step S14, the wiring WL4a is formed on the polyimide film PID1 so as to be electrically connected to the wiring WL3a. In the wiring formation step S14, first, a seed layer is formed on the polyimide film PID1, on the inner wall surface of the opening OP, and on the wiring WL3a exposed from the opening OP, for example, by sputtering. Second, a resist pattern is formed on the seed layer. Third, electrolytic plating is performed, so that the constituent material of the wiring WL4a grows from the seed layer exposed from the opening of the resist pattern. Fourth, the seed layer that was under the resist pattern is removed by etching. In this manner, the wiring WL4a is formed.

[0038] In the polyimide film forming step S15, a step similar to the polyimide film forming step S13 is performed to form a polyimide film PID2 so as to cover the wiring WL4a. In the dicing step S16, the semiconductor substrate SUB, the interlayer insulating films ILD1, ILD2, and ILD3 are cut along scribe lines. In this manner, the structure of the semiconductor device DEV1 shown in FIGS. 1 and 2 is formed.

[0039] <Variation 1> 17, in the semiconductor device DEV1, a resistor element RE may be formed on an isolation film ISL overlapping with the conductor CN3 in a plan view. The resistor element RE is formed of, for example, polycrystalline silicon containing a dopant. The resistor element RE is formed in the same process as the gate electrode GE. In this way, in the semiconductor device DEV1, the circuit element formed to overlap with the conductor CN3 in a plan view may be a passive element such as the resistor element RE, rather than an active element such as a transistor.

[0040] <Variation 2> 18, in the semiconductor device DEV1, an isolation layer SPL is formed in the semiconductor substrate SUB. The isolation layer SPL is an impurity layer into which a dopant is introduced, and the isolation layer SPL electrically isolates a portion of the semiconductor substrate SUB located between the isolation layer SPL and the upper surface F1 from a portion of the semiconductor substrate SUB located between the isolation layer SPL and the lower surface F2.

[0041] In the semiconductor device DEV1, a hole HL1 is formed in the element isolation film ISL and the semiconductor substrate SUB. The hole HL1 penetrates the element isolation film ISL and reaches a portion of the semiconductor substrate SUB located between the isolation layer SPL and the lower surface F2. An insulating film IF is formed in the hole HL1. In the semiconductor device DEV1, a hole HL2 is formed in the insulating film IF and the semiconductor substrate SUB. The hole HL2 penetrates the insulating film IF and reaches a portion of the semiconductor substrate SUB located between the isolation layer SPL and the lower surface F2. A plug PG4 is formed in the hole HL2. The plug PG4 overlaps the conductor CN3 in a plan view. The plug PG4 is made of, for example, polycrystalline silicon containing a dopant. The plug PG4 is electrically connected to a portion of the semiconductor substrate SUB located between the isolation layer SPL and the lower surface F2, while being electrically insulated from a portion of the semiconductor substrate SUB located between the isolation layer SPL and the upper surface F1. This allows the potential of the portion of the semiconductor substrate SUB located between the isolation layer SPL and the lower surface F2 to be fixed. In this way, in the semiconductor device DEV1, a structure other than a circuit element may be formed at a position overlapping with the conductor CN3 in a plan view. Note that as a structure other than a circuit element, for example, a dummy pattern may be formed at a position overlapping with the conductor CN3 in a plan view.

[0042] <Variation 3> 19, 20, and 21, in the semiconductor device DEV1, a resistor chain RCH may be formed so as to overlap with the conductor CN3 in a plan view. The resistor chain RCH has a plurality of wirings WL2b, a plurality of wirings WL1d, a plurality of plugs PG2c, and a plurality of plugs PG2d. For example, the resistor chain RCH is formed around the entire periphery of the outer periphery portion PER in a plan view.

[0043] The multiple wirings WL2b are formed in the same layer. More specifically, the multiple wirings WL2b are formed in the same layer as the wirings WL2a. The multiple wirings WL1d are formed in the same layer. More specifically, the multiple wirings WL1d are formed in the same layer as the wirings WL1a, WL1b, and WL1c. The multiple wirings WL2b and the multiple wirings WL1d are made of, for example, aluminum or an aluminum alloy. From another perspective, the multiple wirings WL1d are formed in the same process as the wirings WL1a, WL1b, and WL1c, and the wiring WL2b is formed in the same process as the wirings WL2a.

[0044] The multiple wirings WL2b are arranged at intervals along the outer periphery PER in a plan view, and the multiple wirings WL1d are arranged at intervals along the outer periphery PER in a plan view. Each of the multiple wirings WL2b has an end WL2ba and an end WL2bb. Each of the multiple wirings WL1d has an end WL1da and an end WL1db. In a plan view, the end WL2ba of one of two adjacent wirings WL2b overlaps the end WL1da of one wiring WL1d, and the end WL2bb of the other of the two adjacent wirings WL2b overlaps the end WL1db of that one wiring WL1d.

[0045] The plurality of plugs PG2c and the plurality of plugs PG2d are formed in the interlayer insulating film ILD2. The plurality of plugs PG2c and the plurality of plugs PG2d are formed of, for example, tungsten. From another perspective, the plurality of plugs PG2c and the plurality of plugs PG2d are formed in the same process as the plugs PG2a. Each of the plurality of plugs PG2c electrically connects the end WL2ba and the end WL1da, which overlap with each other in a planar view. Each of the plurality of plugs PG2d electrically connects the end WL2bb and the end WL1db, which overlap with each other in a planar view.

[0046] The semiconductor device DEV1 may have a pad PD1 and a pad PD2. The pads PD1 and PD2 are formed on an interlayer insulating film ILD3. The pads PD1 and PD2 are made of aluminum or an aluminum alloy. From another perspective, the pads PD1 and PD2 are formed in the same process as the wiring WL3a and the conductor CN3. One end of the resistor chain RCH is electrically connected to the pad PD1, and the other end of the resistor chain RCH is electrically connected to the pad PD2.

[0047] The propagation of cracks that occur during dicing in the dicing step S16 is usually stopped by the seal ring SR. However, if the seal ring SR does not stop the propagation of the cracks, the propagation of the cracks causes damage to the resistor chain RCH, resulting in a change in the electrical resistance value of the resistor chain RCH. Therefore, by forming the resistor chain RCH and measuring the electrical resistance value between the pads PD1 and PD2 after manufacturing the semiconductor device DEV1, it is possible to confirm whether the cracks that occur during dicing in the dicing step S16 have propagated into the semiconductor device DEV1.

[0048] <Effects of semiconductor device DEV1> In order to pass a large current through the semiconductor device DEV1, it is necessary to increase the thickness of the wiring WL3a. Accordingly, the thickness (thickness T) of the conductor CN3 also increases. When the thickness T increases, the width W of the polyimide film PID1 must be increased to ensure adhesion.

[0049] In the semiconductor device DEV1, the inner peripheral edge of the conductor CN3 is located inside both the inner peripheral edges of the conductors CN2 and CN1 in a plan view, and circuit elements such as active elements and passive elements, structures other than circuit elements such as substrate contacts and dummy patterns, and structures for testing the semiconductor device DEV1 are formed at positions overlapping with the conductor CN3 in a plan view. In other words, in the semiconductor device DEV1, the space below the conductor CN3 is effectively used as a space for forming circuit elements and structures other than circuit elements, so that an increase in the chip area is suppressed even if the width W is large.

[0050] (Second embodiment) A semiconductor device DEV2 according to the second embodiment will be described below, focusing mainly on the differences from the semiconductor device DEV1, and overlapping descriptions will not be repeated.

[0051] <Configuration of semiconductor device DEV2> 22 and 23, the semiconductor device DEV2 includes a capacitor CAP. The capacitor CAP includes a plurality of wirings WL2c, a plurality of wirings WL1e, and a plurality of plugs PG2e.

[0052] The multiple wirings WL2c are formed in the same layer. More specifically, the multiple wirings WL2c are formed in the same layer as the wirings WL2a. The multiple wirings WL1e are formed in the same layer. More specifically, the multiple wirings WL1e are formed in the same layer as the wirings WL1a, WL1b, and WL1c. The multiple wirings WL2c and the multiple wirings WL1e are formed of, for example, aluminum or an aluminum alloy. From another perspective, the multiple wirings WL1e are formed in the same process as the wirings WL1a, WL1b, and WL1c, and the wiring WL2c is formed in the same process as the wiring WL2a. The multiple plugs PG2e are formed in the interlayer insulating film ILD2. The plug PG2d is formed of, for example, tungsten. From another perspective, the plug PG2e is formed in the same process as the plug PG2a.

[0053] The multiple wirings WL2c are arranged at intervals along the outer peripheral portion PER so as to overlap with the conductor CN3 in a plan view. The multiple wirings WL1e are arranged at intervals along the outer peripheral portion PER in a plan view. Each of the multiple wirings WL1e faces each of the multiple wirings WL2c with an interlayer insulating film ILD2 interposed therebetween. Each of the multiple plugs PG2e electrically connects the wirings WL2c and WL1e facing each other.

[0054] The semiconductor device DEV2 further includes a wiring WL5a. The wiring WL5a is formed on the element isolation film ISL so as to overlap with the wirings WL2c and the wirings WL1e in a plan view. The wiring WL5a is formed of, for example, polycrystalline silicon containing a dopant. From another perspective, the wiring WL5a is formed in the same process as the gate electrode GE.

[0055] The semiconductor device DEV2 further has a plurality of plugs PG3c and a plurality of plugs PG1e. The plurality of plugs PG3c are formed in the interlayer insulating film ILD3. The plurality of plugs PG3c are made of, for example, tungsten. From another perspective, the plurality of plugs PG3c are formed in the same process as the plugs PG3a. The plurality of plugs PG1e are formed in the interlayer insulating film ILD1. The plurality of plugs PG1e are made of, for example, tungsten. From another perspective, the plurality of plugs PG1e are formed in the same process as the plugs PG1a, PG1b, and PG1c.

[0056] Each of the multiple plugs PG3c electrically connects each of the multiple wirings WL2c to the conductor CN3. However, the wirings WL2c electrically connected to the conductor CN3 by the plug PG3c are alternately arranged with the wirings WL2c that are not electrically connected to the conductor CN3 by the plug PG3c. Each of the multiple plugs PG1e electrically connects each of the multiple wirings WL1e to the wiring WL5a. However, the plug PG1e is not connected to the wiring WL1e that is electrically connected to the conductor CN3 by the plug PG3b, the wiring WL2c, and the plug PG2d. In other words, the wirings WL1e electrically connected to the wiring WL5a by the plug PG1e are alternately arranged with the wirings WL1e that are not electrically connected to the wiring WL5a by the plug PG1e.

[0057] For example, a VDD potential is applied to the wiring WL5a. For example, a ground potential is applied to the conductor CN3. Therefore, charges are accumulated between the wiring WL2c, plug PG2d, and wiring WL1e electrically connected to the wiring WL4a and the wiring WL2c, plug PG2d, and wiring WL1e electrically connected to the conductor CN3.

[0058] <Modification> As shown in FIGS. 24 and 25, in the semiconductor device DEV2, the interlayer insulating film ILD3 may have a first layer ILD3a and a second layer ILD3b. The first layer ILD3a is formed on the interlayer insulating film ILD2, and the second layer ILD3b is formed on the first layer ILD3a. The semiconductor device DEV2 may also have a wiring WL5b. The wiring WL5b is disposed on the first layer ILD3a and covered by the second layer ILD3b. The wiring WL5b extends along the outer periphery PER so as to overlap with the conductor CN3 in plan view. For example, a VDD potential is applied to the wiring WL5b. For example, a ground potential is applied to the conductor CN3. Therefore, charge is accumulated between the conductor CN3 and the wiring WL5b, and the conductor CN3 and the wiring WL5b function as a capacitor CAP.

[0059] <Effects of semiconductor device DEV2> In the semiconductor device DEV2, the capacitor CAP is formed at a position overlapping the conductor CN3 in a plan view. That is, in the semiconductor device DEV2, the space below the conductor CN3 is effectively used as the space for forming the capacitor CAP, so that an increase in the chip area is suppressed even if the width W is increased.

[0060] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0061] CAP capacitor, CN1, CN2, CN3 conductor, DEV1, DEV2 semiconductor device, DL drain layer, DL1, SL1 first portion, DL2, SL2 second portion, F1 top surface, F2 bottom surface, GE gate electrode, GI gate insulating film, HL1, HL2 hole, IF insulating film, ILD1, ILD2, ILD3 interlayer insulating film, ILD3a first layer, ILD3b second layer, ISL element isolation film, OP opening, PD1, PD2 pad, PER periphery, PG1a, PG1b, PG1c, PG1d, PG1e, PG2a, PG2b, PG2c, PG2d, PG2e, PG3a, PG3b, PG3c, PG4 plug, PID1 polyimide film, PID2 polyimide film, PV passivation film, RCH resistor chain, RE resistor element, S1 preparation process, S2 ion implantation process, S3 S4: element isolation film formation step, S5: gate electrode formation step, S6: ion implantation step, S7: sidewall spacer formation step, S8: ion implantation step, S9: interlayer insulating film formation step, S10: plug formation step, S11: wiring formation step, S12: passivation film formation step, S13: polyimide film formation step, S14: wiring formation step, S15: polyimide film formation step, S16: dicing step, SL: source layer, SL1: first portion, SL2: second portion, SPL: isolation layer, SR: seal ring, SUB: semiconductor substrate, SWS: sidewall spacer, TR: trench, WE: well layer, WL1db, WL1da, WL2ba, WL2bb: end, WL1b, WL1c, WL1e, WL1d, WL1a, WL2c, WL2b, WL2a, WL3a, WL4a, WL5a, WL5b: wiring, T: thickness, W: width.

Claims

1. a semiconductor substrate; a seal ring; the seal ring is formed on an outer periphery of the semiconductor substrate in a plan view, the seal ring has a plurality of conductors stacked on top of one another; Each of the plurality of conductors has an inner periphery and an outer periphery; A semiconductor device, wherein the inner peripheral edge of a first conductor located in the top layer of the plurality of conductors is located, in a planar view, more inward than any of the inner peripheral edges of a plurality of second conductors located in a layer lower than the first conductor of the plurality of conductors.

2. The semiconductor device according to claim 1 , wherein the outer periphery of the first conductor overlaps with the outer peripheries of all of the second conductors in a plan view.

3. a first wiring formed in the same layer as the first conductor; a passivation film covering the first conductor and the first wiring; a polyimide film formed on the passivation film; 2. The semiconductor device according to claim 1, further comprising a second wiring formed on said polyimide film and electrically connected to said first wiring.

4. The semiconductor device according to claim 3 , wherein an end of said polyimide film overlaps said first conductor in a plan view.

5. The semiconductor device according to claim 4 , wherein the first conductor has a thickness of 3 μm or more.

6. 5. The semiconductor device according to claim 4, wherein the distance between the inner peripheral edge of the first conductor and the outer peripheral edge of the first conductor is 10 [mu]m or more.

7. further comprising a circuit element formed in a layer below the first conductor; The semiconductor device according to claim 1 , wherein the circuit element at least partially overlaps the first conductor in a plan view.

8. 8. The semiconductor device according to claim 7, wherein the circuit element is an active element.

9. 8. The semiconductor device according to claim 7, wherein the circuit element is a passive element.

10. an impurity layer formed in the semiconductor substrate; a first plug formed in the semiconductor substrate; the semiconductor substrate has an upper surface and a lower surface; a portion of the semiconductor substrate located between the lower surface and the impurity layer is electrically isolated from a portion of the semiconductor substrate located between the impurity layer and the upper surface; the first plug is electrically connected to a portion of the semiconductor substrate located between the lower surface and the impurity layer, and is electrically insulated from a portion of the semiconductor substrate located between the upper surface and the impurity layer; The semiconductor device according to claim 1 , wherein the first plug at least partially overlaps the first conductor in a plan view.

11. a dummy pattern formed in a layer below the first conductor; The semiconductor device according to claim 1 , wherein the dummy pattern at least partially overlaps the first conductor in a plan view.

12. further comprising a resistor chain; the resistor chain overlaps the first conductor in a plan view, the resistor chain includes a plurality of third wirings formed in a first layer located below the first conductor, a plurality of fourth wirings formed in a second layer located below the first layer, a plurality of second plugs, and a plurality of third plugs; the third wirings are arranged along the outer periphery at intervals in a plan view, the plurality of fourth wirings are arranged along the outer periphery at intervals in a plan view, each of the plurality of third wirings has a first end and a second end; each of the plurality of fourth wirings has a third end and a fourth end; the third end portion of one of two adjacent ones of the plurality of fourth wirings and the fourth end portion of the other of the two adjacent ones of the plurality of fourth wirings overlap with the first end portion and the second end portion of one of the plurality of third wirings, respectively, in a plan view; 2. The semiconductor device according to claim 1, wherein each of the plurality of second plugs and each of the plurality of third plugs electrically connects between the first end and the third end and between the second end and the fourth end, respectively.

13. The semiconductor device according to claim 12 , wherein the resistor chain is formed around the entire periphery of the outer periphery in plan view.

14. further comprising a capacitor; the capacitor has a plurality of fifth wirings formed in a third layer located below the first conductor, a plurality of sixth wirings formed in a fourth layer located below the third layer, and a plurality of fourth plugs; the plurality of fifth wirings and the plurality of sixth wirings are arranged at intervals along the outer periphery of the semiconductor substrate in a plan view, 2. The semiconductor device according to claim 1, wherein each of the plurality of fifth wirings overlaps each of the plurality of sixth wirings in a plan view and is electrically connected to each of the plurality of sixth wirings by each of the plurality of fourth plugs.

15. further comprising a capacitor; the capacitor includes the first conductor and a seventh wiring; 2 . The semiconductor device according to claim 1 , wherein said seventh wiring is located in a layer below said first conductor, and extends along said outer periphery while facing said first conductor in a plan view.

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