Semiconductor memory device

Abstract

To improve a write margin without reducing a reading speed.SOLUTION: A semiconductor storage device (1) includes a memory cell array (3) in which a plurality of memory cells (MC) are connected to a bit line pair (BLT), and a write circuit which sets a low-potential side bit line to a negative potential in response to a negative potential boost signal. In the data read operation, the word line is activated after a first predetermined time elapses from the transition of the input clock signal to read the stored value of the memory cell, and in the data write operation, the word line is activated after a second predetermined time longer than the first predetermined time elapses from the transition of the input clock signal based on the replica bit line signal, and the negative potential boost signal is activated after a third predetermined time longer than the first predetermined time elapses.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor memory device. [Background technology]

[0002] In recent years, as semiconductor processes have become more miniaturized, the voltage required for semiconductor devices has become lower, making stable write operations to static random access memories (SRAMs) a problem. A known conventional technology for solving this problem is the negative bit line write assist technology.

[0003] For example, in Patent Document 1, a capacitance element for generating a negative potential is provided on the bit line of an SRAM. Then, when writing to the SRAM, a write assist operation of the negative bit line method is realized by changing the control signal of the capacitance element after activating the word line and before the bit line becomes 0 V. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-151847 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in conventional technology, the bit line is changed to the L level while the word line is activated, which causes a through current to flow before the stored value in the memory is inverted, resulting in an increase in power consumption.

[0006] Furthermore, in conventional technology, the control signal is changed before the bit line reaches 0V, but the potential of the bit line may not have dropped sufficiently when the capacitor is controlled. If the capacitor is operated to generate a negative potential when the bit line potential has not dropped sufficiently, the bit line cannot be brought to a sufficiently negative potential. This makes the write operation unstable, resulting in reduced yield and reliability.

[0007] Therefore, it is conceivable to increase the capacitance of the capacitor to control the bit line to a sufficiently negative potential even when the bit line potential has not dropped sufficiently (including when the bit line potential is slightly above 0 V due to a through current), but this would result in an increase in the area.

[0008] Furthermore, in conventional technology, when a word line is activated, a current flows through the path from the bit line with a low-level stored value to the memory cell in the unselected memory cell column where no programming is performed. This current flow continues while the word line is high, which increases power consumption.

[0009] An object of the present disclosure is to provide a semiconductor memory device that solves the above problems without reducing the read speed. [Means for solving the problem]

[0010] In one aspect of the present disclosure, a semiconductor memory device that performs read operations and write operations in response to an input clock signal includes a memory cell array including a plurality of memory cells, each of which is connected to a corresponding word line and bit line pair; and a write circuit that has the function of setting one bit line of the bit line pair connected to the memory cell to be written to a low potential and sets the low-potential side bit line to a negative potential in response to a negative potential boost signal. During a data read operation on the memory cell, the word line is activated after a first predetermined time has elapsed from a transition of the input clock signal, thereby reading out the stored value of the memory cell. During a data write operation to the memory cell, the word line is activated after a second predetermined time has elapsed from the transition of the input clock signal, the second predetermined time being longer than the first predetermined time, and the negative potential boost signal is activated after a third predetermined time has elapsed, the third predetermined time being longer than the first predetermined time, thereby setting the low-potential side of the bit line pair to a negative potential.

[0011] According to this embodiment, the timing of activating the word line relative to the transition of the input clock signal during a write operation is delayed compared to the timing during a read operation of the memory cell. This allows the potential of the bit line to be lowered quickly and reliably, and the word line is activated after the potential of the bit line has sufficiently decreased. This suppresses the through current flowing through the bit line of the selected column, thereby reducing power consumption.

[0012] Furthermore, the timing at which one bit line of a bit line pair to be written to is set to a negative potential during a write operation is delayed compared to the read operation of the memory cell. This ensures that the bit line is set to a negative potential, enabling a stable write operation. This improves yield and reliability. Furthermore, because the bit line potential is boosted to a negative potential after it has sufficiently dropped, there is no need to increase the capacitance of the capacitive element to set the bit line to a negative potential, thereby preventing an increase in the area of ​​the semiconductor memory device. [Effects of the Invention]

[0013] According to the present disclosure, in a semiconductor memory device, while the read speed in a read operation is maintained as high as possible, in a write operation, the potential of the bit line is quickly and reliably lowered sufficiently before the bit line is set to a negative potential, i.e., a write assist operation is initiated, thereby improving the write margin compared to conventional technology. [Brief explanation of the drawings]

[0014] [Figure 1A] FIG. 1 is a functional block diagram illustrating a portion of the configuration of a semiconductor memory device (first embodiment); [Figure 1B] FIG. 1 is a diagram showing an example of a circuit configuration of an amplifier circuit constituting a semiconductor memory device (first embodiment); [Figure 1C] FIG. 1 is a diagram showing an example of a circuit configuration of a control circuit constituting a semiconductor memory device (first embodiment); [Figure 2] FIG. 1B is a diagram showing an example of a circuit configuration of the memory cell of FIG. 1A; [Figure 3] FIG. 1B is a diagram showing an example of a circuit configuration of the replica cell of FIG. 1A. [Figure 4] 1 is a timing chart showing an example of operation of a semiconductor memory device (first embodiment); [Figure 5A] 1A and 1B, which are views of a semiconductor memory device (second embodiment) [Figure 5B] FIG. 1B is a diagram illustrating a semiconductor memory device (second embodiment) according to the present invention. [Figure 5C] FIG. 1C is a diagram illustrating a semiconductor memory device (second embodiment). [Figure 6] 10 is a timing chart showing an example of operation of the semiconductor memory device (second embodiment); DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same reference numerals may be used to refer to signal lines and signals passing through the signal lines.

[0016] First Embodiment The semiconductor memory device 1 includes a memory cell array 3, a replica bit line circuit 4, an amplifier circuit 2, and a control circuit 6.

[0017] FIG. 1 (FIGS. 1A to 1C) shows a configuration example of a semiconductor memory device 1 according to the first embodiment. In other words, the semiconductor memory device 1 includes a configuration 1a in FIG. 1A, a configuration 1b in FIG. 1B, and a control circuit 6 in FIG. 1C. FIG. 1A shows a configuration example of a memory cell array 3 and a replica bit line circuit 4 and their peripheral circuits as configuration 1a. FIG. 1B shows a configuration example of an amplifier circuit 2 and its peripheral circuits as configuration 1b.

[0018] -Memory cell array- As shown in FIG. 1A, the memory cell array 3 includes a plurality of memory cells MC arranged in an array of m rows (m is a natural number) by n columns (n ​​is a natural number).

[0019] The memory cell array 3 includes a plurality of word lines WL (m in FIG. 1A) arranged corresponding to the rows of the memory cells MC, and a plurality of bit line pairs BLT (n in FIG. 1A) arranged corresponding to the columns of the memory cells MC. The bit line pair BLT is composed of a pair of bit lines BL and BLX. The word lines WL extend in a first direction (hereinafter referred to as the "row direction"). The bit lines BL and BLX extend in a second direction (hereinafter referred to as the "column direction") intersecting the first direction. Each memory cell MC is connected to the word line WL of the row and the bit line pair BLT (bit lines BL and BLX) of the column corresponding to its arrangement position.

[0020] The word lines WL are connected to a word line driver 8. The word line driver 8 includes a row decoder 81 and a driver circuit 82. The row decoder 81 decodes a row address specified by a CPU (not shown). The driver circuit 82 is a driver that activates the word line WL corresponding to the address decoded by the row decoder 81.

[0021] The bit line pair BLT is connected to an amplifier circuit 2, which will be described later.

[0022] Fig. 2 is a circuit diagram showing the internal configuration of memory cell MC of Fig. 1A. In Fig. 2, memory cell MC includes N-type transistors NA1 and NA2, P-type transistors PL1 and PL2, and N-type transistors ND1 and ND2.

[0023] The gate of the N-type transistor NA1 is connected to the word line WL and the source is connected to the bit line BL. The gate of the N-type transistor NA2 is connected to the word line WL and the source is connected to the bit line BLX. The source of the P-type transistor PL1 is supplied with a power supply voltage VDD and is connected to the drain of the N-type transistor NA1. The gate of the N-type transistor ND1 is connected to the gate of the P-type transistor PL1, the drain is connected to the drain of the P-type transistor PL1, and the source is connected to the ground potential VSS. The gate of the P-type transistor PL2 is connected to the drain of the N-type transistor NA1, the source is supplied with a power supply voltage VDD, and the drain is connected to the drain of the N-type transistor NA2. The gate of the N-type transistor ND2 is connected to the gate of the P-type transistor PL2, the drain is connected to the drain of the P-type transistor PL2, and the source is connected to the ground potential VSS. The connection node between the gate of the P-type transistor PL1 and the gate of the N-type transistor ND1 is connected to the drain of the N-type transistor NA2.

[0024] Here, the P-type transistor PL1 and the N-type transistor ND1 form a first inverter. The P-type transistor PL2 and the N-type transistor ND2 form a second inverter. The input terminal of the first inverter is connected to the output terminal of the second inverter, and the output terminal of the first inverter is connected to the input terminal of the second inverter, thereby forming a latch circuit.

[0025] -Replica bit line circuit- 1A, the replica bit line circuit 4 includes a plurality of replica memory cells RMC arranged in the column direction. In the example of FIG. 1A, the replica bit line circuit 4 includes m replica memory cells RMC.

[0026] Fig. 3 is a circuit diagram showing the internal configuration of the replica memory cell RMC of Fig. 1A. In Fig. 3, the transistors constituting the replica memory cell RMC have the same size as the transistors constituting the memory cell MC shown in Fig. 2.

[0027] The replica memory cell RMC differs from the memory cell MC in that the power supply voltage VDD is supplied to the gate of the P-type transistor PL1 and the gate of the N-type transistor ND1 in the latch circuit described above.

[0028] The replica memory cells RMC differ from the memory cells MC in that the gate of the N-type transistor NA1 is connected to a replica word line TRKWL (hereinafter referred to as the "TRKWL signal"). The TRKWL signals of some replica memory cells RMC are connected to a word line driver 8, and the TRKWL signals of the remaining replica memory cells RMC are connected to a ground potential VSS. The delay amount, which will be described later, can be adjusted by changing the number of replica memory cells RMC connected to this word line driver 8. In the following description, the replica memory cells RMC whose TRKWL signal is connected to the word line driver 8 may be referred to as the first replica memory cell RMC, and the replica memory cells RMC whose TRKWL signal is connected to the ground potential VSS may be referred to as the second replica memory cell RMC, to distinguish them from each other. The input signal input from the TRKWL signal of the first replica memory cell RMC is generated based on a precharge signal PCG (hereinafter referred to as the "PCG signal") and a read enable signal RE (hereinafter referred to as the "RE signal").

[0029] During a data read operation of the memory cell MC in the semiconductor memory device 1 (hereinafter simply referred to as "during a read operation"), the TRKWL signal of the first replica memory cell RMC goes to "H level" (hereinafter simply referred to as "H"), causing the replica bit line TRKBL to go to "L level" (hereinafter simply referred to as "L"). This causes a replica bit line signal TRKBL (hereinafter simply referred to as "TRKBL signal") to be output from the first replica memory cell RMC. Then, a sense amplifier enable signal SAE (hereinafter simply referred to as "SAE signal"), which will be described later, is generated based on the TRKBL signal.

[0030] Furthermore, during a data write operation to the memory cells MC in the semiconductor memory device 1 (hereinafter simply referred to as "write operation"), the TRKWL signal becomes 'L' and the first replica memory cells RMC do not operate. As a result, the first replica memory cells RMC and the second replica memory cells RMC act only as load capacitances for the replica bit lines TRKBL.

[0031] The replica bit line TRKBL is branched at a connection position with the replica memory cell RMC located at the farthest end as viewed from the amplifier circuit 2. The branched signal line is folded back at a position farther from the amplifier circuit 2 than the replica memory cell RMC located at the farthest end, and is connected to one input terminal of the NOR circuit 9.

[0032] The RE signal is input to the other input terminal of the NOR circuit 9. A signal line WATMG connected to the output terminal of the NOR circuit 9 extends in parallel with the replica bit line TRKBL.

[0033] The NOR circuit 9 outputs a fixed signal (here, a signal at L level) during a read operation, and outputs a signal that changes according to the TRKBL signal during a write operation. The WATMG signal output from the NOR circuit 9 is used for a write assist operation in a control circuit, which will be described later. The specific write assist operation will be described later.

[0034] -Amplifier circuit- 1B, in this example, one amplifier circuit 2 is provided for every two columns. Specifically, the column connected to the bit line pair BLT[0] (hereinafter referred to as the “first column”) and the column connected to the bit line pair BLT[1] (hereinafter referred to as the “second column”) are connected to the amplifier circuit 2.

[0035] The amplifier circuit 2 includes a sense amplifier circuit 21, a write circuit, a negative potential boost signal generating circuit, and a negative potential generating circuit 25.

[0036] (Sense amplifier circuit) The sense amplifier circuit 21 amplifies the signal on the bit line pair BLT in response to the SAE signal and outputs the amplified signal to the read data line pair RDT. The read data line pair RDT is made up of a pair of read data lines RD and RDX.

[0037] More specifically, in this example, a column selector 23 is provided between the first and second columns and the sense amplifier circuit 21. The column selector 23 selects one of the first and second columns based on a column selection signal NRCA (NRCA[0], NRCA[1]). The column selection signal NRCA is generated by the column control circuit 22 based on the column selection signal NCOL[1:0]. Hereinafter, the column selection signal NCOL[0] will be simply referred to as NCOL[0], and the column selection signal NCOL[1] will be simply referred to as NCOL[1].

[0038] The sense amplifier circuit 21 receives the signal of the bit line pair BLT of the selected column, amplifies the signal, and outputs it to the read data line pair RDT.

[0039] The NSAE signal, which is an inverted signal of the SAE signal, is generated based on the TRKBL signal and the IWE signal in the signal generation circuit 63 of the control circuit 6. The signal generation circuit 63 and the IWE signal will be described later.

[0040] (Write circuit) The write circuit includes a write amplifier that sets one bit line of the bit line pair BLT to a high potential and the other bit line to a low potential. The write amplifier also has a function of pulling down the bit line on the low potential side of the bit line pair BLT (the "other bit line") to a negative potential in response to a negative potential boost signal BOOSTX (hereinafter referred to as the "BOOSTX signal"). The write circuit also includes a write driver 26 that is driven by a write signal WRITE (hereinafter referred to as the "WRITE signal"). The WRITE signal is generated based on a write enable signal WEB (hereinafter referred to as the "WEB signal") and a PCG signal. Each column also includes a precharge circuit 24 that operates based on the PCG signal.

[0041] (Negative voltage boost signal generation circuit) The negative potential boost signal generation circuit 27 is a circuit that generates a BOOSTX signal based on a timing adjustment signal NWTA (hereinafter referred to as an "NWTA signal"), which will be described later, and supplies the signal to the write amplifier.

[0042] (RDCEN signal generation circuit) The signal generation circuit 54 generates a clock enable signal RDCEN (hereinafter referred to as the "RDCEN signal") based on the TRKBL signal and the IWE signal. The IWE signal is an internal signal obtained by latching and inverting the WEB signal. In other words, the IWE signal changes according to the WEB signal.

[0043] In other words, the RDCEN signal is a signal used to activate a word line after a predetermined time has elapsed since the transition of the input clock signal. In other words, the RDCEN signal is a signal that adjusts the timing from the transition of the input clock signal to the activation of the word line WL. The specific function of the RDCEN signal will be explained later in the section "Operation of the Semiconductor Memory Device."

[0044] In this example, the signal generating circuit 54 is configured with a NAND circuit that receives the TRKBL signal at one input terminal, receives the IWE signal at the other input terminal, and outputs the RDCEN signal. One input terminal of this NAND circuit is connected to a replica circuit whose output signal changes in response to the WRITE signal in addition to the replica bit line TRKBL.

[0045] The replica circuits are made up of a first replica circuit 51, a second replica circuit 52, and a third replica circuit 53.

[0046] The first replica circuit 51 is a replica circuit of the write driver 26. Specifically, it is a replica circuit that uses transistors of the same size and polarity as the write driver 26, and is configured so that the delay between input and output is as close to the same as that of the write driver 26. The first replica circuit 51 receives the same WRITE signal as the write driver 26.

[0047] The second replica circuit 52 is a replica circuit of the path formed by the inverter IN1 and the transistors TP1 and TN1 in Fig. 1B, and is designed so that the delay between the input and output is as similar as possible. The output signal of the first replica circuit 51 is input to the second replica circuit 52.

[0048] 1B, and is designed so that the delay between the input and output is as close to the same as possible. The output signal of the second replica circuit 52 is input to the third replica circuit 53, and the output is connected to one input terminal of a NAND circuit in the signal generation circuit 54.

[0049] In this way, by providing the first to third replica circuits 51 to 53 in the generation path of the RDCEN signal that sets the timing of the BOOSTX signal, it is possible to generate a delay equivalent to the operation of the write amplifier circuit.

[0050] -Control circuit- FIG. 1C shows an example of the configuration of the control circuit 6.

[0051] The control circuit 6 is a circuit that generates control signals for each part based on an input clock signal CLK (hereinafter referred to as "CLK signal") and various control signals. In this example, the control circuit 6 includes a clock generation circuit 61 and three signal generation circuits 62, 63, and 64.

[0052] (clock generation circuit) The clock generation circuit 61 generates an internal clock signal ICLK (hereinafter referred to as "ICLK signal") based on the CLK signal and the clock enable signal CEB.

[0053] (signal generation circuit) The signal generation circuit 62 generates the RDCLK signal that controls the word line driver and its inverted signal, the NRDCLK signal. In this example, the signal generation circuit 62 is composed of a NAND circuit having an RDCEN signal input to one input terminal and an ICLK signal input to the other input terminal, and an inverter connected to the output of the NAND circuit.

[0054] During a read operation, the RDCEN signal is fixed at 'H', so the RDCLK signal changes so that the word line rises in accordance with the rising edge of the ICLK signal (CLK signal). During a write operation, the signal generation circuit 62 changes so that the word line rises after the RDCEN signal becomes 'H' after the ICLK signal changes.

[0055] More specifically, during a write operation, when the IWE signal is 'H' and the TRKBL signal falls, the RDCEN signal rises, causing the RDCLK signal to rise and the NRDCLK signal to fall. The signal changes of the RDCLK and NRDCLK signals control the rising of the word line WL of the driver circuit 82 in FIG. 1. The RDCLK and NRDCLK signals (RDCEN signals) are adjusted so that the word line WL rises when the bit line signal BL (hereinafter referred to as the "BL signal") falls to the ground potential VSS. In other words, during a write operation, even if the ICLK signal changes, the word line WL does not rise until the BL signal falls to the ground potential VSS. In other words, a control is put into place to delay the rising of the word line WL.

[0056] On the other hand, during a read operation, the IWE signal is 'L', so the RDCEN signal is fixed at 'H'. As a result, the RDCLK signal and NRDCLK signal change based on the ICLK signal, regardless of the TRKBL signal. As with a write operation, the rising edge of the word line WL is controlled by the signal changes of the RDCLK signal and NRDCLK signal. In other words, during a read operation, the rising edge of the word line WL is controlled according to the change in the ICLK signal. In other words, there is no control to delay the rising edge of the word line WL.

[0057] The signal generating circuit 63 generates the NSAE signal and the PCGSA signal based on the TRKBL signal and the IWE signal. The PCGSA signal is a signal with an expanded pulse width of the PCG signal.

[0058] The signal generation circuit 64 includes a combinational circuit that generates the RE signal, the IWE signal, and the WRITE signal based on the WEB signal. The signal generation circuit 64 also includes a combinational circuit that generates the NWTA signal based on the IWE signal, the ICLK signal, and the WATMG signal.

[0059] The NWTA signal is a signal used to activate the BOOSTX signal after a predetermined time has elapsed since the transition of the CLK signal, setting the low-potential side of the bit line pair BLT to a negative potential. The NWTA signal also adjusts the timing from the transition of the CLK signal to the activation of the BOOSTX signal. The specific function of the NWTA signal will be described below in "Operation of the Semiconductor Memory Device."

[0060] -Operation of semiconductor memory device- Next, with reference to FIG. 4, a data read operation from the memory cell MC and a data write operation to the memory cell MC in the semiconductor memory device 1 will be described.

[0061] (Data read operation) First, the data read operation of the memory cell MC will be explained. In this example, the first column is selected by setting the column selection signal NCOL[0]='L', and the bit line BL[0]='L' is read. In this example, the memory cell row connected to WL[m-1] (see Figure 1) is selected.

[0062] In the following description, the bit line signal BL[0] will be simply referred to as BL[0]. Similarly, the read data signal RD[0] will be referred to as RD[0], and the read data signal RDX[0] will be referred to as RDX[0].

[0063] First, before the CLK signal rises, the WEB signal becomes 'H'.

[0064] When the 'H' state of the WEB signal is confirmed and the CLK signal rises, the PCG signal and PCGSA signal rise to 'H'. The PCGSA signal goes 'H' only during a read operation.

[0065] When the PCG signal rises, the WL signal and TRKWL signal corresponding to the memory cell MC to be read rise to 'H'. At almost the same time as the PCG signal rises, the NCOL[0] and NREAD signals fall to 'L'. The NREAD signal is a signal that changes based on the WEB signal and PCG signal.

[0066] When the WL signal and the TRKWL signal rise to 'H', the BL[0] and TRKBL signals accordingly begin to fall to 'L'.

[0067] Here, the TRKBL signal is adjusted so that when BL[0] drops to a level required for sense amplifier operation, it drops to the threshold (e.g., 1 / 2VDD) of the NOR circuit 65 (see FIG. 1C). The NOR circuit 65 is a circuit that receives the TRKBL signal as an input.

[0068] The SAE signal changes based on the output of this NOR circuit. Specifically, when BL[0] drops to the level required for sense amplifier operation, the SAE signal rises to 'H'. This activates the sense amplifier circuit 21, reading 'L' as RD[0] and 'H' as RDX[0].

[0069] After the SAE signal goes to 'H', the PCG signal, WL signal, and TRKWL signal go to 'L', and the NCOL[0] and NREAD signals go to 'H'. After that, BL[0] is precharged to 'H'.

[0070] When the read output is determined, the PCGSA signal becomes 'L', the SAE signal also becomes 'L', and the read operation ends. When the sense amplifier circuit 21 operates, 'L' is output as RD[0].

[0071] (Data write operation) Next, we will explain the data write operation to the memory cell MC. In this example, we will explain the case where the first column is selected by setting NCOL[0]='L', and the write data signal WDX[0]='H' is written to BL[0]. In other words, BL[0]='L' is written. Also, in this example, the memory cell row connected to WL[m-1] (see Figure 1) is selected.

[0072] In the following description, the write data signal WD[0] will be simply referred to as WD[0], and the write data signal WDX[0] will be simply referred to as WDX[0]. WDX[x] (x = positive integer) is an inverted signal of WD[x].

[0073] First, before the CLK signal rises, the WEB signal goes low and WDX[0] goes high. WD[x] and WDX[x] are held in the same state while the WL signal and the WRITE signal are high.

[0074] When the WEB signal is set to low and the CLK signal rises, the PCG signal rises to high. When writing data, the PCGSA signal remains low and does not change.

[0075] When the WEB signal goes low, the IWE signal goes high, and the RDCEN signal goes low until the TRKBL signal drops to low. While the RDCEN signal is low, the RDCLK signal remains low, and the NRDCLK signal remains high. Therefore, WL[m-1] remains low.

[0076] When the PCG signal rises, the WRITE signal rises to 'H'. Almost simultaneously with the rise of the PCG signal, NCOL[0] falls to 'L', and the BL[0] and TRKBL signals begin to fall to 'L'.

[0077] Here, the timing of the TRKBL signal is adjusted so that the RDCEN signal becomes 'H' when BL[0] drops to the ground potential VSS. Therefore, after BL[0] drops to the ground potential VSS, the RDCEN signal becomes 'H', and the RDCLK signal and WL[m-1] rise. Then, almost simultaneously with this rise of WL[m-1], the BOOSTX signal becomes 'L'. As a result, the WGND signal (see FIG. 1B) of the negative potential generating circuit 25 becomes negative, which causes the bit line signal BL[0] to become negative, and the desired data ('L' in this example) is written to the memory cell MC to be written. Note that if you want to write 'H' to the memory cell MC, you can set WD[0] to 'H' instead of WDX[0].

[0078] When the write operation is completed, the PCG signal, WL[m-1], and WRITE signal become 'L', and NCOL[0] becomes 'H'. Then, when the PCG signal becomes 'L', BL[0] is precharged to 'H'.

[0079] As described above, according to this embodiment, by using the replica memory cells RMC for the read operation, it is possible to provide the optimum activation timing to the sense amplifier circuit 21. Furthermore, during the read operation, the timing of activating the word line is not delayed, so that the read speed is not reduced.

[0080] For write operations, the timing at which the word line WL is activated during write can be delayed to quickly and reliably lower the potential of the bit line BL sufficiently (to the ground potential VSS in this embodiment). This allows the word line to be activated after the potential of the bit line BL has sufficiently lowered.

[0081] This makes it possible to suppress the through current flowing through the bit line BL of the selected column, thereby achieving low power consumption.

[0082] In addition, since the potential of the bit line BL is boosted to a negative potential after it has sufficiently dropped, the bit line BL can be reliably set to a negative potential, thereby achieving a stable write operation. This improves yield and reliability. Furthermore, since the potential of the bit line BL is boosted to a negative potential after it has sufficiently dropped, there is no need to increase the capacitance value of the capacitive element to set it to a negative potential, and an increase in the area of ​​the semiconductor memory device can be suppressed.

[0083] Furthermore, since the time required to activate the word line during writing is shortened, the charge / discharge current in the unselected columns can be suppressed, thereby reducing power consumption.

[0084] Second Embodiment 5 (FIGS. 5A to 5C) show an example of the configuration of a semiconductor memory device 1 according to the second embodiment. FIG. 5A is a diagram equivalent to FIG. 1A, FIG. 5B is a diagram equivalent to FIG. 1B, and FIG. 5C is a diagram equivalent to FIG. 1C. Here, the differences from the first embodiment will be mainly described.

[0085] This embodiment differs from the first embodiment in that the WATMG signal (TRKBL signal) is not used to generate the BOOSTX signal (NWTA signal), and the TRKBL signal is not used to delay the WL signal during a write operation.

[0086] Specifically, in Fig. 5A, the NOR circuit 9 is omitted from the configuration of Fig. 1A. That is, in this embodiment, the WATMG signal is not output from the configuration 1a of Fig. 5A.

[0087] 5B, the signal generation circuit 54, the first replica circuit 51, the second replica circuit 52, and the third replica circuit 53 are omitted from the configuration of FIG. 1B. That is, in this embodiment, the RDCEN signal is not output from the configuration 1b of FIG. 5B.

[0088] 5C differs from the configuration in FIG. 1C in that a delay circuit 67 is provided in a signal generating circuit 64. In this example, the delay circuit 67 is configured with multiple stages of buffers. In the example in FIG. 5C, the delay circuit 67 is configured with four stages of buffers.

[0089] The input terminal of the delay circuit 67 is connected to the output of an AND logic combinational circuit that receives the ICLK signal and the IWE signal as inputs. The NWTA signal is an output signal obtained by inputting the input signal and output signal of the delay circuit to a NAND logic combinational circuit. In other words, the delay circuit 67 is a circuit that delays the timing so that the word line becomes active after a predetermined time (corresponding to the third predetermined time) has elapsed since the transition of the CLK signal, and corresponds to a second delay circuit.

[0090] In this embodiment, the RDCEN signal uses the output signal of the buffer located at the middle of the multiple stages of buffers that make up the delay circuit. In other words, in this example, the delay circuit 67 includes a delay circuit 66 that generates the RDCEN signal. The delay circuit 66 is a circuit that delays the timing so that the word line becomes active after a predetermined time (corresponding to a second predetermined time) has elapsed since the transition of the CLK signal, and corresponds to a first delay circuit.

[0091] In other words, the signal generating circuit 64 is configured so that the timing of the change in the NWTA signal is later than the timing of the change in the RDCEN signal. That is, the delay circuit 67 is provided with a delay circuit 66 (two-stage buffer) for generating the RDCEN signal, and another delay circuit (two-stage buffer) is interposed after the delay circuit 66 to generate the NWTA signal.

[0092] The configuration other than that described above is the same as or similar to that of the first embodiment, and detailed description thereof will be omitted here.

[0093] -Operation of semiconductor memory device- Next, a data write operation to the memory cell MC in the semiconductor memory device 1 will be described with reference to Fig. 6. Note that a data read operation from the memory cell MC is the same as the operation in Fig. 4.

[0094] (Data write operation) In this example, as in the first embodiment, the operation when BL[0]='L' is written will be described.

[0095] First, before the CLK signal rises, the WEB signal goes low and WDX[0] goes high. WD[x] and WDX[x] are held in the same state while the WL signal and the WRITE signal are high.

[0096] When the WEB signal is set to low and the CLK signal rises, the PCG signal rises to high. When writing data, the PCGSA signal remains low and does not change.

[0097] When the PCG signal rises, the WRITE signal goes high, and at almost the same time, NCOL[0] falls to low, causing BL[0] to fall to low.

[0098] Here, the signal change timing of the RDCEN signal relative to the rising edge of the CLK signal is adjusted by the action of the delay circuit 67. Therefore, after BL[0] drops to the ground potential VSS, the RDCEN signal becomes 'H', and the RDCLK signal and WL[m-1] rise. Then, almost simultaneously with this rising edge of WL[m-1], the BOOSTX signal becomes 'L'. As a result, the WGND signal (see FIG. 5B) of the negative potential generating circuit 25 becomes negative, which causes the bit line signal BL[0] to become negative, and the desired data ('L' in this example) is written to the memory cell MC to be written.

[0099] When the write operation is completed, the PCG signal, WL[m-1], and WRITE signal become 'L', and NCOL[0] becomes 'H'. Then, when the PCG signal becomes 'L', BL[0] is precharged to 'H'. Note that in this embodiment, unlike the first embodiment, the TRKBL signal does not change during the write operation.

[0100] As described above, in this embodiment, as in the first embodiment, the timing of activating the word line is not delayed during the read operation, and therefore the read speed does not decrease.

[0101] In the write operation, the same effects as in the first embodiment can be obtained.

[0102] Specifically, by delaying the timing of activating the word line WL during a write, the potential of the bit line BL can be quickly and reliably lowered sufficiently (to the ground potential VSS in this embodiment). This allows the word line to be activated after the potential of the bit line BL has sufficiently decreased.

[0103] This makes it possible to suppress the through current flowing through the bit line BL of the selected column, thereby achieving low power consumption.

[0104] In addition, since the potential of the bit line BL is boosted to a negative potential after it has sufficiently dropped, the bit line BL can be reliably set to a negative potential, thereby achieving a stable write operation. This improves yield and reliability. Furthermore, since the potential of the bit line BL is boosted to a negative potential after it has sufficiently dropped, there is no need to increase the capacitance value of the capacitive element to set it to a negative potential, and an increase in the area of ​​the semiconductor memory device can be suppressed.

[0105] Furthermore, since the time required to activate the word line during writing is shortened, the charge / discharge current in the unselected columns can be suppressed, thereby reducing power consumption.

[0106] Furthermore, since it is realized with a simpler circuit than the first embodiment, it is possible to achieve a smaller area than the first embodiment. [Industrial Applicability]

[0107] According to the present disclosure, a circuit that generates various operation signals for a semiconductor memory device at appropriate timing can be realized without area overhead, which is extremely useful. [Explanation of symbols]

[0108] 1. Semiconductor memory device 3 Memory Cell Array 4 Replica bit line circuit 21 Sense amplifier circuit 25 Negative voltage boost signal generation circuit 66 Delay circuit (first delay circuit) 67 Delay circuit (second delay circuit) CLK Input clock signal MC memory cell WL Word Line BL bit line BLT bit line pair TRKBL replica bit lines BOOSTX Negative voltage boost signal

Claims

1. A semiconductor memory device that performs read and write operations in response to an input clock signal, a memory cell array including a plurality of memory cells, each of the plurality of memory cells being connected to a corresponding word line and bit line pair; a write circuit that has a function of setting one bit line of a bit line pair connected to the memory cell to be written to a low potential, and sets the bit line on the low potential side to a negative potential in response to a negative potential boost signal; a replica bit line circuit including a plurality of replica memory cells, the plurality of replica memory cells outputting a replica bit line signal to a common replica bit line in response to a replica word line signal; During a data read operation of the memory cell, the word line is activated after a first predetermined time has elapsed since the transition of the input clock signal, thereby reading out the stored value of the memory cell; During a data write operation to the memory cell, the word line is activated after a second predetermined time, which is longer than the first predetermined time, has elapsed from a transition of the input clock signal based on the replica bit line signal, and the negative potential boost signal is activated after a third predetermined time, which is longer than the first predetermined time, has elapsed, to set the low potential side of the bit line pair to a negative potential. A semiconductor memory device characterized by:

2. 2. The semiconductor memory device according to claim 1, a signal generation path of the negative potential boost signal is provided with a replica circuit of a write driver that is driven during the write operation in addition to the replica bit line; A semiconductor memory device characterized by:

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