Semiconductor memory device

Abstract

To provide a semiconductor memory device capable of improving reliability of operation.SOLUTION: A semiconductor memory device according to an embodiment includes a first plurality of word lines stacked above a substrate, a second plurality of word lines stacked above the first plurality of word lines, a selection gate line provided above the second plurality of word lines, an intermediate pillar MMP provided above the substrate and penetrating the first plurality of word lines in a Z direction, and an upper pillar UMP provided above the intermediate pillar MMP and penetrating the second plurality of word lines and the selection gate line in the Z direction. The second plurality of word lines include the upper layer word line UU disposed around the upper layer portion of the upper pillar UMP, the middle layer word line UM disposed around the middle layer portion below the upper layer portion, and the lower layer word line UL disposed around the lower layer portion below the middle layer portion, and the film thickness of the upper layer word line UU is larger than the film thickness of the middle layer word line UM.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memories capable of storing data in a nonvolatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-48348 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device capable of improving the reliability of its operation is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a first plurality of word lines stacked above a substrate, a second plurality of word lines stacked above the first plurality of word lines, select gate lines provided above the second plurality of word lines, a first pillar provided above the substrate and piercing the first plurality of word lines in a first direction perpendicular to an upper surface of the substrate, and a second pillar provided above the first pillar and piercing the second plurality of word lines and the select gate lines in the first direction. The second plurality of word lines include upper layer word lines arranged around upper layer portions of the second pillars, middle layer word lines arranged around middle layer portions below the upper layer portions, and lower layer word lines arranged around lower layer portions below the middle layer portions, and the thickness of the upper layer word lines is thicker than the thickness of the middle layer word lines. [Brief explanation of the drawings]

[0006] [Figure 1]1 is a block diagram showing a circuit configuration of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram of a block of the memory cell array according to the first embodiment. [Figure 3] FIG. 1 is a diagram showing a planar layout of a semiconductor memory device according to a first embodiment. [Figure 4] FIG. 2 is a diagram for explaining the cross-sectional structure of a memory region according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] 3A and 3B are diagrams for explaining the cross-sectional structure of an extraction region according to the first embodiment. [Figure 7] 1 is a cross-sectional view showing an outline of the structure of a memory pillar and a word line according to a first embodiment. [Figure 8] 3 is a cross-sectional view showing details of the structure of a memory pillar and a word line according to the first embodiment. FIG. [Figure 9] 5 is a flowchart showing a method for manufacturing a contact of the semiconductor memory device according to the first embodiment. [Figure 10] 5A to 5C are cross-sectional views showing a method for manufacturing a contact of the semiconductor memory device according to the first embodiment. [Figure 11] 5A to 5C are cross-sectional views showing a method for manufacturing a contact of the semiconductor memory device according to the first embodiment. [Figure 12] 5A to 5C are cross-sectional views showing a method for manufacturing a contact of the semiconductor memory device according to the first embodiment. [Figure 13] 5A to 5C are cross-sectional views showing a method for manufacturing a contact of the semiconductor memory device according to the first embodiment. [Figure 14] 5A to 5C are cross-sectional views showing a method for manufacturing a contact of the semiconductor memory device according to the first embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing an outline of the structure of a memory pillar and a word line according to a second embodiment. [Figure 16] FIG. 10 is a cross-sectional view showing details of the structure of a memory pillar and a word line according to the second embodiment. [Figure 17]FIG. 10 is a cross-sectional view showing an outline of the structure of a memory pillar and a word line according to a first modification of the second embodiment. [Figure 18] FIG. 10 is a cross-sectional view showing an outline of the structure of a memory pillar and a word line according to Modification 2 of the second embodiment. [Figure 19] FIG. 10 is a cross-sectional view showing an outline of the structure of a memory pillar and a word line according to a third embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing details of the structure of a memory pillar and a word line according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] In the following description, components having the same function and configuration are denoted by the same reference numerals. Furthermore, the embodiments described below are merely examples of devices and methods for embodying the technical ideas of the embodiments, and do not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0008] A semiconductor memory device according to an embodiment will be described below. As an example of the semiconductor memory device, a three-dimensional stacked NAND flash memory in which memory cell transistors are stacked three-dimensionally above a semiconductor substrate will be used. The NAND flash memory is a semiconductor memory capable of storing data in a nonvolatile manner.

[0009] For example, in a semiconductor memory device, a plurality of word lines are stacked on a substrate, and a row decoder is provided for supplying voltage to the word lines. Memory pillars are formed in the stacking direction of the word lines so as to penetrate the plurality of word lines. Contacts are formed at the ends of the word lines to connect the word lines to the row decoder.

[0010] When forming contacts, the contact holes may penetrate the target word lines and reach the word lines below, or may reach close to the word lines below. In such cases, defects such as short circuits between the upper and lower word lines may occur during inspection before shipment or during use after shipment.

[0011] In the embodiment, the thickness of the word lines in some layers among the plurality of stacked word lines is increased, thereby reducing the occurrence of the above-mentioned problems. Several embodiments will be described below.

[0012] 1. First embodiment A semiconductor memory device according to a first embodiment will be described.

[0013] 1.1 Circuit configuration of semiconductor memory device First, a description will be given of the circuit configuration of the semiconductor memory device of the first embodiment. Fig. 1 is a block diagram showing the circuit configuration of the semiconductor memory device of the first embodiment.

[0014] The semiconductor memory device 10 of the first embodiment includes, for example, a NAND flash memory and stores data in a nonvolatile manner. A memory controller 1 is connected to the semiconductor memory device 10 via a NAND bus. The semiconductor memory device 10 is controlled by the memory controller 1.

[0015] The semiconductor memory device 10 includes a memory cell array 11, an input / output circuit 12, a logic control circuit 13, a ready / busy circuit 14, a register group 15, a sequencer (or a control circuit) 16, a voltage generation circuit 17, a row decoder 18, a column decoder 19, a data register 20, and a sense amplifier 21. The register group 15 includes a status register 15A, an address register 15B, and a command register 15C.

[0016] The memory cell array 11 includes one or more blocks BLK0, BLK1, BLK2, ..., BLKn (n is an integer equal to or greater than 0). Each of the blocks BLK0 to BLKn includes a plurality of memory cell transistors (hereinafter also referred to as memory cells) associated with rows and columns. The memory cell transistors are electrically erasable and programmable non-volatile memory cells. The memory cell array 11 includes a plurality of word lines, a plurality of bit lines, and a source line for applying voltages to the memory cell transistors. The specific configuration of the block BLKn will be described later.

[0017] The input / output circuit 12 and the logic control circuit 13 are connected to the memory controller 1 via input / output terminals (or NAND buses). The input / output circuit 12 transmits and receives I / O signals DQ (e.g., DQ0, DQ1, DQ2, ..., DQ7) to and from the memory controller 1 via the input / output terminals. The I / O signals DQ communicate commands, addresses, data, etc.

[0018] The logic control circuit 13 receives external control signals from the memory controller 1 via the input / output terminals (or NAND bus). The external control signals include, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and a write protect signal WPn. The "n" added to a signal name indicates that the signal is active low.

[0019] The chip enable signal CEn enables selection of a semiconductor memory device 10 when multiple semiconductor memory devices 10 are implemented, and is asserted when the semiconductor memory device 10 is selected. The command latch enable signal CLE enables a command transmitted as the signal DQ to be latched in the command register 15C. The address latch enable signal ALE enables an address transmitted as the signal DQ to be latched in the address register 15B. The write enable signal WEn enables data transmitted as the signal DQ to be stored in the input / output circuit 12. The read enable signal REn enables data read from the memory cell array 11 to be output as the signal DQ. The write protect signal WPn is asserted when write and erase operations to the semiconductor memory device 10 are prohibited.

[0020] The ready / busy circuit 14 generates a ready / busy signal R / Bn in response to control from the sequencer 16. The ready / busy signal R / Bn indicates whether the semiconductor memory device 10 is in a ready state or a busy state. The ready state indicates that the semiconductor memory device 10 is in a state where it can accept commands from the memory controller 1. The busy state indicates that the semiconductor memory device 10 is in a state where it cannot accept commands from the memory controller 1. By receiving the ready / busy signal R / Bn from the semiconductor memory device 10, the memory controller 1 can know whether the semiconductor memory device 10 is in a ready state or a busy state.

[0021] The status register 15A stores status information STS necessary for the operation of the semiconductor memory device 10. The status register 15A transfers the status information STS to the input / output circuit 12 in accordance with an instruction from the sequencer 16.

[0022] The address register 15B stores the address ADD transferred from the input / output circuit 12. The address ADD includes a row address and a column address. The row address includes, for example, a block address specifying a block BLKn to be operated, and a page address specifying a word line WL to be operated in the specified block.

[0023] The command register 15C stores the command CMD transferred from the input / output circuit 12. The command CMD includes, for example, a write command instructing the sequencer 16 to perform a write operation, a read command instructing a read operation, and an erase command instructing an erase operation.

[0024] The status register 15A, the address register 15B, and the command register 15C are implemented by, for example, an SRAM (static random access memory).

[0025] The sequencer 16 receives a command from the command register 15C and controls the semiconductor memory device 10 in an integrated manner in accordance with a sequence based on this command.

[0026] The sequencer 16 controls the voltage generation circuit 17, row decoder 18, column decoder 19, data register 20, sense amplifier 21, etc. to perform write, read, and erase operations. Specifically, the sequencer 16 controls the voltage generation circuit 17, row decoder 18, data register 20, and sense amplifier 21 based on a write command received from the command register 15C to write data to multiple memory cell transistors specified by the address ADD. The sequencer 16 also controls the voltage generation circuit 17, row decoder 18, column decoder 19, data register 20, and sense amplifier 21 based on a read command received from the command register 15C to read data from the multiple memory cell transistors specified by the address ADD. The sequencer 16 also controls the voltage generation circuit 17, row decoder 18, column decoder 19, data register 20, and sense amplifier 21 based on an erase command received from the command register 15C to erase data stored in the block specified by the address ADD. The circuit including the column decoder 19 and the data register 20 is called a column control circuit.

[0027] The voltage generating circuit 17 receives a power supply voltage VDD and a ground voltage VSS via power supply terminals from outside the semiconductor memory device 10. The power supply voltage VDD is an external voltage supplied from outside the semiconductor memory device 10. The ground voltage VSS is an external voltage, such as 0 V, supplied from outside the semiconductor memory device 10.

[0028] The voltage generation circuit 17 generates a plurality of voltages required for write, read, and erase operations using the power supply voltage VDD. The voltage generation circuit 17 supplies the generated voltages to the memory cell array 11, the row decoder 18, the sense amplifier 21, etc.

[0029] The row decoder 18 receives a row address from the address register 15B and decodes the row address. Based on the result of decoding the row address, the row decoder 18 selects one of the blocks and selects a word line WL in the selected block BLKn. Furthermore, the row decoder 18 transfers the voltages supplied from the voltage generating circuit 17 to the selected block BLKn.

[0030] The column decoder 19 receives a column address from the address register 15B and decodes the column address, and selects a latch circuit in the data register 20 based on the result of decoding the column address.

[0031] The data register 20 includes a plurality of latch circuits, which temporarily store write data or read data.

[0032] During a data read operation, the sense amplifier 21 senses and amplifies data read from the memory cell transistor to the bit line. Furthermore, the sense amplifier 21 temporarily stores the read data DAT read from the memory cell transistor and transfers the stored read data DAT to the data register 20. During a data write operation, the sense amplifier 21 temporarily stores the write data DAT transferred from the input / output circuit 12 via the data register 20. Furthermore, the sense amplifier 21 transfers the write data DAT to the bit line.

[0033] Next, a description will be given of the circuit configuration of the memory cell array 11 in the semiconductor memory device 10 of the first embodiment. As described above, the memory cell array 11 has a plurality of blocks BLK0 to BLKn. The circuit configuration of block BLKn will be described below.

[0034] 2 is a circuit diagram of a block BLKn in the memory cell array 11. The block BLKn includes, for example, a plurality of string units SU0, SU1, SU2, and SU3. Hereinafter, when a string unit SU is referred to, it refers to each of the string units SU0 to SU3. The string unit SU includes a plurality of NAND strings (or memory strings) NS.

[0035] For ease of explanation, an example will be shown in which the NAND string NS includes, for example, eight memory cell transistors MT0, MT1, MT2, ..., MT7 and two select transistors ST1 and ST2. Hereinafter, when a memory cell transistor MT is referred to, it will refer to each of the memory cell transistors MT0 to MT7.

[0036] The memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a non-volatile manner. The memory cell transistors MT0 to MT7 are connected in series between the source of the select transistor ST1 and the drain of the select transistor ST2. The memory cell transistor MT can store one bit of data or two or more bits of data.

[0037] The gates of the select transistors ST1 included in the string unit SU0 are connected to a select gate line SGD0. Similarly, the gates of the select transistors ST1 of the string units SU1 to SU3 are connected to select gate lines SGD1 to SGD3, respectively. Each of the select gate lines SGD0 to SGD3 is independently controlled by a row decoder 18.

[0038] The gates of the multiple select transistors ST2 included in the string unit SU0 are connected to a select gate line SGS. Similarly, the gates of the select transistors ST2 of each of the string units SU1 to SU3 are connected to a select gate line SGS. Note that individual select gate lines SGS may be connected to the gates of the select transistors ST2 of the string units SU0 to SU3. The select transistors ST1 and ST2 are used to select the string unit SU in various operations.

[0039] The control gates of the memory cell transistors MT0 to MT7 included in the block BLKn are connected to word lines WL0 to WL7, respectively. Each of the word lines WL0 to WL7 is independently controlled by a row decoder 18.

[0040] Each of the bit lines BL0, BL1, BL2, ..., BLm (m is a natural number equal to or greater than 0) is connected to a plurality of blocks BLK0 to BLKn, and is connected to one NAND string NS in a string unit SU included in the block BLKn. That is, each of the bit lines BL0 to BLm is connected to the drains of the select transistors ST1 of a plurality of NAND strings NS in the same column among the NAND strings NS arranged in a matrix in the block BLKn. Also, the source line SL is connected to the plurality of blocks BLK0 to BLKn. That is, the source line SL is connected to the sources of the select transistors ST2 included in the block BLKn.

[0041] In other words, a string unit SU includes multiple NAND strings NS connected to different bit lines BL and the same select gate line SGD. A block BLKn includes multiple string units SU that share a word line WL. The memory cell array 11 also includes multiple blocks BLK0 to BLKn that share a bit line BL.

[0042] A block BLKn is, for example, a data erasure unit. That is, data stored in memory cell transistors MT included in a block BLKn is erased all at once. Data in multiple blocks is erased sequentially, one block at a time. Data in multiple blocks is erased simultaneously in parallel. Note that data may be erased in units of string units SU, or may be erased in units smaller than a string unit SU.

[0043] The multiple memory cell transistors MT that share a word line WL within one string unit SU are called a cell unit CU. A collection of 1-bit data stored in each of the multiple memory cell transistors MT included in a cell unit CU is called a page. The storage capacity of a cell unit CU changes depending on the number of bits of data stored in the memory cell transistors MT. For example, a cell unit CU stores 1 page of data when each memory cell transistor MT stores 1 bit of data, 2 pages of data when storing 2 bits of data, and 3 pages of data when storing 3 bits of data.

[0044] The write and read operations for the cell units CU are performed in units of pages, i.e., the read and write operations are performed collectively for multiple memory cell transistors MT connected to one word line WL arranged in one string unit SU.

[0045] The number of string units included in the block BLKn is not limited to SU0 to SU3 and can be set arbitrarily. The number of NAND strings NS included in the string unit SU, and the number of memory cell transistors and select transistors included in the NAND string NS can also be set arbitrarily. Furthermore, the memory cell transistors MT may be of a MONOS (metal-oxide-nitride-oxide-silicon) type that uses an insulating film as a charge storage layer, or may be of an FG (floating gate) type that uses a conductive layer as a charge storage layer.

[0046] 1.2 Structure of semiconductor memory device An example of the structure of a semiconductor memory device 10 according to a first embodiment will be described. In the drawings referred to below, the X direction corresponds to the extension direction of the word lines WL, the Y direction corresponds to the extension direction of the bit lines BL, and the Z direction corresponds to the direction perpendicular to the surface of the semiconductor substrate of the semiconductor memory device 10. Hatching is appropriately added to the plan view to make the drawing easier to understand. The hatching added to the plan view does not necessarily relate to the material or characteristics of the hatched components. In each of the plan view and cross-sectional view, wiring, contacts, interlayer insulating films, etc. are appropriately omitted to make the drawing easier to understand.

[0047] 1.2.1 Planar layout of semiconductor memory device An example of a planar layout of the semiconductor memory device 10 of the first embodiment will be described with reference to Fig. 3. Fig. 3 is a diagram showing the planar layout of the semiconductor memory device 10. Fig. 3 shows areas corresponding to blocks BLK0 and BLK1.

[0048] As shown in FIG. 3, the semiconductor memory device 10 includes a plurality of slits SLT and SHE, a plurality of memory pillars MP, a plurality of bit lines BL, and a plurality of contacts CC and CV.

[0049] A plurality of slits SLT and SHE are arranged in the Y direction. For example, three slits SHE are arranged between one slit SLT and another slit SLT. Each slit SLT and SHE extends along the X direction. Each slit SLT crosses the memory region MR and the lead-out regions (or staircase regions) HR1 and HR2. Each slit SHE crosses the memory region MR and the select gate lines SGD in the lead-out regions HR1 and HR2. That is, each slit SLT or SHE separates and insulates adjacent wiring layers (or conductive layers) via that slit SLT or SHE. Specifically, each slit SLT separates and insulates a plurality of wiring layers corresponding to the word lines WL0 to WL7 and the select gate lines SGD and SGS, respectively. Each slit SHE separates and insulates a plurality of wiring layers corresponding to the word lines WL0 to WL7 and the select gate lines SGD, respectively.

[0050] Each memory pillar MP functions as, for example, one NAND string NS. The memory pillars MP are arranged in, for example, four staggered rows in the memory region MR and in the region between adjacent slits SLT or SHE. In this example, each region separated by a slit SLT or SHE corresponds to one string unit SU. The number and arrangement of memory pillars MP between adjacent slits SLT or SHE can be changed as appropriate.

[0051] A plurality of bit lines BL are arranged in the X direction. Each bit line BL extends in the Y direction. Each bit line BL overlaps at least one memory pillar MP for each string unit SU. In this example, two bit lines BL overlap one memory pillar MP. A contact CV is provided between one of the plurality of bit lines BL overlapping the memory pillar MP and the memory pillar MP. Each memory pillar MP is connected to the associated bit line BL via the contact CV.

[0052] In each of the lead-out regions HR1 and HR2, the select gate line SGS, word lines WL0 to WL7, and select gate line SGD each have a portion that does not overlap with an upper wiring layer (or conductive layer). The shape of the portion that does not overlap with the upper wiring layer is called a terrace, step, rimstone, etc. Hereinafter, in this specification, the portion that does not overlap with the upper wiring layer will be called a terrace portion. Specifically, terrace portions are provided between the select gate line SGS and word line WL0, between word line WL0 and word line WL1, between word line WL1 and word line WL2, between word line WL2 and word line WL3, between word line WL3 and word line WL4, between word line WL4 and word line WL5, between word line WL5 and word line WL6, between word line WL6 and word line WL7, and between word line WL7 and select gate line SGD.

[0053] Each of the contacts CC is used to connect the word lines WL0 to WL7 and the select gate lines SGS and SGD to the row decoder 18. Each contact CC is arranged on a terrace portion of each of the word lines WL0 to WL7 and the select gate lines SGS and SGD. Here, an example has been shown in which the contacts CC on the terrace portions of the word lines WL0 to WL7 and the select gate line SGS are arranged in a line in the X direction, but they may also be arranged with a stagger in the Y direction.

[0054] For example, the contacts CC associated with block BLK0 are arranged in lead-out region HR1, and the contacts CC associated with block BLK1 are arranged in lead-out region HR2. In other words, for example, even-numbered blocks BLK are connected to the row decoder 18 via contacts CC in lead-out region HR1. Odd-numbered blocks BLK are connected to the row decoder 18 via contacts CC in lead-out region HR2.

[0055] In the planar layout of the semiconductor memory device 10, the above-described memory region MR and lead-out regions HR1 and HR2 are repeatedly arranged in the Y direction. The arrangement of the contacts CC for each block BLK is not limited to the above-described layout. For example, if one lead-out region HR is omitted, the contacts CC corresponding to each block BLK are arranged together in one lead-out region HR adjacent to the memory region MR. Furthermore, contacts CC may be arranged on both sides of the lead-out regions HR1 and HR2, and a voltage may be applied from both sides of each block BLK. The lead-out region HR may be arranged so as to be sandwiched between the memory regions MR.

[0056] 1.2.2 Cross-sectional structure of semiconductor memory device An example of the cross-sectional structure of the memory region MR in the semiconductor memory device 10 of the first embodiment will be described with reference to FIG. 4. FIG. 4 is a diagram for explaining the cross-sectional structure of the memory region MR in the semiconductor memory device 10. FIG. 4 shows a cross section along the Y direction, including memory pillars MP and slits SLT. The memory pillars MP in the semiconductor memory device 10 of the first embodiment have three layers of memory pillars, but FIG. 4 shows a case where the memory pillars MP consist of a single layer in order to make the structure of the memory pillars MP and their surroundings easier to understand. The structure of the three layers of memory pillars in the semiconductor memory device 10 and the word lines around them will be described later.

[0057] The memory region MR includes a semiconductor substrate 30, insulating layers 31 to 33, conductive layers 40 to 44, memory pillars MP, contacts CV, and slits SLT.

[0058] A conductive layer 40 is provided on the semiconductor substrate 30. The conductive layer 40 is formed, for example, in the shape of a plate extending along the XY plane and is used as the source line SL. The conductive layer 40 includes, for example, polysilicon doped with phosphorus.

[0059] An insulating layer 31 is provided on the conductive layer 40. A conductive layer 41 is provided on the insulating layer 31. The conductive layer 41 is formed, for example, in the shape of a plate extending along the XY plane and is used as the select gate line SGS. The conductive layer 41 includes, for example, tungsten or polysilicon doped with phosphorus. The select gate line SGS may be composed of multiple conductive layers 41. When the select gate line SGS is composed of multiple conductive layers 41, the multiple conductive layers 41 may be composed of different conductors.

[0060] On the conductive layer 41, insulating layers 32 and conductive layers 42 are alternately stacked. Each of the plurality of conductive layers 42 is formed, for example, in the shape of a plate extending along the XY plane. The plurality of conductive layers 42 are used as word lines WL0 to WL7, in order from the conductive layer 40 side. The conductive layer 42 contains, for example, tungsten. The insulating layer 32 is, for example, an oxide layer containing silicon oxide (SiO2).

[0061] A conductive layer 43 is provided on the uppermost insulating layer 32. The conductive layer 43 is formed, for example, in a plate shape extending along the XY plane and is used as a select gate line SGD. The select gate line SGD may be composed of multiple conductive layers 43. The conductive layer 43 includes, for example, tungsten.

[0062] An insulating layer 33 is provided on the conductive layer 43. A conductive layer 44 is provided on the insulating layer 33. The conductive layer 44 is formed, for example, in a line shape extending in the Y direction and is used as a bit line BL. In a region not shown, a plurality of conductive layers 44 are arranged in the X direction. The conductive layer 44 contains, for example, copper.

[0063] Each memory pillar MP extends along the Z direction. Each memory pillar MP penetrates the insulating layers 31 and 32 and the conductive layers 41 to 43. The lower part of the memory pillar MP contacts the conductive layer 40. The upper part of the memory pillar MP reaches the insulating layer 33.

[0064] Each memory pillar MP includes, for example, a semiconductor layer 50, a tunnel insulating layer (also referred to as a tunnel insulating film) 51, a charge storage layer (for example, an insulating layer) 52, and a block insulating layer 53.

[0065] The semiconductor layer 50 extends along the Z direction. For example, the lower end of the semiconductor layer 50 is in contact with the conductive layer 40. The upper end of the semiconductor layer 50 is included in a layer including the insulating layer 33. The tunnel insulating layer 51 is disposed on a side surface of the semiconductor layer 50. The charge storage layer 52 is disposed on a side surface of the tunnel insulating layer 51. The block insulating layer 53 is disposed on a side surface of the charge storage layer 52. Note that the memory pillar MP may have a structure in which a core insulating layer is provided inside the semiconductor layer 50.

[0066] The intersection of the memory pillar MP and the conductive layer 41 (i.e., the select gate line SGS) functions as a select transistor ST2. The intersection of the memory pillar MP and the plurality of conductive layers 42 (i.e., the word lines WL) functions as memory cell transistors MT0 to MT7. The intersection of the memory pillar MP and the conductive layer 43 (i.e., the select gate line SGD) functions as a select transistor ST1.

[0067] The semiconductor layer 50 functions as a channel layer for each of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. A current path for the NAND string NS is formed inside the semiconductor layer 50. The charge storage layer 52 functions as a layer that stores charge in the memory cell transistors MT.

[0068] A columnar contact CV is provided on the semiconductor layer 50 of each memory pillar MP. The illustrated region shows the contact CV corresponding to one of the two memory pillars MP. A contact CV is connected to the memory pillar MP to which the contact CV is not connected in the region described above in a region not shown. One conductive layer 44 (i.e., a bit line BL) is in contact with the contact CV.

[0069] The slit SLT includes, for example, a spacer SP and a contact LI. At least a portion of the slit SLT is formed in a plate shape extending along the XZ plane, and separates the insulating layers 31 and 32 and the conductive layers 41 to 43. The lower end of the slit SLT is in contact with, for example, the conductive layer 40. The upper end of the slit SLT is included in a layer including the insulating layer 33. In the slit SLT, at least a portion of the contact LI extends in the X direction. The spacer SP is provided on a side surface of the contact LI. The contact LI and the plurality of conductive layers 41 to 43 are separated and insulated by the spacer SP.

[0070] Next, the cross-sectional structure of the memory pillar MP provided in the memory region MR will be described. Fig. 5 shows a cross section taken along line VV in Fig. 4, illustrating a cross section of the memory pillar MP in a layer that is parallel to the surface of the semiconductor substrate 30 and includes the conductive layer 42.

[0071] As described above, the memory pillar MP has, for example, a semiconductor layer 50, a tunnel insulating layer 51, a charge storage layer 52, and a block insulating layer 53. Specifically, the semiconductor layer 50 is provided, for example, in the center of the memory pillar MP. The tunnel insulating layer 51 surrounds the side surfaces of the semiconductor layer 50. The charge storage layer 52 surrounds the side surfaces of the tunnel insulating layer 51. The block insulating layer 53 surrounds the side surfaces of the charge storage layer 52. The conductive layer 42 surrounds the side surfaces of the block insulating layer 53. Note that the memory pillar MP may have a structure in which a core insulating layer is provided inside the semiconductor layer 50.

[0072] The tunnel insulating layer 51 functions as a potential barrier when charges are injected from the semiconductor layer 50 into the charge storage layer 52, or when charges stored in the charge storage layer 52 diffuse into the semiconductor layer 50. The tunnel insulating layer 51 includes, for example, silicon oxide (SiO2).

[0073] The charge storage layer 52 has a function of storing charges injected into the memory cell transistors MT0 to MT7 from the semiconductor layer 50. The charge storage layer 52 includes, for example, silicon nitride (SiN).

[0074] The block insulating layer 53 prevents the charge stored in the charge storage layer 52 from diffusing into the conductive layer 42 (word line WL). The block insulating layer 53 includes, for example, an aluminum oxide layer, a silicon oxide layer, and a silicon nitride layer.

[0075] Next, an example of the cross-sectional structure of the lead-out region HR1 in the semiconductor memory device 10 of the first embodiment will be described with reference to Fig. 6. Fig. 6 is a diagram for explaining the cross-sectional structure of the lead-out region HR1 in the semiconductor memory device 10. Fig. 6 shows a cross section along the X direction of the region corresponding to the lead-out region HR1 and the even-numbered blocks BLK in Fig. 4.

[0076] In the lead-out region HR1, the ends of the select gate line SGS (conductive layer 41), the word lines WL0 to WL7 (conductive layer 42), and the select gate line SGD (conductive layer 43) are each provided in a stepped shape. Also provided in the lead-out region HR1 are, for example, contacts CC, contacts V1 and V2, and conductive layers 45, 46, and 47.

[0077] Specifically, the conductive layer 41 has a terrace portion that does not overlap with the upper conductive layers 42 and 43 in the Z direction. Each conductive layer 42 has a terrace portion that does not overlap with the upper conductive layers 42 and 43 in the Z direction. The conductive layer 43 has a terrace portion in the Z direction. A plurality of contacts CC are provided on the terrace portions of the conductive layers 41 to 43, respectively.

[0078] For example, a conductive layer 45 is provided on each contact CC. The conductive layer 45 is included in the wiring layer M0. A contact V1 is provided on the conductive layer 45. A conductive layer 46 is provided on the contact V1. The conductive layer 46 is included in the wiring layer M1. A contact V2 is provided on the conductive layer 46. A conductive layer 47 is provided on the contact V2. The conductive layer 47 is included in the wiring layer M2.

[0079] 6 shows only the pair of contacts V1 and V2 and conductive layers 46 and 47 provided in the conductive layer 45 corresponding to the word line WL3. The other conductive layers 45 are connected to the pair of contacts V1 and V2 and conductive layers 46 and 47 in regions not shown.

[0080] The structure in the region corresponding to the lead-out region HR1 and the odd-numbered blocks BLK is similar to a structure in which the contacts CC are omitted from the structure shown in Fig. 6. The structure in the region corresponding to the lead-out region HR2 and the odd-numbered blocks BLK is similar to a structure in which the structure shown in Fig. 6 is inverted with the YZ plane as the plane of symmetry.

[0081] 1.2.3 Memory Pillar and Wordline Structure Next, the structures of the memory pillars MP and word lines WL in the semiconductor memory device 10 of the first embodiment will be described in detail with reference to Figures 7 and 8. Figure 7 is a cross-sectional view showing an outline of the structure of the memory pillars MP and word lines in the semiconductor memory device 10. Figure 8 is a cross-sectional view showing the details of the structure of the memory pillars MP and word lines in the semiconductor memory device 10.

[0082] In the above-mentioned Figure 4, the memory pillar MP was simplified to one in order to explain the cross-sectional structure of the memory region MR, but in the semiconductor memory device 10 of this embodiment, as shown in Figures 7 and 8, the memory pillar MP can be structurally divided into three memory pillars, namely, a lower pillar LMP, a middle pillar MMP, and an upper pillar UMP.

[0083] In the cross section of the XZ plane or the YZ plane, the cross section of each of the lower pillar LMP, the intermediate pillar MMP, and the upper pillar UMP has a tapered shape that narrows from the top end to the bottom end, that is, from the bit line BL side toward the source line SL. The cross section of each of the upper ends of the lower pillar LMP, the intermediate pillar MMP, and the upper pillar UMP is thicker than the cross section of each of the lower ends.

[0084] The diameter of the lower end of the middle pillar MMP along the XY plane is larger than the diameter of the upper end of the lower pillar LMP along the XY plane. The boundary between the lower end of the middle pillar MMP and the upper end of the lower pillar LMP is the boundary between the middle pillar MMP and the lower pillar LMP. The diameter of the lower end of the upper pillar UMP along the XY plane is larger than the diameter of the upper end of the middle pillar MMP along the XY plane. The boundary between the lower end of the upper pillar UMP and the upper end of the middle pillar MMP is the boundary between the upper pillar UMP and the middle pillar MMP.

[0085] The lower pillar LMP, the intermediate pillar MMP, and the upper pillar UMP are stacked in the Z direction on the source line SL. A plurality of word lines stacked in the Z direction are provided around the lower pillar LMP, the intermediate pillar MMP, and the upper pillar UMP.

[0086] First, with reference to FIG. 7, an outline of the structure of the memory pillars MP and word lines WL in the semiconductor memory device 10 of the first embodiment will be described.

[0087] As shown in FIG. 7, source lines SL are provided above a semiconductor substrate 30. Select gate lines SGS are provided above the source lines SL. A dummy word line WLLD1 is provided above the select gate line SGS. A plurality of word lines WLL1, WLL2, ..., WLLi (i is an integer equal to or greater than 1) are stacked above the dummy word line WLLD1. Furthermore, a dummy word line WLLD2 is provided above the word line WLLi.

[0088] A dummy word line WLMD1 is provided above the dummy word line WLLD2. A plurality of word lines WLM1, WLM2, . . . WLMi are stacked above the dummy word line WLMD1. Furthermore, a dummy word line WLMD2 is provided above the word line WLMi.

[0089] The word lines WLM1 to WLMi are divided into lower word lines ML, middle word lines MM, and upper word lines MU from the dummy word line WLMD1 (or source line SL) side. The lower word lines ML include a plurality of word lines stacked directly above the dummy word line WLMD1. The middle word lines MM include a plurality of word lines stacked directly above the lower word lines ML. The upper word lines MU include a plurality of word lines stacked directly above the middle word lines MM.

[0090] The upper word lines MU are arranged near the upper ends of the intermediate pillars MMP, the lower word lines ML are arranged near the lower ends of the intermediate pillars MMP, and the middle word lines MM are arranged between the upper word lines MU and the lower word lines ML.

[0091] A dummy word line WLUD1 is provided above the dummy word line WLMD2. A plurality of word lines WLU1, WLU2, ..., WLUi are stacked above the dummy word line WLUD1. A dummy word line WLUD2 is provided above the word line WLUi. Furthermore, a select gate line SGD is provided above the dummy word line WLUD2.

[0092] The word lines WLU1 to WLUi are divided into lower word lines UL, middle word lines UM, and upper word lines UU from the dummy word line WLUD1 (or source line SL) side. The lower word lines UL include a plurality of word lines stacked directly above the dummy word lines WLUD1. The middle word lines UM include a plurality of word lines stacked directly above the lower word lines UL. The upper word lines UU include a plurality of word lines stacked directly above the middle word lines UM.

[0093] The upper word line UU is located near the top end of the upper pillar UMP, the lower word line UL is located near the boundary between the upper pillar UMP and the middle pillar MMP, and the middle word line UM is located between the upper word line UU and the lower word line UL.

[0094] The word lines WLL1 to WLLi, WLM1 to WLMi, and WLU1 to WLUi are each electrically connected to the row decoder 18 via contacts CC, other contacts, and conductive layers. The select gate lines SGD and SGS are each electrically connected to the row decoder 18 via contacts CC, other contacts, and conductive layers. The dummy word lines are not electrically connected to the row decoder 18.

[0095] On the source line SL, a lower pillar LMP, an intermediate pillar MMP, and an upper pillar UMP extending in the Z direction are stacked in this order in the Z direction. Specifically, the lower pillar LMP is provided on the source line SL. On the lower pillar LMP, an intermediate pillar MMP is provided in the Z direction. On the intermediate pillar MMP, an upper pillar UMP is provided in the Z direction. That is, the lower end of the lower pillar LMP is connected to the source line SL, and the lower end of the intermediate pillar MMP is connected to the upper end of the lower pillar LMP. Furthermore, the lower end of the upper pillar UMP is connected to the upper end of the intermediate pillar MMP.

[0096] The lower pillar LMP penetrates in the Z direction the select gate line SGS, the dummy word line WLLD1, the word lines WLL1 to WLLi, and the dummy word line WLLD2, which are stacked in the Z direction. In other words, the select gate line SGS, the dummy word line WLLD1, the word lines WLL1 to WLLi, and the dummy word line WLLD2, which are stacked in the Z direction, are arranged around the lower pillar LMP, which extends in the Z direction, in the X and Y directions.

[0097] The intermediate pillar MMP penetrates in the Z direction through the dummy word line WLMD1, the multiple word lines WLM1-WLMi, and the dummy word line WLMD2, which are stacked in the Z direction. In other words, the dummy word line WLMD1, the multiple word lines WLM1-WLMi, and the dummy word line WLMD2, which are stacked in the Z direction, are arranged around the intermediate pillar MMP, which extends in the Z direction, in the X and Y directions.

[0098] The upper pillar UMP penetrates in the Z direction through the dummy word line WLUD1, the multiple word lines WLU1 to WLUi, the dummy word line WLUD2, and the select gate line SGD, which are stacked in the Z direction. In other words, the dummy word line WLUD1, the multiple word lines WLU1 to WLUi, the dummy word line WLUD2, and the select gate line SGD, which are stacked in the Z direction, are arranged around the upper pillar UMP, which extends in the Z direction, in the X and Y directions.

[0099] The film thickness of the word lines WL provided around the lower pillars LMP, the middle pillars MMP, and the upper pillars UMP will be described below.

[0100] Among the word lines WLU1-WLUi and word lines WLM1-WLMi arranged around the upper pillar UMP and the middle pillar MMP, the thickness of each of the upper word lines UU, lower word lines UL, and upper word lines MU is thicker than the thickness of each of the middle word lines UM. The thicknesses of each of the upper word lines UU, lower word lines UL, and upper word lines MU are approximately equal, i.e., substantially the same. The thickness of each of the middle word lines MM and lower word lines ML is approximately equal, i.e., substantially the same, as the thickness of each of the middle word lines UM.

[0101] The thickness of each of the dummy word lines WLUD1, WLUD2, and WLMD2 is thicker than the thickness of each of the middle word lines UM. The thickness of each of the dummy word lines WLUD1, WLUD2, and WLMD2 is approximately equal to the thickness of each of the upper word lines UU, lower word lines UL, and upper word lines MU.

[0102] The select gate line SGD is thicker than the upper word line UU and the lower word line UL, and the dummy word line WLMD1 is approximately the same as the middle word line UM.

[0103] The word lines WLL1-WLLi arranged around the lower pillar LMP have a thickness that is approximately equal to, i.e., the same as, the thickness of each of the middle word lines UM. Similarly, the dummy word lines WLLD1 and WLLD2 have a thickness that is approximately equal to, i.e., the same as, the thickness of each of the middle word lines UM. Furthermore, the select gate line SGS has a thickness that is thicker than the thickness of each of the upper word lines UU and lower word lines UL.

[0104] Although the above description shows a case where three memory pillars, i.e., a lower pillar LMP, a middle pillar MMP, and an upper pillar UMP, are stacked, this is not a limitation, and two or four or more memory pillars may be stacked. Also, while the above description shows a case where the number of word lines provided around each of the lower pillar LMP, the middle pillar MMP, and the upper pillar UMP is equal to i, this is not a limitation. The number of word lines provided around each of the lower pillar LMP, the middle pillar MMP, and the upper pillar UMP may be different.

[0105] Next, the structure of the memory pillars MP and word lines WL in the semiconductor memory device 10 of the first embodiment will be described in detail with reference to Fig. 8. In Fig. 8, the interlayer insulating layers between the conductive layers are omitted.

[0106] 8, a conductive layer 40 is provided above a semiconductor substrate 30 via an insulating layer. The conductive layer 40 is formed in a flat plate shape along the XY plane. The conductive layer 40 functions as a source line SL. The main surface of the semiconductor substrate 30 or the conductive layer 40 corresponds to the XY plane.

[0107] On the conductive layer 40, a plurality of slits SLT are arranged in the X direction along the YZ plane. A structure on the conductive layer 40 and between adjacent slits SLT corresponds to, for example, one string unit SU. Specifically, on the conductive layer 40 and between adjacent slits SLT, a conductive layer 41, a plurality of conductive layers 42a, a plurality of conductive layers 42b, a conductive layer 43, and a conductive layer 44 are provided in this order from bottom to top. Of these conductive layers, adjacent conductive layers in the Z direction are stacked with an interlayer insulating film interposed between them. Each of the conductive layers 41, 42a, 42b, 43, and 44 is formed in a flat plate shape along the XY plane.

[0108] The memory pillars MP (including pillars LMP, MMP, and UMP) are arranged, for example, in a staggered pattern in the Y direction (not shown). Each of the memory pillars MP functions as one NAND string NS. Each memory pillar MP, i.e., the stacked lower pillar LMP, middle pillar MMP, and upper pillar UMP, is provided to penetrate the conductive layers 41, 42a, 42b, and 43 so as to reach the upper surface of the conductive layer 43 from the upper surface of the conductive layer 40.

[0109] The lower pillar LMP is provided on the conductive layer 40. A junction JT1 is provided between the lower pillar LMP and the middle pillar MMP. The middle pillar MMP is joined to the lower pillar LMP via the junction JT1. A junction JT2 is provided between the middle pillar MMP and the upper pillar UMP. The upper pillar UMP is joined to the middle pillar MMP via the junction JT2.

[0110] A conductive layer 41 provided around the lower pillar LMP functions as a select gate line SGS. A plurality of conductive layers 42a around the lower pillar LMP function, in order from the bottom up, as a dummy word line WLLD1, word lines WLL1 to WLLi, and a dummy word line WLLD2, respectively.

[0111] The multiple conductive layers 42a provided around the intermediate pillar MMP function, from the bottom up, as a dummy word line WLMD1 and word lines WLM1 to WLMi-2, respectively. The multiple conductive layers 42b around the intermediate pillar MMP function, from the bottom up, as word lines WLMi-1, WLMi, and a dummy word line WLMD2, respectively.

[0112] The multiple conductive layers 42b provided around the upper pillar UMP function, from the bottom up, as a dummy word line WLUD1, word lines WLU1, and WLU2, respectively. The multiple conductive layers 42a around the upper pillar UMP function, from the bottom up, as word lines WLU3 to WLUi-2, respectively, and the multiple conductive layers 42b function as word lines WLUi-1, WLUi, and a dummy word line WLUD2, respectively. Furthermore, the conductive layer 43 around the upper pillar UMP functions as a select gate line SGD.

[0113] The intersection of the lower pillar LMP and the select gate line SGS functions as a select transistor ST2. The intersection of the lower pillar LMP and the dummy word lines WLLD1 and WLLD2 functions as a dummy transistor. Each dummy transistor is a memory cell in which data is not stored. The intersection of the lower pillar LMP and the word lines WLL1 to WLLi functions as a memory cell transistor. Each memory cell transistor is a memory cell in which data is stored or can be stored.

[0114] The intersections of the middle pillar MMP and the dummy word lines WLMD1 and WLMD2 function as dummy transistors. Each dummy transistor is a transistor in which data is not stored. The intersections of the middle pillar MMP and the word lines WLM1 to WLMi function as memory cell transistors. Each memory cell transistor is a memory cell in which data is stored or can be stored.

[0115] The intersections of the upper pillar UMP and the dummy word lines WLUD1 and WLUD2 function as dummy transistors. Each dummy transistor is a transistor in which data is not stored. The intersections of the upper pillar UMP and the word lines WLU1 to WLUi function as memory cell transistors. Each memory cell transistor is a memory cell in which data is stored or can be stored. Furthermore, the intersections of the upper pillar UMP and the select gate line SGD function as select transistor ST1.

[0116] A conductive layer 44 is provided above the upper pillar UMP via an interlayer insulating film. The conductive layer 44 is formed in a line shape extending in the X direction and functions as a bit line (or wiring layer) BL. A plurality of conductive layers 44 are arranged in the Y direction (not shown). Each conductive layer 44 is electrically connected to one memory pillar MP corresponding to each string unit SU. Specifically, in each string unit SU, a contact BLC is provided on the semiconductor layer 50 in each memory pillar MP, and one conductive layer 44 is provided on the contact BLC. The contact BLC includes a conductive layer, for example, tungsten.

[0117] The numbers of word lines WL, dummy word lines, and select gate lines SGD and SGS are changed according to the numbers of memory cell transistors MT, dummy transistors, and select transistors ST1 and ST2, respectively. The select gate lines SGS may be formed of multiple conductive layers each provided in multiple layers. The select gate lines SGD may be formed of multiple conductive layers each provided in multiple layers.

[0118] In the above-described structure, as mentioned above, the thickness of each of the upper word lines UU, lower word lines UL, and upper word lines MU is thicker than the thickness of each of the middle word lines UM, and the thickness of the other word lines except for the upper word lines UU, lower word lines UL, and upper word lines MU is approximately equal to the thickness of each of the middle word lines UM.

[0119] The thickness of each of the dummy word lines WLUD1, WLUD2, and WLMD2 is thicker than the thickness of each of the middle word lines UM. The thickness of the other dummy word lines other than the dummy word lines WLUD1, WLUD2, and WLMD2 is approximately equal to the thickness of each of the middle word lines UM.

[0120] The film thickness of each of the select gate lines SGD and SGS is thicker than the film thickness of each of the upper word lines UU and lower word lines UL.

[0121] For example, the number of word lines WLL1-WLLi provided around the lower pillar LMP is several hundred. Similarly, the number of word lines WLM1-WLMi provided around the middle pillar MMP is several hundred. The number of word lines WLU1-WLUi provided around the upper pillar UMP is several hundred.

[0122] The number of word lines included in the upper-layer word lines UU is, for example, 5 to 30, and preferably 5 to 10. Similarly, the number of word lines included in the lower-layer word lines UL is, for example, 5 to 30, and preferably 5 to 10. The number of word lines included in the upper-layer word lines MU is also 5 to 30, and preferably 5 to 10. That is, the number of word lines included in the upper-layer word lines UU, the number of word lines included in the lower-layer word lines UL, and the number of word lines included in the upper-layer word lines MU are each at least 5.

[0123] The word lines WLU1 to WLUi each have a thickness of, for example, 20 to 30 nm. Similarly, the word lines WLM1 to WLMi each have a thickness of, for example, 20 to 30 nm. The word lines WLL1 to WLLi each have a thickness of, for example, 20 to 30 nm. The dummy word lines WLUD1, WLUD2, WLMD1, WLMD2, WLLD1, and WLLD2 each have a thickness of, for example, 20 to 30 nm.

[0124] In this embodiment, the thickness of the thickened word lines is set to be approximately 0.5 to 3 nm thicker than the thickness of the non-thickened word lines. For example, if the thickness of the word lines included in the middle word lines UM is 20 nm, the thickness of the word lines included in the upper word lines UU is 20.5 to 23 nm. If the thickness of the word lines included in the middle word lines UM is 25 nm, the thickness of the word lines included in the upper word lines UU is 25.5 to 28 nm.

[0125] Similarly, for example, if the thickness of the word lines included in the middle word lines UM is 20 nm, the thickness of the word lines included in the lower word lines UL is 20.5 to 23 nm. If the thickness of the word lines included in the middle word lines UM is 25 nm, the thickness of the word lines included in the lower word lines UL is 25.5 to 28 nm.

[0126] For example, if the thickness of the word lines included in the middle word lines UM is 20 nm, the thickness of the word lines included in the upper word lines MU is 20.5 to 23 nm. If the thickness of the word lines included in the middle word lines UM is 25 nm, the thickness of the word lines included in the upper word lines MU is 25.5 to 28 nm.

[0127] The same is true for the thicknesses of the dummy word lines WLUD1, WLUD2, and WLMD2. When the thickness of the word lines included in the middle word lines UM is 20 nm, the thickness of each of the dummy word lines WLUD1, WLUD2, and WLMD2 is 20.5 to 23 nm. When the thickness of the word lines included in the middle word lines UM is 25 nm, the thickness of each of the dummy word lines WLUD1, WLUD2, and WLMD2 is 25.5 to 28 nm.

[0128] The thickness of each of the select gate lines SGD and SGS is thicker than the thickness of each of the word lines included in the upper word line UU, the lower word line UL, and the upper word line MU. The thickness of each of the select gate lines SGD and SGS is, for example, 30 to 40 nm.

[0129] 1.3 Contact manufacturing method Next, a description will be given of a manufacturing method of the contacts CC formed in the lead-out region HR1 of the semiconductor memory device 10 of the first embodiment. The contacts CC are formed on terrace portions provided at the ends of the word lines WL and the select gate lines SGD and SGS in the lead-out region HR1.

[0130] 9 is a flowchart showing a method for manufacturing the contacts CC in the semiconductor memory device 10 of the first embodiment. 10 to 14 are cross-sectional views showing the method for manufacturing the contacts CC in the semiconductor memory device 10.

[0131] First, as shown in FIG. 10, an insulating layer, for example, an oxide layer 31, is formed above a semiconductor substrate 30 using, for example, CVD (Chemical Vapor Deposition). Further, insulating layers, for example, oxide layers 32 and nitride layers 61 are alternately stacked (S1). The nitride layers 61 are sacrificial layers that replace the conductive layers that become the word lines and select gate lines in a replacement process described later. In this process, the nitride layers 61 corresponding to the word lines to be thickened (i.e., the upper word line UU, the lower word line UL, and the upper word line MU) are formed thicker than the other nitride layers. The oxide layers 31 and 32 contain, for example, silicon oxide (SiO2). The nitride layer 61 contains, for example, silicon nitride (SiN).

[0132] Next, as shown in Fig. 11, a staircase structure is formed in the oxide layers 31, 32 and the nitride layer 61 using a slimming method or the like, which involves repeatedly reducing the mask area and performing anisotropic etching, such as RIE (Reactive Ion Etching) (S2). In this process, the oxide layers 31, 32 and the nitride layer 61 are processed into a staircase shape, with one set of one oxide layer and one nitride layer forming one step. Thereafter, the insulating layer 33 is formed.

[0133] Next, a memory pillar MP (not shown) (see the MP shown in FIG. 3) is formed in the oxide layers 31, 32 and the nitride layer 61 in the memory region MR (S3). The memory pillar MP is formed to penetrate the oxide layers 31, 32 and the nitride layer 61 in the memory region MR in the Z direction.

[0134] Next, for example, using RIE, grooves for forming slits SLT (not shown) (see SLT shown in FIG. 3) are processed in the oxide layers 31 and 32 and the nitride layer 61 in the memory region MR (S4). The grooves are holes along the XZ plane, and a cross section of the nitride layer 61 is exposed in the grooves.

[0135] Next, as shown in FIG. 12, the nitride layer 61 is replaced with a conductive layer using, for example, a replacement process to form the word lines WL and the select gate lines SGS and SGD (S5). The replacement process is a process of replacing the nitride layer 61 with a conductive layer. Specifically, first, the nitride layer 61 is removed through the trenches by wet etching. Next, a conductive layer is formed in the gaps where the nitride layer 61 was removed, using, for example, CVD. After that, a process such as etch-back is performed to form a conductive layer 42 as the word lines WL, a conductive layer 41 as the select gate lines SGS, and a conductive layer 43 as the select gate lines SGD. The conductive layers 41, 42, and 43 contain, for example, tungsten.

[0136] 13, contact holes 71 for forming contacts CC are processed in the insulating layer 33 (S6). Specifically, for example, RIE is used to etch the insulating layer 33 on the terrace portions provided at the ends of the conductive layers 41, 42, and 43 to form the contact holes 71. When forming the contact holes 71, since the word lines WL are formed thick in the thickened word lines (i.e., the upper word lines UU, the lower word lines UL, and the upper word lines MU), it is possible to prevent the contact holes 71 from penetrating the word lines WL and reaching the word lines WL below or reaching close to the word lines WL below.

[0137] Next, as shown in FIG. 14, a conductive layer is buried in the contact holes 71 to form contacts CC (S7). Specifically, a conductive layer is formed in the contact holes 71 using, for example, CVD. Thereafter, excess conductive layer is removed using, for example, CMP (Chemical Mechanical Polishing), to form contacts CC. Each contact CC contacts the conductive layer 42, or 41, 43, at the terrace portion. As a result, each contact CC is electrically connected to the conductive layer 42, or 41, 43. This completes the manufacture of the contacts CC.

[0138] Thereafter, conductive layers 45, 46, and 47, contacts V1 and V2, an insulating layer 33, etc. are formed, and the contact CC is connected to the row decoder 18. As a result, the word lines WL and the select gate lines SGS and SGD are electrically connected to the row decoder 18 via the contact CC, the conductive layers 45, 46, and 47, and the contacts V1 and V2.

[0139] 1.4 Effects of the First Embodiment According to the first embodiment, it is possible to provide a semiconductor memory device that can improve the reliability of its operation.

[0140] The effects of the first embodiment will be described below. For example, in a semiconductor memory device, multiple word lines are stacked in the Z direction on a substrate, and a row decoder is provided to supply voltage to the word lines. Memory pillars are provided in the Z direction so as to penetrate the multiple word lines. Contacts CC are formed at the ends of each word line to connect the word line to the row decoder.

[0141] When forming contact CCs, the contact holes may penetrate the target word lines and reach the word lines located below or near the word lines when processing the contact holes to form the contact CCs. In such cases, problems such as short-circuiting between the upper and lower word lines may occur before or after shipment.

[0142] In the first embodiment, among the multiple stacked word lines WL, the word lines in some layers where the above-mentioned defects are likely to occur, i.e., the upper word lines UU around the upper pillars UMP, the lower word lines UL, and the upper word lines MU around the middle pillars MMP, are made thicker. That is, the word lines WL included in the upper word lines UU, the word lines WL included in the lower word lines UL, and the word lines WL included in the upper word lines MU are made thicker than the word lines WL included in the middle word lines UM.

[0143] This prevents the contact hole from penetrating the target word line WL and reaching the word line WL below, or reaching the vicinity of the word line WL below, during contact hole processing, thereby reducing the occurrence of the above-mentioned problems.

[0144] As described above, according to the semiconductor memory device 10 of the first embodiment, it is possible to reduce defects such as short circuits occurring between the upper and lower word lines WL, thereby improving the reliability of operation.

[0145] 2. Second embodiment A semiconductor memory device according to a second embodiment will be described. In the second embodiment, an example in which the upper word lines UU provided around the upper pillars UMP are formed to have a large film thickness will be described. In the second embodiment, differences from the first embodiment will be mainly described.

[0146] 2.1 Memory pillar and word line structure The structures of the memory pillars MP and word lines WL in the semiconductor memory device 10 of the second embodiment will be described with reference to Figures 15 and 16. Figure 15 is a cross-sectional view showing an overview of the structure of the memory pillars MP and word lines in the semiconductor memory device 10. Figure 16 is a cross-sectional view showing the details of the structure of the memory pillars MP and word lines in the semiconductor memory device 10.

[0147] The film thickness of the word lines WL provided around the lower pillars LMP, the middle pillars MMP, and the upper pillars UMP will be described below.

[0148] 15 and 16, among the word lines WLU1-WLUi and word lines WLM1-WLMi provided around the upper pillar UMP and the middle pillar MMP, the thickness of each upper word line UU is thicker than the thickness of each middle word line UM. The thicknesses of the middle word line UM, lower word line UL, upper word line MU, middle word line MM, and lower word line ML are approximately the same.

[0149] The thickness of the dummy word line WLUD2 is thicker than the thickness of each of the middle word lines UM. The thickness of the dummy word line WLUD2 is approximately equal to, i.e., the same as, the thickness of each of the upper word lines UU. The thickness of each of the dummy word lines WLUD1, WLMD1, and WLMD2 is approximately equal to, i.e., the same as, the thickness of each of the middle word lines UM. In addition, the thickness of the select gate line SGD is thicker than the thickness of each of the upper word lines UU.

[0150] The word lines WLL1-WLLi arranged around the lower pillar LMP have a thickness that is approximately equal to, i.e., the same as, the thickness of each of the middle word lines UM. Similarly, the dummy word lines WLLD1 and WLLD2 have a thickness that is approximately equal to, i.e., the same as, the thickness of each of the middle word lines UM. Furthermore, the select gate line SGS has a thickness that is thicker than the thickness of each of the upper word lines UU.

[0151] In this embodiment, the thickness of the thickened word lines is set to be approximately 0.5 to 3 nm thicker than the thickness of the non-thickened word lines. For example, if the thickness of the word lines included in the middle word lines UM is 20 nm, the thickness of the word lines included in the upper word lines UU is 20.5 to 23 nm. If the thickness of the word lines included in the middle word lines UM is 25 nm, the thickness of the word lines included in the upper word lines UU is 25.5 to 28 nm.

[0152] The same applies to the film thickness of the dummy word line WLUD2. When the film thickness of the word line included in the middle word line UM is 20 nm, the film thickness of the dummy word line WLUD2 is 20.5 to 23 nm. When the film thickness of the word line included in the middle word line UM is 25 nm, the film thickness of the dummy word line WLUD2 is 25.5 to 28 nm.

[0153] 2.2 Variations Modifications 1 and 2 of the second embodiment will be described below.

[0154] 17, the structure of the word lines WL in Modification 1 will be described. Modification 1 is an example in which the upper word lines UU are formed thick, and in addition, the lower word lines UL are formed thick.

[0155] 17 is a cross-sectional view showing an outline of the structure of memory pillars and word lines in Modification 1. Of the word lines WLU1-WLUi and word lines WLM1-WLMi provided around the upper pillar UMP and middle pillar MMP, the thickness of each of the upper word lines UU and lower word lines UL is thicker than the thickness of each of the middle word lines UM. The thicknesses of the upper word lines UU and lower word lines UL are approximately equal, i.e., substantially the same. Furthermore, the thicknesses of the middle word lines UM, upper word lines MU, middle word lines MM, and lower word lines ML are approximately equal, i.e., substantially the same.

[0156] The thickness of each of the dummy word lines WLUD1 and WLUD2 is thicker than the thickness of each of the middle word lines UM. The thickness of each of the dummy word lines WLUD1 and WLUD2 is approximately equal to, i.e., the same as, the thickness of each of the upper word lines UU. The thickness of each of the dummy word lines WLMD1 and WLMD2 is approximately equal to, i.e., the same as, the thickness of each of the middle word lines UM. In addition, the thickness of the select gate line SGD is thicker than the thickness of each of the upper word lines UU.

[0157] The word lines WLL1-WLLi arranged around the lower pillar LMP have a thickness that is approximately equal to, i.e., the same as, the thickness of each of the middle word lines UM. Similarly, the dummy word lines WLLD1 and WLLD2 have a thickness that is approximately equal to, i.e., the same as, the thickness of each of the middle word lines UM. Furthermore, the select gate line SGS has a thickness that is thicker than the thickness of each of the upper word lines UU.

[0158] 18, the structure of the word lines WL in Modification 2 will be described. Modification 2 is an example in which the upper word lines UU are formed to have a large thickness, and in addition, the upper word lines MU provided around the intermediate pillars MMP are also formed to have a large thickness.

[0159] 18 is a cross-sectional view showing an outline of the structure of memory pillars and word lines in Modification 2. Of the word lines WLU1-WLUi and word lines WLM1-WLMi provided around the upper pillar UMP and middle pillar MMP, the thickness of each of the upper word lines UU and MU is thicker than the thickness of each of the middle word lines UM. The thicknesses of the upper word lines UU and upper word lines MU are approximately equal, i.e., substantially the same. Furthermore, the thicknesses of the middle word lines UM, lower word lines UL, middle word lines MM, and lower word lines ML are approximately equal, i.e., substantially the same.

[0160] The thickness of each of the dummy word lines WLUD2 and WLMD2 is thicker than the thickness of each of the middle word lines UM. The thicknesses of the dummy word lines WLUD2 and WLMD2 are approximately equal, i.e., are substantially the same. The thickness of each of the dummy word lines WLUD1 and WLMD1 is approximately equal, i.e., are substantially the same, as the thickness of each of the middle word lines UM. In addition, the thickness of the select gate line SGD is thicker than the thickness of each of the upper word lines UU.

[0161] The word lines WLL1-WLLi arranged around the lower pillar LMP have a thickness that is approximately equal to, i.e., the same as, the thickness of each of the middle word lines UM. Similarly, the dummy word lines WLLD1 and WLLD2 have a thickness that is approximately equal to, i.e., the same as, the thickness of each of the middle word lines UM. Furthermore, the select gate line SGS has a thickness that is thicker than the thickness of each of the upper word lines UU.

[0162] 2.3 Effects of the second embodiment According to the second embodiment, it is possible to provide a semiconductor memory device that can improve the reliability of its operation.

[0163] The effects of the second embodiment will be described below. In the second embodiment, among the multiple stacked word lines WL, the word lines in some layers where defects such as short circuits between the word lines above and below are likely to occur, i.e., the upper-layer word lines UU around the upper pillar UMP, are made thicker. That is, the word lines WL included in the upper-layer word lines UU are made thicker than the word lines WL included in the middle-layer word lines UM. This prevents the contact holes from penetrating the target word lines WL and reaching the word lines WL below, or from reaching the vicinity of the word lines WL below, during contact hole processing, thereby reducing the occurrence of the above-mentioned defects.

[0164] In Modification 1, among the multiple stacked word lines WL, the word lines in some layers where defects such as short circuits between the upper and lower word lines are likely to occur, i.e., the upper word lines UU and lower word lines UL around the upper pillar UMP, are made thicker. That is, the word lines WL included in the upper word lines UU and the word lines WL included in the lower word lines UL are made thicker than the word lines WL included in the middle word lines UM.

[0165] In Modification 2, among the multiple stacked word lines, the word lines in some layers where defects such as short circuits between the word lines above and below are likely to occur, i.e., the upper word lines UU around the upper pillar UMP and the upper word lines MU around the middle pillar MMP, are made thicker. That is, the word lines WL included in the upper word lines UU and the word lines WL included in the upper word lines MU are made thicker than the word lines WL included in the middle word lines UM.

[0166] This prevents the contact hole from penetrating the target word line WL and reaching the word line WL below, or reaching the vicinity of the word line WL below, during contact hole processing, thereby reducing the occurrence of the above-mentioned problems.

[0167] As described above, according to the semiconductor memory device 10 of the second embodiment and the modified example, it is possible to reduce defects such as short circuits occurring between the upper and lower word lines WL, and to improve the reliability of operation.

[0168] 3. Third embodiment A semiconductor memory device according to a third embodiment will be described. In the third embodiment, an example will be described in which the thicknesses of the upper word lines UU, middle word lines UM, and lower word lines UL around the upper pillar UMP are gradually reduced. In the third embodiment, differences from the first embodiment will be mainly described.

[0169] 3.1 Memory pillar and word line structure The structures of the memory pillars MP and word lines WL in the semiconductor memory device 10 of the third embodiment will be described with reference to Figures 19 and 20. Figure 19 is a cross-sectional view showing an outline of the structure of the memory pillars MP and word lines in the semiconductor memory device 10. Figure 20 is a cross-sectional view showing the details of the structure of the memory pillars MP and word lines in the semiconductor memory device 10.

[0170] The film thickness of the word lines WL provided around the lower pillars LMP, the middle pillars MMP, and the upper pillars UMP will be described below.

[0171] 19 and 20, in the word lines WLU1-WLUi and word lines WLM1-WLMi, the thickness of each upper word line UU is thicker than the thickness of each middle word line UM. The thickness of each middle word line UM is thicker than the thickness of each lower word line UL. That is, the thicknesses of the upper word line UU, middle word line UM, and lower word line UL become gradually thinner in the order described.

[0172] The thickness of each upper word line MU is approximately equal to, i.e., the same as, the thickness of each lower word line UL. The thickness of each upper word line MU, middle word line MM, and lower word line ML is approximately equal to, i.e., the same as, the thickness of each lower word line UL.

[0173] The thickness of the dummy word line WLUD2 is thicker than the thickness of each of the middle word lines UM. The thickness of the dummy word line WLUD2 is approximately equal to, i.e., the same as, the thickness of each of the upper word lines UU. The thickness of each of the dummy word lines WLUD1, WLMD1, and WLMD2 is approximately equal to, i.e., the same as, the thickness of each of the upper word lines MU. In addition, the thickness of the select gate line SGD is thicker than the thickness of each of the upper word lines UU.

[0174] The film thickness of each of the word lines WLL1-WLLi provided around the lower pillar LMP is approximately equal to, i.e., substantially the same as, the film thickness of each of the upper word lines MU. Similarly, the film thickness of each of the dummy word lines WLLD1 and WLLD2 is approximately equal to, i.e., substantially the same as, the film thickness of each of the upper word lines MU. Furthermore, the film thickness of the select gate line SGS is thicker than the film thickness of each of the upper word lines UU. Note that the film thickness of each of the upper word lines MU may be set thinner than the film thickness of each of the lower word lines UL.

[0175] In this embodiment, the thickness of the thickened word lines is set to be approximately 0.5 to 3 nm thicker than the thickness of the non-thickened word lines. For example, if the thickness of the word lines included in the lower word lines UL is 20 nm, the thickness of the word lines included in the middle word lines UM is 20.5 to 23 nm, and the thickness of the word lines included in the upper word lines UU is 21 to 26 nm. If the thickness of the word lines included in the lower word lines UL is 25 nm, the thickness of the word lines included in the middle word lines UM is 25.5 to 28 nm, and the thickness of the word lines included in the upper word lines UU is 26 to 31 nm.

[0176] The thickness of the dummy word line WLUD2 is approximately equal to the thickness of each of the upper word lines UU. When the thickness of the word line included in the lower word line UL is 20 nm, the thickness of the dummy word line WLUD2 is 21 to 26 nm. When the thickness of the word line included in the lower word line UL is 25 nm, the thickness of the dummy word line WLUD2 is 26 to 31 nm.

[0177] 3.2 Effects of the third embodiment According to the third embodiment, it is possible to provide a semiconductor memory device that can improve the reliability of its operation.

[0178] The effects of the third embodiment will be described below. In the third embodiment, among the multiple stacked word lines WL, the word lines in some layers where defects such as short circuits are likely to occur between the word lines above and below, i.e., the upper word lines UU, middle word lines UM, and lower word lines UL around the upper pillar UMP, are gradually made thinner. In other words, the film thickness is gradually increased from the lower word lines UL to the middle word lines UM and then to the upper word lines UU. That is, the word lines WL included in the upper word lines UU are made thicker than the word lines WL included in the middle word lines UM. Furthermore, the word lines WL included in the middle word lines UM are made thicker than the word lines WL included in the lower word lines UL.

[0179] This prevents the contact hole from penetrating the target word line WL and reaching the word line WL below, or reaching the vicinity of the word line WL below, during contact hole processing, thereby reducing the occurrence of the above-mentioned problems.

[0180] As described above, according to the semiconductor memory device 10 of the third embodiment, it is possible to reduce defects such as short circuits occurring between the upper and lower word lines WL, thereby improving the reliability of operation.

[0181] 4.Other In the above embodiment, a NAND flash memory is used as an example of the semiconductor memory device, but the present invention is not limited to a NAND flash memory, and can be applied to other semiconductor memories in general that have a structure similar to that of the lead-out region described in the embodiment, and can also be applied to various semiconductor devices other than semiconductor memories. Also, the order of the processes in the flowcharts described in the above embodiment can be changed as much as possible.

[0182] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0183] 10...Semiconductor memory device, 11...Memory cell array, 12...Input / output circuit, 13...Logic control circuit, 14...Ready / busy circuit, 15...Register group, 15A...Status register, 15B...Address register, 15C...Command register, 16...Sequencer, 17...Voltage generation circuit, 18...Row decoder, 19...Column decoder, 20...Data register, 21...Sense amplifier, 30...Semiconductor substrate, 31...Insulating layer (e.g., oxide nitride layer), 32...insulating layer (e.g., oxide layer), 33...insulating layer, 40, 41, 42, 42a, 42b, 43, 44, 45, 46, 47...conductive layer, 61...nitride layer, 71...contact hole, CC...contact, MP...memory pillar, UMP...upper pillar, MMP...middle pillar, LMP...lower pillar, UU...upper word line, UM...middle word line, UL...lower word line, MU...upper word line, MM...middle word line, ML...lower word line.

Claims

1. a first plurality of word lines stacked above the substrate; a second plurality of word lines stacked above the first plurality of word lines; a select gate line provided above the second plurality of word lines; a first pillar provided above the substrate and penetrating the first plurality of word lines in a first direction perpendicular to an upper surface of the substrate; a second pillar provided above the first pillar and passing through the second plurality of word lines and the select gate lines in the first direction; Equipped with the second plurality of word lines include upper layer word lines arranged around an upper layer portion of the second pillar, middle layer word lines arranged around a middle layer portion below the upper layer portion, and lower layer word lines arranged around a lower layer portion below the middle layer portion; the upper word line has a thickness greater than that of the middle word line; Semiconductor memory device.

2. the upper layer word line is disposed near an upper end of the second pillar, the lower word line is disposed near a boundary between the first pillar and the second pillar; the middle layer word line is arranged between the upper layer word line and the lower layer word line; 2. The semiconductor memory device according to claim 1.

3. a joint portion provided between the first pillar and the second pillar, the lower layer word line is disposed near the junction; 3. The semiconductor memory device according to claim 2.

4. a dummy word line disposed between the upper word line and the select gate line; The dummy word line has a thickness greater than that of the intermediate word line.

2. The semiconductor memory device according to claim 1.

5. a row decoder for supplying a voltage; the second plurality of word lines and the select gate lines are electrically connected to the row decoder; the dummy word line is not electrically connected to the row decoder; 5. The semiconductor memory device according to claim 4.

6. each of the intersections of the second plurality of word lines and the second pillar functions as a memory cell; A portion where the select gate line and the second pillar intersect functions as a select transistor.

2. The semiconductor memory device according to claim 1.

7. The memory cell is configured to be able to store data.

7. The semiconductor memory device according to claim 6.

8. A portion where the dummy word line and the second pillar intersect is configured so that no data is stored.

5. The semiconductor memory device according to claim 4.

9. the lower word line has a thickness greater than that of the middle word line; 2. The semiconductor memory device according to claim 1.

10. Among the first plurality of word lines, upper-layer word lines arranged around the upper layer portion of the first pillar have a thickness greater than a thickness of the middle-layer word lines.

10. The semiconductor memory device according to claim 9.

11. the upper layer word line around the upper layer portion of the first pillar is disposed near the boundary between the first pillar and the second pillar.

11. The semiconductor memory device according to claim 10.

12. Among the first plurality of word lines, upper-layer word lines arranged around the upper layer portion of the first pillar have a thickness greater than a thickness of the middle-layer word lines.

2. The semiconductor memory device according to claim 1.

13. the upper layer word line around the upper layer portion of the first pillar is disposed near the boundary between the first pillar and the second pillar.

13. The semiconductor memory device according to claim 12.

14. the thickness of the middle word line is thicker than the thickness of the lower word line; 2. The semiconductor memory device according to claim 1.

15. a first plurality of word lines stacked above the source lines; a second plurality of word lines stacked above the first plurality of word lines; a select gate line provided above the second plurality of word lines; a first pillar provided above the source line and penetrating the first plurality of word lines in a first direction perpendicular to an upper surface of the source line; a second pillar provided above the first pillar and passing through the second plurality of word lines and the select gate lines in the first direction; Equipped with the second plurality of word lines include upper layer word lines arranged around an upper layer portion of the second pillar, middle layer word lines arranged around a middle layer portion below the upper layer portion, and lower layer word lines arranged around a lower layer portion below the middle layer portion; the upper word line has a thickness greater than that of the middle word line; Semiconductor memory device.

16. the upper layer word line is disposed near an upper end of the second pillar, the lower word line is disposed near a boundary between the first pillar and the second pillar; the middle layer word line is arranged between the upper layer word line and the lower layer word line; 16. The semiconductor memory device according to claim 15.

17. the lower word line has a thickness greater than that of the middle word line; 16. The semiconductor memory device according to claim 15.

18. Among the first plurality of word lines, upper-layer word lines arranged around the upper layer portion of the first pillar have a thickness greater than a thickness of the middle-layer word lines.

18. The semiconductor memory device according to claim 17.

19. the upper layer word line around the upper layer portion of the first pillar is disposed near the boundary between the first pillar and the second pillar.

19. The semiconductor memory device according to claim 18.

20. the thickness of the middle word line is thicker than the thickness of the lower word line; 16. The semiconductor memory device according to claim 15.

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