Semiconductor memory device and method of manufacturing the same

Abstract

Embodiments described herein relate generally to a semiconductor memory device and a method of manufacturing the semiconductor memory device.SOLUTION: In one embodiment, a semiconductor memory device includes a stacked body and a columnar body. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. When a direction intersecting the first direction is defined as a second direction, and a virtual center line extending in the first direction through the center of the columnar body in the second direction is defined, the following is obtained. The columnar body includes a memory film, a semiconductor film, and an insulating portion. The insulating part includes a first insulating part adjacent to a plurality of first selection gate lines, and a second insulating part adjacent to at least a part of word lines. In a region between the center line and the semiconductor film, a thickness of the second insulating portion in the second direction is smaller than a thickness of the first insulating portion in the second direction.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. [Background technology]

[0002] A NAND flash memory in which memory cells are arranged three-dimensionally is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-41054 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a semiconductor memory device and a method for manufacturing the semiconductor memory device that can improve electrical characteristics. [Means for solving the problem]

[0005] In one embodiment, the semiconductor memory device includes a stack, a pillar, and a bit line. The stack includes a plurality of gate electrode layers and a plurality of insulating layers. The gate electrode layers and the insulating layers are alternately stacked layer by layer in a first direction. The pillar extends in the first direction within the stack. The bit line is disposed on a first side of the pillar in the first direction. The gate electrode layers include a plurality of word lines and a plurality of first select gate lines. Memory cell transistors are formed at the intersections of the word lines and the pillar. The first select gate lines are disposed on a second side of the word lines opposite the first side. First select transistors are formed at the intersections of the first select gate lines and the pillar. A direction intersecting the first direction is defined as a second direction, and an imaginary center line extending in the first direction through the center of the pillar in the second direction is defined as follows in a cross section along the first and second directions: The columnar body includes a memory film including a charge storage portion, a semiconductor film provided on the inner periphery of the memory film in the second direction, an insulating portion provided on the inner periphery of the semiconductor film in the second direction, and a cavity portion adjacent to at least a portion of the insulating portion in the first direction. The insulating portion includes a first insulating portion adjacent to the plurality of first select gate lines in the second direction, and a second insulating portion adjacent to the cavity in the second direction and adjacent to at least some of the word lines included in the plurality of word lines in the second direction. When viewed in a region between the center line and the semiconductor film, the thickness of the second insulating portion in the second direction is smaller than the thickness of the first insulating portion in the second direction. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a part of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing an equivalent circuit of a part of the memory cell array according to the first embodiment. [Figure 3] FIG. 1 is a cross-sectional view showing a part of a semiconductor memory device according to a first embodiment. [Figure 4]FIG. 4 is a cross-sectional view of the semiconductor memory device shown in FIG. 3 taken along line F4-F4. [Figure 5] 4 is an enlarged cross-sectional view showing a region surrounded by line F5 of the memory cell array shown in FIG. 3. [Figure 6] FIG. 6 is a cross-sectional view of the memory cell array shown in FIG. 5 taken along line F6-F6. [Figure 7] 6 is an enlarged cross-sectional view showing a region surrounded by line F7 of the memory cell array shown in FIG. 5. [Figure 8] 8 is an enlarged cross-sectional view showing a region surrounded by line F8 of the memory cell array shown in FIG. 7; [Figure 9] FIG. 4 is a diagram showing the profile of impurity concentration in an insulating portion according to the first embodiment. [Figure 10A] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10B] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10C] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10D] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10E] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10F] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10G] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10H] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10I] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10J] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 10K] 3A to 3C are cross-sectional views illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 11]FIG. 4 is a diagram for explaining the influence of the thickness of the second insulating portion in the first embodiment. [Figure 12] FIG. 10 is a cross-sectional view showing a memory cell array according to a first modified example of the first embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing a memory cell array according to a second modification of the first embodiment. [Figure 14] 14 is an enlarged cross-sectional view showing a region surrounded by line F14 of the memory cell array shown in FIG. 13. [Figure 15] FIG. 10 is a cross-sectional view showing a memory cell array according to a second embodiment. [Figure 16] FIG. 10 is a cross-sectional view showing a memory cell array according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] A semiconductor memory device and a method for manufacturing the semiconductor memory device according to the embodiment will be described below with reference to the drawings. In the following description, components having the same or similar functions will be assigned the same reference numerals. Further, duplicate descriptions of those components may be omitted. In the following description, reference numerals ending with a distinguishing number or letter may have the number or letter omitted if they do not need to be distinguished from each other.

[0008] In this application, terms are defined as follows: "Parallel," "orthogonal," or "same" may include the cases of "substantially parallel," "substantially orthogonal," or "substantially the same," respectively. "Connection" is not limited to mechanical connection, but may also include electrical connection. That is, "connection" is not limited to the case where multiple elements are directly connected, but may include the case where multiple elements are connected with another element interposed therebetween. "Adjacent" is not limited to the case where multiple elements are in contact with each other, but may include the case where multiple elements are adjacent with another element interposed therebetween.

[0009] The +X direction, −X direction, +Y direction, −Y direction, +Z direction, and −Z direction are defined as follows: The +X direction is the direction in which the word lines WL, which will be described later, extend (see FIG. 3). The −X direction is the opposite direction of the +X direction. When the +X direction and the −X direction are not distinguished, they are simply referred to as the X direction. The +Y direction is a direction that intersects (e.g., is perpendicular to) the X direction. The +Y direction is the direction in which the bit lines BL extend (see FIG. 4). The −Y direction is the opposite direction of the +Y direction. When the +Y direction and the −Y direction are not distinguished, they are simply referred to as the Y direction. The +Z direction is a direction that intersects (e.g., is perpendicular to) the X direction and the Y direction. The +Z direction is the direction from the bit lines BL, which will be described later, toward the stack 40 (see FIG. 3). The −Z direction is the opposite direction of the +Z direction. When the +Z direction and the −Z direction are not distinguished, they are simply referred to as the Z direction. In this application, the +Z direction side may be referred to as "upper" and the -Z direction side as "lower." Also, in this application, the position in the Z direction may be referred to as "height." However, these expressions are used for convenience of explanation and do not define the direction of gravity. The Z direction is an example of a "first direction." The X direction is an example of a "second direction." The -Z direction side is an example of a "first side." The +Z direction side is an example of a "second side." In the drawings described below, illustrations of configurations that are not relevant to the explanation may be omitted.

[0010] (First embodiment) <1. Configuration of Semiconductor Memory Device> FIG. 1 is a block diagram showing a portion of a semiconductor memory device 1 according to a first embodiment. The semiconductor memory device 1 is, for example, a nonvolatile semiconductor memory device, such as a NAND flash memory. The semiconductor memory device 1 can be connected to an external host device and is used as a storage space for the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, a command register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0011] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k-1) (k is an integer equal to or greater than 1). A block BLK is a collection of memory cell transistors. A block BLK is used as a unit for erasing data. The memory cell array 11 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with one bit line and one word line.

[0012] The command register 12 holds the command CMD that the semiconductor memory device 1 receives from the host device. The address register 13 holds address information ADD that the semiconductor memory device 1 receives from the host device. The address information ADD is used to select a block BLK, a word line, and a bit line. The control circuit 14 controls various operations of the semiconductor memory device 1. For example, the control circuit 14 executes a data write operation, a read operation, an erase operation, etc. based on the command CMD held in the command register 12.

[0013] The driver module 15 includes a voltage generation circuit and generates voltages used in various operations of the semiconductor memory device 1. The row decoder module 16 transfers a voltage applied to a signal line corresponding to a selected word line to the selected word line. The sense amplifier module 17 applies a desired voltage to each bit line during a write operation. During a read operation, the sense amplifier module 17 determines the data stored in each memory cell transistor based on the voltage of each bit line and transfers the determination result to the host device as read data DAT.

[0014] 2. Electrical Configuration of Memory Cell Array Fig. 2 is a diagram showing an equivalent circuit of a part of the memory cell array 11. Fig. 2 shows one block BLK included in the memory cell array 11. The block BLK includes a plurality of strings STR (for example, five strings STR0 to STR4).

[0015] Each string STR includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). Each NAND string NS includes a plurality of memory cell transistors MT0 to MTn (n is an integer equal to or greater than 1), one or more drain-side select transistors STD, and one or more source-side select transistors STS.

[0016] In each NAND string NS, memory cell transistors MT0 to MTn are connected in series. Each memory cell transistor MT includes a control gate and a charge storage section. The control gate of the memory cell transistor MT is connected to one of word lines WL0 to WLn. Each memory cell transistor MT stores charge in the charge storage section in response to a voltage applied to the control gate via the word line WL, thereby retaining data in a non-volatile manner.

[0017] The drain of the drain-side select transistor STD is connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side select transistor STD is connected to one end of the series-connected memory cell transistors MT0 to MTn. The control gate of the drain-side select transistor STD is connected to one of the drain-side select gate lines SGD0 to SGD4. The drain-side select transistor STD is electrically connected to the row decoder module 16 via the drain-side select gate line SGD. The drain-side select transistor STD connects the NAND string NS to the bit line BL when a predetermined voltage is applied to the corresponding drain-side select gate line SGD.

[0018] The drain of the source-side select transistor STS is connected to the other end of the series-connected memory cell transistors MT0 to MTn. The source of the source-side select transistor STS is connected to a source line SL. The control gate of the source-side select transistor STS is connected to a source-side select gate line SGS. The source-side select transistor STS connects the NAND string NS to the source line SL when a predetermined voltage is applied to the source-side select gate line SGS.

[0019] In the same block BLK, the control gates of the memory cell transistors MT0 to MTn are commonly connected to the corresponding word lines WL0 to WLn. In the same string STR, the control gates of the drain-side select transistors STD are commonly connected to the corresponding drain-side select gate line SGD. The control gates of the source-side select transistors STS are commonly connected to the source-side select gate line SGS. In the memory cell array 11, the bit line BL is shared by NAND strings NS to which the same column address is assigned in multiple strings STR.

[0020] <3. Structure of semiconductor memory device> Next, the structure of the semiconductor memory device 1 will be described. 3 is a cross-sectional view showing a part of the semiconductor memory device 1. The semiconductor memory device 1 has, for example, a first chip 2 and a second chip 3. The second chip 3 is a chip bonded to the first chip 2.

[0021] <3.1 First Chip> The first chip 2 is a circuit chip including a peripheral circuit, and includes, for example, a semiconductor substrate 21, a peripheral circuit 22, an insulating portion 23, and a plurality of pads 24.

[0022] The semiconductor substrate 21 is, for example, a substrate that serves as the base of the first chip 2. At least a portion of the semiconductor substrate 21 is plate-shaped and extends along the X and Y directions. The semiconductor substrate 21 is made of, for example, a semiconductor material such as silicon.

[0023] The peripheral circuit 22 is a circuit for causing the memory cell array 11 to function. The peripheral circuit 22 includes a plurality of transistors 22a and a plurality of wirings 22b. The peripheral circuit 22 includes one or more of the command register 12, address register 13, control circuit 14, driver module 15, row decoder module 16, and sense amplifier module 17. An insulating section 23 covers the peripheral circuit 22. A plurality of pads 24 are provided on the surface of the insulating section 23. Each pad 24 is electrically connected to the peripheral circuit 22.

[0024] <3.2 Second Chip> The second chip 3 is an array chip including a memory cell array 11. The second chip 3 has, for example, the memory cell array 11, an insulating section 31, and a plurality of pads 32. Here, the insulating section 31 and the plurality of pads 32 will be described, and the memory cell array 11 will be described later.

[0025] The insulating section 31 covers the memory cell array 11 from the -Z direction side. A plurality of pads 32 are provided on the surface of the insulating section 31. Each pad 32 is electrically connected to a wiring (e.g., wiring 71 or wiring 72) included in a wiring section 70 of the memory cell array 11, which will be described later. In this embodiment, the first chip 2 and the second chip 3 are integrated by bonding the plurality of pads 24 of the first chip 2 and the plurality of pads 32 of the second chip 3 face to face with each other.

[0026] <4. Memory Cell Array> Next, the memory cell array 11 will be described. 3, the memory cell array 11 includes an array region AR and a hook-up region FR. The array region AR is an area where a plurality of memory pillars MH (described later) are provided and where data can be stored. The hook-up region FR is an area where a plurality of contacts CC (described later) are provided and where a plurality of gate electrode layers 41 (described later) are connected to a wiring portion 70. The hook-up regions FR are provided, for example, on both sides of the array region AR in the X direction.

[0027] 3, the memory cell array 11 includes, for example, a stacked body 40, a source line SL, a plurality of memory pillars MH, a plurality of bit lines BL, a plurality of contacts CH for the memory pillars, a plurality of contacts VY for the memory pillars, a contact CC for the gate electrode layer, a wiring portion 70, a support HR, and a plurality of separating portions 80 (see FIG. 4). The memory pillars MH will be described later.

[0028] 4.1 Laminate The stacked body 40 includes, for example, a plurality of gate electrode layers 41, a plurality of insulating layers 42, an insulating layer 43, and an insulating portion 44. The plurality of gate electrode layers 41 and the plurality of insulating layers 42 are stacked alternately one by one in the Z direction.

[0029] The gate electrode layers 41 extend along the X and Y directions. Each gate electrode layer 41 includes a conductive material (for example, tungsten, molybdenum, or silicon doped with impurities).

[0030] Of the multiple gate electrode layers 41, one or more (for example, multiple) gate electrode layers 41 located at the top function as source-side select gate lines SGS. The source-side select gate lines SGS are provided in common to multiple memory pillars MH aligned in the X direction or Y direction. The intersections of the source-side select gate lines SGS and channel layers 52 (described later) of each memory pillar MH function as the source-side select transistors STS described above. The source-side select gate lines SGS are an example of "first select gate lines." The source-side select transistors STS are an example of "first select transistors."

[0031] Of the multiple gate electrode layers 41, one or more (for example, multiple) gate electrode layers 41 located at the bottom function as drain-side select gate lines SGD. The drain-side select gate lines SGD are provided in common for multiple memory pillars MH aligned in the X direction or Y direction. The intersections of the drain-side select gate lines SGD and channel layers 52 (described later) of each memory pillar MH function as the drain-side select transistors STD described above. The drain-side select gate lines SGD are an example of "second select gate lines." The drain-side select transistors STD are an example of "second select transistors."

[0032] Of the multiple gate electrode layers 41, at least some of the remaining gate electrode layers 41 provided between the gate electrode layers 41 functioning as source-side select gate lines SGS and drain-side select gate lines SGD function as word lines WL. The word lines WL are provided in common to multiple memory pillars MH aligned in the X and Y directions. In this embodiment, the intersections between the word lines WL and channel layers 52 (described later) of each memory pillar MH function as the memory cell transistors MT described above.

[0033] The multiple gate electrode layers 41 have different lengths in the X direction in the hookup region FR. For example, the lengths of the multiple gate electrode layers 41 in the X direction are greater as the gate electrode layer 41 is located closer to the +Z direction. As a result, the ends of the multiple gate electrode layers 41 are arranged in a stepped pattern in the hookup region FR.

[0034] The insulating layer 42 is an interlayer insulating film provided between two gate electrode layers 41 adjacent to each other in the Z direction, and insulates the two gate electrode layers 41. The insulating layer 42 extends in the X direction and the Y direction. The insulating layer 42 is formed of, for example, a film containing silicon and oxygen (for example, a silicon oxide film).

[0035] The insulating layer 43 is an insulating layer provided above the uppermost gate electrode layer 41. The insulating layer 43 is disposed between the uppermost gate electrode layer 41 and the source line SL. The insulating layer 43 extends in the X and Y directions. The insulating layer 43 is formed of, for example, a film containing silicon and oxygen (e.g., a silicon oxide film). For example, the thickness of the insulating layer 43 in the Z direction is greater than the thickness of the insulating layer 42 in the Z direction.

[0036] The insulating portion 44 is an insulating portion provided in the hook-up region FR. The insulating portion 44 covers the ends of the gate electrode layers 41 arranged in a stepped manner from the -Z direction side. The insulating portion 44 is formed using, for example, TEOS (tetraethyl orthosilicate (Si(OC2H5)4)).

[0037] <4.2 Source line> The source lines SL are provided on the insulating layer 43. The source lines SL are, for example, conductive layers or semiconductor layers extending in the X and Y directions. The source lines SL are formed of, for example, a conductive material such as tungsten or molybdenum, or a semiconductor material containing silicon.

[0038] 4.3 Bit lines The bit line BL is a wiring for selecting one memory pillar MH from among the multiple memory pillars MH. The multiple bit lines BL are arranged below (on the -Z direction side of) the stack 40. The multiple bit lines BL are spaced apart in the X direction and lined up in the X direction. Each bit line BL extends in the Y direction. Each bit line BL extends so as to pass below the corresponding multiple memory pillars MH.

[0039] Each bit line BL is connected to a channel layer 52 of a memory pillar MH (described later) via a contact VY and a contact CH. This allows any memory cell transistor MT to be selected from multiple memory cell transistors MT arranged three-dimensionally by combining word lines WL and bit lines BL.

[0040] 4.4 Contact for gate electrode layer The contacts CC are electrical connection parts that electrically connect the gate electrode layer 41 and wiring 72 (described later) included in the wiring part 70. The contacts CC are provided, for example, in the hook-up region FR of the memory cell array 11. The contacts CC extend in the Z direction within the stacked body 40 and are connected to different gate electrode layers 41. The contacts CC are conductive. The contacts CC are formed of a conductive material (for example, tungsten, molybdenum, or silicon doped with impurities).

[0041] <4.5 Wiring section> The wiring section 70 is disposed, for example, between the stacked body 40 and the semiconductor substrate 21. The wiring section 70 includes, for example, a plurality of wirings 71, a plurality of vias V1, and a plurality of wirings 72.

[0042] The wiring 71 is an electrical connection portion that electrically connects the bit line BL and the pad 32. The multiple wirings 71 are arranged, for example, below the multiple bit lines BL. Each wiring 71 extends, for example, in the X direction or the Y direction. A via V1 is provided between the wiring 71 and the bit line BL to electrically connect the wiring 71 and the bit line BL.

[0043] The wiring 72 is an electrical connection portion that electrically connects the conductive layer contact CC and the pad 32. The wiring 72 is electrically connected to the gate electrode layer 41 via the conductive layer contact CC. A voltage is applied to the wiring 72 to select the gate electrode layer 41 (word line WL, drain side select gate line SGD, or source side select gate line SGS).

[0044] <4.6 Support> The supports HR are provided in the hook-up regions FR. The supports HR extend through the stack 40 in the Z direction in the hook-up regions FR. The supports HR are made of, for example, an insulating material. The supports HR support the multiple insulating layers 42 so that they do not collapse during a replacement process, which will be described later.

[0045] <4.7 Divided Part> Next, the dividing portion 80 will be described. 4 is a cross-sectional view of the semiconductor memory device 1 shown in FIG. 3 taken along line F4-F4. A plurality of dividing portions 80 are provided in the stacked body 40. The plurality of dividing portions 80 are arranged separately in the Y direction. Each of the plurality of dividing portions 80 extends in the Z direction within the stacked body 40, and divides one or more gate electrode layers 41, including the lowest layer among the plurality of gate electrode layers 41, in the Y direction. The plurality of dividing portions 80 include, for example, a plurality of dividing portions ST and a plurality of dividing portions SHE.

[0046] <4.7.1 Separation ST> The dividing portions ST are walls that divide the stacked body 40 in the Y direction. The dividing portions ST are arranged separately in the Y direction. The dividing portions ST extend in the Z direction, penetrate the stacked body 40, and extend in the X direction. The dividing portions ST are walls that extend along the X and Z directions. The dividing portions ST divide each of all of the gate electrode layers 41 included in the stacked body 40 in the Y direction.

[0047] <4.7.2 Divided part SHE> The dividing portion SHE is a dividing portion that is shorter in length in the Z direction than the dividing portion ST, and is a wall portion that divides the lower end portion of the stack 40 in the Y direction. The dividing portions SHE are arranged separately in the Y direction. In this embodiment, a plurality of (for example, four) dividing portions SHE are present between two dividing portions ST adjacent to each other in the Y direction. The dividing portion SHE is provided at the lower end portion of the stack 40, and extends in the Z direction partway through the stack 40, and also extends in the X direction. In other words, the dividing portion SHE is a wall portion that extends along the X direction and the Z direction.

[0048] The dividing portion SHE penetrates through some of the gate electrode layers 41, including the lowest layer, of the multiple gate electrode layers 41, and divides the some of the gate electrode layers 41 in the Y direction. For example, the dividing portion SHE penetrates through each of all of the gate electrode layers 41 that function as drain-side select gate lines SGD. On the other hand, the dividing portion SHE does not reach the gate electrode layers 41 that function as word lines WL. The dividing portion SHE divides only the gate electrode layers 41 that function as drain-side select gate lines SGD in the Y direction. The dividing portion SHE is formed, for example, from a film containing silicon and oxygen (for example, a silicon oxide film).

[0049] <5. Memory Pillar> Next, the memory pillar MH will be described. The memory pillars MH are aligned in the X and Y directions. Each memory pillar MH extends in the Z direction within the stack 40 and penetrates the stack 40. The memory pillar MH is an example of a "columnar body."

[0050] 5 is an enlarged cross-sectional view of a region surrounded by line F5 of the memory cell array 11 shown in Fig. 3. The memory pillar MH includes, for example, a memory film (multilayer film) 51, a channel layer 52, an insulating portion 53, a cavity portion (air gap) 54, and a cap portion 55.

[0051] The memory film 51 is disposed on the outer periphery of the memory pillar MH. The memory film 51 extends in the Z direction. For example, the memory film 51 extends over the entire length of the memory pillar MH in the Z direction except for the upper end of the memory pillar MH. The memory film 51 is located between the multiple gate electrode layers 41 and the channel layer 52. The memory film 51 includes, for example, a block insulating film 61, a charge trap film 62, and a tunnel insulating film 63.

[0052] The block insulating film 61 is disposed on the outermost periphery of the memory pillar MH. The block insulating film 61 is provided between the multiple gate electrode layers 41 and the charge trap film 62. The block insulating film 61 is an insulating film that suppresses back tunneling. Back tunneling is a phenomenon in which charges return from the word line WL to the charge trap film 62. The block insulating film 61 is formed in an annular shape and extends in the Z direction. For example, the block insulating film 61 extends over the entire length of the memory pillar MH in the Z direction except for the upper end of the memory pillar MH. The block insulating film 61 is a stacked structure film in which multiple insulating films, such as a film containing silicon and oxygen or a film containing metal and oxygen, are stacked. An example of a film containing metal and oxygen is an aluminum oxide film. The block insulating film 61 may contain a high-dielectric-constant material (high-k material) such as silicon nitride or hafnium oxide. The block insulating film 61 is an example of a "first insulating film."

[0053] The charge trap film 62 is provided on the inner periphery of the block insulating film 61 in the X and Y directions. The charge trap film 62 is located between the block insulating film 61 and the tunnel insulating film 63. The charge trap film 62 is formed in an annular shape and extends in the Z direction. For example, the charge trap film 62 extends over the entire length of the memory pillar MH in the Z direction except for the upper end of the memory pillar MH. The charge trap film 62 is a functional film that has a large number of crystal defects (trap levels) and can trap charges in the crystal defects. The charge trap film 62 is formed of, for example, a film containing silicon and nitrogen. Portions 62a of the charge trap film 62 adjacent to each word line WL (see FIG. 6) are an example of a "charge storage portion" that can store information by accumulating charges.

[0054] The tunnel insulating film 63 is provided on the inner periphery side of the charge trap film 62 in the X direction and the Y direction. The tunnel insulating film 63 is provided between the charge trap film 62 and the channel layer 52. The tunnel insulating film 63 is, for example, annular along the outer periphery of the channel layer 52 and extends in the Z direction along the channel layer 52. The tunnel insulating film 63 extends, for example, over the entire length of the memory pillar MH in the Z direction except for the upper end of the memory pillar MH. The tunnel insulating film 63 is a potential barrier between the charge trap film 62 and the channel layer 52. The tunnel insulating film 63 is formed of a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen. The tunnel insulating film 63 is an example of a "second insulating film."

[0055] The channel layer 52 is provided on the inner periphery of the memory film 51 in the X and Y directions. The channel layer 52 is formed in a ring shape. The channel layer 52 extends in the Z direction. For example, the channel layer 52 covers the entire length of the memory pillar MH in the Z direction. The channel layer 52 is formed of a semiconductor material such as polysilicon. The channel layer 52 may be doped with impurities. When a voltage is applied to the word line WL, the channel layer 52 forms a channel to electrically connect the bit line BL and the source line SL. The channel layer 52 is an example of a "semiconductor film."

[0056] 6 is a cross-sectional view taken along line F6-F6 of the memory cell array 11 shown in FIG. 5. With the above-described configuration, a MANOS (Metal-Al-Nitride-Oxide-Silicon) memory cell transistor MT is formed at the same height as each word line WL, including the edge of the word line WL adjacent to the memory pillar MH, the block insulating film 61, the charge trap film 62, the tunnel insulating film 63, and the channel layer 52. Note that the memory film 51 may have a floating gate type charge storage portion (floating gate electrode) as the charge storage portion instead of the charge trap film 62. The floating gate type charge storage portion is formed of, for example, polysilicon containing impurities.

[0057] Returning to FIG. 5, the remaining configuration of the memory pillar MH will be described. The insulating portion 53 is provided on the inner periphery side of the channel layer 52 in the X direction and the Y direction. The insulating portion 53 fills at least a part of the inside of the channel layer 52. The insulating portion 53 is formed of a film containing silicon and oxygen (e.g., a silicon oxide film). The insulating portion 53 extends in the Z direction. For example, the insulating portion 53 extends over the entire length of the memory pillar MH in the Z direction except for the lower end of the memory pillar MH.

[0058] The cavity 54 is provided inside a part of the insulating part 53. For example, the cavity 54 is provided on the inner periphery of the insulating part 53 in the X and Y directions, in a part of the insulating part 53 in the Z direction. The cavity 54 is adjacent to at least a part of the insulating part 53 in the Z direction.

[0059] The cap portion 55 is provided below the insulating portion 53. The cap portion 55 is a semiconductor portion made of a semiconductor material such as amorphous silicon or polysilicon. The cap portion 55 is doped with, for example, an impurity. The cap portion 55 is disposed on the inner periphery side of the lower end portion of the memory film 51 and is formed integrally with the channel layer 52. The cap portion 55, together with the lower end portion of the channel layer 52, forms the lower end portion of the memory pillar MH. A contact CH contacts the cap portion 55 from the -Z direction side.

[0060] <6. Arrangement of gate electrode layer> Next, the arrangement of the gate electrode layer 41 will be described. 5, the gate electrode layers 41 include a plurality of (e.g., four) source-side select gate lines SGS, a plurality of (e.g., four) drain-side select gate lines SGD, and a plurality of word lines WL. For example, the Z-direction thickness T11 of the source-side select gate lines SGS is greater than the Z-direction thickness T13 of the word lines WL. The Z-direction thickness T12 of the drain-side select gate lines SGD is greater than the Z-direction thickness T13 of the word lines WL. Note that the Z-direction thickness T11 of the source-side select gate lines SGS may be the same as the Z-direction thickness T13 of the word lines WL. The Z-direction thickness T12 of the drain-side select gate lines SGD may be the same as the Z-direction thickness T13 of the word lines WL.

[0061] The source-side select gate lines SGS are, for example, a group of gate electrode layers 41 among the above-mentioned gate electrode layers 41 that are located at the end of the stacked body 40 in the +Z direction and to which a voltage is applied at the same time. The drain-side select gate lines SGD are a group of gate electrode layers 41 among the above-mentioned gate electrode layers 41 that are located at the end of the stacked body 40 in the −Z direction and to which a voltage is applied at the same time.

[0062] For example, the drain-side select gate line SGD is a gate electrode layer 41 to which a lower voltage (e.g., half the voltage or less) is applied compared to the data word line WLA (described later) corresponding to the unselected memory cell transistor MT (memory cell transistor MT not to be written) during a write operation to the memory cell transistor MT. Note that the drain-side select gate line SGD may be set to 0 V during a write operation to the memory cell transistor MT when an operation mode is applied in which the channel layer 52 of the memory pillar MH and the source line SL are electrically connected during a write operation to the memory cell transistor MT.

[0063] For example, the source-side select gate line SGS is a gate electrode layer 41 that is set to 0 V during a write operation to the memory cell transistor MT. Note that, when an operation mode is applied in which the channel layer 52 of the memory pillar MH and the source line SL are electrically connected during a write operation to the memory cell transistor MT, a voltage that is half or less than that applied to the data word line WLA (described later) corresponding to the unselected memory cell transistor MT (memory cell transistor MT not to be written) may be applied to the source-side select gate line SGS.

[0064] The plurality of word lines WL includes a plurality (for example, five or less) of first dummy word lines WLD1, a plurality (for example, five or less) of second dummy word lines WLD2, and a plurality of data word lines WLA.

[0065] In this application, a "dummy word line" refers to a word line WL that forms, at its intersection with a memory pillar MH, a memory cell transistor MT that functions as a dummy memory cell transistor MTD. The dummy memory cell transistor MTD has the same configuration as the memory cell transistor MT used to store valid data, but is a transistor that is not used to store valid data. The dummy memory cell transistor MTD is arranged to prevent the influence of the operation of applying a voltage to the source-side select gate line SGS or the drain-side select gate line SGD during a write operation from affecting unselected memory cell transistors MT (memory cell transistors MT that are not the target of writing).

[0066] 5, the word lines WL include five or less (e.g., three) first dummy word lines WLD1 as a predetermined number of first dummy word lines WLD1 that are closest to the source-side select gate lines SGS among the word lines WL. The first dummy word lines WLD1 are an example of a "first word line."

[0067] Similarly, the plurality of word lines WL includes a predetermined number of second dummy word lines WLD2 that are closest to the plurality of drain-side select gate lines SGD among the plurality of word lines WL, and the number of second dummy word lines WLD2 is five or less (for example, three). The second dummy word lines WLD2 are an example of a "second word line."

[0068] The remaining word lines WL among the plurality of word lines WL are data word lines WLA that form memory cell transistors MT used to hold valid data. The data word line WLA located at the top among the plurality of data word lines WLA is the word line WL located below one of the lowest first dummy word lines WLD1. The data word line WLA located at the bottom among the plurality of data word lines WLA is the word line WL located above one of the highest second dummy word lines WLD2. The data word line WLA is an example of a "third word line."

[0069] In addition, when the memory pillars MH are configured in multiple stages in the Z direction (for example, when a first memory pillar MH and a second memory pillar MH arranged below the first memory pillar MH are connected in the Z direction), the word lines WL located near the connection portions of the memory pillars MH may be provided as dummy word lines. In this case, the dummy word lines located near the connection portions of the memory pillars MH correspond to another example of the "third word line."

[0070] 7. Structure of the insulating part of the memory pillar Next, the structure of the insulating portion 53 of the memory pillar MH will be described. As shown in FIG. 5, the insulating portion 53 includes, for example, a first insulating portion 53a, a second insulating portion 53b, and a third insulating portion 53c.

[0071] <7.1 First insulating part> The first insulating portion 53a is located at the top of the first to third insulating portions 53a, 53b, and 53c. In this embodiment, the first insulating portion 53a is located above the cavity portion 54. In this embodiment, the first insulating portion 53a is a solid portion that fills the inner periphery of the channel layer 52.

[0072] The first insulating portion 53a is adjacent to a plurality (for example, all) of the source-side select gate lines SGS in the X and Y directions. In this embodiment, the first insulating portion 53a is adjacent to some (for example, two) of the plurality (for example, three) of the first dummy word lines WLD1 in the X and Y directions. On the other hand, the first insulating portion 53a is not adjacent to another portion (for example, the bottommost one) of the plurality (for example, three) of the first dummy word lines WLD1 in the X and Y directions.

[0073] Alternatively, instead of the above example, the first insulating portion 53a may be adjacent to all of the first dummy word lines WLD1 in the X direction and the Y direction. On the other hand, the first insulating portion 53a does not have to be adjacent to all of the first dummy word lines WLD1 in the X direction and the Y direction.

[0074] <7.2 Second insulating part> The second insulating portion 53b is located in the middle of the first to third insulating portions 53a, 53b, and 53c. In this embodiment, the second insulating portion 53b is a portion adjacent to the cavity portion 54 in the X and Y directions. In this embodiment, the second insulating portion 53b is a hollow portion in which the cavity portion 54 is provided. The second insulating portion 53b has an annular shape that follows the inner circumferential surface of the channel layer 52.

[0075] The second insulating portion 53b is adjacent to a plurality (for example, all) of the data word lines WLA in the X direction and the Y direction. In this embodiment, the second insulating portion 53b is adjacent to some (for example, the bottommost one) of the above-mentioned plurality (for example, three) of first dummy word lines WLD1 in the X direction and the Y direction.

[0076] The second insulating portion 53b is adjacent to a plurality (for example, all) of the second dummy word lines WLD2 in the X direction and the Y direction. Note that the second insulating portion 53b does not have to be adjacent to some or all of the second dummy word lines WLD2 in the X direction and the Y direction.

[0077] The second insulating portion 53b is adjacent to some (e.g., three) of the multiple (e.g., four) drain-side select gate lines SGD in the X and Y directions. On the other hand, the second insulating portion 53b is not adjacent to another part (e.g., the bottommost one) of the multiple (e.g., four) drain-side select gate lines SGD in the X and Y directions.

[0078] Alternatively, instead of the above example, the second insulating portion 53b may be adjacent to all of the drain-side select gate lines SGD in the X and Y directions. On the other hand, the second insulating portion 53b does not have to be adjacent to all of the drain-side select gate lines SGD in the X and Y directions.

[0079] The second insulating portion 53b may be partially interrupted midway in the Z direction. In other words, a part of the channel layer 52 may be exposed to the cavity 54 at a position adjacent to some of the word lines WL in the X direction and the Y direction.

[0080] <7.3 Third insulating section>

[0081] The third insulating portion 53c is located at the bottom of the first to third insulating portions 53a, 53b, and 53c. In this embodiment, the third insulating portion 53c is located below the cavity portion 54. In this embodiment, the third insulating portion 53c is a solid portion that fills the inner periphery of the channel layer 52.

[0082] The third insulating portion 53c is adjacent to some (for example, the bottommost) of the multiple (for example, four) drain-side select gate lines SGD in the X and Y directions. Note that the third insulating portion 53c may be adjacent to all of the drain-side select gate lines SGD in the X and Y directions. The third insulating portion 53c is not an essential component and may be omitted.

[0083] <7.4 Cavity> The cavity 54 has a first end 54e1 and a second end 54e2. The first end 54e1 is the end (upper end) on the +Z direction side. The second end 54e2 is the end (lower end) on the −Z direction side.

[0084] In this embodiment, the first end 54e1 corresponds to the boundary between the first insulating portion 53a and the second insulating portion 53b. In this embodiment, the first end 54e1 is located at the same height as the region where the multiple first dummy word lines WLD1 are provided. For example, the region where the first dummy word lines WLD1 are provided may be the region between the position where the lowest first dummy word line WLD1 among the multiple first dummy word lines WLD1 is provided and the position where the highest first dummy word line WLD1 is provided. For example, the first end 54e1 is located closer to the -Z direction than multiple (e.g., all) source line side select gate lines SGS. For example, the first end 54e1 is located closer to the -Z direction than one word line WL (e.g., one first dummy word line WLD1) among the multiple word lines WL that is located closer to the -Z direction than the multiple source line side select gate lines SGS.

[0085] In this embodiment, the second end 54e2 corresponds to the boundary between the second insulating portion 53b and the third insulating portion 53c. In this embodiment, the second end 54e2 is located at the same height as a region in which multiple drain-side select gate lines SGD are provided. The region in which the drain-side select gate lines SGD are provided may be a region between the position where the lowest drain-side select gate line SGD among the multiple drain-side select gate lines SGD is provided and the position where the highest drain-side select gate line SGD is provided.

[0086] In this embodiment, the second end 54e2 is located closer to the −Z direction than multiple (e.g., all) second dummy word lines WLD2. For example, the second end 54e2 is located closer to the −Z direction than one drain-side selection gate line SGD that is located closer to the −Z direction than the multiple second dummy word lines WLD2 among the multiple drain-side selection gate lines SGD.

[0087] Alternatively, the second end 54e2 may be located at the same height as the region where the plurality of second dummy word lines WLD2 are provided. For example, the region where the second dummy word lines WLD2 are provided may be the region between the position where the lowest dummy word line WLD2 among the plurality of second dummy word lines WLD2 is provided and the position where the highest dummy word line WLD2 is provided. In another example, the position in the Z direction of the second end 54e2 may be located between the lowest second dummy word line WLD2 and the highest drain line side select gate line SGD.

[0088] Alternatively, the second end 54e2 may be located further in the +Z direction in FIG. 5 than the region in which the plurality of second dummy word lines WLD2 are provided. For example, the second end 54e2 may be located further in the +Z direction than the topmost second dummy word line WLD2 (the second dummy word line WLD2 located furthest in the +Z direction) of the plurality of second dummy word lines WLD2. For example, the second end 54e2 may be located between the topmost second dummy word line WLD2 of the plurality of second dummy word lines WLD2 and a word line WL that is within tenth position in the +Z direction from the topmost second dummy word line WLD2. For example, the second end 54e2 may be located between the topmost second dummy word line WLD2 of the plurality of second dummy word lines WLD2 and a word line WL that is within fiveth position in the +Z direction from the topmost second dummy word line WLD2.

[0089] <7.5 Dimensional relationship of insulating parts> 7 is an enlarged cross-sectional view of the area surrounded by line F7 of the memory cell array 11 shown in FIG. Here, the center line CL of the memory pillar MH is defined. The center line CL is a virtual center line that extends in the Z direction and passes through the center C of the memory pillar MH in the X direction in the cross section along the X and Z directions.

[0090] In this embodiment, when viewed in a cross section along the X and Z directions in the region R between the center line CL and the channel layer 52, the thickness T2 in the X direction of the second insulating portion 53b is smaller than the thickness T1 in the X direction of the first insulating portion 53a.

[0091] In the present application, the "thickness of the first insulating portion" and the "thickness of the second insulating portion" are considered to exclude the thickness of portions where the thickness changes abruptly compared to other portions, such as the boundary between the first insulating portion 53a and the second insulating portion 53b. Furthermore, in the present application, the "thickness of the second insulating portion" is considered to exclude the thickness of portions near the connections between the memory pillars MH (for example, portions adjacent in the X direction to the upper five word lines WL and the lower five word lines WL that are close to the connections between the memory pillars MH) when the memory pillars MH have a multi-stage configuration in the Z direction.

[0092] In this embodiment, when viewed in region R, the maximum thickness T2max of the second insulating portion 53b in the X direction is smaller than the maximum thickness T1max of the first insulating portion 53a in the X direction. Furthermore, when viewed in region R, the minimum thickness T2min of the second insulating portion 53b in the X direction is smaller than the minimum thickness T1min of the first insulating portion 53a in the X direction. Furthermore, when viewed in region R, the maximum thickness T2max of the second insulating portion 53b in the X direction is smaller than the minimum thickness T1min of the first insulating portion 53a in the X direction.

[0093] For ease of explanation, "maximum thickness T1max" and "maximum thickness T2max" are shown in Fig. 7, but the portions where the thickness of the first insulating portion 53a is greatest or the portions where the thickness of the second insulating portion 53b is greatest are not limited to the positions shown in the figure. Similarly, for ease of explanation, "minimum thickness T1min" and "minimum thickness T2min" are shown in Fig. 7, but the portions where the thickness of the first insulating portion 53a is least or the portions where the thickness of the second insulating portion 53b is least are not limited to the positions shown in the figure.

[0094] In this embodiment, the second insulating portion 53b extends in the Z direction so as to be adjacent to all of the data word lines WLA. When viewed in region R, the thickness T2 of the second insulating portion 53b in the X direction is smaller than the thickness T1 (e.g., minimum thickness T1min) of the first insulating portion 53a in the X direction over the entire length of the second insulating portion 53b in the Z direction.

[0095] In this embodiment, when viewed in region R, the maximum thickness T2max of the second insulating portion 53b in the X direction is smaller than the minimum thickness T1min of the first insulating portion 53a in the X direction. For convenience of explanation, the "maximum thickness T2max" is illustrated in FIG. 7, but the portion where the thickness of the second insulating portion 53b is greatest is not limited to the position illustrated. For example, the thickness of the second insulating portion 53b may be greatest at the end of the second insulating portion 53b on the -Z direction side.

[0096] In this embodiment, when viewed in region R, the thickness T2 (e.g., maximum thickness T2max) of the second insulating portion 53b in the X direction is equal to or less than half the thickness T1 (e.g., maximum thickness T1max) of the first insulating portion 53a in the X direction. From another perspective, when viewed in region R, the minimum thickness T2min of the second insulating portion 53b in the X direction is equal to or less than half the minimum thickness T1min of the first insulating portion 53a in the X direction.

[0097] <7.6 Dimensional relationship between insulating layer and other functional layers> Fig. 8 is an enlarged cross-sectional view of a region surrounded by line F8 of the memory cell array 11 shown in Fig. 7. In this embodiment, each gate electrode layer 41 includes, for example, a conductive portion 45, a barrier metal film 46, and an insulating film 47.

[0098] The conductive portion 45 is a portion that forms the main portion of the gate electrode layer 41. The conductive portion 45 extends in a layered manner in the X and Y directions. The conductive portion 45 includes the above-mentioned conductive material (for example, tungsten, molybdenum, or silicon doped with an impurity).

[0099] The barrier metal film 46 is a film for suppressing diffusion of the conductive material contained in the conductive portion 45. The barrier metal film 46 includes, for example, a material containing titanium, a material containing titanium and nitrogen, a material containing tantalum, a material containing tantalum and nitrogen, or a material containing tungsten and nitrogen. The barrier metal film 46 is provided along the surface of the conductive portion 45. The barrier metal film 46 is provided between the conductive portion 45 and the insulating film 47. A portion of the barrier metal film 46 extends in the Z direction along the edge of the conductive portion 45 facing the memory pillar MH, and is located between the conductive portion 45 and the memory pillar MH.

[0100] The insulating film 47 is an insulating film that improves the voltage resistance of the gate electrode layer 41. The insulating film 47 is formed, for example, of a film containing aluminum and oxygen (for example, an aluminum oxide film). The insulating film 47 is provided along the surface of the barrier metal film 46. The insulating film 47 is provided along the surface of the gate electrode layer 41. A part of the insulating film 47 extends in the Z direction along the edge of the barrier metal film 46 facing the memory pillar MH, and is located between the barrier metal film 46 and the memory pillar MH.

[0101] In this embodiment, the block insulating film 61 includes a first portion 61a and a second portion 61b. The first portion 61a is formed in an annular shape along the outer periphery of the charge trap film 62 and extends in the Z direction. For example, the first portion 61a extends over the entire length of the memory pillar MH in the Z direction except for the upper end of the memory pillar MH.

[0102] On the other hand, the second portion 61b is formed by a part of the insulating film 47 of the multiple gate electrode layers 41. The second portion 61b is formed in a ring shape along the outer periphery of the first portion 61a of the block insulating film 61, and exists at a height corresponding to the height at which the gate electrode layers 41 are arranged. In this embodiment, the block insulating film 61 is formed by the first portion 61a and the second portion 61b.

[0103] In this embodiment, the X-direction thickness T2 of the second insulating portion 53b is smaller than the X-direction thickness T4 of the memory film 51. For example, the X-direction thickness T2 of the second insulating portion 53b is smaller than the X-direction thickness T4a of the block insulating film 61. Note that the "X-direction thickness of the block insulating film 61" is the sum of the X-direction thickness of the first portion 61a of the block insulating film 61 and the X-direction thickness of the second portion 61b of the block insulating film 61.

[0104] From another perspective, the X-direction thickness T2 of the second insulating portion 53b is smaller than the sum of the X-direction thickness T4b of the charge trap film 62 and the X-direction thickness T4c of the tunnel insulating film 63. From another perspective, the X-direction thickness T2 of the second insulating portion 53b is smaller than the sum of the X-direction thickness T4b of the charge trap film 62 and the X-direction thickness T5 of the channel layer 52. From another perspective, the X-direction thickness T2 of the second insulating portion 53b is smaller than the sum of the X-direction thickness T4c of the tunnel insulating film 63 and the X-direction thickness T5 of the channel layer 52.

[0105] In this embodiment, the minimum thickness T2min of the second insulating portion 53b in the X direction is 10 nm or less. In other words, the thickness T2 of at least a part of the second insulating portion 53b in the X direction is 10 nm or less.

[0106] In this embodiment, the average thickness of the second insulating portion 53b in the X direction is 10 nm or less. In this application, the "average thickness of the second insulating portion" refers to the average value of thicknesses of the second insulating portion 53b measured at five locations, for example, by dividing the entire length of the second insulating portion 53b in the Z direction into five equal parts.

[0107] In this embodiment, the maximum thickness T2max of the second insulating portion 53b in the X direction is 10 nm or less. In other words, the thickness T2 of the second insulating portion 53b in the X direction is 10 nm or less over the entire length of the second insulating portion 53b in the Z direction.

[0108] <7.7 Impurity concentration in insulating parts> Next, the impurity concentration of the insulating portion 53 will be described. Impurities are implanted into the insulating portion 53. The impurities are, for example, donor impurities (elements with more valence electrons than tetravalent elements, for example, pentavalent elements). The impurity is, for example, phosphorus (P), but is not limited to this.

[0109] FIG. 9 is a diagram showing the profile of the impurity concentration (e.g., phosphorus concentration) in the insulating portion 53. In this embodiment, the impurity concentration in the first insulating portion 53a is higher than the impurity concentration in the second insulating portion 53b. In this embodiment, the impurity concentration in the first insulating portion 53a changes sharply in the Z direction. For example, when viewed in the direction proceeding toward the -Z direction, the rate of decrease in the impurity concentration in the first insulating portion 53a is higher than the rate of decrease in the impurity concentration in the second insulating portion 53b. For example, the rate of decrease in the impurity concentration in the first insulating portion 53a is more than twice the rate of decrease in the impurity concentration in the second insulating portion 53b.

[0110] Here, when the impurity concentration in the first insulating portion 53a varies greatly in the Z direction, the GIDL (Gate-Induced-Drain-Leakage current) current generated using the source line side select gate line SGS can be increased. Increasing the GIDL current makes it easier to perform an erase operation to erase data stored in the memory cell transistor MT.

[0111] <8. Manufacturing method> Next, a method for manufacturing the semiconductor memory device 1 will be described. 10A to 10K are cross-sectional views illustrating a method for manufacturing the semiconductor memory device 1. Note that Fig. 10A to 10K are illustrated based on the posture during manufacturing.

[0112] First, as shown in FIG. 10A, an insulating layer 102 is formed on a semiconductor substrate 101. Next, an insulating layer 43 is formed on the insulating layer 102. Next, sacrificial layers 111 and insulating layers 42 are alternately stacked one by one on the insulating layer 43 in the Z direction. The sacrificial layer 111 is formed, for example, of a film containing silicon and nitrogen (e.g., a silicon nitride film). The sacrificial layer 111 is a layer that will be replaced with a gate electrode layer 41 in a replacement process described later. Next, an insulating layer 103 is formed on the uppermost sacrificial layer 111. This forms a stacked body 40A including the insulating layer 43, multiple sacrificial layers 111, multiple insulating layers 42, and insulating layer 103. The sacrificial layer 111 is an example of a "first layer" and a "first insulating layer." The insulating layer 42 is an example of a "second layer" and a "second insulating layer."

[0113] 10B, holes H1 are formed in the stack 40A by, for example, etching. The holes H1 penetrate the insulating layer 103, the plurality of sacrificial layers 111, the plurality of insulating layers 42, and the insulating layer 43 in the Z direction. The holes H1 are holes in which memory pillars MH will be formed in a later process.

[0114] 10C, materials for the first portion 61a of the block insulating film 61, the charge trap film 62, the tunnel insulating film 63, and the channel layer 52 are supplied in this order into the hole H1. As a result, the first portion 61a of the block insulating film 61, the charge trap film 62, the tunnel insulating film 63, and the channel layer 52 are formed inside the hole H1. As a result, the first portion 61a of the block insulating film 61, the charge trap film 62, and the tunnel insulating film 63 form the memory film 51A.

[0115] 10D, an insulating material is supplied to the inner periphery of the channel layer 52. As a result, an insulating portion 121 is formed at the lower portion (e.g., the lower end) of the hole H1 on the inner periphery of the channel layer 52. The insulating portion 121 is formed, for example, from a material containing silicon and oxygen (e.g., silicon oxide).

[0116] The insulating portion 121 is formed, for example, by alternately forming an insulating film by atomic layer deposition (ALD) and supplying a gas (for example, nitrogen trifluoride (NF3)) to suppress the formation of an insulating film on the side surface of the channel layer 52. For example, by using the above-mentioned method, the insulating portion 121 is formed only in the lower portion (for example, the lower end) of the hole H1. Note that the method for forming the insulating portion 121 is not limited to the above-mentioned example. Instead of the above example, a method in which the insulating portion 121 is formed up to above the lower end of the hole H1 may be used.

[0117] Next, as shown in FIG. 10E, unnecessary portions of the insulating portion 121 are removed. This removes portions of the insulating portion 121 adjacent in the X and Y directions to the sacrificial layers 111 that will be replaced by the data word lines WLA in a replacement process described later among the multiple sacrificial layers 111. As a result, for example, the channel layer 52 is exposed inside the hole H1 in the portions adjacent in the X and Y directions to the sacrificial layers 111 that will be replaced by the data word lines WLA. The unnecessary portions of the insulating portion 121 can be removed by wet etching using diluted hydrofluoric acid, for example. By performing this process, the insulating portion 121 from which the unnecessary portions have been removed forms the above-mentioned first insulating portion 53a. This makes it easier to form the second insulating portion 53b in regions corresponding to many word lines WL (for example, all of the data word lines WLA).

[0118] 10F, an insulating material is supplied to the inner periphery of the channel layer 52 under supply conditions adjusted in advance. As a result, a second insulating portion 53b and a third insulating portion 53c are formed so as to form a cavity 54 inside the memory pillar MH. That is, the second insulating portion 53b is formed along the inner periphery surface of the channel layer 52 and has the cavity 54 on the inner periphery side, and the third insulating portion 53c closes the upper end of the second insulating portion 53b. As described above, the second insulating portion 53b may be partially interrupted midway in the Z direction.

[0119] 10G, unnecessary portions of the insulating portion 53 are removed to form the cap portion 55. This forms the main portion of the memory pillar MH.

[0120] Next, as shown in FIG. 10H, a replacement step is performed. In the replacement step, a wet etching solution is supplied from a groove (not shown) to remove the plurality of sacrificial layers 111. Next, a conductive material is supplied into the space where the plurality of sacrificial layers 111 have been removed, thereby forming the plurality of gate electrode layers 41. This forms the above-described stacked body 40. Thereafter, the contacts CH, the contacts VY, the plurality of bit lines BL, the wiring portion 70, the insulating portion 31, and the like are formed. This forms the above-described chip 3.

[0121] 10I, chip 3 is turned upside down and separately formed chip 2 and chip 3 are bonded together. Next, semiconductor substrate 101 and insulating layer 102 are removed by, for example, etching. As a result, the upper end of memory film 51 is exposed to the outside.

[0122] Next, as shown in FIG. 10J, impurities (e.g., phosphorus) are implanted from the +Z direction side. In this embodiment, a first insulating portion 53a that is relatively thick in the X direction is present at the upper end of the memory pillar MH. Therefore, the impurities are easily taken into the first insulating portion 53a, and the impurities are less likely to move toward the second insulating portion 53b. As a result, the insulating portion 53 has a profile in which the impurity concentration in the Z direction changes significantly inside the first insulating portion 53a.

[0123] Next, as shown in FIG. 10K, unnecessary portions (upper ends) of the memory film 51 are removed. Next, the source lines SL are formed so as to cover the insulating layer 43 and the upper ends of the memory pillars MH. Next, the remaining insulating portions and the like are formed. This completes the semiconductor memory device 1.

[0124] <9. Effect> Next, an example of the operation of the semiconductor memory device 1 will be described. 11 is a diagram for explaining the influence of the thickness T2 of the second insulating portion 53b in the X direction. Fig. 11 shows the relationship between the thickness T2 of the second insulating portion 53b in the X direction and drain-induced barrier lowering (DIBL), which was discovered through research by the present inventors. The "drain-induced barrier lowering" here refers to the susceptibility of the threshold voltage of the memory cell transistor MT to fluctuations due to the drain voltage.

[0125] 11, the present inventors have found that the smaller the thickness T2 of the second insulating portion 53b in the X direction, the better the drain-induced barrier lowering. For example, the present inventors have found that when the thickness T2 of the second insulating portion 53b in the X direction is 10 nm or less, the improvement in the drain-induced barrier lowering increases rapidly.

[0126] <10. Advantages> In recent years, semiconductor memory devices are expected to achieve even higher density. However, as the density of semiconductor memory devices increases, the influence of interference between adjacent word lines WL increases, which may cause the distribution of threshold voltages of memory cell transistors MT to widen. This widening of the distribution of threshold voltages of memory cell transistors MT degrades the electrical characteristics of the semiconductor memory device.

[0127] Therefore, the semiconductor memory device 1 of this embodiment includes a stacked body 40 and a memory pillar MH. The memory pillar MH includes a memory film 51 including a charge storage portion 62a, a channel layer 52 provided on the inner periphery of the memory film 51 in the X direction, an insulating portion 53 provided on the inner periphery of the channel layer 52 in the X direction, and a cavity 54 adjacent to at least a portion of the insulating portion 53 in the Z direction. The insulating portion 53 includes a first insulating portion 53a adjacent to the multiple source line-side select gate lines SGS in the X direction, and a second insulating portion 53b adjacent to the cavity 54 in the X direction and adjacent to at least some of the multiple word lines WL in the X direction. When viewed in the region R between the center line CL and the channel layer 52, the thickness T2 in the X direction of the second insulating portion 53b is smaller than the thickness T1 in the second direction X of the first insulating portion 53a.

[0128] With this configuration, the thickness T2 of the second insulating portion 53b in the X direction is small, which improves the drain-induced barrier lowering and prevents the threshold voltage distribution of the memory cell transistors MT from widening. Therefore, even if the density of the semiconductor memory device 1 increases, the influence of interference between adjacent word lines WL can be prevented from increasing. This improves the electrical characteristics of the semiconductor memory device 1.

[0129] On the other hand, when the thickness T1 of the first insulating portion 53a in the second direction X is large, the change in impurity concentration in the first insulating portion 53a in the Z direction can be made large. Increasing the change in impurity concentration in the first insulating portion 53a in the Z direction can increase the GIDL (Gate-Induced-Drain-Leakage current) current generated using the source-side select gate line SGS. Increasing the GIDL current facilitates the erase operation of erasing data stored in the memory cell transistor MT. From this perspective, too, the electrical characteristics of the semiconductor memory device 1 can be improved.

[0130] In this embodiment, the maximum thickness T2max in the X direction of the second insulating portion 53b is smaller than the maximum thickness T1max in the X direction of the first insulating portion 53a in the region R. With this configuration, the thickness T2 in the X direction of the second insulating portion 53b is smaller, which makes it easier to further improve the drain-induced barrier lowering.

[0131] In this embodiment, the maximum thickness T2max in the X direction of the second insulating portion 53b is smaller than the minimum thickness T1min in the X direction of the first insulating portion 53a in the region R. With this configuration, the thickness T2 in the X direction of the second insulating portion 53b is smaller, which makes it easier to further improve the drain-induced barrier lowering.

[0132] In this embodiment, the thickness T2 of the second insulating portion 53b in the X direction is equal to or less than half the thickness T1 of the first insulating portion 53a in the X direction when viewed in the region R. With this configuration, the thickness T2 of the second insulating portion 53b in the X direction is smaller, which makes it easier to further improve the drain-induced barrier lowering.

[0133] In this embodiment, the second insulating portion 53b is adjacent to the multiple data word lines WLA in the X direction. When viewed in region R, the thickness T2 of the second insulating portion 53b in the X direction is smaller than the thickness T1 of the first insulating portion 53a in the X direction over the entire length of the second insulating portion 53b in the Z direction. This configuration makes it easier to further improve the drain-induced barrier lowering for the memory cell transistors MT corresponding to the multiple data word lines WLA.

[0134] In this embodiment, the minimum thickness T2min of the second insulating portion 53b in the X direction is 10 nm or less. With this configuration, the thickness T2 of the second insulating portion 53b in the X direction is smaller, which makes it easier to further improve the drain-induced barrier lowering.

[0135] In this embodiment, the concentration of impurities contained in the first insulating portion 53a is higher than the concentration of impurities contained in the second insulating portion 53b. This configuration allows the change in the impurity concentration in the first insulating portion 53a in the Z direction to be greater. This makes it easier to increase the GIDL current generated using the source line side select gate line SGS.

[0136] In this embodiment, the change in the impurity concentration in the first insulating portion 53a in the Z direction is greater than the change in the impurity concentration in the second insulating portion 53b in the Z direction. This configuration can further increase the change in the impurity concentration in the first insulating portion 53a in the Z direction. This makes it easier to increase the GIDL current generated using the source line side select gate line SGS.

[0137] In this embodiment, the first end 54e1 of the cavity 54 is located closer to the -Z direction than the source-side select gate lines SGS. This configuration makes it easier to increase the thickness of the first insulating portion 53a in the X direction. This allows for a larger change in impurity concentration in the first insulating portion 53a in the Z direction, making it easier to increase the GIDL current generated using the source-side select gate lines SGS.

[0138] In this embodiment, the first end 54e1 of the cavity 54 is located on the -Z direction side of one of the word lines WL (e.g., one dummy word line WLD1) that is closest to the source line side select gate lines SGS. This configuration makes it easy to increase the thickness in the X direction of the first insulating portion 53a adjacent to the source line side select gate lines SGS. This makes it easier to increase the change in impurity concentration in the first insulating portion 53a in the Z direction, and makes it easier to increase the GIDL current generated using the source line side select gate line SGS.

[0139] <11. Variations> Next, several modified examples will be described. In each modified example, the configuration other than that described below is the same as that of the first embodiment.

[0140] (First Modification) 12 is a cross-sectional view showing a memory cell array 11 of a first modification. In the first modification, the position in the Z direction of the first end 54e1 of the cavity 54 is located between the lowest source-side select gate line SGS and the highest first dummy word line WLD1. Even with this configuration, the same effects as those of the semiconductor memory device 1 of the first embodiment can be achieved.

[0141] (Second Modification) 13 is a cross-sectional view showing a memory cell array 11 of a second modified example. In the second modified example, a part of the cavity 54 is provided inside the first insulating portion 53a.

[0142] 14 is an enlarged cross-sectional view showing a region surrounded by line F14 of the memory cell array 11 shown in FIG. 13. In this modification, the minimum thickness T1min in the X direction of the first insulating portion 53a is the dimension between the cavity 54 and the channel layer 52. Even with this configuration, it is possible to achieve the same effects as those of the semiconductor memory device 1 of the first embodiment.

[0143] (Second embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment in that the second insulating portion 53b is not present. Note that the configuration other than that described below is the same as the configuration of the first embodiment.

[0144] FIG. 15 is a cross-sectional view showing a memory cell array 11 of the second embodiment. In this embodiment, the insulating portion 53 does not have a second insulating portion 53b. The insulating portion 53 is formed of a first insulating portion 53a and a third insulating portion 53c. In this embodiment, in a region adjacent to a plurality of data word lines WLA, the inner surface of the channel layer 52 is exposed to the cavity portion 54. Even with this configuration, it is possible to achieve the same effects as the semiconductor memory device 1 of the first embodiment.

[0145] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the first embodiment in that a separating portion SHEU is provided to separate the source line side select gate line SGS. Note that the configuration other than that described below is the same as that of the first embodiment.

[0146] FIG. 16 is a cross-sectional view showing a memory cell array 11 of the third embodiment. In this embodiment, the multiple dividing portions 80 have multiple dividing portions SHEU in addition to the dividing portion ST and dividing portion SHE described above. The dividing portion SHEU is a dividing portion whose length in the Z direction is shorter than that of the dividing portion ST, and is a wall portion that divides the upper end portion of the stacked body 40 in the Y direction. The multiple dividing portions SHEU are arranged separately in the Y direction. In this embodiment, multiple dividing portions SHEU (for example, four) are present between two dividing portions ST adjacent to each other in the Y direction. The dividing portion SHEU is provided at the upper end portion of the stacked body 40, extends in the Z direction halfway through the stacked body 40, and also extends in the X direction. In other words, the dividing portion SHEU is a wall portion along the Z direction and the X direction.

[0147] The dividing portion SHEU penetrates some of the gate electrode layers 41, including the uppermost layer, of the plurality of gate electrode layers 41, and divides the some of the gate electrode layers 41 in the Y direction. For example, the dividing portion SHEU penetrates each of all of the gate electrode layers 41 that function as source-side select gate lines SGS. The dividing portion SHEU may also penetrate each of some or all of the gate electrode layers 41 that function as first dummy word lines WLD1. On the other hand, the dividing portion SHEU does not reach the gate electrode layers 41 that function as data word lines WLA. The dividing portion SHEU divides only the gate electrode layers 41 that function as source-side select gate lines SGS in the Y direction. The dividing portion SHEU is formed, for example, from a film containing silicon and oxygen (for example, a silicon oxide film).

[0148] Even with this configuration, it is possible to achieve the same effects as the semiconductor memory device 1 of the first embodiment.

[0149] A number of embodiments and modifications have been described above. However, the embodiments and modifications are not limited to the examples described above. For example, the embodiments and modifications described above may be realized in combination with each other.

[0150] According to at least one embodiment described above, the semiconductor memory device includes a stacked body, a pillar, and a bit line. The stacked body includes a plurality of gate electrode layers and a plurality of insulating layers. When a direction intersecting the first direction is defined as a second direction and an imaginary center line extending in the first direction through the center of the pillar in the second direction is defined as follows: The pillar includes a memory film, a semiconductor film, and an insulating portion. The insulating portion includes a first insulating portion adjacent to a plurality of first select gate lines and a second insulating portion adjacent to at least some word lines. When viewed in a region between the center line and the semiconductor film, the thickness of the second insulating portion in the second direction is smaller than the thickness of the first insulating portion in the second direction. This configuration can improve the electrical characteristics of the semiconductor memory device.

[0151] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0152] 1...Semiconductor memory device 40...Laminate 41...gate electrode layer 42...insulating layer 51...Memory film 52...Channel layer (semiconductor film) 53...Insulation part 53a...First insulating part 53b...Second insulating part 53c...Third insulating section 54...Cavity part 54e1...first end of cavity 54e2...Second end of the cavity 61...Block insulating film (first insulating film) 62...Charge trap film 63...Tunnel insulating film (second insulating film) MH...Memory pillar (columnar body) BL...bit line SGS...Source side select gate line (first select gate line) SGD: Drain side select gate line (second select gate line) WL...word line WLD1...First dummy word line (first word line) WLD2: Second dummy word line (second word line) WLA...Data word line (third word line) CL…Center line

Claims

1. a stacked body including a plurality of gate electrode layers and a plurality of insulating layers, the plurality of gate electrode layers and the plurality of insulating layers being alternately stacked one layer at a time in a first direction; a columnar body extending in the first direction within the stack; a bit line disposed on a first side of the pillar in the first direction; Equipped with The plurality of gate electrode layers are a plurality of word lines each having a memory cell transistor formed at an intersection with the pillar; a plurality of first select gate lines arranged on a second side opposite to the first side with respect to the plurality of word lines, and each having a first select transistor formed at an intersection with the pillar-shaped body; Including, When a direction intersecting the first direction is defined as a second direction, The columnar body is a memory film including a charge storage portion; a semiconductor film provided on the inner periphery side of the memory film in the second direction; an insulating portion provided on an inner periphery side of the semiconductor film in the second direction; a cavity portion adjacent to at least a portion of the insulating portion in the first direction; Including, The insulating portion is a first insulating portion adjacent to the plurality of first select gate lines in the second direction; a second insulating portion adjacent to the cavity portion in the second direction and adjacent to at least some of the word lines included in the plurality of word lines in the second direction; Including, In a cross section along the first direction and the second direction, a virtual center line is defined that passes through a center in the second direction of the columnar body and extends in the first direction, and when viewed from a region between the center line and the semiconductor film, the thickness of the second insulating portion in the second direction is smaller than the thickness of the first insulating portion in the second direction. Semiconductor memory device.

2. When viewed from the region, a maximum thickness of the second insulating portion in the second direction is smaller than a maximum thickness of the first insulating portion in the second direction.

2. The semiconductor memory device according to claim 1.

3. When viewed from the region, a maximum thickness of the second insulating portion in the second direction is smaller than a minimum thickness of the first insulating portion in the second direction.

3. The semiconductor memory device according to claim 1.

4. When viewed from the region, the thickness of the second insulating portion in the second direction is equal to or less than half the thickness of the first insulating portion in the second direction.

3. The semiconductor memory device according to claim 1.

5. the plurality of gate electrode layers are arranged on the first side with respect to the plurality of word lines, and further include a plurality of second select gate lines, each having a second select transistor formed at an intersection with the pillar; the plurality of word lines include five or less first word lines that are closest to the plurality of first select gate lines among the plurality of word lines, five or less second word lines that are closest to the plurality of second select gate lines among the plurality of word lines, and a plurality of third word lines that are the remaining word lines among the plurality of word lines; the second insulating portion is adjacent to the third word lines in the second direction; When viewed from the region, the thickness of the second insulating portion in the second direction is smaller than the thickness of the first insulating portion over the entire length of the second insulating portion in the first direction.

3. The semiconductor memory device according to claim 1.

6. the memory film includes a first insulating film, a charge trap film provided on an inner circumferential side of the first insulating film, and a second insulating film provided on an inner circumferential side of the charge trap film; a thickness of the second insulating portion in the second direction being smaller than a thickness of the memory film in the second direction; 3. The semiconductor memory device according to claim 1.

7. The minimum thickness of the second insulating portion in the second direction is 10 nm or less.

3. The semiconductor memory device according to claim 1.

8. When viewed in a direction proceeding toward the first side of the first direction, a reduction rate of the impurity concentration in the first insulating portion is greater than a reduction rate of the impurity concentration in the second insulating portion; 3. The semiconductor memory device according to claim 1.

9. an end of the cavity on the second side is located closer to the first side than the plurality of first select gate lines; 3. The semiconductor memory device according to claim 1.

10. an end of the cavity on the second side is located closer to the first side than one word line among the plurality of word lines that is closest to the plurality of first select gate lines; 3. The semiconductor memory device according to claim 1.

11. the semiconductor film is exposed to the cavity at a position adjacent to some of the word lines included in the plurality of word lines in the second direction; 3. The semiconductor memory device according to claim 1.

12. a stacked body including a plurality of gate electrode layers and a plurality of insulating layers, the plurality of gate electrode layers and the plurality of insulating layers being alternately stacked one layer at a time in a first direction; a columnar body extending in the first direction within the stack; a bit line disposed on a first side of the pillar in the first direction; Equipped with The plurality of gate electrode layers are a plurality of word lines each having a memory cell transistor formed at an intersection with the pillar; a plurality of first select gate lines arranged on a second side opposite to the first side with respect to the plurality of word lines, and each having a first select transistor formed at an intersection with the pillar-shaped body; Including, When a direction intersecting the first direction is defined as a second direction, The columnar body is a memory film including a charge storage portion; a semiconductor film provided on the inner periphery side of the memory film in the second direction; an insulating portion provided on an inner periphery side of the semiconductor film in the second direction; a cavity portion adjacent to at least a portion of the insulating portion in the first direction; Including, the insulating portion includes a portion adjacent to the plurality of first select gate lines in the second direction, the semiconductor film is exposed to the cavity at a position adjacent to at least some of the word lines included in the plurality of word lines in the second direction; Semiconductor memory device.

13. forming a laminate in which the first layers and the second layers are alternately stacked in a first direction; forming a hole extending in the first direction in the laminate; forming a memory film including a charge storage portion along an inner peripheral surface of the hole, and a semiconductor film provided on the inner peripheral side of the memory film; forming an insulating portion at a lower portion of the hole on the inner periphery side of the semiconductor film; removing an upper end of the insulating portion by wet etching to form a first insulating portion; forming a second insulating portion that is along the inner circumferential surface of the semiconductor film and has a cavity on the inner circumferential side, and a third insulating portion that closes an upper end of the second insulating portion; A method for manufacturing a semiconductor memory device, comprising:

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