Semiconductor memory device and control method thereof

Abstract

To provide a memory which suppresses a leakage current or a hot carrier of a selection transistor in a non-conductive state in a data reading operation.SOLUTION: The memory comprises a string including cells connected in series. The first select transistor is connected to a cell at one end of the string. The second select transistor is connected to a cell at the other end of the string. The first control line is provided in common to the strings and connected to the gates of the cells. The first selection line is connected to a gate of the first selection transistor and is provided for each first unit including a plurality of strings. The second selection line is connected to a gate of the second selection transistor and provided for each second unit including a plurality of first units. In a data read operation, the driving unit makes a first non-selection voltage applied to a non-selected first selection line in a selected second unit selected as a read target different from a second non-selection voltage applied to a first selection line in the non-selected second unit.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor memory device and a control method thereof. [Background technology]

[0002] NAND flash memory has select transistors at both ends of a string of multiple memory cells connected in series. During a data read operation, the select transistors connected to strings that are not the target of data read are in a non-conductive state. However, in the non-conductive state, an increase in leakage current or hot carriers has been a problem. Summary of the Invention [Problem to be solved by the invention]

[0003] A semiconductor memory device and a driving method thereof are provided that can suppress leakage current or hot carriers in a non-conductive select transistor during a data read operation. [Means for solving the problem]

[0004] The semiconductor memory device according to this embodiment includes a plurality of strings, each including a plurality of memory cells connected in series. A plurality of first selection transistors are connected to memory cells at one end of the plurality of strings. A plurality of second selection transistors are connected to memory cells at the other end of the plurality of strings. A plurality of first control lines are provided in common to the plurality of strings and are connected to gates of the plurality of memory cells, respectively. A plurality of first selection lines are connected to gates of the plurality of first selection transistors, and are provided corresponding to first units including a plurality of strings. A plurality of second selection lines are connected to gates of the plurality of second selection transistors, and are provided corresponding to second units including a plurality of first units, respectively. A drive unit drives the voltages of the plurality of first selection lines. In a data read operation, the drive unit differentiates a first non-selection voltage applied to unselected first selection lines in a selected second unit selected as a read target among the plurality of second units from a second non-selection voltage applied to first selection lines in unselected second units not selected as a read target among the plurality of second units. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor memory device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array. [Figure 3] 1 is a cross-sectional view showing an example of the configuration of a semiconductor memory device according to an embodiment. [Figure 4] FIG. [Figure 5] FIG. 1 is a cross-sectional view illustrating a memory cell having a three-dimensional structure. [Figure 6] FIG. 1 is a cross-sectional view illustrating a memory cell having a three-dimensional structure. [Figure 7] 1 is a plan view showing a memory cell array and a method for controlling a read operation according to the present embodiment; [Figure 8] FIG. 1 illustrates a NAND string during a data read operation. [Figure 9]Diagram showing the states of a NAND string and the energy levels of the channel. [Figure 10] Diagram showing the states of a NAND string and the energy levels of the channel. DETAILED DESCRIPTION OF THE INVENTION

[0006] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual. In the specification and drawings, the same elements are designated by the same reference numerals.

[0007] 1 is a block diagram showing an example of the configuration of a semiconductor memory device according to this embodiment. The semiconductor memory device 1 is, for example, a NAND flash memory capable of storing data in a non-volatile manner, and is controlled by an external memory controller 1002. Communication between the semiconductor memory device 1 (hereinafter referred to as memory 1) and the memory controller 1002 supports, for example, the NAND interface standard.

[0008] As shown in FIG. 1, the memory 1 includes, for example, a memory cell array MCA, a command register 1011, an address register 1012, a sequencer 1013, a driver module 1014, a row decoder module 1015, and a sense amplifier module 1016.

[0009] The memory cell array MCA includes a plurality of blocks BLK(0) to BLK(n) (n is an integer equal to or greater than 1). A block BLK is a set of a plurality of memory cells capable of storing data non-volatilely, and is used, for example, as a unit for erasing data. The memory cell array MCA is also provided with a plurality of bit lines and a plurality of word lines. Each memory cell is associated with, for example, one bit line and one word line.

[0010] The command register 1011 holds a command CMD that the memory 1 receives from the memory controller 1002. The command CMD includes, for example, an instruction to make the sequencer 1013 execute a read operation, a write operation, an erase operation, or the like.

[0011] The address register 1012 holds address information ADD that the memory 1 receives from the memory controller 1002. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used to select a block BLK, a word line, and a bit line, respectively.

[0012] The sequencer 1013 controls the overall operation of the memory 1. For example, the sequencer 1013 controls the driver module 1014, the row decoder module 1015, the sense amplifier module 1016, etc. based on the command CMD held in the command register 1011 to execute a read operation, a write operation, an erase operation, etc.

[0013] The driver module 1014 generates voltages used in read operations, write operations, erase operations, etc. The driver module 1014 applies voltages to the word lines, the drain side select gate lines SGD, and the source side select gate lines SGS based on the page address PA held in the address register 1012, for example.

[0014] The row decoder module 1015 includes a plurality of row decoders. The row decoder selects one block BLK in the corresponding memory cell array MCA based on a block address BA held in the address register 1012. Then, the row decoder transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0015] In a write operation, the sense amplifier module 1016 applies a desired voltage to each bit line serving as a data line in accordance with write data DAT received from the memory controller 1002. In a read operation, the sense amplifier module 1016 determines the data stored in the memory cell based on the voltage of the bit line, and transfers the determination result to the memory controller 1002 as read data DAT.

[0016] The memory 1 and memory controller 1002 described above may be combined to form a single semiconductor storage device. Examples of such a semiconductor storage device include a memory card such as an SD™ card and an SSD (solid state drive).

[0017] 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array MCA. One block BLK is extracted from a plurality of blocks BLK included in the memory cell array MCA. The block BLK includes a plurality of string units SU(0) to SU(k) (k is an integer equal to or greater than 1).

[0018] Each string unit SU(i) (i = 0 to k) includes a plurality of NAND strings NS associated with bit lines BL(0) to BL(m) (m is an integer equal to or greater than 1), respectively. Each NAND string NS includes, for example, memory cells MC(0) to MC(15) connected in series. Select transistors STD(i) and STS are connected to the ends of the NAND string NS. The memory cells MC include a control gate and a charge storage layer and retain data in a non-volatile manner. Each of the select transistors STD(i) and STS is used to select the string unit SU during various operations.

[0019] In each NAND string NS, the memory cells MC(0) to MC(15) are connected in series. The drain of the select transistor STD(i) is connected to the associated bit line BL. The source of the select transistor STD(i) is connected to the memory cell MC(15) at one end of the series-connected memory cells MC(0) to MC(15). The drain of the select transistor STS is connected to the memory cell MC(0) at the other end of the series-connected memory cells MC(0) to MC(15). The source of the select transistor STS is connected to a source layer BSL. The sources of the multiple select transistors STS are commonly connected to the source layer BSL, which serves as a reference voltage layer to which a reference voltage (e.g., ground voltage) is applied.

[0020] The word lines WL(0) to WL(15) are provided in common to multiple NAND strings NS in the same block BLK. Therefore, the control gates of the memory cells MC(0) to MC(15) in the same block BLK are commonly connected to the word lines WL(0) to WL(15), respectively.

[0021] In the same string unit SU(i), the gates of the multiple select transistors STD(i) are commonly connected to a drain-side select gate line SGD(i) as a first select line. That is, the drain-side select gate line SGD(i) is connected to the gates of the multiple select transistors STD and is provided corresponding to each string unit SU(i).

[0022] In the same block BLK, the gates of multiple select transistors STS are commonly connected to a source-side select gate line SGS, which serves as a second select line. The source-side select gate line SGS is connected to the gates of multiple select transistors STS and is provided for each block BLK. As a result, the word lines WL(0) to WL(15) and the source-side select gate line SGS are driven for each block BLK. On the other hand, the drain-side select gate line SGD(i) is driven for each string unit SU(i).

[0023] In the circuit configuration of the memory cell array MCA described above, the bit line BL is shared by the NAND strings NS to which the same column address is assigned in each string unit SU. The source layer BSL is shared by, for example, multiple blocks BLK.

[0024] A set of memory cells MC connected to a common word line WL in one string unit SU is referred to as a cell unit CU. For example, the storage capacity of a cell unit CU including memory cells MC each storing one bit of data is defined as "one page of data." A cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cells MC.

[0025] The memory cell array MCA included in the memory 1 according to this embodiment is not limited to the circuit configuration described above. For example, the number of memory cells MC included in each NAND string NS and the number of select transistors STD and STS may be arbitrary. The number of string units SU included in each block BLK may also be arbitrary.

[0026] Hereinafter, the select transistors STD and STS are also referred to as the drain-side select transistor STD and the source-side transistor STS, respectively. Also, the "(i)" may be omitted.

[0027] FIG. 3 is a cross-sectional view showing an example of the configuration of the memory 1 according to this embodiment. Hereinafter, the stacking direction of the stack 20 is referred to as the Z direction. A direction that intersects with, for example, a direction perpendicular to, the Z direction is referred to as the Y direction. A direction that intersects with, for example, a direction perpendicular to, both the Z direction and the Y direction is referred to as the X direction. In FIG. 3, the memory 1 is shown with the +Z direction as the upside. However, in some cases, the -Z direction may be described as the upside. In this specification, the ±Z directions are an example of the first direction.

[0028] The memory 1 includes an array chip 2 having a memory cell array and a CMOS chip 3 having a CMOS circuit. The array chip 2 and the CMOS chip 3 are bonded together at a bonding surface B1 and are electrically connected to each other via wiring joined at the bonding surface. FIG. 3 shows the array chip 2 provided on the CMOS chip 3. Note that hereinafter, the memory cell array will also be referred to as 2m.

[0029] The CMOS chip 3 includes a substrate 30, a transistor 31, a via 32, wirings 33 and 34, and an interlayer insulating film 35.

[0030] The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a P-type MOSFET provided on the substrate 30. The transistor 31 constitutes, for example, a CMOS (Complementary MOS) circuit that controls the memory cell array of the array chip 2. The plurality of transistors 31 constitute logic circuits such as a sense amplifier, a row decoder, a column decoder, etc. Semiconductor elements other than the transistor 31, such as resistor elements and capacitor elements, may be formed on the substrate 30.

[0031] The via 32 electrically connects the transistor 31 and the wiring 33, or the wiring 33 and the wiring 34. The wiring 33 and 34 form a multilayer wiring structure within the interlayer insulating film 35. The wiring 34 is buried in the interlayer insulating film 35 and is exposed almost flush with the surface of the interlayer insulating film 35. The wiring 33 and 34 are electrically connected to the transistor 31, etc. The via 32 and the wiring 33 and 34 are made of a metal such as copper or tungsten. The interlayer insulating film 35 covers and protects the transistor 31, the via 32, and the wiring 33 and 34. The interlayer insulating film 35 is made of an insulating film such as a silicon oxide film.

[0032] The array chip 2 includes a stacked body 20, a columnar body CL, a source layer BSL, a metal layer 40, a contact plug CCw, a contact plug 29, a bonding pad 50, wirings 23 and 24, a via 28, and an interlayer insulating film 25.

[0033] The stacked body 20 is provided above the transistor 31 and is located in the +Z direction with respect to the substrate 30. The stacked body 20 is configured by alternately stacking a plurality of electrode films 21 and a plurality of insulating films 22 along the Z direction. The stacked body 20, together with the columns CL, configures a memory cell array. The electrode films 21 are made of a conductive metal such as tungsten. The insulating films 22 are made of an insulating film such as a silicon oxide film. The insulating films 22 insulate the electrode films 21 from one another. That is, the plurality of electrode films 21 are stacked in an insulated state from one another. The number of stacked electrode films 21 and insulating films 22 is arbitrary. The insulating films 22 may be, for example, a porous insulating film or an air gap.

[0034] One or more electrode films 21 at the top and bottom ends of the stacked body 20 in the Z direction function as source-side select gate lines SGS and drain-side select gate lines SGD, respectively. The electrode film 21 between the source-side select gate lines SGS and the drain-side select gate lines SGD functions as word lines WL. The source-side select gate lines SGS are provided on the side of the stacked body 20 that is closer to the source layers BSL. The drain-side select gate lines SGD are provided on the side of the stacked body 20 that is farther from the source layers BSL.

[0035] The select transistors STD in Fig. 2 are connected between the semiconductor bodies of the pillars CL (210 in Figs. 5 and 6) and the bit lines BL, respectively, and the select transistors STS are connected between the semiconductor bodies of the pillars CL and the common source layer BSL, respectively.

[0036] A plurality of pillars CL are provided within the stacked body 20. The pillars CL extend through the stacked body 20 in the stacking direction (Z direction) of the stacked body 20, from a via 28 connected to the bit line 23 to the source layer BSL. One pillar CL is provided corresponding to one NAND string NS(i). That is, one NAND string NS(i) is composed of one pillar CL and multiple word lines WL. One end of the NAND string NS(i) is connected to a bit line BL, for example, via a via 28. The other end of the NAND string NS(i) is connected in common to, for example, the source layer BSL. The bit line BL is a wiring 23 provided below the stacked body 20 and extending in the X direction. Therefore, the bit line BL is also referred to as a bit line 23. Note that FIG. 3 shows a case where the pillars CL are formed in two stages in the Z direction. However, the pillars CL may be formed in three or more stages.

[0037] As will be described later with reference to FIG. 4, a plurality of slits ST are provided in the stacked body 20. The slits ST extend in the Y direction and penetrate the stacked body 20 in the stacking direction (Z direction) of the stacked body 20. An insulating film such as a silicon oxide film is filled in the slits ST, and the insulating film is configured in a plate shape. The slits ST electrically divide the electrode films 21 of the stacked body 20. Alternatively, the inner walls of the slits ST may be covered with an insulating film such as a silicon oxide film, and a conductive material may be further embedded inside the insulating film. In this case, the conductive material can also function as a source wiring connected to the source layer BSL.

[0038] A source layer BSL is provided on the stacked body 20. The source layer BSL is provided corresponding to the stacked body 20. The stacked body 20 (memory cell array 2m) is provided on a surface F1 side of the source layer BSL, and a metal layer 40 is provided on the opposite surface F2 side. The source layer BSL is commonly connected to ends of multiple pillars CL and applies a common source voltage to multiple pillars CL in the same memory cell array 2m. In other words, the source layer BSL functions as a common source electrode for the memory cell array 2m including multiple blocks BLK. The source layer BSL is made of a conductive material such as doped polysilicon. The metal layer 40 is made of a metal material having a lower resistance than the source layer BSL, such as copper, aluminum, or tungsten.

[0039] On the other hand, a bonding pad 50 is provided in an area above the surface F2 of the source layer BSL where the source layer BSL is not provided. The bonding pad 50 is connected to a metal wire or the like (not shown) and receives a power supply or a signal from outside the memory 1. The bonding pad 50 is provided so as to be connected to one end of the contact plug 29 in the Z direction. The bonding pad 50 is connected to the transistor 31 of the CMOS chip 3 via the contact plug 29, the wiring 24, and the wiring 34. The external power supply supplied from the bonding pad 50 is supplied to the transistor 31. Alternatively, a signal is supplied to the transistor 31 or the memory cell array 2m via the bonding pad 50.

[0040] The contact plugs CCw are provided on the periphery of the stacked body 20 and extend in the Z direction within the interlayer insulating film 25. The contact plugs CCw are electrically connected between the electrode films 21 (word lines WL) and the wiring 24. The contact plugs CCw are provided in staircase portions 2s where the electrode films 21 are formed in a staircase shape at the end of the stacked body 20, and are electrically connected to each electrode film 21. The contact plugs CCw are provided to transmit a word line voltage from the CMOS chip 3 to each electrode film 21. The contact plugs CCw are made of a metal such as copper or tungsten.

[0041] In this embodiment, the array chip 2 and the CMOS chip 3 are formed separately and are bonded together at the bonding surface B1. Therefore, the array chip 2 does not include a transistor 31. Furthermore, the CMOS chip 3 does not include a stacked body 20 (memory cell array 2m).

[0042] A via 28, a wiring 23, and a wiring 24 are provided below the stacked body 20. The wirings 23 and 24 are buried in an interlayer insulating film 25. The wiring 24 is exposed and substantially flush with the surface of the interlayer insulating film 25. The wirings 23 and 24 are electrically connected to the semiconductor body of the columnar body CL (210 in FIGS. 5 and 6), etc. The via 28, the wiring 23, and the wiring 24 are made of a metal such as copper or tungsten. The interlayer insulating film 25 covers and protects the stacked body 20, the via 28, the wiring 23, and the wiring 24. The interlayer insulating film 25 is made of an insulating film such as a silicon oxide film.

[0043] The interlayer insulating film 25 and the interlayer insulating film 35 are bonded to each other at the bonding surface B1, and as a result, the wiring 24 and the wiring 34 are bonded to each other in a substantially flush manner at the bonding surface B1. As a result, the array chip 2 and the CMOS chip 3 are electrically connected to each other via the wiring 24 and the wiring 34.

[0044] FIG. 4 is a plan view showing the stack 20. The stack 20 includes a staircase portion 2s and a memory cell array 2m. The staircase portion 2s is provided, for example, at an end of the stack 20. The memory cell array 2m is sandwiched or surrounded by the staircase portion 2s. The slits ST are provided in the Z direction from the staircase portion 2s at one end of the stack 20, through the memory cell array 2m, to the staircase portion 2s at the other end of the stack 20, dividing the stack 20 into blocks BLK. The slits ST are made of an insulating material. Alternatively, the slits ST may include a source wiring that is electrically isolated from the electrode film 21 of the stack 20 and electrically connected to the source layer BSL.

[0045] The slits SHE are provided in the memory cell array 2m. The slits SHE are shallower in the Z direction than the slits ST and extend in the Y direction substantially parallel to the slits ST. The slits SHE divide the electrode films 21 corresponding to the drain-side select gate lines SGD into string units SU. On the other hand, the slits SHE do not reach the electrode films 21 corresponding to the word lines WL in the Z direction and do not divide the word lines WL. For the slits SHE, an insulating film such as a silicon oxide film is used, for example.

[0046] The portion of the stack 20 sandwiched between two slits ST shown in FIG. 4 corresponds to a block BLK. The block BLK constitutes, for example, the minimum unit for erasing data. The slit SHE is provided within the block BLK. Multiple slits SHE may be provided within one block BLK. The portion of the stack 20 between the slit ST and the slit SHE or between two adjacent slits SHE corresponds to a string unit (also called a finger) SU. The drain-side select gate line SGD is separated into string units SU by the slits SHE. Therefore, when writing and reading data, the drain-side select gate line SGD can select one string unit SU within the block BLK.

[0047] 5 and 6 are cross-sectional views illustrating a memory cell having a three-dimensional structure. A plurality of pillars CL are provided in memory holes MH provided in the stacked body 20. Each pillar CL extends from one end of the stacked body 20 through the stacked body 20 along the Z direction, and is provided within the stacked body 20 and the source layer BSL. Each of the pillars CL includes a semiconductor body 210, a memory film 220, and a core layer 230. Each pillar CL includes a core layer 230 provided in its center, a semiconductor body (semiconductor layer) 210 provided around the core layer 230, and a memory film 220 provided around the semiconductor body 210. The semiconductor body 210 extends in the stacking direction (Z direction) within the stacked body 20. The semiconductor body 210 is electrically connected to the source layer BSL. The memory film 220 is provided between the semiconductor body 210 and the electrode film 21 and has a charge trapping portion. A plurality of pillars CL, one selected from each string unit, are commonly connected to one bit line 23 through vias 28 shown in Fig. 3. Each of the pillars CL is provided, for example, in the region of the memory cell array 2m.

[0048] As shown in FIG. 6, the shape of the memory hole MH in the XY plane is, for example, a circle or an ellipse. A block insulating film 221a constituting part of the memory film 220 may be provided between the electrode film 21 and the insulating film 22. The block insulating film 221a is, for example, silicon oxide or metal oxide. One example of a metal oxide is aluminum oxide. A barrier film 21b may be provided between the electrode film 21 and the insulating film 22 and between the electrode film 21 and the memory film 220. When the electrode film 21 is made of tungsten, for example, the barrier film 21b is, for example, titanium nitride. The block insulating film 221a suppresses back tunneling of charges from the electrode film 21 to the memory film 220. The barrier film 21b improves adhesion between the electrode film 21 and the block insulating film 221a.

[0049] The semiconductor body 210 has, for example, a cylindrical shape with a bottom. The semiconductor body 210 is made of, for example, polysilicon. The semiconductor body 210 is made of, for example, undoped silicon. The semiconductor body 210 may also be p-type silicon. The semiconductor body 210 serves as the channels of the drain-side select transistor, the memory cell MC, and the source-side select transistor. That is, the multiple memory cells MC have storage regions between the semiconductor body 210 and the electrode film 21 that serves as the word line WL, and are stacked in the Z direction. One end of the multiple semiconductor bodies 210 in the same memory cell array 2m is electrically connected in common to the source layer BSL.

[0050] The memory film 220 includes, for example, a cover insulating film 221, a charge trapping film 222, a tunnel insulating film 223, and a block insulating film 221a. Portions of the memory film 220 other than the block insulating film 221a are provided between the inner wall of the memory hole MH and the semiconductor body 210. The memory film 220 has, for example, a cylindrical shape. The charge trapping film 222 and the tunnel insulating film 223 each extend in the Z direction.

[0051] The cover insulating film 221 is provided between the insulating film 22 and the charge trapping film 222, and between the block insulating film 221a and the charge trapping film 222. The cover insulating film 221 contains, for example, silicon oxide. The cover insulating film 221 protects the charge trapping film 222 from being etched when a sacrificial film (not shown) is replaced with the electrode film 21 (replacement step).

[0052] The charge trapping film 222 is provided between the cover insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 contains, for example, silicon nitride, and has trap sites that trap charges within the film. The portion of the charge trapping film 222 sandwiched between the electrode film 21, which becomes the word line WL, and the semiconductor body 210 constitutes the storage region of the memory cell MC as a charge trap portion. The threshold voltage of the memory cell MC changes depending on the presence or absence of charge in the charge trap portion or the amount of charge trapped in the charge trap portion. This allows the memory cell MC to retain information.

[0053] The tunnel insulating film 223 is provided between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 includes, for example, silicon oxide or a combination of silicon oxide and silicon nitride. The tunnel insulating film 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 into the charge trapping film 222 (write operation), and when holes are injected from the semiconductor body 210 into the charge trapping film 222 (erase operation), the electrons and holes each pass through (tunnel) the potential barrier of the tunnel insulating film 223.

[0054] The core layer 230 fills the internal space of the cylindrical semiconductor body 210. The core layer 230 has, for example, a columnar shape. The core layer 230 includes, for example, silicon oxide and is insulating.

[0055] FIG. 7 is a plan view showing the memory cell array 2m according to this embodiment and a method of controlling a read operation.

[0056] The memory cell array 2m includes a plurality of pillars CL (i.e., NAND strings NS). The plurality of NAND strings NS are divided into blocks BLK by slits ST. Furthermore, within each block BLK, the drain-side select gate lines SLD of the plurality of NAND strings NS are divided into string units SU by slits SHE. Furthermore, a plurality of string units (fingers) SU constitute a finger unit FU. For example, FIG. 7 shows one block BLK, two finger units FU, and six string units SU. Three string units SU are provided corresponding to one finger unit FU. Note that the number of blocks BLK, the number of finger units FU, and the number of string units SU are not limited. Note that a dummy cell DM that does not function as a memory cell MC may be provided directly below the slit SHE between adjacent finger units FU.

[0057] A plurality of bit lines BL are provided in common for a plurality of string units SU and a plurality of finger units FU. The plurality of bit lines BL extend in the X direction perpendicular to the slits ST and SHE. A plurality of NAND strings NS included in the same string unit SU are connected to different bit lines BL via vias 28. The bit lines BL transmit data from a selected memory cell MC to the sense amplifier module 1016.

[0058] 1 selects and drives the word lines WL, the drain-side select gate lines SGD, the source-side select gate lines SGS, etc. The sense amplifier module 1016 detects data from the memory cell array 2m via the bit lines BL.

[0059] 7, the row decoder module 1015 selects the first finger unit FU1 as a read target among the multiple finger units FU. Furthermore, the row decoder module 1015 selects the first string unit SU1 as a read target among the multiple string units SU in the first finger unit FU1.

[0060] In this case, the driver module 1014 applies a first select voltage VSG to the source-side select gate line SGS1 corresponding to the first finger unit FU1 and the drain-side select gate line SGD1 corresponding to the first string unit SU1. The first select voltage VSG is higher than the first non-select voltage VSS and the second non-select voltage VDD. As a result, although not shown in FIG. 7, the select transistor STS connected to the source-side select gate line SGS1 becomes conductive (ON state). Also, the select transistor STD connected to the drain-side select gate line SGD1 becomes conductive (ON state). Therefore, the multiple string units SU included in the finger unit FU1 are selectively electrically connected to the source layer BSL. Furthermore, the multiple NAND strings NS included in the first string unit SU1 are selectively electrically connected to the multiple bit lines BL. As a result, the multiple NAND strings NSsel included in the first string unit SU1 are selectively electrically connected between the source layer BSL and the bit line BL. The multiple NAND strings NSsel included in the first string unit SU1 are each connected to a different bit line BL. Therefore, data of a selected memory cell connected to the selected word line WL among the plurality of memory cells included in each NAND string NSsel is read out via the corresponding bit line BL.

[0061] Meanwhile, the row decoder module 1015 deselects the second string unit SU2 of the first finger unit FU1, which is not the first string unit SU1, as a read target. In this case, the driver module 1014 applies a first unselect voltage VSS to the drain-side select gate line SGD2 corresponding to the second string unit SU2 in the first finger unit FU1. The first unselect voltage VSS is lower than the first select voltage VSG and the second unselect voltage VDD. The first select voltage VSG is, for example, about 5 V, which is a voltage sufficiently higher than the threshold voltage of the memory cell MC. The first unselect voltage VSS is, for example, about 0 V, which is a voltage sufficiently lower than the threshold voltage of the memory cell MC. The second unselect voltage VDD is, for example, about 1.5 V. The select transistor STS connected to the source-side select gate line SGS1 is in an on state, while the select transistor STD connected to the drain-side select gate line SGD2 is in a non-conductive state (off state). Therefore, the second string unit SU2 included in the finger unit FU1 is electrically connected to the source layer BSL but electrically isolated from the bit line BL, so that data is not read from the second string unit SU2.

[0062] Furthermore, the row decoder module 1015 deselects the second finger unit FU2 from the plurality of finger units FU, excluding it from the read target. In this case, the driver module 1014 applies the first deselect voltage VSS to the source-side select gate line SGS2 corresponding to the second finger unit FU2. This turns off the select transistor STS connected to the source-side select gate line SGS2. Therefore, the plurality of string units SU included in the finger unit FU2 are electrically isolated from the source layer BSL.

[0063] The driver module 1014 also applies a second unselect voltage VDD to the drain-side select gate line SGD3 corresponding to the second finger unit FU2. The second unselect voltage VDD is lower than the first select voltage VSG and higher than the first unselect voltage VSS. The select transistors STD and STS are turned on by the first select voltage VSG but are turned off by the first and second unselect voltages VSS and VDD. Therefore, the select transistor STD connected to the drain-side select gate line SGD3 is turned off. This electrically isolates the multiple string units SU included in the finger unit FU2 from the bit line BL. Therefore, the channels (semiconductor bodies 210) of the memory cells of the NAND string NS included in the finger unit FU2 are electrically floating.

[0064] 8 is a diagram showing NAND strings in a data read operation. NAND string NS1 is a NAND string NSsel selected as a read target. NAND strings NS2 and NS3 are unselected NAND strings. NAND string NS2 is an unselected NAND string in the first finger unit FU1 that is the read target. NAND string NS3 is an unselected NAND string in the second finger unit FU2 that is not the read target.

[0065] As described above, the first select voltage VSG is applied to the source-side select gate line SGS1 and the drain-side select gate line SGD1 of the NAND string NS1, which turns on the select transistors STS1 and STD1.

[0066] The driver module 1014 lowers the voltage of the selected word line WLsel to be read and raises the voltage of the other unselected word lines WL that are not to be read. As a result, in the NAND string NS1, only the selected memory cell MCsel connected to the selected word line WLsel is turned off, and the unselected memory cells MC connected to the other unselected word lines WL are turned on. Note that in FIG. 8, memory cells MC other than the memory cell MCsel are unselected memory cells. As a result, the selected memory cell MCsel is electrically connected between the source layer BSL and the bit line BL via the unselected memory cells MC. As a result, the data held in the selected memory cell MCsel is transmitted to the bit line BL.

[0067] In the NAND string NS2, the memory cells MC connected to the selected word line WLsel are turned off, and the memory cells MC connected to the other unselected word lines WL are turned on. Since the select transistor STS2 is on, the memory cells MC on the select transistor STS side of the memory cells MC connected to the selected word line WLsel are electrically connected to the source layer BSL. Since the select transistor STD2 is off, the memory cells MC on the select transistor STD side of the memory cells MC connected to the selected word line WLsel are electrically isolated from the source layer BSL and the bit line BL and are in a floating state.

[0068] Furthermore, in the NAND string NS3 in the second finger unit FU2, the memory cells MC connected to the selected word line WLsel are turned off, and the memory cells MC connected to the other unselected word lines WL are turned on. Both the select transistors STS3 and STD3 are turned off. Therefore, the memory cells MC included in the NAND string NS3 are electrically isolated from the source layers BSL and bit lines BL and are in a floating state.

[0069] In the NAND string NS3, the channels (semiconductor bodies 210) of all memory cells MC are electrically floating. Therefore, the voltage of the channels of the memory cells MC rises as the voltage of the unselected word lines WL rises. This voltage rise of the channels of the memory cells MC is called a boost. That is, in a read operation, the channels of the memory cells MC in the NAND string NS3 in the unselected finger unit FU2 are boosted.

[0070] Fig. 9 is a diagram showing the state and channel energy level of NAND string NS2. Fig. 10 is a diagram showing the state and channel energy level of NAND string NS3. Note that the horizontal axis of the energy level graphs at the bottom of each of Figs. 9 and 10 indicates the position of NAND string NS2, and the vertical axis indicates the energy level E. The energy level E indicates the energy level of electrons.

[0071] 9, the channels of some memory cells MC are in a floating state, but the source layers BSL are connected via the select transistors STS2, so the channels of the NAND string NS2 are not boosted significantly by the voltage of the unselected word lines WL.

[0072] Here, if the off-voltage of the drain-side select gate line SGD2 is too high, the leakage current flowing through the select transistor STD2 increases. For example, if the voltage of the drain-side select gate line SGD2 is a second unselect voltage VDD, which is higher than the first unselect voltage VSS, the energy barrier of the select transistor STD2 decreases from ESS to EDD, as shown in Figure 9. This makes it easier for the leakage current to flow through the select transistor STD2, increasing the leakage current. Therefore, it is preferable to set the voltage of the drain-side select gate line SGD2 to the first unselect voltage VSS, which is lower than the second unselect voltage VDD.

[0073] On the other hand, in the NAND string NS3 shown in Fig. 10, the channels of all the memory cells MC are in a floating state. Therefore, the channels of the NAND string NS3 are boosted to a voltage higher than that of the NAND string NS2 by the voltage of the unselected word lines WL.

[0074] Here, if the off-voltage of the drain-side select gate line SGD3 is too low, the number of hot carriers (electrons) passing through the select transistor STD3 increases. For example, if the voltage of the drain-side select gate line SGD3 is the first non-select voltage VSS, which is lower than the second non-select voltage VDD, the number of hot carriers tunneling through the energy barrier in the select transistor STD3 increases, as shown in Figure 10. Therefore, it is preferable to set the voltage of the drain-side select gate line SGD3 to the second non-select voltage VDD, which is higher than the first non-select voltage VSS.

[0075] That is, if the voltage of the drain side select gate line SGD2 and the voltage of the drain side select gate line SGD3 are equal, the leakage current flowing through the select transistor STD2 increases, or the hot carriers passing through the select transistor STD3 increase.

[0076] In contrast, in this embodiment, the driver module 1014 differentiates the voltage of the drain-side select gate line SGD2 of the unselected NAND string NS2 in the first finger unit FU1 to be read from the voltage of the drain-side select gate line SGD3 of the NAND string NS3 in the unselected second finger unit FU2, thereby suppressing the leakage current in the select transistor STD2 and hot carriers in the select transistor STD3.

[0077] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0078] 1. Memory MCA Memory Cell Array 1014 Driver Module 1015 Row Decoder Module 1016 Sense Amplifier Module BLK Block FU Finger Unit SU String Unit NS NAND string MC memory cell BL bit line STD,STS select transistor WL Word Line BSL Source Layer SGD Drain side select gate line SGS Source side select gate line

Claims

1. a plurality of strings each including a plurality of memory cells connected in series; a plurality of first selection transistors respectively connected to the memory cells at one ends of the plurality of strings; a plurality of second selection transistors respectively connected to the memory cells at the other ends of the plurality of strings; a plurality of first control lines provided in common to the plurality of strings and connected to gates of the plurality of memory cells, respectively; a plurality of first selection lines connected to gates of the plurality of first selection transistors, the first selection lines being provided corresponding to first units each including a plurality of the strings; a plurality of second selection lines connected to gates of the plurality of second selection transistors, the second selection lines being provided corresponding to second units each including a plurality of the first units; a drive unit that drives voltages of the plurality of first selection lines, and that, in a data read operation, makes a first non-selection voltage applied to the unselected first selection lines in a selected second unit selected as a read target among the plurality of second units different from a second non-selection voltage applied to the first selection lines in an unselected second unit not selected as a read target among the plurality of second units; A semiconductor memory device comprising:

2. 2. The semiconductor memory device according to claim 1, wherein said first non-selection voltage is lower than said second non-selection voltage.

3. 2. The semiconductor memory device according to claim 1, wherein a first selection voltage applied to said first selection line selected as a read target in said selected second unit is higher than said first and second non-selection voltages.

4. 2. The semiconductor memory device according to claim 1, wherein a voltage applied to said second selection line corresponding to said selected second unit is said first selection voltage.

5. one of the first selection transistors selected as a read target in the selection second unit is in a conductive state, the unselected first selection transistor in the selected second unit and the first selection transistor in the unselected second unit are in a non-conductive state, the second selection transistor in the selection second unit is in a conductive state, 2. The semiconductor memory device according to claim 1, wherein said second selection transistor in said unselected second unit is in a non-conductive state.

6. the plurality of first selection transistors are electrically connected to a plurality of data lines that transmit data from the memory cells, respectively; 2. The semiconductor memory device according to claim 1, wherein said plurality of second selection transistors are electrically connected in common to a reference voltage layer to which a reference voltage is applied.

7. a stacked body in which electrode films and first insulating films are alternately stacked in a first direction; a plurality of first columns each including a semiconductor layer provided to penetrate the stacked body in the first direction; a reference voltage layer provided in common on one end side of the semiconductor layer of the plurality of first columnar bodies; a plurality of data lines provided on the other end sides of the semiconductor layer of the plurality of first columns, the first selection transistors are connected between the semiconductor layers of the first columns and the data lines, respectively; 2. The semiconductor memory device according to claim 1, wherein said plurality of second selection transistors are connected between said semiconductor layers of said plurality of first columns and said reference voltage layer, respectively.

8. a plurality of strings each including a plurality of memory cells connected in series; a plurality of first selection transistors each connected to the memory cell at one end of the plurality of strings; a plurality of second selection transistors each connected to the memory cell at the other end of the plurality of strings; a plurality of first control lines provided in common to the plurality of strings and connected to gates of the plurality of memory cells; a plurality of first selection lines connected to gates of the plurality of first selection transistors and provided corresponding to a plurality of first units each including a plurality of the strings; a plurality of second selection lines connected to gates of the plurality of second selection transistors and provided corresponding to a plurality of second units each including a plurality of the first units; and a drive unit that drives voltages of the plurality of first selection lines; In a data read operation, a first unselection voltage is applied to the unselected first selection lines in a selected second unit selected as a read target among the plurality of second units, and a second unselection voltage different from the first unselection voltage is applied to the first selection lines in the unselected second units not selected as a read target among the plurality of second units. A method for driving a semiconductor memory device comprising the steps of:

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