Semiconductor device

Abstract

To provide a semiconductor device in which a NOR type memory cell array and an NAND type memory cell array are integrated.SOLUTION: The flash memory includes a memory cell array in which a NOR type memory cell array 110A and an NAND type memory cell array 110B are integrated, a word line WL connected to each of the memory cells MC, and a bit line BL commonly connected to the NOR type memory cell array 110A and the NAND type memory cell array 110B. The NOR-type memory cell array 110A includes a plurality of memory cells connected in series between the bit line side selection transistor BL _ SEL and the source line side selection transistor SL _ SEL, and one memory cell includes a memory cell transistor and a sidewall transistor connected in parallel. The NAND memory cell array 110B includes a plurality of memory cells connected in series between a bit line side select transistor BL _ SEL and a source line side select transistor SL _ SEL.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a memory cell array in which NOR type memory cells and NAND type memory cells are integrated. [Background technology]

[0002] NOR flash memory allows random access and high-speed readout, while NAND flash memory allows for highly integrated memory cell arrays and can program large amounts of data quickly, but takes longer to read than NOR flash memory.

[0003] As an example of integrating memory cell arrays with different cell structures, Patent Document 1 discloses a nonvolatile memory including a memory cell array in which a NOR type array and a resistance variable type array are formed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 7170117 Summary of the Invention [Problem to be solved by the invention]

[0005] If NOR flash memory and NAND flash memory could be integrated on a single chip, it would be possible to provide a flash memory that combines the advantages of each. However, NOR flash memory has an array structure in which memory cells are connected between bit lines and source lines, while NAND flash memory has an array structure in which multiple memory cells are connected in series between bit lines and source lines. It is difficult to integrate such different array structures on a single chip, and even if one were to try to do so, it would be expected that the process would be extremely complicated and cumbersome.

[0006] In view of the above-mentioned conventional problems, an object of the present invention is to provide a semiconductor device in which a NOR type memory cell array and a NAND type memory cell array are integrated. [Means for solving the problem]

[0007] The semiconductor device of the present invention includes a memory cell array in which a NOR type memory cell array and a NAND type memory cell array are integrated, and the memory cell array has an active region formed in a semiconductor substrate so as to extend in the bit line direction, a trench adjacent to the active region, a charge storage layer formed on the active region for each memory cell and including a nitride layer sandwiched between insulating layers, a first conductive layer formed on the charge storage layer for each memory cell, and a second conductive layer extending in the word line direction and electrically connected to the first conductive layer.

[0008] In one embodiment, the semiconductor device further includes a bit line commonly connected to the NOR memory cell array and the NAND memory cell array. In one embodiment, the semiconductor device further includes a first bit line connected to the NOR memory cell array and a second bit line connected to the NAND memory cell array, the first bit line being isolated from the second bit line. In one embodiment, the first bit line is connected to a first sense circuit, the second bit line is connected to a second sense circuit, the first sense circuit senses data in a selected memory cell of the NOR memory cell array, and the second sense circuit senses data in a selected memory cell of the NAND memory cell array. In one embodiment, the first conductive layer and the second conductive layer form a word line. In one embodiment, the NOR memory cell array further includes a sidewall insulator formed in the trench and on a sidewall of the active region, the second conductive layer contacting the sidewall insulator within the trench. In one embodiment, a NOR memory cell includes a memory cell transistor formed on the surface side of the active region and a sidewall transistor including the sidewall insulator, and the memory cell transistor and the sidewall transistor are connected in parallel. In one embodiment, the trench is aligned with the sidewalls of the active region, the first conductive layer, and the charge storage layer. In one embodiment, the charge storage layer has an ONO structure of oxide / nitride / oxide, a structure including a stack of multiple types of insulating films other than oxide between a silicon substrate and the nitride layer, or a structure including a stack of multiple types of insulating films other than oxide between the nitride and the first conductive layer. In one embodiment, an array of NOR memory cells includes multiple memory cells connected in series between a bit line side select transistor and a source line side select transistor, and an array of NAND memory cells includes multiple memory cells connected in series between a bit line side select transistor and a source line side select transistor.

[0009] The semiconductor device of the present invention includes a memory cell array in which a NOR type memory cell array and a NAND type memory cell array are integrated, word lines connected to each of the memory cells, and bit lines connected in common to the NOR type memory cell array and the NAND type memory cell array, the NOR type memory cell array includes a plurality of memory cells connected in series between a bit line side select transistor and a source line side select transistor, and one memory cell includes a memory cell transistor and a sidewall transistor connected in parallel, and the NAND type memory cell array includes a plurality of memory cells connected in series between the bit line side select transistor and the source line side select transistor.

[0010] In one embodiment, the threshold voltage of the sidewall transistor is set higher than the voltage of the selected word line and lower than the voltage of the unselected word lines. In one embodiment, the semiconductor device includes a control means for controlling reading and writing of the memory cell array, the control means enabling page-by-page reading and writing of the NOR type memory cell array and memory cell-by-memory cell reading and writing of the NAND type memory cell array. [Effects of the Invention]

[0011] According to the present invention, a memory cell array has an active region formed in a semiconductor substrate so as to extend in the bit line direction, a trench adjacent to the active region, a charge storage layer formed on the active region for each memory cell and including a nitride layer sandwiched between insulating layers, a first conductive layer formed on the charge storage layer for each memory cell, and a second conductive layer extending in the word line direction and electrically connected to the first conductive layer.Therefore, a NOR type memory cell array and a NAND type memory cell array can be easily integrated into a memory cell array using compatible processes. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a block diagram showing the overall configuration of a flash memory according to an embodiment of the present invention; [Figure 1A]FIG. 10 is a block diagram showing another example of the configuration of the flash memory according to the embodiment of the present invention. [Figure 2] 1 is a diagram showing equivalent circuits of a NOR type memory cell array and a NAND type memory cell array formed in the memory cell array of the present embodiment. [Figure 2A] FIG. 10 is a diagram illustrating an equivalent circuit of another configuration example of the memory cell array of the present embodiment. [Figure 3] 1 is a plan view of a NOR type memory cell and a NAND type memory cell array formed in a memory cell array of the present embodiment. [Figure 4] FIG. 4A is a plan view of a portion including an active region and a trench of a NAND memory cell array, and FIG. 4B is a cross-sectional view taken along line A1-A1 of FIG. 4A. [Figure 5] 4 is a cross-sectional view of the NAND memory cell array of FIG. 3 taken along line A2-A2. [Figure 6] 6(A) is a cross-sectional view taken along line B1-B1 in which the NOR memory cell shown in FIG. 3 is formed, and FIG. 6(B) is a cross-sectional view taken along line B2-B2 in which the NOR memory cell shown in FIG. 3 is not formed. [Figure 7] FIG. 7A is an equivalent circuit of a NOR memory cell of this embodiment, and FIG. 7B is a cross-sectional view for explaining two transistors formed in the NOR memory cell. [Figure 8] FIG. 8(A) is a diagram showing the threshold distribution of memory cells, and FIG. 8(B) is a table showing the bias voltages of the various parts during a read operation of a NOR type memory cell array. [Figure 9] FIG. 9A is a diagram showing a part of a NOR type memory cell array during a program operation, and FIG. 9B is a table showing bias voltages at various parts of the NOR type memory cell array during a program operation. [Figure 10] 10 is a table showing bias voltages at various parts during an erase operation of a NOR type memory cell array. [Figure 11] 1A to 1C are diagrams illustrating a manufacturing process of a NAND memory cell array according to an embodiment of the present invention. [Figure 12] 1A to 1C are diagrams illustrating a manufacturing process of a NAND memory cell array according to an embodiment of the present invention. [Figure 13] Figure 13(A) is a plan view of the substrate when the first control gate, charge storage layer, and substrate are etched through a mask pattern, and Figure 13(B) is a plan view of the substrate when the heights of the first control gate and trench insulator are made approximately the same. [Figure 14] 1A to 1C are diagrams illustrating a manufacturing process of a NOR type memory cell array according to the present embodiment. [Figure 15] 1A to 1C are diagrams illustrating a manufacturing process of a NOR type memory cell array according to the present embodiment. [Figure 16] FIG. 16(A) is a plan view of the substrate after the mask pattern M1 has been removed, and FIG. 16(B) is a plan view of the substrate after the mask pattern M2 has been formed. [Figure 17] 1A to 1C are diagrams illustrating manufacturing processes for a cell array region and a peripheral region of a flash memory according to an embodiment of the present invention. [Figure 17A] 10A to 10C are diagrams showing other manufacturing processes for the cell array region and the peripheral region of the flash memory of the present embodiment. [Figure 18] 1A to 1C are diagrams illustrating manufacturing processes for a cell array region and a peripheral region of a flash memory according to an embodiment of the present invention. [Figure 19] 1A to 1C are diagrams illustrating manufacturing processes for a cell array region and a peripheral region of a flash memory according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] The semiconductor device according to the present invention includes a memory cell array in which a NOR memory cell array and a NAND memory cell array are integrated on the same substrate, thereby realizing a large memory capacity and enabling high-speed readout. The NOR memory cell array and the NAND memory cell array have similar structures including common components, and therefore can be manufactured using compatible processes. It should be noted that the drawings include exaggerated portions to facilitate understanding of the invention and do not necessarily represent the scale of the actual product. [Example]

[0014] Next, an embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a block diagram showing an outline of the overall configuration of a flash memory according to an embodiment of the present invention. As shown in the figure, a flash memory 100 of this embodiment comprises a memory cell array 110 in which a NOR type memory cell array 110A (hereinafter referred to as a NOR type array) and a NAND type memory cell array 110B (hereinafter referred to as a NAND type array) are formed, an input / output buffer 120 connected to an external input / output terminal I / O, an address register 130 that receives address data from the input / output buffer 120, a controller 140 that controls each unit based on command data and external control signals from the input / output buffer 120, and a controller 140 that selects blocks and writes words in the memory cell array 110 based on row address information Ax from the address register 130. The memory cell array 110 includes a word line selection and drive circuit 150 for selecting lines, a page buffer / sense circuit 160 for sensing data read from the memory cell array 110 and holding data to be programmed in the memory cell array 110, a column selection circuit 170 for selecting columns (bit lines) of the page buffer / sense circuit 160 based on column address information Ay from the address register 130, and an internal voltage generation circuit 180 for generating various voltages required for reading, programming, erasing, etc. (program voltage Vpgm, read voltage Vread, erase voltage Vers, program and read pass voltage Vpass, etc.).

[0015] 1, the page buffer / sense circuit 160 and the column select circuit 170 are provided in common to the NOR array 110A and the NAND array 110B, but this is merely an example, and individual sense circuits may be provided for the NOR array 110A and the NAND array 110B. For example, as shown in FIG. 1A, the NOR array 110A is provided with a sense amplifier (SA) 160A and a column select circuit 170A, and the NAND array 110B is provided with a page buffer / sense circuit 160B and a column select circuit 170B. The sense amplifier 160A and the page buffer / sense circuit 160B operate independently, with the sense amplifier 160A enabling data to be read from or written to a selected memory cell of the NOR array 110A, and the page buffer / sense circuit 160B enabling data to be read from or written to a selected page of the NAND array 110N. By separating the sense amplifier 160A and the page buffer / sense circuit 160B in this way, it is possible to achieve high-speed reading, which is an advantage of the NOR type array.

[0016] The memory cell array 110 includes a NOR array 110A and a NAND array 110B integrated on a substrate. The NOR array 110A includes, for example, multiple blocks arranged in a column direction, and the NAND array 110B includes, for example, multiple blocks arranged in a column direction. FIG. 2 shows an equivalent circuit of one block of the NOR array 110A and an equivalent circuit of one block of the NAND array 110B. Bit lines BL0 to BLm-1 are common to the multiple blocks arranged in the column direction of the NOR array 110A and the multiple blocks arranged in the column direction of the NAND array 110B. In the memory cell array 110, memory cells MC connected to one word line WL can be referred to as one page, and memory cells in multiple pages sandwiched between bit line side select transistors BL_SEL and source line side select transistors SL_SEL can be referred to as one block, similar to a typical NAND flash memory.

[0017] 2, the bit lines BL0 to BLm-1 are commonly connected to the NOR array 110A and the NAND array 110B. However, this is merely an example, and the bit lines BL0 to BLm-1 may be separated for the NOR array 110A and the NAND array 110B. For example, as shown in FIG. 2A, the bit lines BL0 to BLm-1 are connected to blocks i and i+1 of the NOR array 110A, and each of these bit lines is connected to a sense amplifier 160A. On the other hand, the bit lines BL0 to BLm-1 are connected to blocks j and j+1 of the NAND array 110B, and each of these bit lines is connected to a page buffer / sense circuit 160B. In this way, by separating the bit lines of the NOR array 110A and the NAND array 110B, the load on the bit lines can be reduced, resulting in faster read and write operations. The sense amplifiers 160A may be prepared in the same number as the bit lines BL0 to BLm-1 (the number for one page), or may be prepared in the same number as one or a plurality of bit lines, and the bit line selected by the switch circuit may be connected to the sense amplifier 160A.

[0018] A plurality of NAND strings are formed in one block of the NAND array 110B, and each NAND string includes a bit line side select transistor BL_SEL, a source line side select transistor SL_SEL, and a plurality of memory cells MC connected in series therebetween. The memory cells MC may store binary data or multi-level data.

[0019] The bit line side select transistor BL_SEL is connected to a corresponding bit line among the bit lines BL0 to BLm-1, and has its gate connected to a select gate line SGD. The source line side select transistor SL_SEL is connected to a common source line SL, and has its gate connected to a select gate line SGS. Here, four memory cells MC are shown as an example, and word lines WL0 to WL3 are connected to the gates of the memory cells MC, respectively.

[0020] The word lines WL and select gate lines SGD, SGS of each block of the NAND array 110B are connected to a word line selection / drive circuit 150. Bit lines BL0 to BLm-1 are connected in common to each block, and one end of each is connected to a page buffer / sense circuit 160. As shown in FIGS. 1A and 2A above, when the NOR array 110A and the NAND array 110B are provided with separate sense amplifiers 160A and page buffer / sense circuits 160B, the bit lines BL0 to BLm-1 of the NOR array 110A are connected to the sense amplifiers 160A, and the bit lines BL0 to BL1-m of the NAND array 110B are connected to the page buffer / sense circuit 160B.

[0021] On the other hand, in the NOR memory cell 110A, a plurality of memory cells MC are connected in series between a bit line side select transistor BL_SEL connected to a select gate line SGD and a source line side select transistor SL_SEL connected to a select gate line SGS. One memory cell MC includes a memory cell transistor CELL_TR and a sidewall transistor SE_TR connected in parallel. Each memory cell MC is connected to a corresponding word line WL0 to WL3 in the row direction, the bit line side select transistor BL_SEL is connected to a corresponding bit line among the bit lines BL0 to BLm-1, and the source line side select transistor SL_SEL is connected to a common source line SL. Here, four memory cells MC are shown as an example.

[0022] The word line selection / drive circuit 150 selects a block of the NOR array 110A or a block of the NAND array 110B based on row address information Ax, and drives the select gate lines SGD / SGS and word lines WL0 to WL3 in the selected block. The page buffer / sense circuit 160 senses data read from a selected page of the NOR array 110A or the NAND array 110B, or holds data to be programmed into a selected page of the NOR array 110A or the NAND array 110B. As shown in Figures 1A and 2A above, when the sense amplifiers 160A and the page buffer / sense circuit 160B are provided separately for the NOR array 110A and the NAND array 110B, the sense amplifiers 160A sense data read from a selected memory cell or a selected page of the NOR array 110A or store data to be programmed therein, and the page buffer / sense circuit 160B senses data read from a selected page of the NAND array 110B or store data to be programmed therein.

[0023] The controller 140 is configured by a microcontroller or state machine including ROM / RAM, and controls the read, program, erase, and other operations of the NOR array 110A and the NAND array 110B. The NAND array 110B allows for page-by-page read, page-by-page program, and block-by-block erase. On the other hand, the NOR array 110A allows for memory cell read, memory cell program, and page-by-page erase in addition to page-by-page read, page-by-page program, and block-by-block erase.

[0024] Next, the NAND array 110B will be described in detail. Fig. 3 is a plan view of the NOR array 110A and the NAND array 110B corresponding to the equivalent circuit in Fig. 2. Fig. 4(A) is a plan view of the active region, trenches, and first and second control gates of the NAND array, and Fig. 4(B) is a cross-sectional view taken along line A1-A1 in Fig. 4(A).

[0025] Active regions 210 extending in the bit line direction are formed in a P-type silicon substrate or P-type well 200, and each active region 210 in the bit line direction is isolated by a trench 220 extending in the bit line direction. The active regions 210 provide channel regions and N-type source / drain diffusion regions for memory cells. A charge storage layer 230 is formed on the active regions 210, and is made up of multiple insulating layers sandwiching SiN layers. The charge storage layer 230 is patterned on the active region 210 for each memory cell.

[0026] The charge storage layer 230 may have, for example, an ONO structure of oxide / nitride / oxide, or may have multiple types of insulating films stacked between the silicon substrate and the nitride layer instead of a single oxide layer.Furthermore, multiple types of insulating films may be stacked between the nitride and the gate instead of a single oxide layer.

[0027] A first control gate (CG1) 240 is formed on the charge storage layer 230 and patterned to match the charge storage layer 230. The first control gate 240 may be made of, for example, impurity-doped conductive polysilicon, or may be made by stacking multiple low-resistance materials, such as TaN, and another metal layer. A second control gate (CG2) 250 is formed on the first control gate 240 and patterned to extend in the word line direction (row direction). The second control gate 250 is electrically connected to the first control gate 240. The second control gate 250 is preferably low-resistance and is made of a metal material such as Al or Cu. The first control gate 240 may be made of the same material as the second control gate 250, or a different material.

[0028] Although not shown here, the second control gate 250 of the bit line side select transistor and the source line side select transistor similarly constitutes the SGD gate line and the SGS gate line together with the first control gate 240, respectively, and the second control gate 250 is electrically connected to the first control gate 240 of the bit line side select transistor and the source line side select transistor, respectively.

[0029] FIG. 5 is a cross-sectional view of the NAND array 110B shown in FIG. 3 taken along line A2-A2, i.e., a cross-section in the bit line direction. As shown in the figure, an N-well 202 is formed in a P-type silicon substrate 200, and a P-well 204 is formed within the N-well 202. The P-well 204 provides an active region 210 and also provides N-type diffusion regions 212 for the source / drains of the memory cells, bit line side select transistors, and source line side select transistors. A charge storage layer 230 is formed on the P-well 204, and a first control gate 240 and a second control gate 250 are formed on the charge storage layer 230. A diffusion region 212A of the bit line side select transistor is electrically connected to a bit line BL via a contact CT1, and a diffusion region 212B of the source line side select transistor is electrically connected to a source line SL via a contact CT2.

[0030] In one embodiment, the charge storage layer 230 has, for example, an oxide / nitride / oxide ONO structure, which provides a SONOS structure formed between a silicon substrate (or silicon well) and a first control gate 240 made of polysilicon. During a program operation, the charge storage layer 230 stores charges that have tunneled from the channel region through the oxide layer by FN tunneling on the inner surface of the nitride layer, and during an erase operation, the charges stored in the charge storage layer are released to the channel region by FN tunneling through the oxide layer.

[0031] In this embodiment, the thickness of the nitride layer (SiN layer) of the charge storage layer 230 is sufficiently smaller than the thickness of the floating gate of the FG structure, and the nitride layer is an insulating film, so that the capacitive coupling between adjacent memory cells can be reduced compared to the FG structure, and as a result, it is possible to narrow the threshold distribution of the memory cells. Furthermore, if the nitride layer of the charge storage layer is formed continuously in the word line direction (if it is not separated for each memory cell), there is a problem that the threshold of the memory cell fluctuates when electrons held in the nitride layer are attracted to holes and move, or when holes are attracted to electrons and move. However, by separating the charge storage layer for each memory cell as in this embodiment, the above problem can be solved.

[0032] Next, the NOR array 110A will be described in detail. Fig. 6(A) is a cross-sectional view taken along the line B1-B1 of the region where memory cells of the NOR array 110A shown in Fig. 3 are formed. The NOR array 110A is formed on the same substrate 200 as the NAND array 110B. Similar to the NAND array 110B, the NOR array 110A has active regions 210 extending in the bit line direction and trenches 220 isolating the active regions 210 formed on the substrate 200. Similar to the NAND array 110B, a charge storage layer 230 patterned for each memory cell is formed on the active region 210, and a first control gate (CG1) 240 patterned for each memory cell is formed above the charge storage layer 230.

[0033] In the case of the NOR array 110A, a trench insulator 260 is filled in the trench 220 so that the outermost surface S is lower than the outermost surface of the active region 210. In addition, a sidewall insulator 262 is formed so as to cover the sidewalls of the first control gate 240 and the charge storage layer 230, and the bottom of the sidewall insulator 262 is connected to the trench insulator 260.

[0034] The outermost surface of the first control gate 240 is exposed by the sidewall insulator 262, and second control gates 250 extending in the word line direction are formed on the first control gates 240. The second control gates 250 are electrically connected to the first control gates 240 directly below them, and together with the first control gates 240, the second control gates 250 form each of the word lines WL0 to WL3. The first control gates 240 and second control gates 250 of the NOR array 110A are configured in the same manner as those of the NAND array 110B.

[0035] Although not shown here, the second control gate 250 of the bit line side select transistor and the source line side select transistor similarly constitutes the SGD gate line and the SGS gate line together with the first control gate 240, respectively, and the second control gate 250 is electrically connected to the first control gate 240 of the bit line side select transistor and the source line side select transistor, respectively.

[0036] 6B is a cross-sectional view taken along line B2-B2 of an area of ​​the NOR array 110B shown in FIG. 3 where no memory cells are formed. An N-type diffusion region 280 for the memory cell is formed on the surface of the active region 210 adjacent to the channel region of the memory cell, i.e., on the surface of the active region 210 exposed by the word line. Furthermore, an N-type diffusion region 280A is formed to a certain depth on the opposite side of the active region 210, and this diffusion region 280A is connected to the diffusion region 280 on the surface.

[0037] Unlike the memory cell region, the charge storage layer 230 and the first control gate 240 are not formed on the active region 210, and the sidewall insulator 262 protrudes from the surface of the active region 210. Also, the second control gate 250 is not formed, and instead, an interlayer insulating film 290 is formed to cover the trench insulator 260, the sidewall insulator 262, and the active region 210.

[0038] FIG. 7(A) is an equivalent circuit of a NOR memory cell, and FIG. 7(B) is a cross-sectional view of the NOR memory cell. A single NOR memory cell includes a memory cell transistor CELL_TR and a sidewall transistor SW_TR connected in parallel. The memory cell transistor CELL_TR includes a channel region on the outermost surface of the active region 210, a charge storage layer 230 and a first control gate 240 on the active region 210, and an N-type diffusion region 280 serving as a source / drain. The sidewall transistor CELL_TR includes a channel region on the side of the active region 210, a sidewall insulator 262 serving as a gate insulating film, and an N-type diffusion region 280A serving as a source / drain. The threshold voltage of the sidewall transistor CELL_TR is adjusted by the film thickness of the sidewall insulator 262, the boron concentration in the channel region, and other factors.

[0039] In the NOR array 110A as in the NAND array 110B, in one embodiment, the charge storage layer 230 has an oxide / nitride / oxide ONO structure, and the ONO structure provides a SONOS structure formed between the silicon substrate (or silicon well) 200 and the first control gate 240 made of polysilicon. During a program operation, the charge storage layer 230 stores charges that have tunneled from the channel region through the oxide layer by FN tunneling at the interface with the nitride layer, and during an erase operation, the charges stored in the charge storage layer are released to the channel region by FN tunneling through the oxide layer.

[0040] In this embodiment, the NOR array 110A has a configuration in which multiple memory cells are connected in series between the bit line side select transistor and the source line side select transistor, and therefore has a configuration similar to that of the NAND array 110B. Therefore, when the NOR array 110A and the NAND array 110B are formed on the same substrate, the manufacturing process can be simplified by using compatible processes.

[0041] Next, the operation of the flash memory 100 of this embodiment will be described. In a read operation of the NAND array 110B, a certain voltage (e.g., 0V) is applied to a selected word line, a read pass voltage (e.g., 4.5V) is applied to unselected word lines, a high-level voltage (e.g., 4.5V) is applied to select gate lines SGD / SGS, and 0V is applied to the source line SL. In a program operation, a high-level program voltage Vpgm (e.g., 15 to 20V) is applied to a selected word line, a program pass voltage (e.g., 10V) is applied to unselected word lines, a high-level voltage is applied to select gate line SGD, and a low-level voltage is applied to select gate line SGS. In an erase operation, 0V is applied to a selected word line in a selected block, and a low-level voltage is applied to select gate lines SGD / SGS. These operations are the same as those of a general NAND flash memory.

[0042] Next, the read operation of the NOR array 110A will be described. FIG. 8A shows the threshold Vt distribution of the memory cell transistor CELL_TR when the NOR array 110A stores one bit per memory cell. WL1 is the voltage applied to the word line WL of the selected memory cell during read. The threshold Vt distribution of the sidewall transistor SW_TR is WL1 must be higher than

[0043] The threshold voltage Vt of the "1" cell is V WL1 The threshold voltage Vt of the memory cell transistor CELL_TR is set lower than V WL1 If the threshold voltage Vt of a "0" cell is V, the selected memory cell transistor CELL_TR is turned on, but the sidewall transistor SW_TR is turned off. WL1 The threshold voltage Vt of the memory cell transistor CELL_TR is set higher than V WL1 If the voltage is higher than 0 V, the selected memory cell transistor CELL_TR is in the off state and the sidewall transistor SW_TR is in the off state.

[0044] The bias voltages for each part during a read operation are shown in the table in Figure 8(B). It is possible to simultaneously read one page of cells in a selected block. To correctly read the selected cells, a voltage V is applied to the unselected word lines. WL2 is applied, where V WL2 is set higher than the threshold Vt of the sidewall transistor SW_TR. Therefore, all of the sidewall transistors SW_TR connected to unselected word lines are turned on, that is, all unselected memory cells are turned on regardless of the threshold Vt of their memory transistors CELL_TR, and the sidewall transistor SW_CELL of the selected memory cell is turned off, so that data in the selected memory cell transistor CELL_TR is read correctly. During a read operation, a voltage higher than the threshold Vt of the source line side select transistor SL_TR and the bit line side select transistor BL_SEL is applied to the SGS gate and SGD gate, turning on these select transistors.

[0045] For example, in FIG. 2, when data is read from a memory cell MC connected to word line WL1, the sidewall transistor SW_TR connected to word line WL1 is in the off state, and the sidewall transistors SW_TR connected to unselected word lines WL0, WL2, and WL3 are all in the on state, and a current flows from the bit line BL to the source line SL according to the data "0" or "1" held in the memory cell transistor CELL_TR connected to word line WL1, and this current is sensed by the page buffer / sense circuit 160.

[0046] During read, the unselected cell array (unselected block) is V WL、 V SGS and V SGDare grounded. That is, the word lines WL and the SGS and SGD gates of the unselected cell arrays are grounded during read. To prevent read errors from the unselected cell arrays, the threshold voltage Vt of the source line side select transistors and bit line side select transistors must be higher than 0V. As a result, the unselected cell arrays can be completely turned off. Therefore, when a positive bias is applied to the bit line BL and the source line and P-well are grounded, if the cell being read in the selected block is a "1" cell, current flows from the bit line BL to the source line SL, but in the unselected blocks, no current flows from the bit line BL to the source line SL.

[0047] In a NOR array, like a NAND array, memory cells are connected between source line select transistors and bit line select transistors, so the relatively long gate lengths of the source line select transistors and bit line select transistors minimize leakage current between the bit lines and source lines of unselected blocks. This allows the gate length of the memory cells themselves to be shortened, reducing the effective cell size and the memory cell area.

[0048] The bias voltages during programming are shown in the table in Figure 9(B). In the programming operation, it is possible to program cells in one page at a time. Figure 9(A) shows two NOR cell arrays surrounded by dashed lines, and shows an example in which cell M1 connected to word line WL1 is programmed with "0" and cell M2 is programmed with "1" (i.e., "0" programming inhibit).

[0049] 0V is applied to the bit line BL of the left cell array, and some positive voltage (1.2 to 3V) is applied to the bit line BL of the right cell array. A high voltage (V program =8 to 16V) is applied to other word lines WL in the same cell array, and V program Almost half the voltage (V passA positive bias (1-2V) is applied to the SGD gate, which must be higher than the threshold voltage Vt of the bit line side select transistor BL_SEL. 0V is applied to the SGS gate, a positive bias (1-2V) is applied to the source line SL, and the P-well is grounded.

[0050] Applying 0V to the left bit line BL and applying a positive bias to the SGD gate turns on the bit line side select transistor BL_SEL and grounds the source side of the source line side select transistor SL_SEL. pass By applying V to the unselected cells, the unselected cells are also turned on, and 0V is transferred to the channel region of the selected cell (the left-hand cell M1 connected to WL1). The channel is grounded and a high voltage (V program ) allows electrons to tunnel into the charge storage layer, thus increasing the threshold voltage Vt of cell M1 and programming cell M1 to the "0" state.

[0051] Meanwhile, a slight positive bias is applied to the right bit line BL, so that the bit line side select transistor BL_SEL is turned off. By applying 0V to the SGS gate, the source line side select transistor SL_SEL is turned off. Therefore, the channel of the right NOR cell array is isolated from the bit line BL and the source line SL. Then, V is applied to the unselected word line WL and the selected word line WL1. pass and V program By applying a voltage of 0 V to the NOR cell array on the right, the channel region of the NOR cell array on the right can be boosted. This reduces the voltage difference between the silicon surface and the word line WL, preventing electron tunneling from the silicon surface to the charge storage layer, and preventing the threshold voltage Vt of cell M2 from shifting. Therefore, the selected cell M2 is programmed to "1." This programming sequence is essentially the same as programming conventional NAND flash memory.

[0052] Also, during program operation, the V WL、 VSGS and V SGD The non-selected blocks are grounded, and the source line side select transistors and bit line side select transistors, which have relatively long gate lengths, can be used to completely turn off the non-selected blocks. This allows the gate length of the memory cells themselves to be shortened, thereby reducing the effective cell size.

[0053] Next, the erase operation will be explained. The bias voltages during the erase operation are shown in the table in Figure 10. In a NOR array, it is possible to erase one block at a time. All word lines WL of the selected block are grounded, and V is applied to the P-well. erase By applying a voltage (8 to 16V), electrons in the charge storage layer move to the silicon surface, or holes on the silicon surface tunnel into the charge storage layer. This shifts the cell's threshold voltage Vt downward, and the cell enters the "1" state. The bit line BL, source line SL, SGS gate line, SGD gate line, and word line WL of the unselected block are in a floating state. The word line WL is in a floating state, and V WL V p-well Since the threshold voltage Vt of the cells in the unselected blocks is automatically boosted to a value close to .gt., the threshold voltage Vt of the cells in the unselected blocks does not shift.

[0054] The thickness of the sidewall insulating film (Tox: effective oxide thickness) which is the gate insulating film of the sidewall transistor is V program or V erase To avoid breakdown of the sidewall insulating film, the electric field applied between the second control gate and the sidewall of the silicon (active region) must be 5MV / cm or less (V program / Tox≦5MV / cm, and V erase / Tox≦5MV / cm).

[0055] Next, the manufacturing process of the NAND array of the flash memory of this embodiment will be described with reference to Figures 11 to 13. As shown in Figure 11(A), a three-layer insulating film 310, for example, an oxide film such as SiO2, a SiN film such as Si3N4, and an oxide film such as SiO2, is formed on the surface of a P-type silicon substrate or P-type well 300 (hereinafter referred to as a substrate for convenience) by CVD or the like. In the following description, the three-layer insulating film 310 will be referred to as a charge storage layer. Furthermore, a first control gate 320, for example, made of polysilicon, is formed on the charge storage layer 310.

[0056] 11(B), a mask material 330 such as a resist is formed. Next, the mask material 330 is patterned by a photolithography process to form mask patterns M1 that are spaced apart at regular intervals and extend in the bit line direction, as shown in FIG. 11(C).

[0057] 12(D), the exposed first control gate 320, charge storage layer 310, and substrate 300 are simultaneously anisotropically etched using a mask pattern M1 to form a stack of patterned charge storage layer 310 and first control gate 320 on the substrate 300, and at the same time, trenches 340 that define active regions 302 are formed in the substrate 300. FIG. 13(A) is a plan view of the substrate when the first control gate 320, charge storage layer 310, and substrate 300 have been etched using the mask pattern M1, and FIG. 12(D) corresponds to the cross section taken along line C1-C1 in FIG. 13(A).

[0058] The stack of the charge storage layer 310 and the first control gate 320 extends in the bit line direction, and the trench 340 is formed to be self-aligned to the sidewall of the stack of the charge storage layer 310 and the first control gate 320. Therefore, the trench 340 is formed with high precision without causing any positional error between the stack of the charge storage layer 310 and the first control gate 320. In addition, the charge storage layer 310 is protected from etching because it is covered by the first control gate 320.

[0059] 12(E), an insulating film 350 is formed on the entire surface of the substrate 300 including the trench 340, and then the insulating film 350 is etched to the vicinity of the surface of the substrate 300 so that a trench insulator 350A remains in the trench 340. At this time, the mask pattern M1 protects the first control gate 320 from etching.

[0060] Next, as shown in FIG. 12(F), the trench insulator 350A is etched by surface polishing to expose the surface of the mask pattern M1. Next, as shown in FIG. 12(G), the mask pattern M1 is removed, and the trench insulator 350A is surface polished to make the height of the trench insulator 350A approximately the same as that of the first control gate 320. In this way, the active region 302 extending in the bit line direction is isolated by the trench isolation region 350A, and a stack of the charge storage layer 310 and the first control gate 320 is formed on the active region 302. FIG. 13(B) is a plan view of the substrate when the heights of the first control gate 320 and the trench insulator 350A are made approximately the same, and FIG. 12(G) corresponds to the cross section taken along line C2-C2 in FIG. 13(B). Note that the process shown in FIG. 12(G) is not necessarily required.

[0061] Next, the manufacturing process of the NOR array of the flash memory of this embodiment will be described with reference to FIGS. 14 to 16. After the previously described processes of FIGS. 11A to 11C, the exposed first control gate 320, charge storage layer 310, and substrate 300 are simultaneously anisotropically etched using a mask pattern M1 shown in FIG. 14A, forming a stack of the charge storage layer 310 and first control gate 320 patterned in the bit line direction on the substrate 300. Simultaneously with this patterning, trenches 340 that define active regions 302 are formed in the substrate 300. Next, as shown in FIG. 14B, an insulating film 350 is formed over the entire surface of the substrate 300, including the trenches 340. The processes up to this point are the same as those in the manufacturing method of the NAND array.

[0062] Next, the insulating film 350 is etched so that the trench insulator 350A remains in the trench 340. At this time, the mask pattern M1 protects the first control gate 320 from etching.

[0063] Next, as shown in FIG. 14(C), the mask pattern M1 is removed. The outermost surface of the trench insulator 350A in the trench 340 is located lower than the outermost surface of the active region 302. Thus, the active region 302 extending in the bit line direction is isolated by the trench insulator 350A, and a stack of the charge storage layer 310 and the first control gate 320 is formed on the active region 302. FIG. 16(A) is a plan view of the substrate after removing the mask pattern M1, and FIG. 14(C) corresponds to the cross section taken along line D1-D1 in FIG. 16(A).

[0064] 15(D), an insulating film 360 is formed on the entire surface of the substrate, and the insulating film 360 is anisotropically etched to form a sidewall insulating film 360A that covers the sidewalls of the charge storage layer 310 and the first control 310, as shown in FIG. 15(E). The sidewall insulating film 360A is connected to the trench insulator 350A at the bottom.

[0065] Next, as shown in FIG. 15(F), a conductive material 370 is formed over the entire substrate, and a mask pattern M2 extending in the word line direction is formed thereon. FIG. 16(B) is a plan view of the substrate after the mask pattern M2 has been formed, and FIG. 15(F) corresponds to the cross section taken along line D2-D2 in FIG. 16(B). The conductive material 370 is etched through the mask pattern M2 to pattern a second control gate extending in the word line direction. At this time, in areas where memory cells will not be formed, the conductive material 370, first control gate 320, and charge storage layer 310 exposed by the mask pattern M2 are simultaneously etched, exposing the active region 302, as shown in FIG. 15(G). FIG. 15(G) corresponds to the cross section taken along line D3-D3 in FIG. 16(B).

[0066] Next, phosphorus or arsenic ions are implanted into the exposed active region 302 to form N-type diffusion regions 280, 280A on the surface and side surfaces of the active region 220, as shown in Fig. 6(B). Next, an insulating film is formed over the entire surface of the substrate, including the second control gate, and the insulating film is planarized by CMP or the like until the surface of the second control gate is exposed.

[0067] In this manner, the NOR array 110A and the NAND array 110B may be fabricated on the same substrate using a common or compatible process for fabricating the charge storage layer 310 and first control gate 320 stack.

[0068] Next, the manufacturing process for the cell array region and peripheral region of the flash memory of this embodiment will be described with reference to Figures 17 to 19. As shown in Figure 17(A), a charge storage layer 410 and a first control gate (CG1) 420 are formed on the entire surface of a P-type silicon substrate 400, and then a mask pattern M3 is formed to cover the cell array region. Next, as shown in Figure 17(B), the mask pattern M3 is used as an etching mask to etch away the charge storage layer 410 and the first control gate 420 on the peripheral region.

[0069] After removing the mask pattern M3, as shown in FIG. 17(C), a gate insulating film 430 is formed on the entire surface of the substrate 400, including the peripheral region. The gate insulating film 430 is, for example, a silicon oxide film. Sense amplifiers, decoders, and the like are formed in the peripheral region, and these circuits include transistors driven at high voltages and transistors driven at low voltages. Therefore, the gate insulating film 430 is formed with multiple thicknesses, including thick and thin films suitable for high and low voltages. After the gate insulating film 430 is formed, a gate material 440 for the transistors in the peripheral region is formed on the entire surface of the substrate 400. The gate material 440 is, for example, polysilicon.

[0070] Next, the gate insulating film 430 and the gate material 440 are etched back or planarized to expose the first control gate 420 in the cell array region and the gate material 440 in the peripheral region, as shown in Fig. 17(D). Through these steps, the charge storage layer 410 and the first control gate 420 in the cell array region can be formed separately from the gate insulating film 430 and the gate material 440 in the peripheral region.

[0071] In the above process, the gate insulating film 430 and gate material 440 are formed after removing the mask pattern M3. However, this is just an example, and the mask pattern M3 may be left. As shown in FIG. 17A(C)′, a gate insulating film 430A and a gate material 440A are formed over the entire surface of the substrate, including the mask pattern M3. In this case, the height of the mask pattern M3 in the cell array region is set to be approximately the same as the height of the gate material 440A when the gate insulating film 430A in the peripheral region is a thick insulating film with a high breakdown voltage. Furthermore, the gate insulating film 430A around the boundary between the cell array region and the peripheral region is a thick insulating film with a high breakdown voltage.

[0072] 17A(D)', a planarization process is performed to expose the mask pattern M3 in the cell array region and the gate material 440A in the peripheral region, and then the mask pattern M3 is removed. Through these processes, the charge storage layer 410 and the first control gate 420 in the cell array region can be formed separately from the gate insulating film 430A and the gate material 440A in the peripheral region.

[0073] After the first control gate 420 in the cell array region and the gate material 440 in the peripheral region are formed separately, a mask pattern M4 is formed as shown in FIG. 18(E), and the gate materials, gate insulating film, and silicon in the cell array region and the peripheral region are simultaneously etched to form trenches 450 and 452 in the substrate 400. The trench 450 formed in the cell array region may have a different size and / or depth than the trench 452 formed in the peripheral region.

[0074] After removing the mask pattern M4, an insulating material 460 is formed to fill the trenches 450 and 452, as shown in FIG. 18(F). The insulating material 460 is, for example, a silicon oxide film. Next, as shown in FIG. 18(G), the insulating material 460 is etched to form trench insulators 460A in the trenches 450 and 452. In the peripheral region, the trench insulator 460A filling the trench 452 is etched to the same height as the gate material 440 and is not etched any deeper.

[0075] Next, as previously described with reference to FIGS. 15(D) and 15(E), a sidewall insulating film (not shown here) is formed to cover the sidewalls of the active region 302, the charge storage layer 310, and the first control gate 320.

[0076] 19(H), a conductive material 470, which is a precursor of the second control gate, is formed on the entire surface of the substrate 400, including the first control gate 420 and the gate material 440. The conductive material 470 is not particularly limited, but may be a metal material such as Al or Cu. The conductive material 470 is electrically connected to the first control gate 420 and the gate material 440. Alternatively, a silicide metal may be formed between the conductive material 470 and the first control gate 420 and the gate material 440.

[0077] Next, as shown in FIG. 19(I), the conductive material 470 in the region where the charge storage layer 410 and the first control gate 420 are to be formed in the cell array is patterned to extend in the word line direction, forming a second control gate 470A. The second control gate 470A is electrically connected to a corresponding plurality of first control gates 420 in the row direction, providing a word line. Furthermore, by patterning the conductive material 470, the underlying first control gates 420 and charge storage layer 410 are simultaneously etched, exposing the active region. Meanwhile, in the peripheral region, the conductive material 470 is patterned to form a wiring layer 470B electrically connected to the gate material 440 and the like.

[0078] After patterning the second control gate 470A, ion implantation is performed to form N-type impurity regions for source / drain in the exposed active region 402. Then, bit lines BL and source lines SL are formed in the cell array region, similar to a conventional NAND flash memory.

[0079] As described above, the flash memory of this embodiment includes a memory cell array 110 in which a NOR array 110A and a NAND array 110B are integrated on a silicon substrate. The memory cell array 110 has a charge storage layer between the silicon and the control gate, which is composed of multiple insulating layers including SiN. The control gate is composed of two layers: a first control gate formed on the charge storage layer and a second control gate formed on the first control gate. The charge storage layer and the first control gate are successively deposited on silicon (Si). The first control gate, the charge storage layer, and the silicon are simultaneously etched to form a trench isolation region self-aligned to the first control gate and the charge storage layer. A second control gate is then formed on the first control gate, and the first control gate and the second control gate are electrically connected to each other to form a word line. The ends of the word lines in the cell array region are connected to a row decoder, which applies biases to the word lines WL for read, write (program), and erase operations.

[0080] Although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0081] 100: Flash memory 110: Memory cell array 110A: NOR type memory cell array 110B: NAND type memory cell array 200: Substrate 210: Active region 220: trench 230: charge storage layer 240: First control gate 250: Second control gate 260: Trench insulator 262: Sidewall insulator 280, 280A: Diffusion region 290: Interlayer insulating film 300: Substrate 302: Active region 310: Insulating layer (charge storage layer) 320: First control gate 330: Mask material 340: Trench 350: Insulating film 350A: Trench insulator 360: insulating film 360A: sidewall insulating film 400: Silicon substrate 410: Charge storage layer 420: First control gate 430: Gate insulating film 440: Gate material 450, 452: Trench 460: Insulating materials 460A: Trench insulators 470: Conductive material 470A: Second control gate

Claims

1. a memory cell array in which a NOR type memory cell array and a NAND type memory cell array are integrated; The memory cell array an active region formed in a semiconductor substrate so as to extend in a bit line direction; a trench adjacent to the active region; a charge storage layer formed on the active region for each memory cell, the charge storage layer including a nitride layer sandwiched between insulating layers; a first conductive layer formed on the charge storage layer for each memory cell; a second conductive layer extending in a word line direction and electrically connected to the first conductive layer; A semiconductor device having:

2. 2. The semiconductor device according to claim 1, further comprising a bit line commonly connected to the NOR type memory cell array and the NAND type memory cell array.

3. 2. The semiconductor device according to claim 1, further comprising: first bit lines connected to a NOR type memory cell array and second bit lines connected to a NAND type memory cell array, the first bit lines being isolated from the second bit lines.

4. 4. The semiconductor device according to claim 3, wherein the first bit line is connected to a first sense circuit, the second bit line is connected to a second sense circuit, the first sense circuit senses data of a selected memory cell of a NOR type memory cell array, and the second sense circuit senses data of a selected memory cell of a NAND type memory cell array.

5. 2. The semiconductor device according to claim 1, wherein said first conductive layer and said second conductive layer form a word line.

6. The NOR type memory cell array further includes a sidewall insulator formed in the trench and on a sidewall of the active region; The semiconductor device according to claim 1 , wherein said second conductive layer contacts said sidewall insulator within said trench.

7. The NOR type memory cell includes a memory cell transistor formed on the surface side of the active region and a sidewall transistor including the sidewall insulator, 7. The semiconductor device according to claim 6, wherein said memory cell transistor and said sidewall transistor are connected in parallel.

8. The semiconductor device of claim 1 , wherein the trench is aligned with sidewalls of the active region, the first conductive layer, and the charge storage layer.

9. 2. The semiconductor device according to claim 1, wherein the charge storage layer comprises an ONO structure of oxide / nitride / oxide, or a structure including a stack of multiple types of insulating films other than oxide between a silicon substrate and the nitride layer, or a structure including a stack of multiple types of insulating films other than oxide between the nitride and the first conductive layer.

10. 2. The semiconductor device according to claim 1, wherein the array of NOR type memory cells includes a plurality of memory cells connected in series between a bit line side select transistor and a source line side select transistor, and the array of NAND type memory cells includes a plurality of memory cells connected in series between a bit line side select transistor and a source line side select transistor.

11. a memory cell array in which a NOR type memory cell array and a NAND type memory cell array are integrated; a word line connected to each of the memory cells; a NOR type memory cell array and a bit line connected to a NAND type memory cell array; The NOR type memory cell array includes a plurality of memory cells connected in series between a bit line side select transistor and a source line side select transistor, and each memory cell includes a memory cell transistor and a sidewall transistor connected in parallel, A NAND memory cell array is a semiconductor device that includes a plurality of memory cells connected in series between a bit line side select transistor and a source line side select transistor.

12. 12. The semiconductor device according to claim 11, wherein said bit line is commonly connected to a NOR type memory cell array and a NAND type memory cell array.

13. 12. The semiconductor device according to claim 11, wherein the bit lines include first bit lines connected to a NOR type memory cell array and second bit lines connected to a NAND type memory cell array, and the first bit lines are separated from the second bit lines.

14. 14. The semiconductor device according to claim 13, wherein the first bit line is connected to a first sense circuit, the second bit line is connected to a second sense circuit, the first sense circuit senses data of a selected memory cell of a NOR type memory cell array, and the second sense circuit senses data of a selected memory cell of a NAND type memory cell array.

15. 12. The semiconductor device according to claim 11, wherein a threshold voltage of the sidewall transistor is set higher than a voltage of a selected word line and lower than a voltage of an unselected word line.

16. The semiconductor device includes a control unit for controlling reading and writing of the memory cell array, 12. The semiconductor device according to claim 11, wherein said control means enables reading and writing in page units of a NOR type memory cell array and reading and writing in memory cell units, and enables reading and writing in page units of a NAND type memory cell array.

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