Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device capable of forming a suitable electrode layer and a method for manufacturing the same are provided. [Solution] According to one embodiment, a semiconductor device includes a stacked film including a plurality of first insulating films and a plurality of electrode layers alternately arranged in a first direction, and a plurality of columnar portions extending in the first direction within the stacked film. A first columnar portion of the plurality of columnar portions includes a second insulating film provided on a side surface of the plurality of first insulating films and the plurality of electrode layers and containing a metal element, a third insulating film provided on a side surface of the second insulating film and containing silicon, a charge storage layer provided on a side surface of the third insulating film, a fourth insulating film provided on a side surface of the charge storage layer, and a semiconductor layer provided on a side surface of the fourth insulating film.

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] When manufacturing a 3D semiconductor memory, multiple electrode layers (e.g., word lines) stacked vertically are formed by, for example, a replacement process using slits. In this case, problems arise, such as the need to form slits for the replacement process, the high difficulty of the replacement process, and the long time it takes to complete the replacement process. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-100596 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of forming a suitable electrode layer and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a stacked film including a plurality of first insulating films and a plurality of electrode layers alternately arranged in a first direction, and a plurality of columnar portions extending in the first direction within the stacked film, wherein a first columnar portion of the plurality of columnar portions includes a second insulating film provided on a side surface of the plurality of first insulating films and the plurality of electrode layers and containing a metal element, a third insulating film provided on a side surface of the second insulating film and containing silicon, a charge storage layer provided on a side surface of the third insulating film, a fourth insulating film provided on a side surface of the charge storage layer, and a semiconductor layer provided on a side surface of the fourth insulating film. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view showing the structure of a semiconductor device according to a first embodiment. [Figure 3] 1 is a perspective view showing a structure of a semiconductor device according to a first embodiment; [Figure 4] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 5] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 6] 1A and 1B are a plan view and a cross-sectional view (1 / 5) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 1A and 1B are a plan view and a cross-sectional view (2 / 5) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 3A and 3B are a plan view and a cross-sectional view (3 / 5) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 4A and 4B are a plan view and a cross-sectional view (4 / 5) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 5A and 5B are a plan view and a cross-sectional view (5 / 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 1A and 1B are plan views showing the structure of the semiconductor device of the first embodiment and the structure of a semiconductor device of a comparative example of the first embodiment. [Figure 12] 1A to 1C are plan views showing the structures of semiconductor devices according to first and second modified examples of the first embodiment. [Figure 13] 2A and 2B are a plan view and a graph for explaining dimensions of the semiconductor device of the first embodiment. [Figure 14] 10A and 10B are a plan view and a graph for explaining dimensions of a semiconductor device according to a third modified example of the first embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a fourth modified example of the first embodiment. [Figure 16] 10A and 10B are a plan view and a graph showing the structure of a semiconductor device according to a second embodiment. [Figure 17]10A and 10B are a cross-sectional view and a plan view for explaining the structure of a semiconductor device according to a third embodiment. [Figure 18] 10 is a cross-sectional view (1 / 3) showing a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 19] 10 is a cross-sectional view (2 / 3) showing a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 20] 10 is a cross-sectional view (3 / 3) illustrating a method for manufacturing a semiconductor device according to a fourth embodiment. [Figure 21] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a fifth embodiment. [Figure 22] FIG. 10 is a plan view showing the structure of a semiconductor device according to a fifth embodiment. [Figure 23] 11A and 11B are cross-sectional views and a plan view (1 / 7) showing a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 24] 10A and 10B are cross-sectional views and a plan view (2 / 7) showing a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 25] 10A and 10B are a cross-sectional view and a plan view (3 / 7) illustrating a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 26] 10A and 10B are cross-sectional views and a plan view (4 / 7) showing a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 27] 10A and 10B are cross-sectional views and a plan view (5 / 7) showing a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 28] 10A and 10B are cross-sectional views and a plan view (6 / 7) showing a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 29] 10A and 10B are a cross-sectional view and a plan view (7 / 7) showing a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 30] 13A to 13C are plan views showing a method for manufacturing a semiconductor device according to a modified example of the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 30, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0008] (First embodiment) 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention, which is, for example, a three-dimensional semiconductor memory.

[0009] The semiconductor device of this embodiment includes a substrate 1, a stacked film 2, and multiple columnar portions 3. The stacked film 2 includes multiple insulating films 2a and multiple electrode layers 2b. Each columnar portion 3 includes a block insulating film 3a, a charge storage layer 3b, a tunnel insulating film 3c, a channel semiconductor layer 3d, and a core insulating film 3e. The block insulating film 3a in each columnar portion 3 includes an insulating film 11 and an insulating film 12. The insulating film 2a, the insulating film 11, the insulating film 12, and the tunnel insulating film 3c are examples of a first, second, third, and fourth insulating films, respectively. The channel semiconductor layer 3d is an example of a semiconductor layer, and each columnar portion 3 is an example of a first columnar portion.

[0010] The substrate 1 is, for example, a semiconductor substrate such as a Si (silicon) substrate. FIG. 1 shows an X direction and a Y direction that are parallel to the surface of the substrate 1 and perpendicular to each other, and a Z direction that is perpendicular to the surface of the substrate 1. In this specification, the +Z direction is treated as the upward direction, and the −Z direction is treated as the downward direction. The −Z direction may or may not coincide with the direction of gravity. The Z direction is an example of a first direction.

[0011] The laminated film 2 is formed on the substrate 1. The laminated film 2 may be formed above the substrate 1 via another film (e.g., an interlayer insulating film). The laminated film 2 includes a plurality of insulating films 2a and a plurality of electrode layers 2b arranged alternately in the Z direction. Each insulating film 2a is, for example, an SiO2 film (silicon oxide film). Each electrode layer 2b is, for example, a metal layer such as a Mo (molybdenum) layer. Each electrode layer 2b functions, for example, as a word line, a source-side selection line, or a drain-side selection line.

[0012] FIG. 1 shows a plurality of memory holes MH formed in a laminated film 2. Each memory hole MH extends in the Z direction and has a circular shape in a plan view. Each memory hole MH of this embodiment penetrates the laminated film 2 in the Z direction and reaches the substrate 1. Each memory hole MH is an example of a first recess.

[0013] Each columnar portion 3 is formed in a corresponding one of the memory holes MH. Therefore, each columnar portion 3 extends in the Z direction and has a circular shape in a plan view. Furthermore, each columnar portion 3 of this embodiment penetrates the stacked film 2 in the Z direction to reach the substrate 1. Each columnar portion 3 includes an insulating film 11, an insulating film 12, a charge storage layer 3b, a tunnel insulating film 3c, a channel semiconductor layer 3d, and a core insulating film 3e, which are formed in this order on the side surfaces of the substrate 1 and the stacked film 2 and on the upper surface of the substrate 1.

[0014] The insulating film 11 is formed on the side surfaces of the substrate 1, the insulating films 2a, and the electrode layers 2b, and on the upper surface of the substrate 1. The insulating film 11 is made of, for example, AlO x The Al element in the insulating film 11 is an example of a metal element in the first insulating film.

[0015] The insulating film 12 is formed on the side and upper surfaces of the insulating film 11. The insulating film 12 is, for example, an SiO2 film.

[0016] The charge storage layer 3b is formed on the side and upper surfaces of the insulating film 12. The charge storage layer 3b is, for example, an insulating film such as a SiN film (silicon nitride film). The charge storage layer 3b may also be a semiconductor layer such as a polysilicon layer. The charge storage layer 3b of this embodiment is capable of storing signal charges of a three-dimensional semiconductor memory.

[0017] The tunnel insulating film 3c is formed on the side and top surfaces of the charge storage layer 3b. The tunnel insulating film 3c is, for example, an SiO2 film.

[0018] The channel semiconductor layer 3d is formed on the side and top surfaces of the tunnel insulating film 3c. The channel semiconductor layer 3d is, for example, a polysilicon layer. In this embodiment, the channel semiconductor layer 3d functions as channels for multiple cell transistors (memory cells) and multiple select transistors in the three-dimensional semiconductor memory.

[0019] The core insulating film 3e is formed on the side and top surfaces of the channel semiconductor layer 3d and is, for example, an SiO2 film.

[0020] The insulating film 11 of this embodiment is not part of the stacked film 2 but part of the columnar section 3, and specifically, is formed on the side surfaces of the plurality of insulating films 2a and the plurality of electrode layers 2b. A method for forming such an insulating film 11 will be described later.

[0021] The semiconductor device of this embodiment does not necessarily have to include the substrate 1 below the laminated film 2. For example, when the semiconductor device of this embodiment is manufactured by bonding two or more substrates together, the semiconductor device of this embodiment may include a substrate above the laminated film 2 instead of including the substrate 1 below the laminated film 2.

[0022] Each electrode layer 2b in this embodiment may include a barrier metal layer and an electrode material layer, examples of which will be described later.

[0023] Fig. 2 is a plan view showing the structure of the semiconductor device of the first embodiment. Fig. 2 shows an XY cross section at the position of arrow A1 shown in Fig. 1. On the other hand, Fig. 1 shows an XZ cross section at the position of arrow A2 shown in Fig. 2.

[0024] 2 shows a plurality of pillars 3 arranged in a triangular lattice shape in a plan view. In this embodiment, the triangular lattice is formed of a plurality of equilateral triangles. The triangular lattice may be formed of a plurality of triangles other than equilateral triangles, for example, a plurality of isosceles triangles. Examples of such triangular lattices will be described later.

[0025] The laminated film 2 includes a plurality of insulating films 2a and a plurality of electrode layers 2b, as well as a plurality of insulating films 2c. Specifically, the laminated film 2 includes a plurality of insulating films 2a and a plurality of composite layers alternately formed in the Z direction, and each of these composite layers includes one electrode layer 2b and one insulating film 2c, as shown in FIG. 2. Each insulating film 2c is, for example, a SiN film. Each insulating film 2c is an example of a fifth insulating film. One insulating film 2c shown in FIG. 2 includes a plurality of portions P separated from each other. Each portion P is an example of a first portion.

[0026] One electrode layer 2b and one insulating film 2c shown in Figure 2 are provided between two insulating films 2a (Figure 1) adjacent to each other in the Z direction. These two insulating films 2a are examples of an upper insulating film and a lower insulating film. Also, one electrode layer 2b and one insulating film 2c shown in Figure 2 are examples of a predetermined electrode layer and a predetermined fifth insulating film, respectively.

[0027] One electrode layer 2b shown in Fig. 2 has a shape including multiple annular portions in a plan view. These multiple annular portions are arranged in a triangular lattice shape and are arranged so as to partially overlap one another. Each annular portion is arranged so as to annularly surround a corresponding one of the columnar portions 3. Each annular portion is an example of a surrounding portion that surrounds a columnar portion.

[0028] As described above, one insulating film 2c shown in FIG. 2 includes a plurality of portions P that are separated from one another. These plurality of portions P are provided in one electrode layer 2b shown in FIG. 2. Each portion P is sandwiched between three columnar portions 3 in plan view, and also sandwiched between three annular portions of the electrode layer 2b in plan view. Each portion P is formed on a side surface of the electrode layer 2b. Furthermore, each portion P has a shape that approximates a triangle in plan view.

[0029] When manufacturing the semiconductor device of this embodiment, multiple cavities C are formed around each memory hole MH. Each cavity C around each memory hole MH is formed between two insulating films 2a (FIG. 1) adjacent to each other in the Z direction. FIG. 2 shows the positions of the two cavities C around the two memory holes MH with dashed lines. In FIG. 2, these two cavities C are arranged so as to partially overlap each other. In one electrode layer 2b shown in FIG. 2, each annular portion is formed in a corresponding one cavity C. In other words, each annular portion of the electrode layer 2b corresponds to a portion within one cavity C in the electrode layer 2b. Each cavity C is an example of a second recess.

[0030] FIG. 3 is a perspective view showing the structure of the semiconductor device of the first embodiment.

[0031] 3 shows the shape of one memory hole MH and the shape of the cavity C around this memory hole MH. When manufacturing the semiconductor device of this embodiment, as described above, multiple cavities C are formed around each memory hole MH. Each cavity C has a shape that surrounds this memory hole MH in an annular shape in plan view.

[0032] Fig. 4 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. Fig. 1 shows an XZ cross section at the position of arrow A2 shown in Fig. 2. On the other hand, Fig. 4 shows an XZ cross section at the position of arrow A3 shown in Fig. 2. Note that Fig. 4 omits the illustration of the internal structure of each columnar portion 3 (similar omissions will be adopted as appropriate in other figures described later).

[0033] As described above, the laminated film 2 includes a plurality of insulating films 2a, a plurality of electrode layers 2b, and a plurality of insulating films 2c. Specifically, the laminated film 2 includes a plurality of insulating films 2a and a plurality of composite layers alternately formed in the Z direction, and each composite layer includes one electrode layer 2b and one insulating film 2c, as shown in Fig. 4. In Fig. 4, each insulating film 2c includes a plurality of portions P that are separated from each other.

[0034] 4 shows the positions of a plurality of memory holes MH with dashed lines. FIG. 4 also shows the positions of a plurality of cavities C around these memory holes MH with dashed lines. However, to avoid making FIG. 4 difficult to understand, FIG. 4 shows only the positions of some of these cavities C with dashed lines. As described above, each annular portion of each electrode layer 2b is provided in a corresponding one of the cavities C.

[0035] 5 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment, which shows an enlarged XZ cross section of FIG.

[0036] 5, the insulating film 11, insulating film 12, charge storage layer 3b, tunnel insulating film 3c, channel semiconductor layer 3d, and core insulating film 3e in the columnar portion 3 are formed in this order on the right side surface of the stacked film 2. In FIG. 5, the side surface of the electrode layer 2b is recessed to the left with respect to the side surface of the insulating film 2a. As a result, part of the columnar portion 3 extends into each cavity C.

[0037] In this embodiment, such a depression may or may not be formed on the side surface of the electrode layer 2b.

[0038] Figures 6 to 10 are plan views and cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment. Figure 6(a) is a plan view corresponding to Figure 2, and Figure 6(b) is a cross-sectional view corresponding to Figure 1. The same applies to Figures 7(a) to 10(b).

[0039] First, a plurality of insulating films 2a and a plurality of insulating films 2c are alternately formed on the substrate 1 to form a laminated film 2 on the substrate 1 (FIGS. 6(a) and 6(b)). As a result, the laminated film 2 is formed to include a plurality of insulating films 2a and a plurality of insulating films 2c alternately in the Z direction.

[0040] Next, a plurality of memory holes MH are formed in the laminated film 2 by lithography and RIE (Reactive Ion Etching) (FIGS. 6(a) and 6(b)). In this embodiment, each memory hole MH is formed so as to penetrate the laminated film 2 in the Z direction and reach the substrate 1.

[0041] Next, a chemical solution is supplied into each memory hole MH to remove the plurality of insulating films 2c from each memory hole MH (FIGS. 7(a) and 7(b)). As a result, a plurality of cavities C are formed around each memory hole MH. Each cavity C is formed between two insulating films 2a adjacent to each other in the Z direction.

[0042] In this embodiment, multiple cavities C are formed in each insulating film 2c so as to partially overlap one another, as shown in Fig. 7(a). Also, as shown in Fig. 7(a), these multiple cavities C are formed by removing only a portion of the insulating film 2c, leaving multiple portions P of the insulating film 2c. According to this embodiment, by removing each insulating film 2c so that the portions P remain, it is possible to prevent the stacked film 2 from collapsing after the removal of each insulating film 2c.

[0043] Next, a conductive layer 2b' is formed on the entire surface of the substrate 1 (FIGS. 8(a) and 8(b)). As a result, the conductive layer 2b' is formed in each cavity C, on the side and bottom surfaces of each memory hole MH, and on the upper surface of the laminated film 2. In FIG. 8(b), the conductive layer 2b' is formed from the multiple memory holes MH to the multiple cavities C. The conductive layer 2b' is, for example, a Mo layer. The conductive layer 2b' is formed as the material of the multiple electrode layers 2b shown in FIG.

[0044] Next, the excess conductive layer 2b' is removed by etching so that the conductive layer 2b' remains in each cavity C (FIGS. 9(a) and 9(b)). As a result, a stacked film 2a including a plurality of insulating films 2a and a plurality of electrode layers 2b alternately arranged in the Z direction is formed on the substrate 1. At this time, the above-mentioned depressions shown in FIG. 5 may occur.

[0045] Next, the insulating film 11, the insulating film 12, the charge storage layer 3b, the tunnel insulating film 3c, the channel semiconductor layer 3d, and the core insulating film 3e are formed in this order on the entire surface of the substrate 1 (FIGS. 10(a) and 10(b)). As a result, a columnar portion 3 is formed in each memory hole MH.

[0046] Next, excess insulating film 11, insulating film 12, charge storage layer 3b, tunnel insulating film 3c, channel semiconductor layer 3d, and core insulating film 3e are removed so as to leave a columnar portion 3 in each memory hole MH (FIGS. 10(a) and 10(b)). In this manner, the semiconductor device shown in FIGS. 1 and 2 is manufactured.

[0047] 11A and 11B are plan views showing the structure of the semiconductor device of the first embodiment and the structure of a semiconductor device of a comparative example of the first embodiment. Figures 11A and 11B are plan views corresponding to Figure 2.

[0048] As shown in FIG. 11(b), the semiconductor device of the comparative example includes regions R1 and R2 adjacent to each other in the Y direction. Each of regions R1 and R2 includes a plurality of columnar portions 3. The semiconductor device of the comparative example further includes a slit ST provided between regions R1 and R2. The slit ST penetrates the stacked film 2 in the Z direction and extends in the Z and X directions. The semiconductor device of the comparative example further includes an insulating film 21 formed in the slit ST. The insulating film 21 is, for example, a SiO2 film.

[0049] In the comparative example, a replacement step of replacing a plurality of insulating films 2c with a plurality of electrode layers 2b is performed by using slits ST. Specifically, the plurality of insulating films 2c are removed through the slits ST, thereby forming a plurality of cavities, and a plurality of electrode layers 2b are formed in the plurality of cavities through the slits ST.

[0050] In this case, problems arise such as the need to form slits ST for the replacement process, the high process difficulty of the replacement process, and the long time required for the replacement process. For example, forming slits ST increases the area of ​​the semiconductor device in a plan view. Regarding the process difficulty, problems arise such as the difficulty of removing the insulating film 2c at a position away from the slits ST and the precipitation of silica due to the high etching selectivity between the SiO2 film and the SiN film.

[0051] On the other hand, the semiconductor device of this embodiment does not have a slit ST, as shown in Figure 11(a). In this embodiment, the replacement process of replacing the multiple insulating films 2c with multiple electrode layers 2b is performed using the memory holes MH. Specifically, the multiple insulating films 2c are removed from the memory holes MH, thereby forming multiple cavities C, and multiple electrode layers 2b are formed in these multiple cavities C from the memory holes MH.

[0052] According to this embodiment, the replacement step is performed without forming the slits ST, thereby reducing the area of ​​the semiconductor device in plan view. Furthermore, according to this embodiment, the insulating films 11 and 12 of the block insulating film 3a have not yet been formed when the insulating film 2c is removed, so the etching selectivity when removing the insulating film 2c can be reduced. This makes it possible to suppress silica precipitation. Furthermore, according to this embodiment, the replacement step is performed using a large number of small memory holes MH instead of large slits ST, so the replacement step can be performed in a short time and the insulating film 2c can be easily removed. Furthermore, according to this embodiment, the electrode layer 2b can be easily formed by using the memory holes MH instead of the slits ST.

[0053] 12A and 12B are plan views showing the structures of semiconductor devices according to first and second modifications of the first embodiment, respectively, and correspond to FIG.

[0054] The semiconductor device of the first modified example has regions R1 and R2 adjacent to each other in the Y direction, similar to the semiconductor device of the comparative example (FIG. 12(a)). FIG. 12(a) shows one insulating film 2c in the laminated film 2. The insulating film 2c of this modified example includes multiple portions P and portion P'. Portion P' extends between the multiple columnar portions 3 in region R1 and the multiple columnar portions 3 in region R2, and extends in the X direction. Portion P' is an example of the second portion. Furthermore, regions R1 and R2 are examples of the first and second regions.

[0055] According to this modification, it is possible to divide one electrode layer 2b shown in FIG. 12(a) into a portion within region R1 and a portion within region R2. Furthermore, according to this modification, by making portion P' smaller, it is possible to divide electrode layer 2b while reducing the area of ​​the semiconductor device in a plan view. The area of ​​portion P' is not used in the replacement process like slit ST, so it can be made smaller than slit ST. In this modification, portions P and P' can be formed by removing insulating film 2c so that portions P and P' remain.

[0056] The semiconductor device of the second modification has a structure similar to that of the semiconductor device of the first modification (FIG. 12(b)). The semiconductor device of this modification further includes a plurality of dummy memory holes MH' formed in the portion P'. Each dummy memory hole MH' has the same shape as the memory hole MH and extends in the Z direction within the portion P'. The semiconductor device of this modification further includes a wiring layer 22 formed in each dummy memory hole MH'. The wiring layer 22 is, for example, a metal layer or a semiconductor layer. The wiring layer 22 in each dummy memory hole MH' is used, for example, as wiring that electrically connects components above the stacked film 2 with components below the stacked film 2. The wiring layer 22 in each dummy memory hole MH' is electrically connected, for example, to the substrate 1. The wiring layer 22 is an example of a third conductive layer.

[0057] FIG. 13 is a plan view and a graph for explaining the dimensions of the semiconductor device of the first embodiment.

[0058] FIG. 13(a) shows three memory holes MH adjacent to each other and three cavities C surrounding these memory holes MH. FIG. 13(a) further shows the diameter D of each memory hole MH, the centers V of the three memory holes MH, and the triangle T formed by these centers V. The triangle T shown in FIG. 13(a) is an equilateral triangle.

[0059] Also, FIG. 13(a) shows, as examples of the cavity C, the minimum allowable cavity C1 and the maximum allowable cavity C2. FIG. 13(a) further shows the radius a of the cavity C1 and the radius b of the cavity C2. The radius a is the minimum value of the radius of the cavity C, and the radius b is the maximum value of the radius of the cavity C.

[0060] The radius a is the lower limit value at which the three cavities C shown in FIG. 13(a) contact each other. If the radius of each cavity C is set smaller than the radius a, these cavities C will not contact each other, and each electrode layer 2b (FIGS. 1 and 2) will be separated for each cavity C.

[0061] The radius b is the lower limit value at which the three cavities C shown in FIG. 13(a) contact each other so that no gap remains between these cavities C. If the radius of each cavity C is set larger than the radius b, the portion P of each insulating film 2c (FIGS. 2 and 4) will disappear.

[0062] FIG. 13(b) shows the radius D / 2 of the memory hole MH, the radius a of the cavity C1, and the radius b of the cavity C2 starting from the same center V. The relationship D / 2 < a < b holds among these radii D / 2, a, and b.

[0063] The "etching amount" shown in FIG. 13(b) represents the amount of etching for forming the cavity C from the memory hole MH. The etching amount in this embodiment needs to be set so that the radius of the cavity C falls within the range from a to b. The "allowable width" shown in FIG. 13(b) represents the width of this range.

[0064] In this embodiment, the etching margin when forming the cavity C from the memory hole MH is represented by the following formula (1). Etching margin = tolerance ÷ etching amount (1)

[0065] The etching amount in formula (1) represents the amount of etching when the radius of cavity C is (a+b) / 2, where (a+b) / 2 is the average value of radius a and radius b. The etching amount in formula (1) is expressed by the following formula (2). Etching amount = (a+b) / 2-D / 2 (2)

[0066] On the other hand, the allowable range of the formula (1) is expressed by the following formula (3). Tolerance = ba (3)

[0067] When setting the radii D / 2, a, and b in this embodiment, it is desirable to set the radii D / 2, a, and b so that the etching margin of formula (1) becomes large.

[0068] FIG. 14 is a plan view and a graph for explaining the dimensions of the semiconductor device according to the third modification of the first embodiment.

[0069] The semiconductor device of this modification has the same structure as the semiconductor device of the first embodiment shown in Figures 1 and 2. However, each memory hole MH of this modification has a different diameter D depending on the height.

[0070] 14(a) and 14(b) are plan views corresponding to FIG. 13(a). However, FIG. 14(a) shows the case where the diameter D of each memory hole MH is the maximum value D max FIG. 14(b) shows the XY cross section at a height where the diameter D of each memory hole MH is the minimum value D min The figure shows the XY cross section at the height where

[0071] 14(c) is a graph corresponding to FIG. 13(b). FIG. 14(c) shows the maximum radius D of the memory hole MH, starting from the same center V. max / 2 and the minimum radius D of the memory hole MH min / 2 and the average radius of the memory hole MH, D aveIt shows D / 2, the radius a of cavity C1, and the radius b of cavity C2. These radii D max / 2, D min / 2, D ave / 2, a, and b satisfy the relationship D min / 2 < D ave / 2 < D max / 2 < a < b, and D ave = (D max + D min ) / 2. Figure 14(c) further shows the difference ΔD / 2 between the maximum radius D max / 2 and the minimum radius D min (ΔD / 2 = D max / 2 - D min / 2).

[0072] The etching margin of this modified example is expressed by the above formula (1), similar to the etching margin of the first embodiment. On the other hand, the etching amount of this modified example is expressed by the following formula (4), and the allowable width of this modified example is expressed by the following formula (5). Etching amount = (a + b) / 2 - D ave / 2 ···(4) Allowable width = b - a - ΔD / 2 ···(5)

[0073] The etching amount of this modified example represents the average amount of etching for forming cavity C from memory hole MH. On the other hand, the allowable width of this modified example is the value obtained by subtracting the variation "ΔD / 2" of radius D / 2 from the allowable width "b - a" of the first embodiment.

[0074] When setting the radius D / 2, a, and b of this modified example, it is desirable to set the radius D / 2, a, and b so that the etching margin of formula (1) becomes larger. However, formula (1) in this modified example is calculated using formulas (4) and (5).

[0075] Figure 15 is a cross-sectional view showing the structure of a semiconductor device according to the fourth modified example of the first embodiment.

[0076] The semiconductor device of this modification has a structure similar to that of the semiconductor device of the first embodiment shown in Fig. 5. However, Fig. 15 shows three insulating films 2a, two electrode layers 2b, and two insulating films 2c included in the stacked film 2. Fig. 15 also shows two portions P included in these two insulating films 2c.

[0077] In FIG. 15, each electrode layer 2b of this modification is in contact with two insulating films 2a and one portion P. Here, each electrode layer 2b of this modification includes a barrier metal layer 13 formed on the upper surface of one insulating film 2a, the lower surface of the other insulating film 2a, and the side surface of the portion P, and an electrode material layer 14 formed on the upper surface, lower surface, and side surface of the barrier metal layer 13. The barrier metal layer 13 is, for example, a TiN film (titanium nitride film). The electrode material layer 14 is, for example, a W (tungsten) layer. The barrier metal layer 13 is an example of a first conductive layer, and the electrode material layer 14 is an example of a second conductive layer.

[0078] Each electrode layer 2b in this modified example can be formed by forming a conductive layer 2b' including a barrier metal layer 13 and an electrode material layer 14 in this order in the steps shown in FIGS. 8(a) and 8(b), for example.

[0079] As described above, the replacement step of this embodiment is performed by using the memory holes MH instead of the slits ST. This makes it possible to form the insulating film 11 (block insulating film 3a) having the shape shown in FIG. 1 and the like, and the electrode layer 2b and insulating film 2c having the shapes shown in FIG. 2 and the like. According to this embodiment, by performing the replacement step by using the memory holes MH, it is possible to form a suitable electrode layer 2b, for example, by solving various problems that may arise when forming the electrode layer 2b.

[0080] (Second embodiment) FIG. 16 is a plan view and a graph showing the structure of the semiconductor device of the second embodiment.

[0081] FIG. 16(a) is a plan view corresponding to FIG. 2, FIG. 11(a), etc. FIG. 16(b) is a plan view corresponding to FIG. 13(a), etc. As shown in FIG. 16(a) and FIG. 16(b), the semiconductor device of this embodiment includes a plurality of columnar portions 3 (memory holes MH) arranged in a triangular lattice shape in a plan view. In this embodiment, the triangular lattice is formed by a plurality of isosceles triangles. The triangle T shown in FIG. 16(b) is an isosceles triangle.

[0082] One insulating film 2c shown in FIG. 16(a) includes multiple portions P and multiple portions P'. These portions P' shown in FIG. 16(a) extend in the X direction, similar to the portion P' shown in FIG. 12(a), and divide one electrode layer 2b into multiple portions. These portions of the electrode layer 2b also extend in the X direction. Each portion P' shown in FIG. 16(a) is an example of a second portion.

[0083] The triangle T shown in FIG. 16(b) has one side with a length "2a" and two sides with a length "2ta." According to this embodiment, by making the value of t sufficiently large, it becomes possible to form a plurality of portions P' in the insulating film 2c. According to this embodiment, these portions P' make it possible to effectively suppress collapse of the stacked film 2.

[0084] FIG. 16(c) is a graph for comparing the case where triangle T is an equilateral triangle with the case where triangle T is an isosceles triangle. Value b1 represents the length of each side of triangle T when triangle T is an equilateral triangle. Value b2 represents the length of the equal sides of triangle T when triangle T is an isosceles triangle. Here, b1=2a and b2=2ta. FIG. 16(c) is a graph with t on the horizontal axis and b2 / b1 on the vertical axis.

[0085] According to this embodiment, by forming the triangular lattice from a plurality of isosceles triangles, it is possible to form the portion P′ in the insulating film 2c, which makes it possible to effectively suppress collapse of the laminated film 2.

[0086] (Third embodiment) FIG. 17 is a cross-sectional view and a plan view illustrating the structure of the semiconductor device of the third embodiment.

[0087] Fig. 17(a) is a cross-sectional view corresponding to Fig. 6(b). Each memory hole MH in this embodiment has a different radius depending on its height. In Fig. 17(a), the radius of each memory hole MH is smaller near the upper and lower ends of each memory hole MH and is larger between the upper and lower ends.

[0088] Fig. 17(b) shows an XY cross section at the position of arrow B1 shown in Fig. 17(a), and Fig. 17(c) shows an XY cross section at the position of arrow B2 shown in Fig. 17(a). Fig. 17(b) and Fig. 17(c) show the radius r of each memory hole MH. Each memory hole MH in this embodiment has a different radius r depending on its height.

[0089] In FIG. 17(a), the insulating film 2c at the position of arrow B1 has a portion sandwiched between the memory hole MH on the left side and the memory hole MH on the right side. Hereinafter, this portion will be referred to as the "middle portion." At the position of arrow B1, if the radius r of each memory hole MH (FIG. 17(b)) increases, the width of the middle portion will become shorter, and there is a risk that the portion P of the insulating film 2c will not remain after the wet etching shown in FIGS. 7(a) and 7(b). Note that the portion P is the middle portion that remains after this wet etching. However, the portion P may not remain in the cross section shown in FIG. 17(a), but may remain in a cross section different from the cross section shown in FIG. 17(a) (for example, the portion P does not remain in the cross section shown in FIG. 7(b)).

[0090] 17(a), the insulating film 2c at the position of the arrow B2 has an intermediate portion sandwiched between the memory hole MH on the left side and the memory hole MH on the right side. At the position of the arrow B2, if the radius r of each memory hole MH (FIG. 17(c)) becomes smaller, the width of the intermediate portion becomes longer, and there is a risk that the cavities C will not contact each other after the wet etching shown in FIGS. 7(a) and 7(b).

[0091] 17(a) shows a plurality of insulating films 2c in the laminated film 2, which further includes a plurality of intermediate portions sandwiched between the left memory hole MH and the right memory hole MH. In this embodiment, it is desirable to suppress the width of these intermediate portions from changing depending on the height after the wet etching. In other words, it is desirable to suppress the width of the plurality of portions P formed from these intermediate portions from changing depending on the height.

[0092] Therefore, before forming the stacked film 2 of this embodiment, the shape of each memory hole MH is predicted by simulation. If the simulation reveals that the radius r of a certain insulating film 2c is large, the film quality of that insulating film 2c is set so that the etching rate of that insulating film 2c is low when that insulating film 2c is formed. On the other hand, if the simulation reveals that the radius r of a certain insulating film 2c is small, the film quality of that insulating film 2c is set so that the etching rate of that insulating film 2c is high when that insulating film 2c is formed. This makes it possible to suppress changes in the width of the multiple portions P depending on the height. These film qualities are examples of the first and second film qualities. The types of film qualities of the multiple insulating films 2c in the stacked film 2 may be three or more.

[0093] Each insulating film 2c in this embodiment is, for example, a SiN film. The film quality of each insulating film 2c can be adjusted by, for example, the density of each insulating film 2c and the concentration of impurity oxygen atoms in each insulating film 2c.

[0094] According to this embodiment, by changing the film quality of each of the multiple insulating films 2c in the stacked film 2, it is possible to prevent the width of the multiple portions P from changing depending on the height.

[0095] (Fourth embodiment) 18 to 20 are cross-sectional views showing a method for manufacturing a semiconductor device according to the fourth embodiment. Figures 18(a) to 20(b) are cross-sectional views corresponding to Figure 1. The method for manufacturing a semiconductor device according to this embodiment shown in Figures 18(a) to 20(b) corresponds to a modified example of the method for manufacturing a semiconductor device according to the first embodiment shown in Figures 6(a) to 10(b).

[0096] First, a plurality of insulating films 2a and a plurality of insulating films 2c are alternately formed on the substrate 1 to form a lower laminated film 2-1 on the substrate 1 (FIG. 18(a)). As a result, the lower laminated film 2-1 is formed to include a plurality of insulating films 2a and a plurality of insulating films 2c alternately in the Z direction. The lower laminated film 2-1 corresponds to a part of the laminated film 2.

[0097] Next, a plurality of lower memory holes MH1 are formed in the lower laminated film 2-1 by lithography and RIE (FIG. 18(a)). In this embodiment, each lower memory hole MH1 is formed so as to penetrate the lower laminated film 2-1 in the Z direction and reach the substrate 1. Each lower memory hole MH1 corresponds to a portion of one memory hole MH. Each lower memory hole MH1 is an example of the lower portion of the first recess. The process shown in FIG. 18(a) is performed in the same manner as the processes shown in FIGS. 6(a) and 6(b).

[0098] Next, a chemical solution is supplied into each lower memory hole MH1 to remove the plurality of insulating films 2c from each lower memory hole MH1 (FIG. 18(b)). As a result, a plurality of cavities C are formed around each lower memory hole MH1. Each cavity C is formed between two insulating films 2a adjacent to each other in the Z direction. These cavities C are examples of the second recesses and the third recesses. The process shown in FIG. 18(b) is performed in the same manner as the processes shown in FIGS. 7(a) and 7(b).

[0099] Next, a sacrificial layer 31 is formed in the lower memory holes MH1 and the cavities C provided in the lower stacked film 2-1 (FIG. 19(a)). The sacrificial layer 31 is, for example, an amorphous Si layer or an amorphous C (carbon) layer. The sacrificial layer 31 is an example of a first film.

[0100] Next, a plurality of insulating films 2a and a plurality of insulating films 2c are alternately formed on the lower laminated film 2-1 and the sacrificial layer 31, and an upper laminated film 2-2 is formed on the lower laminated film 2-1 and the sacrificial layer 31 (FIG. 19(b)). As a result, the upper laminated film 2-2 is formed to include a plurality of insulating films 2a and a plurality of insulating films 2c alternately in the Z direction. The upper laminated film 2-2 corresponds to a part of the laminated film 2.

[0101] Next, a plurality of upper memory holes MH2 are formed in the upper laminated film 2-2 by lithography and RIE (FIG. 19(b)). In this embodiment, each upper memory hole MH2 is formed so as to penetrate the upper laminated film 2-2 in the Z direction and reach the sacrificial layer 31 in the corresponding lower memory hole MH1. Each upper memory hole MH2 corresponds to a part of one memory hole MH. Each upper memory hole MH2 is an example of the upper part of the first recess. The process shown in FIG. 19(b) is performed in the same manner as the processes shown in FIGS. 6(a) and 6(b).

[0102] Next, a chemical solution is supplied into each upper memory hole MH2 to remove the plurality of insulating films 2c from each upper memory hole MH2 (FIG. 20(a)). As a result, a plurality of cavities C are formed around each upper memory hole MH2. Each cavity C is formed between two insulating films 2a adjacent to each other in the Z direction. These cavities C are examples of the second recess and the fourth recess. The process shown in FIG. 20(a) is performed in the same manner as the processes shown in FIGS. 7(a) and 7(b).

[0103] Next, the sacrificial layer 31 is removed from the plurality of lower memory holes MH1 and the plurality of cavities C provided in the lower laminated film 2-1 (FIG. 20(b)). In this way, the laminated film 2 is formed to include the lower laminated film 2-1 and the upper laminated film 2-2, and each memory hole MH is formed to include one lower memory hole MH1 and one upper memory hole MH2.

[0104] 8(a) to 10(b) are then carried out, thereby manufacturing a semiconductor device having the same structure as the semiconductor device shown in FIG.

[0105] According to this embodiment, by forming the laminated film 2 into a lower laminated film 2-1 and an upper laminated film 2-2, it becomes possible to easily form, for example, a laminated film 2 including a large number of insulating films 2a, 2c, or a memory hole MH with a large aspect ratio.

[0106] Although the laminated film 2 of this embodiment includes two partial laminated films (lower laminated film 2-1 and upper laminated film 2-2), it may instead include three or more partial laminated films. Also, each memory hole MH of this embodiment may be formed to include a joint portion near the boundary between the lower memory hole MH1 and the upper memory hole MH2.

[0107] (Fifth embodiment) 21 is a cross-sectional view showing the structure of the semiconductor device of the fifth embodiment, which corresponds to FIG.

[0108] The semiconductor device of this embodiment has a structure similar to that of the semiconductor device of the first embodiment shown in Figures 1 and 2. However, the stacked film 2 of this embodiment includes a flat portion P1 and a staircase structure portion P2. The flat portion P1 has a flat upper surface. The staircase structure portion P2 has a staircase-like upper surface and side surfaces.

[0109] The flat portion P1 has the same structure as the laminated film 2 shown in Fig. 1. Fig. 21 shows a plurality of columnar portions 3 (memory holes MH) formed in the laminated film 2. The memory insulating film 3f in each columnar portion 3 includes an insulating film 11, an insulating film 12, a charge storage layer 3b, and a tunnel insulating film 3c in this order.

[0110] Each step of the staircase structure P2 is formed by one insulating film 2a, one electrode layer 2b, and one insulating film 2c (not shown), except that the bottom step of the staircase structure P2 is formed by only one insulating film 2a.

[0111] The semiconductor device of this embodiment further includes an interlayer insulating film 4, a plurality of beam portions 5, and a plurality of contact plugs 6. Each contact plug 6 includes a plug body portion 6a and a plug base portion 6b. Each beam portion 5 is an example of a sixth insulating film, and each contact plug 6 is an example of a plug. The plug body portion 6a is an example of an upper portion of the plug, and the plug base portion 6b is an example of a lower portion of the plug.

[0112] The interlayer insulating film 4 is formed on the staircase structure portion P2 so as to eliminate the step between the upper surface of the flat portion P1 and the upper surface of the staircase structure portion P2. The interlayer insulating film 4 is, for example, an SiO2 film.

[0113] 21 further shows a plurality of holes HR formed in the staircase structure P2 and the interlayer insulating film 4. Each hole HR extends in the Z direction and has a circular shape in plan view. In this embodiment, each hole HR penetrates the interlayer insulating film 4 and the staircase structure P2 in the Z direction to reach the substrate 1.

[0114] Each beam portion 5 is formed in a corresponding hole HR. Therefore, each beam portion 5 extends in the Z direction and has a circular shape in a plan view. Furthermore, each beam portion 5 of this embodiment penetrates the interlayer insulating film 4 and the staircase structure portion P2 in the Z direction to reach the substrate 1. Each beam portion 5 is formed of an insulating film such as an SiO2 film. Each beam portion 5 of this embodiment functions as a beam that suppresses collapse of the stacked film 2.

[0115] FIG. 21 further shows a plurality of contact holes CC and a plurality of extended contact holes CC' formed in the staircase structure P2 and the interlayer insulating film 4. Each contact hole CC extends in the Z direction and has a circular shape in plan view. As shown in FIG. 21, each contact hole CC in this embodiment penetrates the interlayer insulating film 4 and one insulating film 2a in the Z direction. Meanwhile, each extended contact hole CC' is provided below one corresponding contact hole CC. As shown in FIG. 21, each extended contact hole CC' in this embodiment is provided in one electrode layer 2b.

[0116] Each contact plug 6 includes a plug body 6a formed in a corresponding contact hole CC and a plug base 6b formed in a corresponding extended contact hole CC'. Therefore, the plug body 6a of each contact plug 6 extends in the Z direction and has a circular shape in plan view. The plug base 6b of each contact plug 6 is provided in one electrode layer 2b below the plug body 6a and is formed on the side surface of the electrode layer 2b. As a result, each contact plug 6 is electrically connected to a corresponding electrode layer 2b. Each contact plug 6 is a metal plug including, for example, a Mo layer or a W layer.

[0117] Fig. 22 is a plan view showing the structure of the semiconductor device of the fifth embodiment. Fig. 22 shows an XY cross section at the position of arrow A1 shown in Fig. 21. On the other hand, Fig. 21 shows an XZ cross section at the position of arrow A2 shown in Fig. 22.

[0118] The flat portion P1 shown in FIG. 22 has a structure similar to that of the laminated film 2 shown in FIG. 2. For example, the multiple columnar portions 3 shown in FIG. 22 are arranged in the shape of a triangular lattice. The triangular lattice is formed of multiple equilateral triangles. Furthermore, one insulating film 2c shown in FIG. 22 includes multiple portions P formed in one electrode layer 2b. The electrode layer 2b has a shape including multiple annular portions that partially overlap each other, and each columnar portion 3 is surrounded in an annular shape by one annular portion.

[0119] On the other hand, in the staircase structure portion P2 shown in FIG. 22, multiple beam portions 5 are arranged in the same manner as the multiple columnar portions 3. For example, these beam portions 5 are arranged in the shape of a triangular lattice. The triangular lattice is formed by multiple equilateral triangles. Furthermore, the electrode layer 2b includes multiple circular ring portions not only in the flat portion P1 but also in the staircase structure portion P2, and each beam portion 5 is surrounded by a single circular ring portion in an annular shape. The multiple circular ring portions in the flat portion P1 and the staircase structure portion P2 are arranged to partially overlap each other. Each circular ring portion in the flat portion P1 is an example of a surrounding portion that surrounds a columnar portion, and each circular ring portion in the staircase structure portion P2 is an example of a surrounding portion that surrounds a beam portion (sixth insulating film). In a plan view, the diameter of each beam portion 5 is set to be larger than the diameter of each columnar portion 3 in this embodiment, but may instead be set to be equal to or smaller than the diameter of each columnar portion 3.

[0120] Furthermore, in the staircase structure P2 shown in FIG. 22, one contact plug 6 is arranged at one lattice point of the triangular lattice, instead of one beam portion 5. In FIG. 23, the plug body portion 6a (contact hole CC) has a circular shape in a plan view, and the plug base portion 6b (extended contact hole CC′) has a shape close to a hexagon in a plan view. In FIG. 23, the plug base portion 6b is in contact with six annular portions in the electrode layer 2b, and as a result, the contact plug 6 is electrically connected to the electrode layer 2b. In a plan view, the diameter of each contact plug 6 is set to be larger than the diameter of each columnar portion 3 in this embodiment, but may instead be set to be equal to or smaller than the diameter of each columnar portion 3. In a plan view, the diameter of each contact plug 6 is set to be the same as the diameter of each beam portion 5 in this embodiment, but may instead be set to be different from the diameter of each beam portion 5.

[0121] It should be noted that, in order to make the insulating film 2c easier to see, only a portion of the insulating film 2c is shown in FIG.

[0122] Figures 23 to 29 are cross-sectional views and plan views showing a method for manufacturing a semiconductor device according to the fifth embodiment. Figure 23(a) is a cross-sectional view corresponding to Figure 21, and Figure 23(b) is a plan view corresponding to Figure 22. This also applies to Figures 24(a) to 29(b).

[0123] First, a plurality of insulating films 2a and a plurality of insulating films 2c are alternately formed on the substrate 1 to form a stacked film 2 on the substrate 1 (FIGS. 23(a) and 23(b)). As a result, the stacked film 2 is formed to include a plurality of insulating films 2a and a plurality of insulating films 2c alternately in the Z direction. The stacked film 2 of this embodiment is formed by lithography and RIE to include a flat portion P1 and a staircase structure portion P2.

[0124] Next, an interlayer insulating film 4 is formed on the staircase structure portion P2 (FIGS. 23(a) and 23(b)). Next, a plurality of memory holes MH and a plurality of holes HR are formed in the stacked film 2 by lithography and RIE (FIGS. 23(a) and 23(b)). Each memory hole MH in this embodiment is formed so as to penetrate the flat portion P1 in the Z direction and reach the substrate 1. On the other hand, each hole HR in this embodiment is formed so as to penetrate the interlayer insulating film 4 and the staircase structure portion P2 in the Z direction and reach the substrate 1.

[0125] Next, a mask layer 41 is formed on the stacked film 2 (FIGS. 24(a) and 24(b)). The mask layer 41 of this embodiment is formed so that the flat portion P1 is covered with the mask layer 41 and the staircase structure portion P2 is exposed from the mask layer 41. The mask layer 41 is also formed in each memory hole MH. The mask layer 41 is, for example, a C (carbon) layer.

[0126] Next, a chemical solution is supplied into each hole HR to remove the plurality of insulating films 2c in the staircase structure portion P2 from each hole HR (FIGS. 24(a) and 24(b)). As a result, a plurality of cavities C' are formed around each hole HR. Each cavity C' is formed between two insulating films 2a adjacent to each other in the Z direction. Thereafter, the mask layer 41 is removed.

[0127] Next, a chemical solution is supplied into each memory hole MH and each hole HR to remove the plurality of insulating films 2c from each memory hole MH and each hole HR (FIGS. 25(a) and 25(b)). As a result, a plurality of cavities C are formed around each memory hole MH, and the radius of each cavity C' increases. Each cavity C is formed between two insulating films 2a adjacent to each other in the Z direction.

[0128] In this embodiment, multiple cavities C, C' in each insulating film 2c are formed to partially overlap each other, as shown in Figure 25(b). Also, as shown in Figure 25(b), these multiple cavities C, C' are formed by removing only a portion of the insulating film 2c, leaving the insulating film 2c partially intact. According to this embodiment, by removing each insulating film 2c so that the insulating film 2c partially remains, it is possible to prevent the stacked film 2 from collapsing after the removal of each insulating film 2c.

[0129] Next, a columnar portion 3 is formed in each memory hole MH, and a beam portion 5 is formed in each hole HR (FIGS. 26(a) and 26(b)).

[0130] Next, a plurality of contact holes CC are formed in the stacked film 2 by lithography and RIE (FIGS. 27(a) and 27(b)). Each contact hole CC in this embodiment is formed to penetrate the interlayer insulating film 4 and one insulating film 2a in the Z direction and reach one insulating film 2c.

[0131] In Fig. 27(a), each contact hole CC is formed on a part of the insulating film 2c. As shown in Fig. 27(b), the part of the insulating film 2c is surrounded by six cavities C'. In the electrode layer 2b shown in Fig. 27(a), the part inside each cavity C' in the electrode layer 2b corresponds to one annular portion of the electrode layer 2b.

[0132] Next, the portion of the insulating film 2c is removed by etching through each contact hole CC (FIGS. 28(a) and 28(b)). As a result, each extended contact hole CC' in the stacked film 2 is formed below a corresponding one of the contact holes CC.

[0133] Next, a plurality of contact plugs 6 are formed in the laminated film 2 and the interlayer insulating film 4 (FIGS. 29(a) and 29(b)). The plug body 6a of each contact plug 6 is formed in a corresponding contact hole CC, and the plug base 6b of each contact plug 6 is formed in a corresponding extended contact hole CC'. In this embodiment, the plug body 6a and plug base 6b of each contact plug 6 are simultaneously formed by filling the corresponding contact hole CC and extended contact hole CC' with the same metal material. In this manner, the semiconductor device shown in FIGS. 21 and 22 is manufactured.

[0134] 30A and 30B are plan views showing a method for manufacturing a semiconductor device according to a modification of the fifth embodiment, and correspond to FIG.

[0135] The process shown in Figure 30(a) corresponds to the process shown in Figures 24(a) and 24(b). The multiple holes HR shown in Figure 30(a) include multiple holes HR1, multiple holes HR2 having diameters larger than the diameters of holes HR1, and multiple holes HR3 having diameters larger than the diameters of holes HR2. Hole HR2 is disposed farther from flat portion P1 than hole HR1. Hole HR3 is disposed farther from flat portion P1 than hole HR2. As a result, the diameters of the multiple holes HR shown in Figure 30(a) increase as they move farther from flat portion P1.

[0136] The process shown in Figure 30(b) corresponds to the process shown in Figures 25(a) and 25(b). According to this modification, by increasing the diameter of the hole HR the farther it is from the flat portion P1, it becomes possible to easily connect the multiple cavities C, C' shown in Figure 30(b). Therefore, when carrying out the method for manufacturing the semiconductor device of the fifth embodiment shown in Figures 23(a) to 29(b), the processes shown in Figures 30(a) and 30(b) may be adopted.

[0137] According to this embodiment, by applying the contents of the first embodiment not only to the flat portion P1 but also to the staircase structure portion P2, it becomes possible to form a suitable electrode layer 2b, beam portion 5, contact plug 6, etc.

[0138] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and method described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the forms of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0139] 1: substrate, 2: laminated film, 2-1: lower laminated film, 2-2: upper laminated film, 2a: insulating film, 2b: electrode layer, 2b': conductive layer, 2c: insulating film, 3: columnar portion, 3a: block insulating film, 3b: charge storage layer, 3c: tunnel insulating film, 3d: channel semiconductor layer, 3e: core insulating film, 3f: memory insulating film, 4: interlayer insulating film, 5: beam portion, 6: contact plug, 6a: plug body, 6b: plug base, 11: insulating film, 12: insulating film, 13: barrier metal layer, 14: electrode material layer, 21: insulating film, 22: wiring layer, 31: sacrificial layer, 41: mask layer

Claims

1. a stacked film including a plurality of first insulating films and a plurality of electrode layers alternately provided in a first direction; a plurality of columnar portions extending in the first direction within the stacked film; A first columnar portion of the plurality of columnar portions is a second insulating film provided on a side surface of the plurality of first insulating films and the plurality of electrode layers and containing a metal element; a third insulating film provided on a side surface of the second insulating film and containing silicon; a charge storage layer provided on a side surface of the third insulating film; a fourth insulating film provided on a side surface of the charge storage layer; a semiconductor layer provided on a side surface of the fourth insulating film, Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein said laminated film further includes a plurality of fifth insulating films alternately provided with said plurality of first insulating films in said first direction.

3. The semiconductor device according to claim 2 , wherein said plurality of fifth insulating films are provided on side surfaces of said plurality of electrode layers.

4. 3. The semiconductor device according to claim 2, wherein said plurality of first insulating films contain silicon and oxygen, and said plurality of fifth insulating films contain silicon and nitrogen.

5. 3. The semiconductor device according to claim 2, wherein said plurality of fifth insulating films include at least a fifth insulating film having a first film quality and a fifth insulating film having a second film quality different from said first film quality.

6. a predetermined electrode layer among the plurality of electrode layers and a predetermined fifth insulating film among the plurality of fifth insulating films are provided between a lower insulating film and an upper insulating film among the plurality of first insulating films, the predetermined electrode layer includes a surrounding portion that annularly surrounds the columnar portion, the predetermined fifth insulating film includes a first portion provided in the predetermined electrode layer; The semiconductor device according to claim 2 .

7. a predetermined electrode layer among the plurality of electrode layers and a predetermined fifth insulating film among the plurality of fifth insulating films are provided between a lower insulating film and an upper insulating film among the plurality of first insulating films, the predetermined electrode layer includes a first conductive layer provided on an upper surface of the lower insulating film, a lower surface of the upper insulating film, and a side surface of the predetermined fifth insulating film, and a second conductive layer provided on an upper surface, a lower surface, and a side surface of the first conductive layer; The semiconductor device according to claim 2 .

8. a sixth insulating film extending in the first direction within the staircase structure portion of the stacked film; 2. The semiconductor device according to claim 1, wherein a predetermined electrode layer of said plurality of electrode layers includes a surrounding portion that annularly surrounds said sixth insulating film.

9. 9. The semiconductor device according to claim 8, further comprising a plug provided on said staircase structure portion of said laminated film and electrically connected to said predetermined electrode layer.

10. 10. The semiconductor device according to claim 9, wherein the plug includes a lower portion provided on a side surface of the predetermined electrode layer, and an upper portion provided on the lower portion and extending in the first direction.

11. The semiconductor device according to claim 1 , wherein the plurality of pillars are arranged in a triangular lattice shape in a plan view.

12. 12. The semiconductor device according to claim 11, wherein said triangular lattice is formed by a plurality of equilateral triangles or a plurality of isosceles triangles.

13. the stacked film further includes a plurality of fifth insulating films alternately provided with the plurality of first insulating films in the first direction, 12. The semiconductor device according to claim 11, wherein a predetermined fifth insulating film of said plurality of fifth insulating films includes a first portion sandwiched between at least three of said plurality of columnar portions.

14. 14. The semiconductor device according to claim 13, wherein the predetermined fifth insulating film among the plurality of fifth insulating films further includes a second portion extending between one or more columnar portions in the first region and one or more columnar portions in the second region.

15. The semiconductor device according to claim 14 , further comprising a third conductive layer extending in the first direction within the second portion.

16. forming a stacked film including a plurality of first insulating films and a plurality of fifth insulating films alternately provided in a first direction; forming a first recess extending in the first direction in the stacked film; removing at least a portion of the plurality of fifth insulating films from the first recesses to form a plurality of second recesses between the plurality of first insulating films; forming a plurality of electrode layers in the plurality of second recesses; forming a columnar portion in the first recess; A method for manufacturing a semiconductor device, comprising:

17. The columnar portion is forming a second insulating film containing a metal element on side surfaces of the first insulating films and the electrode layers in the first recess; forming a third insulating film containing silicon on a side surface of the second insulating film; forming a charge storage layer on a side surface of the third insulating film; forming a fourth insulating film on a side surface of the charge storage layer; forming a semiconductor layer on a side surface of the fourth insulating film; The method for manufacturing a semiconductor device according to claim 16,

18. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the second recesses are formed such that the portions of the fifth insulating films are removed and other portions of the fifth insulating films remain.

19. The stacked film, the first recess, and the plurality of second recesses are forming a lower laminated film of the laminated film; forming a lower portion of the first recess and a plurality of third recesses among the plurality of second recesses in the lower stack film; forming an upper laminate film of the laminate film on the lower laminate film; forming an upper portion of the first recess and a plurality of fourth recesses among the plurality of second recesses in the upper stacked film; The method for manufacturing a semiconductor device according to claim 16,

20. forming the plurality of third recesses in the lower stack film, and then forming a first film in the lower portion of the first recess and in the plurality of third recesses; after forming the upper portion of the first recess in the upper stack film, the first film is removed from the lower portion of the first recess and the plurality of third recesses; The method for manufacturing a semiconductor device according to claim 19.

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