Semiconductor device manufacturing method and semiconductor device

Abstract

A semiconductor device including a vertical PNP bipolar transistor with improved breakdown voltage is provided. The method involves forming a P-type Si semiconductor substrate with N - performing a first heat treatment to form a buried isolation layer of the N - N in the region of the buried isolation layer of the mold + performing a second heat treatment to form a buried layer; - Within the buried isolation layer of the type N + P at a position separated from the buried layer + and performing a third heat treatment to form a buried collector layer of the N type. - The width of the buried isolation layer of the mold in the depth direction is adjusted by the first heat treatment.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to improving the breakdown voltage of a semiconductor device including a vertical PNP. [Background technology]

[0002] To realize wideband, high-frequency analog ICs, it is effective to use a complementary bipolar process that uses vertical PNP bipolar transistors (hereinafter referred to as VPNP).Compared to lateral PNP bipolar transistors, VPNPs can be used with high-speed and high-current specifications, but they require isolation from the substrate (EPI breakdown voltage). The conventional manufacturing process of this type of VPNP is shown in Figure 4. First, a thick oxide film 2 is formed on the entire surface of a Si substrate 1 by thermal oxidation, and then an opening is made by photoetching. Then, ions are implanted to form a N + A buried layer 6 is formed (FIG. 4(a)). In the VNPN area, + The buried layer 6 is N + This serves as the buried collector layer of the mold. Next, after thermal oxidation again, the oxide film is opened by photoetching, and N is formed by ion implantation. - A buried layer 4 is formed (FIG. 4(b)). After that, annealing is performed to recover the crystal defects caused by the ion implantation.

[0003] Next, the oxide film is removed by etching, a photomask is formed on the Si substrate, and ions are implanted through the openings to form P + A buried layer 7 is formed. + The buried layer 7 serves as a buried collector layer in the VPNP area, and serves as part of the element isolation layer 23 in other areas. Thereafter, after annealing and other necessary treatments are performed, epitaxial growth is carried out to form an N-type epitaxial layer 8 (FIG. 4(c)).

[0004] Next, a P collector wall 9, an N base layer 10, an N isolation layer 11, an N base contact 12, a P emitter layer 13, and a P collector contact layer 14 are formed using well-known semiconductor processes. An interlayer insulating film 15 is then formed on top of these, and then aluminum wiring 16 is formed by sputtering. After that, a Si nitride film 17 is formed to stabilize the surface, and a passivation film 18 such as PSG is formed on the top layer. Finally, openings are made in these insulating films, and various electrodes (19-22) are formed (Figure 4(d)).

[0005] In VPNPs designed for high voltages (40V or higher), the maximum operating voltage of the circuit is often determined by the EPI breakdown voltage. If the EPI potential is used indefinitely to ensure this EPI breakdown voltage, an unintended substrate current will flow due to the parasitic transistor formed in the VPNP, limiting the circuit operating range. Figure 5 shows an equivalent circuit including the parasitic transistors formed in a conventional VPNP. As shown in the figure, a parasitic NPN transistor Q2 and a parasitic PNP transistor Q3 are formed, and when these are turned on, an unintended substrate current flows. Figure 6 is a graph showing the change in substrate current when the base-emitter voltage VBE is changed in a VPNP. As this graph shows, increasing the EPI potential also increases the VBE at which substrate current begins to flow. For example, the dotted line shows the case where the EPI potential is undefined. The substrate current begins to rise when VBE is around -1V and saturates at around -1.2V. Therefore, the breakdown voltage when the EPI potential is undefined is less than -1V. Similarly, when the EPI potential is fixed at 0V, 5V, and 10V, the breakdown voltages are less than -1.2V, less than -1.7V, and greater than -2V, respectively. Therefore, as shown in Fig. 5, a bias electrode 19 for fixing the EPI potential is provided. This bias electrode 19 is connected to the N isolation layer 11, and the N isolation layer 11 is connected to the N + N through buried layer 6 -It is connected to buried layer 4. Therefore, when a predetermined voltage is applied to bias electrode 19, the EPI potential can be fixed. In other words, the voltage applied to bias electrode 19 raises the base potential of Q3, reversing the relationship between the emitter potential of Q3 (collector potential of Q1) and the base potential (EPI potential), preventing Q3 from operating. However, there is a limit to the EPI breakdown voltage, which limits the voltage that can be applied to bias electrode 19. An example of a device structure designed to apply a high potential to a bias electrode is the technology disclosed in Patent Document 1. This technology forms an intermediate buried layer between a buried isolation layer and a buried collector layer, and adjusts the concentration profiles of these three buried layers to adjust the spread of the depletion layer to a suitable level, thereby improving the breakdown voltage. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Special Publication No. 05-064851 Summary of the Invention [Problem to be solved by the invention]

[0007] The technology of Patent Document 1 requires ion implantation and diffusion processes to form the intermediate buried layer, and also requires adjusting the concentration profile in the depth direction of the three buried layers, as well as their relative depths and widths, which increases the number of steps and makes it difficult to set manufacturing conditions such as parameters for various manufacturing equipment and to manage the processes. In view of the above problems, an object of the present invention is to provide a semiconductor device including a VPNP bipolar transistor with improved breakdown voltage achieved through a simple process. [Means for solving the problem]

[0008] The method for manufacturing a semiconductor device according to the present embodiment includes the steps of preparing a Si semiconductor substrate having a P-type conductivity and performing a first heat treatment for introducing a first donor into the Si semiconductor substrate, - forming a buried isolation layer of the N - performing a second thermal treatment to introduce second donors into the region of the buried isolation layer of the mold; + forming a buried layer; - performing a third thermal treatment to introduce acceptors into the buried isolation layer of the N + P at a position separated from the buried layer + forming a buried collector layer of the N type; + Connect with the buried layer, P + forming an isolation layer surrounding the buried collector layer of the P + forming a bias electrode connected to the isolation layer surrounding the buried collector layer of the N type; - The width Wn of the buried isolation layer of the mold in the depth direction is adjusted by the first heat treatment. In addition, the above N - The width of the buried isolation layer of the mold in the depth direction is adjusted by the first heat treatment, and as a result, - the width Wn of the buried isolation layer in the depth direction of the mold, and + The ratio Wr (Wr = Wn / Wp) of the width Wp in the depth direction of the buried collector layer of the mold is expressed by the following formula: 1.5≦Wr≦1.7 The value may be set to satisfy the following.

[0009] The semiconductor device according to this embodiment is a semiconductor device including a vertical PNP transistor having a bias electrode for fixing an EPI potential, and includes a Si semiconductor substrate having a P-type conductivity and an N-type electrode formed on the Si semiconductor substrate. - a buried isolation layer of a type, an N isolation layer connected to the bias electrode and surrounding a main portion of the vertical PNP transistor; - embedded isolation layer formed in the N -N-type buried isolation layer and the N-type isolation layer are connected + a buried layer and the N - In the buried isolation layer of the N - P formed at a distance from the buried isolation layer of the mold + and a buried collector layer of the type, and by applying a voltage to the bias electrode, operation of a parasitic transistor included in the vertical PNP transistor is suppressed. In addition, the above N - the width Wn of the buried isolation layer in the depth direction of the mold, and + The ratio Wr (Wr = Wn / Wp) of the width Wp in the depth direction of the buried collector layer of the mold is expressed by the following formula: 1.5≦Wr≦1.7 can be set to a value that satisfies the above. [Effects of the Invention]

[0010] According to one aspect of the present invention, the EPI potential can be set high to suppress the operation of the parasitic transistor of the VPNP, thereby widening the operating voltage range of the circuit. [Brief explanation of the drawings]

[0011] [Figure 1] 1A to 1C are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 2] FIG. 1 shows the concentration profile of a VPNP semiconductor device. [Figure 3] FIG. 10 is a diagram showing the correlation between the ratio of the width in the depth direction of the buried layer and the EPI breakdown voltage. [Figure 4] 1A to 1C are diagrams illustrating a conventional manufacturing process of a semiconductor device. [Figure 5] FIG. 1 is a diagram showing an equivalent circuit including a parasitic transistor of a VPNP semiconductor device. [Figure 6] FIG. 10 is a diagram showing the correlation between EPI voltage and substrate current. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present invention will be described with reference to Figures 1 to 3. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0013] A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described using a complementary bipolar process as an example with reference to Fig. 1. Fig. 1 shows cross sections of a semiconductor device arranged vertically in the order of steps (a) to (e). First, the crystal orientation is <100> A thick oxide film 2 is formed on the entire surface of the Si substrate 1 by thermal oxidation. - After forming a resist having an opening corresponding to the region where the buried layer 4 is to be formed, the thick oxide film 2 is etched to expose the surface of the Si substrate 1. A pad oxide film 3 is formed on this exposed surface, and donor ions are implanted through this pad oxide film 3 to form N - A buried layer 4 is formed. - The buried layer 4 functions as a buried isolation layer. The ion implantation conditions in this embodiment are as follows: phosphorus (P) is used as a donor, ion acceleration energy is 50 keV or more, and a dose amount is 2×10 14 ions / cm 2 The above process resulted in the state shown in Figure 1(a). After that, a heat treatment was carried out in a mixed atmosphere of oxygen and hydrogen at a temperature of 1150°C or higher for 80 minutes (first heat treatment). - The donors in the buried layer 4 diffuse to a depth of approximately 9000 angstroms from the surface of the Si substrate 1, and at the same time, the oxide film on the surface of the Si substrate 1 increases in thickness, filling the openings to the extent that it can prevent the penetration of ions during the next ion implantation. The above process results in the state shown in Figure 1(b).

[0014] Next, photolithography was performed to + A resist is formed with an opening corresponding to the region where the buried layer 6 is to be formed. In the VPNP area, N + The region where the buried layer 6 is to be formed is N -The oxide film is then etched to expose the surface of the Si substrate 1, and a pad oxide film 5 is formed. Donor ions are implanted through the pad oxide film 5, and N + A buried layer 6 is formed. Note that the N + The buried layer 6 is later - It is used to connect the buried layer 4 and the N isolation layer 11 that surrounds the main part of the VPNP in an annular shape, and + The buried layer 6 is N + The ion implantation conditions in this embodiment are as follows: antimony (Sb) is used as a donor, ion acceleration energy is 50 keV or more, and dose is 3.15×10 15 / cm 2 After that, in order to recover the crystal defects caused by the ion implantation, a heat treatment was carried out in a mixed atmosphere of oxygen and hydrogen at a temperature of 1100 to 1250°C for a total of about 5 hours (second heat treatment). + The buried layer 6 diffuses and spreads to a depth of about 7800 angstroms from the surface of the Si substrate 1. At the same time, N - The donors in the buried layer 4 also diffuse to a deeper position.

[0015] Next, the oxide film is completely removed, and the pad is oxidized. + A resist is formed with an opening corresponding to the region where the buried layer 7 is to be formed. In the VPNP area, P + The region where the buried layer 7 is to be formed is N + The area is set within the range surrounded by the buried layer 6. Then, acceptor ions are implanted through the pad oxide film (not shown), and P + A buried layer 7 is formed. Note that the P + The buried layer 7 becomes a buried collector layer, and in other areas it becomes part of the element isolation layer 23. The ion implantation conditions are as follows: boron (B) is used as an acceptor, the ion acceleration energy is 70 keV or more, and the dose is 3.5×10 14 ions / cm 2After that, in order to recover the crystal defects caused by the ion implantation, a heat treatment was carried out in a hydrogen atmosphere at a temperature of 1170°C or higher for about 40 minutes (third heat treatment). + The buried layer is diffused to a depth of about 2600 Å and contains N - Within the buried layer 4 and N + The buried layer 6 is formed at a position separated from the buried layer 6. - This results in further drive-in annealing of the buried layer 4, and the donors diffuse to deeper positions.

[0016] Next, all oxide films on the surface of the Si substrate 1 are removed by etching, and an N-type epitaxial layer 8 is formed by vapor phase growth. - Buried layer 4, N + Buried layer 6 and P + The buried layer 7 expands due to the upward diffusion of impurities. The above steps result in the state shown in Figure 1(d). This is followed by the steps of forming a P collector wall 9 and an N base layer 10, but since these are the same as in the conventional method, their explanations will be omitted.

[0017] Next, the entire surface of the epitaxial layer 8 is thermally oxidized to form an oxide film (not shown), and a resist having an opening corresponding to the region where the N separation layer 11 is to be formed is formed by photolithography. + The oxide film is then etched to expose the surface of the epitaxial layer 8. A pad oxide film (not shown) is formed on the exposed surface, and donor ions are implanted through the pad oxide film to form the N isolation layer 11. The ion implantation conditions are as follows: phosphorus (P) is used as the donor, the ion acceleration energy is 70 keV or more, and the dose is 3.9×10 15 ions / cm 2 The N separation layer 11 is made of N +This is a buried layer of a type, and will be connected to the bias electrode 19 that will be formed later. The N isolation layer 11 is formed in a roughly cylindrical shape so as to surround the parts (main parts) that are necessary for the functioning of the bipolar transistor, such as the emitter, base, and collector that make up the VPNP. At the same time that this N isolation layer 11 is formed in the VPNP area, a collector wall is also formed in the VNPN area. Subsequent processes are the same as conventional, and the semiconductor device shown in FIG. 1(e) is finally formed.

[0018] As described above, in the method for manufacturing a semiconductor device according to this embodiment, - A three-stage heat treatment is applied to the buried layer 4 to expand the diffusion layer. - A step of performing a first heat treatment in the step of forming the buried layer 4, N + A step of performing a second heat treatment in the process of forming the buried layer 6 and P + This is the step of performing the third heat treatment in the process of forming the buried layer 7. - The second and third heat treatments are annealing for the buried layer 4, and drive-in annealing for the same layer. - The second and third heat treatments are performed by diffusing the buried layer 4 to a deep position. + Buried layer 6 and P + Since the buried layer 7 is annealed, the heat treatment conditions should be sufficient to repair the crystal defects in these layers. - By adjusting the conditions of the first heat treatment for buried layer 4, the width of the diffusion in the depth direction that is finally obtained can be determined.

[0019] 2 shows the concentration profile of donors introduced into a VPNP semiconductor device, where the diamond plots represent the semiconductor device according to this embodiment and the square plots represent the conventional semiconductor device. - The width (Wn) of the buried layer 4 in the depth direction from the boundary with the epitaxial layer 8 is about 20.4 μm, and +The width (Wp) of buried layer 7 in the depth direction from the boundary with epitaxial layer 8 was approximately 13.1 μm. The diffusion width ratio (Wr) in the depth direction from the boundary with epitaxial layer 8 was calculated as follows: Wr=Wn / Wp In the case of this embodiment, Wr=1.55 based on the above formula. - In the case where no separate heat treatment was performed on the buried layer 4), Wr was about 1.4. - The buried layer 4 has a large width in the depth direction, and P + The ratio of the width in the depth direction of the buried layer 7 is also large.

[0020] Figure 3 shows the N - Buried layer 4 and P + 1 is a graph in which the horizontal axis represents the width ratio Wr of the buried layer 7 in the depth direction, and the vertical axis represents the EPI breakdown voltage. + Compared with the depth of the buried layer 7, - As the buried layer 4 becomes deeper, the EPI breakdown voltage increases. Plots of Wr ratios less than 1.50 represent the measurement results of conventional semiconductor devices, while plots of ratios equal to or greater than 1.50 represent the measurement results of the semiconductor device according to this embodiment. It can be seen that the above ratio is high in the semiconductor device according to this embodiment, and the EPI breakdown voltage also exceeds 50 V. In other words, the semiconductor device according to this embodiment has improved EPI breakdown voltage, making it possible to set a higher potential to be applied to the bias electrode, which prevents the operation of the parasitic transistor Q3 and thereby widens the operating voltage range of the circuit.

[0021] However, N - The wider the width in the depth direction of the buried layer 4, the lower the cutoff frequency of the VPNP, which causes a problem of slowing down the operating speed. Therefore, in order for the semiconductor device according to this embodiment to fully exhibit its withstand voltage effect, it is desirable that the ratio Wr of the widths in the depth direction of these two diffusion layers be in the range shown in the following formula. 1.5≦Wr≦1.7 Wr is a N - This can be determined by adjusting the conditions of the first heat treatment for the buried layer 4. For example, by increasing the acceleration energy or dose of ion implantation and extending the heat treatment time, the width in the depth direction can be increased. Conversely, by adjusting the heat treatment time, for example, the width in the depth direction can be reduced. It goes without saying that this adjustment can be made in various ways based on the knowledge of those skilled in the art.

[0022] Although the embodiments of the present invention have been described above, various modifications are possible within the spirit and scope of the invention. For example, in the above embodiment, ion implantation followed by heat treatment was used as a means for introducing dopants into the Si substrate 1. However, instead of this, coating diffusion can be used, in which a liquid containing impurities is applied to the substrate surface, dried, and then heat treatment is performed. It is also possible to use vapor phase diffusion, in which a source gas is used to adsorb dopants onto the substrate surface, followed by heat treatment. However, ion implantation allows for better control of the heating profile and can also improve throughput. In the above embodiment, N + The region where the buried layer 6 is to be formed is N - Since the buried layer 4 is set in a circular shape in a plan view, N + The buried layer 6 also has a similar shape. + Buried layer 6 is N - The buried layer 4 and the N isolation layer 11 surrounding the main part of the VPNP in a circular shape do not have to be connected in their entirety in a planar view, and only a portion of them may be connected. However, a circular shape in a planar view is desirable in order to suppress the operation of the parasitic transistor. [Explanation of symbols]

[0023] 1. Si substrate 2. Insulating film 3, 5 Pad oxide film 4 N - Buried layer (buried isolation layer) 6 N+ Embedding Layer 7 P + Buried layer (buried collector layer) 8 Epitaxial Layer 9 P Collector Wall 10 N-based layer 11 N separation layer 12 N base contact 13 P emitter layer 14 P collector contact layer 15 Interlayer insulating film 16 Aluminum wiring 17Si nitride film 18 Passivation 19 Bias electrode 20 Collector electrode 21 Emitter electrode 22 base electrode 23 Element isolation layer

Claims

1. preparing a Si semiconductor substrate having a P-type conductivity; performing a first heat treatment to introduce a first donor into the Si semiconductor substrate; － forming a buried isolation layer in the mold; The N － performing a second thermal treatment to introduce second donors into the region of the buried isolation layer of the type; ＋ forming a buried layer; The N － performing a third thermal treatment to introduce acceptors into the buried isolation layer of the N ＋ P at a position separated from the buried layer ＋ forming a buried collector layer of the mold; The N ＋ Connected to the buried layer, P ＋ forming an isolation layer surrounding the buried collector layer of the mold; The P ＋ forming a biasing electrode connected to the isolation layer surrounding the buried collector layer of the mold; The N － a width Wn of the buried isolation layer of the mold in the depth direction is adjusted by the first heat treatment.

2. The N － As a result of adjusting the width of the buried isolation layer of the mold in the depth direction by the first heat treatment, － the width Wn of the buried isolation layer in the depth direction of the mold, and ＋ The ratio Wr (Wr=Wn / Wp) of the width Wp of the buried collector layer in the depth direction of the mold is expressed by the following formula: 1.5≦Wr≦1.7 2. The method for manufacturing a semiconductor device according to claim 1, wherein the value satisfies the following.

3. A semiconductor device including a vertical PNP transistor having a bias electrode for fixing an EPI potential, a Si semiconductor substrate having a P-type conductivity; The N formed on the Si semiconductor substrate － a buried isolation layer of the mold; an N isolation layer connected to the bias electrode and surrounding a main portion of the vertical PNP transistor; The N － formed in a buried isolation layer of the N － The N-type buried isolation layer and the N-type isolation layer are connected to each other. ＋ an embedding layer; The N － In the buried isolation layer of the N － P formed apart from the buried isolation layer of the mold ＋ a buried collector layer of the semiconductor substrate; A semiconductor device, characterized in that operation of a parasitic transistor included in the vertical PNP transistor is suppressed by applying a voltage to the bias electrode.

4. The N － the width Wn of the buried isolation layer in the depth direction of the mold, and ＋ The ratio Wr (Wr=Wn / Wp) of the width Wp of the buried collector layer in the depth direction of the mold is expressed by the following formula: 1.5≦Wr≦1.7 4. The semiconductor device according to claim 3, wherein the value satisfies the following.

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