printed circuit board

Abstract

To provide a printed circuit board capable of effectively untwisting wiring and therefore minimizing an increase in the number of layers. [Solution] The present disclosure relates to a printed circuit board including a substrate body including a plurality of wiring layers and a plurality of via layers, the plurality of wiring layers including a pair of first wiring patterns arranged spaced apart from each other at substantially the same level based on the thickness direction, and a first rewiring unit including one or more first rewiring layers, the one or more first rewiring layers including a first rewiring pattern arranged at a different level from the pair of first wiring patterns based on the thickness direction, the first rewiring unit being built into the substrate body, and the first rewiring pattern connecting the pair of first wiring patterns to each other.

Description

[Technical Field]

[0001] The present disclosure relates to printed circuit boards. [Background technology]

[0002] Recently, the number of semiconductor chips mounted on package substrates has increased, resulting in an increase in the area of ​​the substrate. Furthermore, the number of wiring lines has also increased, resulting in an increase in the number of layers of the substrate. For example, as the number of wiring lines increases, twisting between the wiring lines may become more frequent. To resolve this twisting, the wiring lines may need to be separated into layers. This may increase the number of layers of the substrate. Furthermore, ground layers may need to be inserted between the separated wiring lines, resulting in an even greater increase in the number of layers. Furthermore, multilayer package substrates may be manufactured using a double-sided lamination method based on the core layer, which may increase the number of layers on the opposite side. However, this increase in the number of layers of the substrate may increase manufacturing time and costs and may also lead to a decrease in yield. Summary of the Invention [Problem to be solved by the invention]

[0003] Among various objects of the present disclosure, one is to provide a printed circuit board that can effectively untwist wires, thereby minimizing an increase in the number of layers. [Means for solving the problem]

[0004] One of the various solutions proposed through this disclosure is to integrate wiring separated into layers into one layer using a rewiring unit including a rewiring pattern.

[0005] For example, one example of a printed circuit board includes a substrate body including a plurality of wiring layers and a plurality of via layers, the plurality of wiring layers including a pair of first wiring patterns spaced apart from each other at substantially the same level in the thickness direction; and a first rewiring unit including one or more first rewiring layers, the one or more first rewiring layers including a first rewiring pattern arranged at a different level from the pair of first wiring patterns in the thickness direction, the first rewiring unit being built into the substrate body, and the first rewiring pattern connecting the pair of first wiring patterns to each other.

[0006] For example, a printed circuit board according to one example may include a pair of first wiring patterns spaced apart from each other on substantially the same layer, a pair of second wiring patterns spaced apart from each other on substantially the same layer, a first rewiring unit including a first rewiring pattern arranged on a different layer from the pair of first wiring patterns and connecting the pair of first wiring patterns to each other, and a second rewiring unit including a second rewiring pattern arranged on a different layer from the pair of second wiring patterns and connecting the pair of second wiring patterns to each other. [Effects of the Invention]

[0007] One of the various advantages of the present disclosure is that it provides a printed circuit board that can effectively untangle twisted wiring, thereby minimizing an increase in the number of layers. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating an example of an electronic device system. [Figure 2] FIG. 1 is a perspective view schematically illustrating an example of an electronic device. [Figure 3] FIG. 1 is a plan perspective view schematically illustrating an example of a printed circuit board. [Figure 4] 4 is a cross-sectional view of the printed circuit board of FIG. 3 taken along the general line II'. [Figure 5]4 is a cross-sectional view of the printed circuit board of FIG. 3 taken along the general line II-II'. [Figure 6] FIG. 1 is a cross-sectional view schematically illustrating an example of a rewiring unit. [Figure 7] FIG. 10 is a cross-sectional view schematically showing another example of a rewiring unit. [Figure 8] FIG. 10 is a cross-sectional view schematically showing another example of a printed circuit board. [Figure 9] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 10] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. [Figure 11] FIG. 10 is a cross-sectional view schematically illustrating yet another example of a printed circuit board. DETAILED DESCRIPTION OF THE INVENTION

[0009] The present disclosure will be described below with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be scaled (or highlighted or simplified) for clarity.

[0010] <Electronic equipment> FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0011] Referring to the drawing, an electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also coupled to other electronic components described below to form various signal lines 1090.

[0012] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Furthermore, these chip-related components 1020 can be combined with one another. The chip-related components 1020 can also be in the form of a package including the above-mentioned chips and electronic components.

[0013] The network-related components 1030 may include, but are not limited to, Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated as such, as well as any of numerous other wireless or wired standards and protocols. The network-related components 1030 may also be combined with the chip-related components 1020.

[0014] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, they are not limited to these and may also include passive elements in the form of chip components used for various other applications. In addition, the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0015] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. Other electronic components may also include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. In addition, other electronic components used for various purposes may also be included depending on the type of electronic device 1000.

[0016] The electronic device 1000 may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0017] FIG. 2 is a perspective view schematically illustrating an example of an electronic device.

[0018] Referring to the drawing, the electronic device may be, for example, a smartphone 1100. The smartphone 1100 houses a motherboard 1110, to which various components 1120 are physically and / or electrically connected. Furthermore, other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110, are housed inside the smartphone 1100. Some of the components 1120 may be the chip-related components described above, such as, but not limited to, a component package 1121. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are mounted on its surface. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active and / or passive components are embedded. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0019] <Printed circuit board> FIG. 3 is a planar perspective view schematically showing an example of a printed circuit board, FIG. 4 is a cross-sectional view taken along the schematic line I-I' of the printed circuit board of FIG. 3, and FIG. 5 is a cross-sectional view taken along the schematic line II-II' of the printed circuit board of FIG. 3.

[0020] Referring to the drawings, a printed circuit board 500A according to an example embodiment may include substrate bodies 110, 120, and 130 each including an insulating layer 110, a wiring layer 120, and a via layer 130, and a redistribution unit 200A embedded in the substrate bodies 110, 120, and 130 and including a dielectric layer 210 and a redistribution layer 220. The wiring layer 120 may include a pair of first wiring patterns L1-1 and L1-2 spaced apart from each other on substantially the same layer, e.g., substantially the same level in the thickness direction. The redistribution layer 220 may include a first redistribution pattern R1 located on a different layer, e.g., a different level in the thickness direction, from the pair of first wiring patterns L1-1 and L1-2. The via layer 130 may include a pair of first connection vias v1-1 and v1-2. The first redistribution pattern R1 may be connected to the pair of first wiring patterns L1-1 and L1-2 via the pair of first connection vias v1-1 and v1-2, respectively. Therefore, the pair of first wiring patterns L1-1 and L1-2 can be connected via the first rewiring pattern R1.

[0021] In this manner, the printed circuit board 500A may include a rewiring unit 200A including a first rewiring pattern R1 that electrically connects the pair of first wiring patterns L1-1 and L1-2 to each other. Therefore, the pair of first wiring patterns L1-1 and L1-2, which may require layer separation, can be formed on substantially the same layer without layer separation. This effectively untangles the wiring and minimizes the number of layers. This reduces the time and cost required to manufacture the board and minimizes yield reductions.

[0022] Meanwhile, the wiring layer 120 may further include a pair of second wiring patterns L2-1 and L2-2 spaced apart from each other in substantially the same layer, e.g., at substantially the same level in the thickness direction. The pair of first wiring patterns L1-1 and L1-2 and the pair of second wiring patterns L2-1 and L2-2 may be arranged in substantially the same layer, e.g., at substantially the same level in the thickness direction. The redistribution layer 220 may further include a second redistribution pattern R2 arranged in a different layer, e.g., at a different level in the thickness direction, from the pair of second wiring patterns L2-1 and L2-2. The first redistribution pattern R1 and the second redistribution pattern R2 may be arranged in substantially the same layer, e.g., at substantially the same level in the thickness direction, but are not limited thereto and may also be arranged at different levels. The via layer 130 may further include a pair of second connection vias v2-1 and v2-2. The second rewiring pattern R2 may be connected to the pair of second wiring patterns L2-1 and L2-2 through a pair of second connection vias v2-1 and v2-2, respectively, so that the pair of second wiring patterns L2-1 and L2-2 may be connected to each other through the second rewiring pattern R2.

[0023] In this way, in the printed circuit board 500A, a pair of first wiring patterns L1-1, L1-2 and a pair of second wiring patterns L2-1, L2-2, which may require layer separation, can be arranged on substantially the same layer, and their twists can be effectively resolved via the first rewiring pattern R1 and the second rewiring pattern R2. This allows for more effective untangling of the wiring, further minimizing an increase in the number of layers. This further reduces the time and cost required to manufacture the board, and further minimizes a reduction in yield.

[0024] Meanwhile, when the substrate bodies 110, 120, and 130 and the rewiring unit 200A are viewed from above, the second rewiring pattern R2 may overlap at least one of the pair of first wiring patterns L1-1 and L1-2. This arrangement allows for more effective untwisting of the wiring and further minimizes an increase in the number of layers. This further reduces the time and cost required to manufacture the substrate and further minimizes a decrease in yield.

[0025] The components of the printed circuit board 500A will be described in more detail below with reference to the drawings.

[0026] The insulating layer 110 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin and / or a thermoplastic resin such as a polyimide. Alternatively, the insulating material may include inorganic fillers, organic fillers, and / or glass fibers (glass fiber, glass cloth, glass fabric) in addition to these resins. For example, the insulating material may be, but is not limited to, copper clad laminate (CCL), prepreg (PPG), Ajinomoto build-up film (ABF), photo imageable dielectric (PID), solder resist (SR), etc. The insulating layer 110 may be composed of multiple layers, which may contain the same insulating material or different insulating materials. The insulating layers 110 may have distinct boundaries, or may be integrated as needed, so that the boundaries between them are unclear.

[0027] The wiring layer 120 may include a metal. Examples of the metal include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the wiring layer 120 may include, but is not limited to, copper (Cu). The wiring layer 120 may perform various functions depending on the design. For example, it may include a signal pattern, a power pattern, a ground pattern, etc. These patterns may each have various forms, such as a line, a plane, or a pad. The wiring layer 120 may include a seed layer and a plating layer. The seed layer may be formed by electroless plating such as chemical copper, or may be formed by a sputtering process as needed. Alternatively, both may be used. The plating layer may be formed by electrolytic plating such as electrolytic copper. If necessary, the wiring layer 120 may further include a copper foil in addition to the seed layer and plating layer. The wiring layer 120 may be composed of multiple layers. The multiple wiring layers 120 can be disposed on or within the multiple insulating layers 110, respectively.

[0028] The via layer 130 may include a metal. Examples of the metal include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but is not limited to this. The via layer 130 may include a plurality of connection vias. Each of the connection vias may perform various functions depending on the design. For example, they may include signal vias, power vias, and ground vias. Each of the connection vias may include filled vias, in which a via hole is filled with metal, or conformal vias, in which metal is disposed along the wall surface of a via hole. They may also include through vias of various shapes. Each of the connection vias may have a vertical shape, a tapered shape, and / or an hourglass shape in cross section. The via layer 130 may include a seed layer and a plating layer. The seed layer can be formed by electroless plating such as chemical copper, or by a sputtering process if necessary. Alternatively, both methods can be used. The plating layer can be formed by electrolytic plating such as electrolytic copper. The via layer 130 can be composed of multiple layers. The multiple via layers 130 can be disposed within the multiple insulating layers 110, respectively.

[0029] The redistribution unit 200A may be a sub-substrate embedded in the substrate body 110, 120, or 130. The redistribution unit 200A may include, but is not limited to, an organic bridge structure in terms of ease of manufacturing, cost reduction, ease of embedding, and yield. The redistribution unit 200A may also include a silicon bridge substrate structure, if necessary. The redistribution unit 200A may include a dielectric layer 210 and a redistribution layer 220 disposed on or within the dielectric layer 210. A redistribution via layer may be disposed within the dielectric layer 210, if necessary. The redistribution unit 200A may be attached to at least one of the plurality of insulating layers 110 via an adhesive film such as a Die Attach Film (DAF) and may be embedded in at least one other of the plurality of insulating layers 110. The redistribution unit 200A may have a single-layer structure (see FIG. 6: 200-1) or a multi-layer structure (see FIG. 7: 200-2). The components included in the redistribution unit 200A will be described in more detail below.

[0030] FIG. 6 is a cross-sectional view schematically showing an example of a rewiring unit.

[0031] Referring to the drawing, a redistribution unit 200-1 according to an example may have a single-layer structure including a dielectric layer 210 and a redistribution layer 220 disposed on the dielectric layer 210. An adhesive film 250 may be attached to the lower surface of the dielectric layer 210. For example, when the twist of the pair of first wiring patterns and the pair of second wiring patterns is relatively simple or as otherwise required, a first redistribution pattern for untwisting the pair of first wiring patterns and a second redistribution pattern for untwisting the pair of second wiring patterns may be disposed spaced apart from each other at substantially the same level in the thickness direction. For example, the first redistribution pattern and the second redistribution pattern may all be formed in one redistribution layer 220.

[0032] The dielectric layer 210 may include an organic insulating material or an inorganic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin and / or a thermoplastic resin such as a polyimide. Alternatively, it may include an inorganic filler together with these resins. For example, the organic insulating material may be, but is not limited to, an Ajinomoto Build-up Film (ABF) or a Photo Imageable Dielectric (PID), which are build-up materials for the substrate. The inorganic insulating material may be, but is not limited to, silicon (Si), and may include, for example, silicon oxide or silicon nitride.

[0033] The redistribution layer 220 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the redistribution layer 220 may include, but is not limited to, copper (Cu). The redistribution layer 220 may perform various functions depending on the design. For example, it may include a signal pattern, a power pattern, a ground pattern, etc. These patterns may each have various forms, such as a line, a plane, or a pad. The redistribution layer 220 may include a seed layer and a plating layer. The seed layer may be formed by electroless plating or, if necessary, by a sputtering process. Alternatively, both may be used. The plating layer may be formed by electrolytic plating, but is not limited thereto, and may be formed by electroless plating and / or a sputtering process.

[0034] The adhesive film 250 may include various insulating materials having adhesive properties. For example, it may include, but is not limited to, epoxy resin, polyimide, silicone resin, etc. Metal particles such as copper (Cu) or silver (Ag) may be added to the adhesive film 250, but it is not limited to this. The adhesive film 250 may be, but is not limited to, a Die Attach Film (DAF).

[0035] FIG. 7 is a cross-sectional view schematically showing another example of the rewiring unit.

[0036] Referring to the drawing, a redistribution unit 200-2 according to another example may have a multilayer structure including a plurality of dielectric layers 210, a plurality of redistribution layers 220 disposed on or within the plurality of dielectric layers 210, and a plurality of redistribution via layers 230 disposed within the plurality of dielectric layers 210 to connect the plurality of redistribution layers 220 to one another. An adhesive film 250 may be attached to a lower surface of the lowest dielectric layer 210 among the plurality of dielectric layers 210. For example, if the twist of the pair of first wiring patterns and the pair of second wiring patterns is somewhat complicated or as otherwise required, a first redistribution pattern for untwisting the pair of first wiring patterns and a second redistribution pattern for untwisting the pair of second wiring patterns may be disposed at different levels in the thickness direction. For example, the first redistribution pattern and the second redistribution pattern may be formed in different redistribution layers 220.

[0037] Each of the plurality of dielectric layers 210 may include an organic insulating material or an inorganic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin and / or a thermoplastic resin such as a polyimide. Alternatively, an inorganic filler may be added to these resins. For example, the organic insulating material may be, but is not limited to, an Ajinomoto Build-up Film (ABF) or a photo imageable dielectric (PID), which are build-up materials for the substrate. The inorganic insulating material may be, but is not limited to, silicon (Si), for example, silicon oxide or silicon nitride. The plurality of dielectric layers 210 may include, but is not limited to, the same insulating material. The plurality of dielectric layers 210 may have distinct boundaries, but are not limited to this, and may be integrated with each other so that the boundaries are unclear.

[0038] Each of the redistribution layers 220 may include a metal. The metal may include, but is not limited to, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the redistribution layers 220 may include, but are not limited to, copper (Cu). Each of the redistribution layers 220 may perform various functions depending on the design. For example, they may include signal patterns, power patterns, and ground patterns. These patterns may each have various forms, such as lines, planes, and pads. Each of the redistribution layers 220 may include a seed layer and a plating layer. The seed layer may be formed by electroless plating, or, if necessary, by a sputtering process. Alternatively, both may be used. The plating layer may be formed by electrolytic plating, but is not limited thereto, and may also be formed by electroless plating and / or a sputtering process. The multiple rewiring layers 220 may have a structure in which rewiring layers 220 including rewiring patterns R and rewiring layers including ground patterns G are alternately stacked, in which case electromagnetic interference can be effectively prevented.

[0039] The uppermost redistribution layer 220 among the plurality of redistribution layers 220 may include a plurality of connection pads P and a ground pattern G disposed between the plurality of connection pads P. The plurality of connection pads P may include a pair of first connection pads respectively coupled to the pair of first wiring patterns and a pair of second connection pads respectively coupled to the pair of second wiring patterns. The uppermost redistribution layer 220 may be thicker than each of the remaining redistribution layers 220, and therefore, it may be easier to connect the pair of first connection vias to the pair of first connection pads and the pair of second connection vias to the pair of second connection pads.

[0040] Each of the redistribution via layers 230 may include a metal. The metal may include, but is not limited to, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal may include, but is not limited to, copper (Cu). Each of the redistribution via layers 230 may include one or more connection vias. The one or more connection vias may perform various functions depending on the design. For example, they may include signal vias, power vias, ground vias, etc. Each of the one or more connection vias may include a filled via in which a via hole is filled with metal, or a conformal via in which metal is disposed along the wall of a via hole. The one or more connection vias included in each of the redistribution via layers 230 may be arranged in the form of a stacked via. Each of the one or more connection vias may penetrate one of the dielectric layers 210, or may penetrate multiple dielectric layers 210 at once if necessary. Each of the one or more connection vias may have a vertical cross-section and / or a tapered cross-section. Each of the multiple redistribution via layers 230 may include a seed layer and a plating layer. The seed layer may be formed by electroless plating, or may be formed by a sputtering process if necessary. Alternatively, both may be used. The plating layer may be formed by electrolytic plating, but is not limited thereto, and may also be formed by electroless plating and / or a sputtering process.

[0041] The adhesive film 250 may include various insulating materials having adhesive properties. For example, it may include, but is not limited to, epoxy resin, polyimide, silicone resin, etc. Metal particles such as copper (Cu) or silver (Ag) may be added to the adhesive film 250, but it is not limited to this. The adhesive film 250 may be, but is not limited to, a Die Attach Film (DAF).

[0042] FIG. 8 is a cross-sectional view schematically showing another example of a printed circuit board.

[0043] Referring to the drawings, a printed circuit board 500B according to another example may include a plurality of insulating layers 110, a plurality of wiring layers 120, and a plurality of via layers 130 as a substrate body 110, 120, 130, and a redistribution unit 200B may be embedded therein. The substrate bodies 110, 120, 130 may be at least a part of a multilayer package substrate structure. For example, the multilayer package substrate may have a double-sided buildup structure based on a core layer, and the substrate bodies 110, 120, 130 shown in the drawings may represent only a portion thereof. Alternatively, the multilayer package substrate may have a coreless multilayer structure built up without a core layer, and the substrate bodies 110, 120, 130 shown in the drawings may represent only a portion thereof. However, the present invention is not limited thereto, and the substrate bodies 110, 120, 130 may be at least a part of another interposer substrate structure in addition to the multilayer package substrate structure.

[0044] A passivation layer 115 having openings exposing at least a portion of the uppermost wiring layer 120 among the plurality of wiring layers 120 may be disposed on the uppermost insulating layer 110 among the plurality of insulating layers 110, and a semiconductor chip 310 may be disposed on the passivation layer 115. The semiconductor chip 310 may include a plurality of bumps B1 including a conductive material. A plurality of electrical connection metals 150 including a solder material may be disposed in the plurality of openings of the passivation layer 115, and the plurality of bumps B1 may be connected to the plurality of electrical connection metals 150, respectively. In this way, the semiconductor chip 310 may be mounted on the passivation layer 115.

[0045] The multiple wiring layers 120 may include a ground pattern G, and the redistribution unit 200B may be attached to the ground pattern G via an adhesive film 250. The redistribution unit 200B may have a single-layer structure (see FIG. 6: 200-1) or a multi-layer structure (see FIG. 7: 200-2) as described above. For example, the redistribution unit 200B may include one or more dielectric layers 210, one or more redistribution layers 220, and one or more redistribution via layers 230. The redistribution unit 200B may provide redistribution of lines or paths that transmit specific electrical signals or power within the substrate body 110, 120, or 130. For example, the redistribution unit 200B may enable connection between the semiconductor chip 310 and the multiple wiring layers 120, and may also enable net redistribution (NR) in a package structure. For example, the redistribution unit 200B may not be used for inter-die connection. Therefore, only one semiconductor chip 310 may be mounted on the passivation layer 115. However, the present invention is not limited to this. When multiple semiconductor chips are mounted, the redistribution unit 200B can provide inter-die connections.

[0046] At least one connection via v included in the plurality of via layers 130 may connect one or more redistribution layers 220 to the plurality of wiring layers 120. Another at least one connection via V included in the plurality of via layers 130 may penetrate the redistribution unit 200B and the adhesive film 250. This other at least one connection via V may be, but is not limited to, a connection via for signal connection between the plurality of wiring layers 120.

[0047] The rest of the description is substantially the same as that given with reference to FIGS. 3 to 7, and therefore, a duplicated description thereof will be omitted.

[0048] FIG. 9 is a cross-sectional view schematically showing still another example of a printed circuit board.

[0049] Referring to the drawings, printed circuit board 500C according to another example may include substrate bodies 110, 120, and 130 that are larger than printed circuit board 500B according to the other example described above, but may include a greater number of insulating layers 110, wiring layers 120, and via layers 130, and may include a plurality of redistribution units 200C-1 and 200C-2, respectively, built into substrate bodies 110, 120, and 130. Each of redistribution units 200C-1 and 200C-2 may include the above-described single-layer structure (see FIG. 6: 200-1) or multi-layer structure (see FIG. 7: 200-2). For example, the plurality of redistribution units 200C-1, 200C-2 may include a first redistribution unit 200C-1 including one or more first dielectric layers 211, one or more first redistribution layers 221, and one or more first redistribution via layers 231, and a second redistribution unit 200C-2 including one or more second dielectric layers 212, one or more second redistribution layers 222, and one or more second redistribution via layers 232. The first and second redistribution units 200C-1, 200C-2 may be attached to and embedded in the substrate bodies 110, 120, 130 via first and second adhesive films 251, 252, respectively.

[0050] The first redistribution unit and the second redistribution unit 200C-1, 200C-2 may be embedded in the substrate bodies 110, 120, 130 at different levels in the thickness direction. The plurality of wiring layers 120 may include a pair of third wiring patterns spaced apart from each other at substantially the same level in the thickness direction, and a pair of fourth wiring patterns spaced apart from each other at the same level in the thickness direction. The pair of third wiring patterns and the pair of fourth wiring patterns may be arranged at different levels in the thickness direction. The one or more first redistribution layers 221 may include a third redistribution pattern connected to a pair of third connection vias v1 included in the plurality of via layers 130 to electrically connect the pair of third wiring patterns. The one or more second redistribution layers 222 may include a fourth redistribution pattern connected to a pair of fourth connection vias v2 included in the plurality of via layers 130 to electrically connect the pair of fourth wiring patterns. The pair of third wiring patterns and third rewiring patterns may be arranged at different levels in the thickness direction, and the pair of fourth wiring patterns and fourth rewiring patterns may be arranged at different levels in the thickness direction.

[0051] The first and second redistribution units 200C-1 and 200C-2 may be bridge units for rewiring a line or path that transmits a specific electrical signal or power within the substrate bodies 110, 120, and 130, respectively. For example, the first and second redistribution units 200C-1 and 200C-2 may enable connection between the semiconductor chip 310 and multiple wiring layers 120, and may also enable net redistribution (NR) in a package structure. For example, the first and second redistribution units 200C-1 and 200C-2 may not be used for inter-die connection. Therefore, only one semiconductor chip 310 may be mounted on the passivation layer 115. However, this is not limited thereto. When multiple semiconductor chips are mounted, the first and / or second redistribution units 200C-1 and 200C-2 may also function as bridge units for inter-die connection.

[0052] The plurality of wiring layers 120 may include a ground pattern G, and at least one other connection via V included in the plurality of via layers 130 may be connected to the ground pattern G by penetrating the second redistribution unit 200C-2 and the second adhesive film 252. If necessary, the at least one other connection via V may also penetrate a ground pattern included in one or more second redistribution layers 222. Such at least one other connection via V may be, but is not limited to, a connection via for ground connection between the plurality of wiring layers 120 and / or between the plurality of wiring layers 120 and one or more redistribution layers 222.

[0053] The rest of the description is substantially the same as that given with reference to FIGS. 3 to 8, and therefore, a duplicated description thereof will be omitted.

[0054] FIG. 10 is a cross-sectional view schematically showing still another example of a printed circuit board.

[0055] Referring to the drawings, a printed circuit board 500D according to another example may include a plurality of insulating layers 111, 112, a plurality of wiring layers 121, 122, and a plurality of via layers 131, 132 as substrate bodies 111, 112, 121, 122, 131, 132, and a plurality of redistribution units 200D-1, 200D-2 may be embedded therein, respectively. The substrate bodies 111, 112, 121, 122, 131, 132 may be at least a part of a multilayer package substrate structure. For example, the multilayer package substrate may have a double-sided build-up structure based on a core layer, and the substrate bodies 111, 112, 121, 122, 131, 132 shown in the drawings may only represent a part thereof. However, the present invention is not limited to this, and the substrate bodies 111, 112, 121, 122, 131, and 132 may be at least a part of another interposer substrate structure in addition to the multilayer package substrate structure.

[0056] The multiple insulating layers 111, 112 may include multiple first insulating layers 111 and multiple second insulating layers 112, and each of the first insulating layers 111 may have a thickness thinner than each of the second insulating layers 112. The multiple wiring layers 121, 122 may include multiple first wiring layers 121 and multiple second wiring layers 122, and each of the first wiring layers 121 may have a smaller average pitch than each of the second wiring layers 122. The multiple via layers 131, 132 may include multiple first via layers 131 and multiple second via layers 132, and each of the first via layers 131 may have a smaller average diameter than each of the second via layers 132. For example, the substrate bodies 111, 112, 121, 122, 131, 132 may have a 2.nD package substrate structure. In addition, the contents described above for the plurality of insulating layers 110, the plurality of wiring layers 120, and the plurality of via layers 130 can be applied substantially similarly to the plurality of insulating layers 111, 112, the plurality of wiring layers 121, 122, and the plurality of via layers 131, 132, respectively.

[0057] A plurality of semiconductor chips 320, 330 may be mounted on the uppermost first insulating layer 111 among the plurality of first insulating layers 111. The plurality of semiconductor chips 320, 330 may be the same or different types of chips, for example, but not limited to, ASICs (Application-Specific Integrated Circuits) and HBMs (High Bandwidth Memory). The plurality of semiconductor chips 320, 330 may be connected to at least a portion of the uppermost first wiring layer 121 among the plurality of first wiring layers 121 via a plurality of bumps B2, B3 and a plurality of electrical connecting metals 152, 153. The plurality of bumps B2, B3 may each include a conductive material, and the plurality of electrical connecting metals 152, 153 may each include, but are not limited to, a solder material.

[0058] The plurality of redistribution units 200D-1, 200D-2 may each have a single-layer structure (see FIG. 6: 200-1) or a multi-layer structure (see FIG. 7: 200-2) as described above. For example, the plurality of redistribution units 200D-1, 200D-2 may include a third redistribution unit 200D-1 including one or more third dielectric layers 213, one or more third redistribution layers 223, and one or more third redistribution via layers 233, and a fourth redistribution unit 200D-2 including one or more fourth dielectric layers 214, one or more fourth redistribution layers 224, and one or more fourth redistribution via layers 234. The third and fourth redistribution units 200D-1, 200D-2 may be attached to and embedded in the substrate bodies 111, 112, 121, 122, 131, 132 via third and fourth adhesive films 253, 254, respectively.

[0059] The third redistribution unit and the fourth redistribution unit 200D-1, 200D-2 may be embedded in the substrate bodies 111, 112, 121, 122, 131, 132 at substantially the same level in the thickness direction. The second wiring layers 122 may include a pair of fifth wiring patterns spaced apart from each other at substantially the same level in the thickness direction, and a pair of sixth wiring patterns spaced apart from each other at the same level in the thickness direction. The pair of fifth wiring patterns and the pair of sixth wiring patterns may be arranged at substantially the same level in the thickness direction. The one or more third redistribution layers 223 may include a fifth redistribution pattern connected to a pair of fifth connection vias v3 included in the plurality of second via layers 132 to electrically connect the pair of fifth wiring patterns. The one or more fourth redistribution layers 224 may include a sixth redistribution pattern connected to a pair of sixth connection vias v4 included in the plurality of second via layers 132 to electrically connect the pair of sixth wiring patterns. The pair of fifth wiring pattern and fifth rewiring pattern may be arranged at different levels in the thickness direction, and the pair of sixth wiring pattern and sixth rewiring pattern may be arranged at different levels in the thickness direction.

[0060] Redistribution and / or inter-die connection may be performed through the third redistribution unit and the fourth redistribution units 200D-1 and 200D-2. For example, the third redistribution unit 200D-1 may provide redistribution of lines or paths that transmit specific electrical signals or power within the substrate bodies 111, 112, 121, 122, 131, and 132. For example, the third redistribution unit 200D-1 may enable connection between the first semiconductor chip 320 and the plurality of wiring layers 121 and 122, and may also enable Net Redistribution (NR) in a package structure. The fourth redistribution unit 200D-2 may provide lines or paths that transmit specific electrical signals or power between the plurality of semiconductor chips 320 and 330. For example, Die-to-Die (DtD) connection may be performed through the fourth redistribution unit 200D-2.

[0061] The rest of the description is substantially the same as that given with reference to FIGS. 3 to 9, and therefore, a duplicated description thereof will be omitted.

[0062] FIG. 11 is a cross-sectional view schematically showing still another example of a printed circuit board.

[0063] Referring to the drawings, a printed circuit board 500E according to another example may include a single redistribution unit 200E instead of the multiple redistribution units 200D-1 and 200D-2 in the substrate bodies 111, 112, 121, 122, 131, and 132 of the printed circuit board 500B according to the other example. The redistribution unit 200E may have a single-layer structure (see FIG. 6: 200-1) or a multi-layer structure (see FIG. 7: 200-2) as described above. For example, the redistribution unit 200E may include a fifth redistribution unit 200E including one or more fifth redistribution layers 225 and one or more fifth redistribution via layers 235. The fifth redistribution unit 200E may be attached to and embedded in the substrate bodies 111, 112, 121, 122, 131, and 132 via a fifth adhesive film 255. The one or more fifth redistribution layers 225 may include at least one redistribution pattern that untwists at least one pair of wiring patterns included in the plurality of wiring layers 121 and 122. The at least one redistribution pattern may be connected to at least one pair of wiring patterns included in the plurality of wiring layers 121 and 122 through at least one pair of connection vias v5 included in the plurality of via layers 131 and 132, respectively.

[0064] Both redistribution and inter-die connection can be performed through the fifth redistribution unit 200E. For example, the fifth redistribution unit 200E can provide redistribution of lines or paths that transmit specific electrical signals or power within the substrate bodies 111, 112, 121, 122, 131, and 132. For example, the fifth redistribution unit 200E can provide connection between the first semiconductor chip 320 and the multiple wiring layers 121 and 122, and can also perform net redistribution (NR) in a package structure. The fifth redistribution unit 200E can also provide lines or paths that transmit specific electrical signals or power between the multiple semiconductor chips 320 and 330. For example, die-to-die (DtD) connection can also be performed through the fifth redistribution unit 200E.

[0065] The rest of the description is substantially the same as that given with reference to FIGS. 3 to 10, and therefore, a duplicated description thereof will be omitted.

[0066] In the present disclosure, thickness, width, length, pitch, depth, etc. can be measured using a scanning microscope or optical microscope based on a cross section obtained by polishing or cutting a printed circuit board. The cut section can be a vertical or horizontal section, and each value can be measured based on the required cut section. If the value is not constant, it can be determined as the average value of values ​​measured at any five points. The width of the upper and / or lower ends of a via can be measured on a cross section obtained by cutting the board thicknesswise along the central axis of the via. The depth of a via can be measured as the distance from the upper end to the lower end of a via on a cross section obtained by cutting the board thicknesswise along the central axis of the via.

[0067] In the present disclosure, the term "cover" may include not only completely covering but also at least partially covering, and may include not only directly covering but also indirectly covering. Furthermore, the term "fill" may include not only completely filling but also roughly filling, and may include the case where there are some gaps or voids, for example.

[0068] In the present disclosure, "substantially" can be determined to include process errors, positional deviations, measurement errors, etc. that occur during the manufacturing process. For example, "being arranged in substantially the same layer or substantially the same level" can include "being arranged in roughly the same layer" or "being arranged in roughly the same level." Furthermore, "having substantially a certain shape" can include not only cases where the shape is completely the same, but also cases where the shape is roughly the same.

[0069] In the present disclosure, the same insulating material may refer not only to the completely same insulating material but also to the same type of insulating material, and therefore, the compositions of the insulating materials are substantially the same, but the specific composition ratios thereof may vary slightly.

[0070] In the present disclosure, the term "cross section" can refer to the cross-sectional shape of an object cut vertically or the cross-sectional shape of an object when viewed from the side, and the term "planar" can refer to the planar shape of an object cut horizontally or the planar shape of an object when viewed from the top or bottom.

[0071] In this disclosure, for convenience, terms such as bottom, lower part, and bottom surface are used to refer to the downward direction based on the cross section of the drawing, and terms such as top, upper part, and top surface are used to refer to the opposite direction. Also, terms such as side and lateral surface are used to refer to a direction perpendicular to the top and bottom surfaces. However, these are definitions of directions for convenience of explanation, and the scope of the claims is not particularly limited by the description of these directions, and the concepts of top and bottom may change at any time.

[0072] In this disclosure, the term "connected" encompasses not only direct connection but also indirect connection via an adhesive layer, etc. Furthermore, the term "electrically connected" encompasses both physical connection and non-physical connection. Furthermore, terms such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0073] The term "one example" used in this disclosure does not mean the same embodiment as the other examples, but is provided to emphasize and describe the unique features that are different from each other. However, the above-described one example does not exclude being realized in combination with the features of another example. For example, even if a matter described in a particular example is not described in another example, it can be understood as being related to the other example unless there is a contrary or contradictory description with that matter in the other example.

[0074] The terms used in this disclosure are merely used to describe an example and are not intended to limit the disclosure. In this case, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0075] 1000 electronic equipment 1010 mainboard 1020 Chip related parts 1030 Network related parts 1040 Other parts 1050 camera 1060 Antenna 1070 display 1080 battery 1090 signal line 1100 smartphones 1110 motherboard 1120 parts 1121 Parts Package 1130 Camera Module 1140 Speaker 500A, 500B, 500C, 500D, 500E Printed Circuit Boards 110, 111, 112 insulating layers 115 Passivation Layer 120, 121, 122 wiring layer 130, 131, 132 via layers 200-1, 200-2, 200A, 200B, 200C-1, 200C-2, 200D-1, 200D-2, 200E Rewiring Unit 210, 211, 212, 213, 214, 215 Dielectric layers 220, 221, 222, 223, 224, 225 redistribution layer 230, 231, 232, 233, 234, 235 Redistribution via layer 250, 251, 252, 253, 254, 255 Adhesive Film 310, 320, 330 semiconductor chips B1, B2, B3 bumps 150, 152, 153 Electrically interconnected metals

Claims

1. a substrate body including a plurality of wiring layers and a plurality of via layers, the plurality of wiring layers including a pair of first wiring patterns spaced apart from each other at substantially the same level in a thickness direction; a first redistribution unit including one or more first redistribution layers, the one or more first redistribution layers including first redistribution patterns disposed at a different level from the pair of first wiring patterns in a thickness direction; the first rewiring unit is built into the substrate body, The first rewiring pattern connects the pair of first wiring patterns to each other.

2. The printed circuit board of claim 1 , wherein the plurality of via layers include a pair of first connection vias that respectively connect the first rewiring pattern to the pair of first wiring patterns.

3. The plurality of wiring layers further include a pair of second wiring patterns disposed at substantially the same level and spaced apart from each other in a thickness direction, the at least one first redistribution layer further includes a second redistribution pattern disposed at a different level from the pair of second redistribution patterns in a thickness direction, The printed circuit board of claim 1 , wherein the second rewiring pattern connects the pair of second wiring patterns to each other.

4. The printed circuit board of claim 3 , wherein the plurality of via layers include a pair of second connection vias that respectively connect the second rewiring pattern to the pair of second wiring patterns.

5. the pair of first wiring patterns and the pair of second wiring patterns are disposed at substantially the same level with respect to the thickness direction; The printed circuit board according to claim 3 , wherein when the substrate body and the first rewiring unit are seen through from above, the second rewiring pattern overlaps with at least one of the pair of first wiring patterns.

6. The printed circuit board according to claim 3 , wherein the first rewiring pattern and the second rewiring pattern are spaced apart from each other at substantially the same level in a thickness direction.

7. The printed circuit board according to claim 3 , wherein the first rewiring pattern and the second rewiring pattern are disposed at different levels in a thickness direction.

8. further including a second redistribution unit including one or more second redistribution layers; the plurality of wiring layers further include a pair of third wiring patterns disposed at substantially the same level and spaced apart from each other in a thickness direction; the at least one second redistribution layer further includes a third redistribution pattern disposed at a different level from the pair of third redistribution patterns in a thickness direction, The printed circuit board of claim 1 , wherein the third rewiring pattern connects the pair of third wiring patterns to each other.

9. The printed circuit board of claim 8 , wherein the plurality of via layers include a pair of third connection vias that respectively connect the third rewiring pattern to the pair of third wiring patterns.

10. the pair of third wiring patterns are disposed at a different level from the pair of first wiring patterns with respect to the thickness direction; The printed circuit board according to claim 8 , wherein the second rewiring unit is embedded in the board body at a different level in the thickness direction from the first rewiring unit.

11. the pair of third wiring patterns are disposed at substantially the same level as the pair of first wiring patterns in the thickness direction; The printed circuit board according to claim 8 , wherein the second redistribution unit is embedded in the board body at substantially the same level as the first redistribution unit in the thickness direction.

12. the plurality of wiring layers include a ground pattern, The printed circuit board according to claim 1 , wherein the first rewiring unit is attached to the ground pattern via an adhesive film.

13. The printed circuit board of claim 12 , wherein the plurality of via layers include a ground connection via that penetrates the first redistribution unit and the adhesive film and is connected to the ground pattern.

14. the one or more first redistribution layers are a plurality of first redistribution layers; The printed circuit board of claim 12 , wherein the first redistribution unit includes the plurality of first redistribution layers and a plurality of first redistribution via layers connecting the plurality of first redistribution layers to each other.

15. The printed circuit board of claim 14 , wherein the plurality of first redistribution layers include a structure in which first redistribution layers including redistribution patterns and first redistribution layers including ground patterns are alternately stacked.

16. a first redistribution layer disposed at an uppermost position among the plurality of first redistribution layers includes a pair of first connection pads respectively connected to the pair of first wiring patterns; The printed circuit board of claim 14 , wherein the uppermost first redistribution layer is thicker than each of the remaining first redistribution layers.

17. a pair of first wiring patterns disposed spaced apart from each other on substantially the same layer; a pair of second wiring patterns disposed spaced apart from each other on substantially the same layer; a first rewiring unit including a first rewiring pattern disposed in a layer different from the pair of first wiring patterns and connecting the pair of first wiring patterns to each other; a second rewiring unit including a second rewiring pattern disposed on a layer different from the pair of second wiring patterns and connecting the pair of second wiring patterns to each other.

18. the printed circuit board has a multilayer wiring board structure including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers; the plurality of wiring layers include the first wiring pattern and the second wiring pattern, 18. The printed circuit board of claim 17, wherein the first redistribution unit and the second redistribution unit are embedded in the insulating layers at substantially the same level in the thickness direction, or at different levels in the thickness direction.

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