Electro-optical devices and electronic equipment

Abstract

An electro-optical device and electronic equipment are provided that can improve the light blocking properties against light incident on a semiconductor layer. [Solution] The electro-optical device comprises a substrate, a pixel electrode, a transistor arranged between the substrate and the pixel electrode, the transistor comprising a semiconductor layer having a source region, a drain region, and a channel region, and a gate electrode, and a first light-shielding portion arranged between the semiconductor layer and the pixel electrode, wherein the first light-shielding portion has a drain connection portion connected to the drain region, the semiconductor layer has a boundary portion between the channel region and the drain region, the drain region has a contact portion in contact with the first light-shielding portion and overlapping with the first light-shielding portion in a planar view, and a first distance between the contact portion and the substrate is shorter than a second distance between the boundary portion and the substrate.

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] 2. Description of the Related Art Electronic devices such as projectors use electro-optical devices such as liquid crystal display devices that can change optical characteristics for each pixel.

[0003] The liquid crystal display device described in Patent Document 1 includes pixel electrodes, TFTs serving as switching elements connected to the pixel electrodes, scanning lines connected to gate electrodes of the TFTs, and a light-shielding film. The scanning lines are arranged so as to shield a portion of the semiconductor film of the TFTs from light. The light-shielding film is provided above the TFTs and is arranged in a mesh pattern so as to shield the area other than the pixel openings from light. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-7806 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the conventional arrangement of the light-shielding film and scanning lines alone does not provide sufficient light-shielding properties for the semiconductor layer. [Means for solving the problem]

[0006] One aspect of the electro-optical device of the present invention comprises a substrate, a pixel electrode, a transistor arranged between the substrate and the pixel electrode, the transistor comprising a semiconductor layer having a source region, a drain region, and a channel region, and a gate electrode, and a first light-shielding portion arranged between the semiconductor layer and the pixel electrode, wherein the first light-shielding portion has a drain connection portion connected to the drain region, the semiconductor layer has a boundary portion between the channel region and the drain region, the drain region has a contact portion in contact with the first light-shielding portion and overlapping with the first light-shielding portion in a planar view, and a first distance between the contact portion and the substrate is shorter than a second distance between the boundary portion and the substrate. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view of an electro-optical device according to an embodiment. [Figure 2] 2 is a cross-sectional view of the electro-optical device shown in FIG. 1 taken along the line AA. [Figure 3] FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the element substrate of FIG. [Figure 4] 3 is a plan view showing a part of the element substrate in the display region of FIG. 2. FIG. [Figure 5] 5 is a cross-sectional view taken along the line A1-A1 in FIG. 4. [Figure 6] 5 is a cross-sectional view taken along the line A2-A2 in FIG. 4. [Figure 7] FIG. 6 is a plan view showing the transistor in FIG. 5. [Figure 8] FIG. 6 is a plan view corresponding to the line B1-B1 in FIG. 5. [Figure 9] FIG. 6 is a plan view corresponding to the line B2-B2 in FIG. 5. [Figure 10] FIG. 5 is a cross-sectional view taken along the line A3-A3 in FIG. [Figure 11] FIG. 6 is a plan view corresponding to the line B3-B3 in FIG. 5. [Figure 12] 6 is an enlarged view showing the positional relationship between the semiconductor layer and the first light-shielding portion shown in FIG. 5. FIG. [Figure 13] This corresponds to the cross section taken along C1-C1 in FIG. [Figure 14]This corresponds to the cross section C2-C2 in Figure 8. [Figure 15] FIG. 6 is a plan view corresponding to the line B4-B4 in FIG. 5. [Figure 16] FIG. 10 is a cross-sectional view showing a second light-shielding portion of a second embodiment. [Figure 17] FIG. 1 is a perspective view showing a personal computer as an example of an electronic device. [Figure 18] FIG. 1 is a plan view showing a smartphone as an example of an electronic device. [Figure 19] FIG. 1 is a schematic diagram illustrating a projector as an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. Note that the dimensions and scale of each part in the drawings may differ from the actual dimensions and some parts are shown schematically to facilitate understanding. Furthermore, the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description to the effect that the present invention is limited thereto.

[0009] 1. Electro-optical devices 1A.Basic configuration FIG. 1 is a plan view of an electro-optical device 100 according to an embodiment. FIG. 2 is a cross-sectional view of the electro-optical device 100 taken along line AA in FIG. 1. Note that the counter substrate 3 is not shown in FIG. 1. For ease of explanation, the following description will appropriately use the mutually perpendicular X-, Y-, and Z-axes. A direction along the X-axis will be referred to as the X1 direction, and a direction opposite to the X1 direction will be referred to as the X2 direction. Similarly, a direction along the Y-axis will be referred to as the Y1 direction, and a direction opposite to the Y1 direction will be referred to as the Y2 direction. A direction along the Z-axis will be referred to as the Z1 direction, and a direction opposite to the Z1 direction will be referred to as the Z2 direction.

[0010] Furthermore, in this specification, "element β on element α" means that element β is located above element α. Therefore, "element β on element α" includes not only the case where element β is in direct contact with element α, but also the case where element α and element β are spaced apart. Furthermore, "electrical connection" between element α and element β includes not only a configuration in which element α and element β are electrically connected by direct bonding, but also a configuration in which element α and element β are indirectly electrically connected via another conductor.

[0011] The electro-optical device 100 shown in FIGS. 1 and 2 is a transmissive electro-optical device that employs an active matrix driving method. The electro-optical device 100 includes an element substrate 2, a counter substrate 3, a frame-shaped sealing member 4, and a liquid crystal layer 5. As shown in FIG. 2, the element substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in this order in the Z1 direction. Note that a view from the Z1 direction or the Z2 direction in which these elements overlap is referred to as a "plan view." Furthermore, although the shape of the electro-optical device 100 shown in FIG. 1 is rectangular in plan view, it may also be a polygon other than a rectangle or a circle.

[0012] The element substrate 2 shown in FIG. 2 includes a first substrate 21 having light-transmitting properties, a laminate 22 having light-transmitting properties, a plurality of pixel electrodes 25 having light-transmitting properties, and a first alignment film 29 having light-transmitting properties. The first substrate 21, the laminate 22, the plurality of pixel electrodes 25, and the first alignment film 29 are laminated in this order in the Z1 direction. Note that "light-transmitting properties" refers to transparency to visible light, and preferably refers to a visible light transmittance of 50% or more. As will be described in detail later, the element substrate 2 also includes a first light-shielding portion 6, a third light-shielding portion 7, and a second light-shielding portion 8 having light-shielding properties, as shown in FIGS. 5 and 6. Note that "light-shielding properties" refers to a property of blocking visible light, and preferably refers to a visible light transmittance of less than 50%, more preferably 10% or less.

[0013] The first substrate 21 shown in FIG. 2 corresponds to a "substrate." The first substrate 21 is a flat plate having translucency and insulating properties, and is formed of, for example, a glass substrate or a quartz substrate. The laminate 22 includes a plurality of insulating films having translucency. The laminate 22 is also provided with various wirings and the like. The pixel electrodes 25 are used to apply an electric field to the liquid crystal layer 5. The pixel electrodes 25 include, for example, a transparent conductive material such as ITO (indium tin oxide), IZO (indium zinc oxide), or FTO (fluorine-doped tin oxide). Although not shown, the element substrate 2 has a plurality of dummy pixel electrodes surrounding the plurality of pixel electrodes 25 in a planar view. The first alignment film 29 is translucent and insulating. The first alignment film 29 aligns liquid crystal molecules in the liquid crystal layer 5. The first alignment film 29 is disposed so as to cover the plurality of pixel electrodes 25. The material of the first alignment film 29 is, for example, polyimide and silicon oxide.

[0014] The counter substrate 3 is disposed opposite the element substrate 2. The counter substrate 3 has a light-transmitting second substrate 31, a light-transmitting inorganic insulating layer 32, a light-transmitting common electrode 33, and a light-transmitting second alignment film 34. Although not shown, the counter substrate 3 also has a light-shielding partition surrounding the plurality of pixel electrodes 25 in a plan view.

[0015] The second substrate 31, inorganic insulating layer 32, common electrode 33, and second alignment film 34 are stacked in this order in the Z2 direction. The second substrate 31 is a flat plate having translucent and insulating properties, such as a glass substrate or a quartz substrate. The inorganic insulating layer 32 is also translucent and insulating, and is formed of an inorganic material containing silicon, such as silicon oxide. The common electrode 33 is a counter electrode disposed across the liquid crystal layer 5 from the plurality of pixel electrodes 25. The common electrode 33 is used to apply an electric field to the liquid crystal layer 5. The common electrode 33 is translucent and conductive. The common electrode 33 includes a transparent conductive material, such as ITO, IZO, or FTO. The second alignment film 34 is translucent and insulating. The second alignment film 34 aligns the liquid crystal molecules in the liquid crystal layer 5. The second alignment film 34 is made of a material such as polyimide or silicon oxide.

[0016] The sealing member 4 is disposed between the element substrate 2 and the opposing substrate 3. The sealing member 4 is formed using an adhesive containing various curable resins such as epoxy resin. The sealing member 4 may also contain a gap material made of an inorganic material such as glass.

[0017] The liquid crystal layer 5 is disposed within the region surrounded by the element substrate 2, the counter substrate 3, and the sealing member 4. The liquid crystal layer 5 is an electro-optical layer whose optical properties change in response to an electric field. The liquid crystal layer 5 contains liquid crystal molecules with positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes in response to the voltage applied to the liquid crystal layer 5.

[0018] As shown in FIG. 1, a plurality of scanning line driving circuits 11, a signal line driving circuit 12, and a plurality of external terminals 13 are arranged on the element substrate 2. Some of the plurality of external terminals 13 are connected to wiring (not shown) drawn from the scanning line driving circuit 11 or the signal line driving circuit 12. The plurality of external terminals 13 also includes a terminal to which a constant potential Vcom is applied. This terminal is electrically connected to a common electrode 33 of the counter substrate 3 via wiring and a conductive material (not shown). Therefore, the constant potential Vcom is supplied to the common electrode 33.

[0019] The electro-optical device 100 has a display area A10 that displays an image and a peripheral area A20 located outside the display area A10 in a planar view. A plurality of pixels P are arranged in a matrix in the display area A10. A plurality of pixel electrodes 25 are arranged in a one-to-one correspondence with the plurality of pixels P. The aforementioned common electrode 33 is provided in common to the plurality of pixels P. The peripheral area A20 surrounds the display area A10 in a planar view. A scanning line driving circuit 11 and a signal line driving circuit 12 are arranged in the peripheral area A20.

[0020] In this embodiment, the electro-optical device 100 is a transmissive type. Specifically, as shown in Fig. 2, an image is displayed by modulating light LL after it is incident on the counter substrate 3 and before it is emitted from the element substrate 2. Note that an image may also be displayed by modulating light that has entered the element substrate 2 and before it is emitted from the counter substrate 3.

[0021] The electro-optical device 100 is also applied to display devices that perform color display, such as personal computers and smartphones, which will be described later. When applied to such display devices, a color filter is appropriately used for the electro-optical device 100. The electro-optical device 100 is also applied to, for example, a projection-type projector, which will be described later. In this case, the electro-optical device 100 functions as a light valve. In this case, the color filter is omitted from the electro-optical device 100.

[0022] 1B. Electrical configuration of element substrate 2 3 is an equivalent circuit diagram showing the electrical configuration of the element substrate 2 of FIG. 1. As shown in FIG. 3, the element substrate 2 has a plurality of transistors 23, n scanning lines 241, m signal lines 242, and n constant potential lines 243. n and m are each an integer of 2 or greater. A transistor 23 is disposed at each intersection of the n scanning lines 241 and the m signal lines 242. Each transistor 23 is, for example, a TFT (Thin Film Transistor) that functions as a switching element. Each transistor 23 includes a gate, a source, and a drain.

[0023] Each of the n scanning lines 241 extends in the X1 direction, and the n scanning lines 241 are arranged at equal intervals in the Y1 direction. Each of the n scanning lines 241 is electrically connected to the gates of the corresponding plurality of transistors 23. The n scanning lines 241 are electrically connected to the scanning line driving circuit 11 shown in FIG. 1. Scanning signals G1, G2, ..., and Gn are supplied line-sequentially to the 1st to nth scanning lines 241 from the scanning line driving circuit 11.

[0024] 3, each of the m signal lines 242 extends in the Y1 direction, and the m signal lines 242 are arranged at equal intervals in the X1 direction. Each of the m signal lines 242 is electrically connected to the sources of the corresponding plurality of transistors 23. The m signal lines 242 are electrically connected to the signal line drive circuit 12 shown in FIG. 1. Image signals S1, S2, ..., and Sm are supplied in parallel to the 1 to m signal lines 242 from the signal line drive circuit 12.

[0025] 3 are electrically insulated from one another and arranged in a grid pattern in plan view. An area surrounded by two adjacent scanning lines 241 and two adjacent signal lines 242 corresponds to a pixel P. A transistor 23, a pixel electrode 25, and a capacitance element 24 are provided for each pixel P. The pixel electrodes 25 are provided in a one-to-one correspondence with the transistors 23. Each pixel electrode 25 is electrically connected to the drain of the corresponding transistor 23.

[0026] Each of the n constant potential lines 243 extends in the X1 direction and is arranged at equal intervals in the Y2 direction. The n constant potential lines 243 are electrically insulated from the n scanning lines 241 and the m signal lines 242 and are spaced apart from them. A constant potential Vcom is applied to each of the n constant potential lines 243. Each of the n constant potential lines 243 is electrically connected to one of two electrodes of a corresponding capacitance element 24. Each capacitance element 24 is a capacitance element for maintaining the potential of a pixel electrode 25. The capacitance elements 24 are provided in a one-to-one correspondence with the transistors 23. The other of the two electrodes of each capacitance element 24 is electrically connected to the corresponding pixel electrode 25. Therefore, a constant potential Vcom is applied to one electrode of the capacitance element 24, and the other electrode is electrically connected to the drain of the transistor 23.

[0027] When the scanning signals G1, G2, ..., and Gn become active in sequence and n scanning lines 241 are selected in sequence, the transistor 23 connected to the selected scanning line 241 is turned on. Then, image signals S1, S2, ..., and Sm having a magnitude corresponding to the gradation to be displayed are received by the pixel P corresponding to the selected scanning line 241 via m signal lines 242 and applied to the pixel electrode 25. This applies a voltage corresponding to the gradation to be displayed to the liquid crystal capacitance formed between the pixel electrode 25 and the common electrode 33 in FIG. 2, and the orientation of the liquid crystal molecules changes in response to the applied voltage. The applied voltage is maintained by the capacitive element 24. This change in the orientation of the liquid crystal molecules modulates light, enabling gradation display.

[0028] 1C. Structure of element substrate 2 Fig. 4 shows a part of the element substrate 2 in the display region A10 in Fig. 2. In the following, the "first direction" is the direction along the Y axis, and the "second direction" is the direction along the X axis.

[0029] As shown in FIG. 4, the display region A10 has a plurality of opening regions A11 and a light-shielding region A12. The opening regions A11 are arranged in a matrix in a plan view. The light-shielding region A12 has a frame shape in a plan view and is located between the opening regions A11. Each opening region A11 is an area where a pixel electrode 25 is arranged and is a light-transmitting area. Meanwhile, a transistor 23 is arranged in the light-shielding region A12. Although not shown in FIG. 4, the light-shielding region A12 is also provided with a plurality of wirings, such as the scanning line 241, signal line 242, and constant potential line 243 shown in FIG. 3, as well as a capacitance element 24.

[0030] Fig. 5 is a cross-sectional view taken along the line A1-A1 in Fig. 4. Fig. 6 is a cross-sectional view taken along the line A2-A2 in Fig. 4.

[0031] 5 and 6, the element substrate 2 includes a first substrate 21, which is a "substrate," and a laminate 22. The laminate 22 includes a plurality of insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229. The insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229 are laminated in this order from the first substrate 21. The insulating layers 221 to 229 are light-transmitting and insulating. The insulating layers 221 to 229 are made of an inorganic material containing silicon, such as silicon oxide or silicon oxynitride.

[0032] The laminate 22 is provided with a transistor 23, a scanning line 241, a signal line 242, a first light-shielding portion 6, a third light-shielding portion 7, and a second light-shielding portion 8. The laminate 22 is further provided with relay electrodes 244, 245, 246, 247, 248, and 249.

[0033] As described above, the first substrate 21 is formed of, for example, a glass substrate or a quartz substrate. The first substrate 21 has a recess 21H. The recess 21H is a depression formed in the first substrate 21, and is formed for each transistor 23. The recess 21H is formed along the Y1 direction, which is the direction in which the semiconductor layer 231 described below extends. A second light-shielding portion 8 is disposed within the recess 21H. The second light-shielding portion 8 is in the form of a film and is formed, for example, using a damascene method. The second light-shielding portion 8 is provided to prevent light from entering the semiconductor layer 231 of the transistor 23. The second light-shielding portion 8 has an elongated shape along the Y axis, which is the direction in which the semiconductor layer 231 of the transistor 23 extends. The second light-shielding portion 8 is flush with the upper surface of the first substrate 21.

[0034] The transistor 23 is disposed on the insulating layer 221. The transistor 23 has a semiconductor layer 231, a gate electrode 232, and a gate insulating film 233. The semiconductor layer 231 is disposed on the insulating layer 221. The gate electrode 232 is disposed on the insulating layer 222. The gate insulating film 233 is interposed between the gate electrode 232 and the semiconductor layer 231. A region of the insulating layer 222 that corresponds to the gate electrode 232 in a plan view corresponds to the gate insulating film 233.

[0035] FIG. 7 is a plan view of the transistor 23 in FIG. 5. The transistor 23 shown in FIGS. 5 and 7 has an LDD (Lightly Doped Drain) structure. The semiconductor layer 231 extends in the Y1 direction in a plan view. The semiconductor layer 231 has a drain region 231a, a source region 231b, a channel region 231c, a lightly doped drain region 231d, and a lightly doped source region 231e. The channel region 231c is located between the drain region 231a and the source region 231b. The lightly doped drain region 231d is located between the channel region 231c and the drain region 231a. The lightly doped source region 231e is located between the channel region 231c and the source region 231b. The semiconductor layer 231 is formed of, for example, polysilicon. The region other than the channel region 231c is doped with impurities that increase conductivity. The conductivity of the channel region 231c is different from that of the other regions. The impurity concentration in the low-concentration drain region 231d is lower than the impurity concentration in the drain region 231a. The low-concentration drain region 231d and the drain region 231a have different electrical conductivities. The impurity concentration in the low-concentration source region 231e is lower than the impurity concentration in the source region 231b. The low-concentration source region 231e and the source region 231b have different electrical conductivities. Note that, for example, the transistor 23 does not need to have an LDD structure, and the low-concentration source region 231e and the low-concentration drain region 231d may be omitted. Furthermore, the semiconductor layer 231 overlaps the second light-shielding portion 8 in a planar view.

[0036] The gate electrode 232 is formed, for example, by doping polysilicon with impurities that increase conductivity. The gate electrode 232 may also be formed using a conductive material such as a metal, a metal oxide, or a metal compound. In plan view, the gate electrode 232 overlaps the channel region 231c of the semiconductor layer 231. The gate insulating film 233 is made of a silicon oxide film formed, for example, by thermal oxidation or a CVD (chemical vapor deposition) method.

[0037] As shown in FIGS. 5 and 6 , a first light-shielding portion 6 and a third light-shielding portion 7 are disposed above and to the sides of the transistor 23. Each of the first light-shielding portion 6 and the third light-shielding portion 7 is formed, for example, by a multi-layer stack. Each of the first light-shielding portion 6 and the third light-shielding portion 7 is formed, for example, by a damascene process. The first light-shielding portion 6 is electrically connected to the drain region 231a of the semiconductor layer 231. The third light-shielding portion 7 is electrically connected to the gate electrode 232. As shown in FIG. 6 , the third light-shielding portion 7 is directly connected to the second light-shielding portion 8, and the third light-shielding portion 7 is electrically connected to the second light-shielding portion 8. The second light-shielding portion 8 functions as a back gate. The first light-shielding portion 6, the third light-shielding portion 7, and the second light-shielding portion 8 can suppress light from entering the low-concentration drain region 231d of the semiconductor layer 231.

[0038] 5, a relay electrode 244 is disposed on the insulating layer 223. The relay electrode 244 is electrically connected to the source region 231b of the semiconductor layer 231 via a contact 271. For example, the contact 271 is a contact plug that fills a hole that penetrates the insulating layers 222 and 223. Note that the relay electrode 244 and the contact 271 are integrally formed from the same material, but may be formed from different materials.

[0039] 5, a scanning line 241, a relay electrode 245, and a relay electrode 246 are arranged on the insulating layer 224. The scanning line 241 is electrically connected to the gate electrode 232 via a third light-shielding portion 7. The relay electrode 245 is electrically connected to the first light-shielding portion 6 via a contact 272 that penetrates the insulating layer 224. The relay electrode 246 is electrically connected to the relay electrode 244 via a contact 273 that penetrates the insulating layer 224. Each of the contacts 272 and 273 is, for example, a contact plug that fills a hole that penetrates the insulating layer 224.

[0040] Relay electrodes 247 and 248 are disposed on the insulating layer 225. The relay electrode 247 is electrically connected to the relay electrode 246 via a contact 275 that penetrates the insulating layer 225. The contact 275 is, for example, formed integrally with the relay electrode 246 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 225. The relay electrode 248 is electrically connected to the relay electrode 245 via a contact 274 that penetrates the insulating layer 225. The contact 274 is formed integrally with the relay electrode 248 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 225.

[0041] The signal line 242 is disposed on the insulating layer 226. The signal line 242 is electrically connected to the relay electrode 247 via a contact 276 that penetrates the insulating layer 226. Therefore, the signal line 242 is electrically connected to the source region 231b via the contact 276, the relay electrode 247, the contact 275, the relay electrode 246, the contact 273, the relay electrode 244, and the contact 271. The contact 276 is formed integrally with the signal line 242 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 226.

[0042] 6, a relay electrode 249 is disposed on the insulating layer 226. The relay electrode 249 is electrically connected to the relay electrode 248 via a contact 277 that penetrates the insulating layer. The contact 277 is formed integrally with the relay electrode 249 and has a trench structure that is provided along the inner wall surface of a hole formed in the insulating layer 226.

[0043] The capacitor 24 is disposed on the insulating layer 227. The capacitor 24 has a pair of electrodes 2401 and 2402 and a dielectric layer 2403. The electrode 2401 is disposed on the insulating layer 227. The electrode 2402 is disposed on the insulating layer 228. The dielectric layer 2403 is disposed between the electrodes 2401 and 2402. The electrode 2401 also serves as the constant potential line 243 in FIG. 2. The electrode 2402 is electrically connected to the relay electrode 249 via a contact 278 that penetrates the insulating layers 227 and 228. Therefore, as shown in FIG. 5 or 6, the electrode 2402 is electrically connected to the drain region 231a via the contact 278, the relay electrode 249, the contact 277, the relay electrode 248, the contact 274, the relay electrode 245, the contact 272, and the first light-shielding portion 6. The contact 278 is formed integrally with the electrode 2402 and has a trench structure provided along the inner wall surfaces of holes formed in the insulating layers 227 and 228 .

[0044] 6, the pixel electrode 25 is disposed on the insulating layer 229. The pixel electrode 25 is electrically connected to the electrode 2402 via a contact 279 that penetrates the insulating layer 229. The contact 279 is formed integrally with the pixel electrode 25 and has a trench structure that is provided along the inner wall surface of a hole formed in the insulating layer 229.

[0045] Each of the aforementioned scan line 241, signal line 242, electrode 2401, electrode 2402, and relay electrodes 244, 245, 246, 247, 248, and 249 includes, for example, a metal such as tungsten (W), titanium (Ti), chromium (Cr), iron, or aluminum (Al), a metal nitride, or a metal silicide. These may be single layers or multilayers. For example, they may be formed of a multilayer structure of an aluminum film and a titanium nitride film.

[0046] Each of the contacts 271 to 279 includes, for example, a metal such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), or aluminum (Al), a metal nitride, or a metal silicide. Each of the contacts 271 to 279 may be a single layer or a multilayer. Each of the contacts 271 to 279 may be formed integrally with or separately from the electrode or wiring to which it is connected. Each of the contacts 271 to 279 may have a trench structure or may be a contact plug.

[0047] 5 and 6 is an example. For example, the element substrate 2 may include a capacitive element other than the capacitive element 24. Although the scanning line 241, the signal line 242, and the capacitive element 24 are arranged in this order in the Z1 direction, they do not have to be arranged in this order.

[0048] 1D. Light shielding of semiconductor layer 231 8 is a plan view corresponding to the line B1-B1 in FIG. 5. As shown in FIG. 8, the first light-shielding portion 6 and the third light-shielding portion 7 surround the low-concentration drain region 231d, which is the boundary between the drain region 231a and the channel region 231c, in a plan view. That is, the first light-shielding portion 6 and the third light-shielding portion 7 are arranged around the low-concentration drain region 231d so as to confine the low-concentration drain region 231d inside in a plan view. Therefore, the low-concentration drain region 231d is arranged within the region formed by the first light-shielding portion 6 and the third light-shielding portion 7 in a plan view.

[0049] In this way, the first light-shielding portion 6 and the third light-shielding portion 7 surround the lightly doped drain region 231d, thereby suppressing light from entering the lightly doped drain region 231d compared to when the first light-shielding portion 6 and the third light-shielding portion 7 do not surround the lightly doped drain region 231d. In particular, light from the sides of the lightly doped drain region 231d can be suppressed. In other words, the first light-shielding portion 6 and the third light-shielding portion 7 surround the lightly doped drain region 231d so as to suppress light from entering from the sides. Therefore, malfunctions of the transistor 23 caused by photocurrent can be suppressed more effectively than before.

[0050] Furthermore, as described above, since the first light-shielding portion 6 is connected to the drain region 231a, a pixel potential is applied to the first light-shielding portion 6. Therefore, the first light-shielding portion 6 is not at a gate potential. For this reason, even if the first light-shielding portion 6 is disposed near the semiconductor layer 231, the influence of the gate potential is unlikely to reach the semiconductor layer 231, and an increase in off-leak current caused by the gate potential approaching the semiconductor layer 231 can be suppressed. Therefore, the first light-shielding portion 6 can be disposed close to the semiconductor layer 231. This can improve the light-shielding properties of the semiconductor layer 231.

[0051] As shown in FIG. 8 , the third light-shielding portion 7 is positioned further outward from the first light-shielding portion 6 than the low-concentration drain region 231d in the X-axis direction. Therefore, the distance between the third light-shielding portion 7 and the low-concentration drain region 231d in the X-axis direction is longer than the distance between the first light-shielding portion 6 and the low-concentration drain region 231d. The third light-shielding portion 7 is located farther from the low-concentration drain region 231d than the first light-shielding portion 6, reducing the possibility that the third light-shielding portion 7, which is the gate potential, will affect the low-concentration drain region 231d. Specifically, this reduces an increase in off-leakage current due to the gate potential approaching regions other than the channel region 231c of the semiconductor layer 231. This reduces degradation of display quality due to the occurrence of black spots, etc. The off-leakage current is leakage current that flows when the transistor 23 is turned off.

[0052] Fig. 9 is a plan view corresponding to the line B2-B2 in Fig. 5. Fig. 9 shows the semiconductor layer 231 and the first light-shielding portion 6 and the third light-shielding portion 7 in the same layer.

[0053] 9 , the first light-shielding portion 6 and the third light-shielding portion 7 are arranged in the same layer as the semiconductor layer 231, sandwiching the low-concentration drain region 231d, which is the boundary portion. The first light-shielding portion 6 and the third light-shielding portion 7 overlap the entire region of the low-concentration drain region 231d, as viewed along the X-axis, in the same layer as the semiconductor layer 231. Therefore, the first light-shielding portion 6 and the third light-shielding portion 7 cover the low-concentration drain region 231d, as viewed along the X-axis. Therefore, the first light-shielding portion 6 and the third light-shielding portion 7 can reduce the risk of light entering the low-concentration drain region 231d from the side of the low-concentration drain region 231d.

[0054] Fig. 10 is a cross-sectional view taken along line A3-A3 in Fig. 4. As shown in Figs. 5, 6, and 10, the first light-shielding portion 6 has a three-dimensional structure that covers the lightly doped drain region 231d. The first light-shielding portion 6 includes a first portion 61, two second portions 62, and a fifth portion 63.

[0055] 5, the first portion 61 of the first light-shielding portion 6 is disposed on the insulating layers 222 and 223. As shown in FIGS. 8 and 9, the first portion 61 is a portion that overlaps with the drain region 231a in plan view. The first portion 61 is a "drain connection portion" that is connected to the drain region 231a.

[0056] Each of the two second portions 62 extends in the Y1 direction from the first portion 61 in a plan view. The two second portions 62 are spaced apart from each other and arranged to sandwich the low-concentration drain region 231d, which is the boundary portion, from both sides in the direction along the X-axis, which is the width direction, in a plan view. The two second portions 62 are spaced apart from the low-concentration drain region 231d, which is the boundary portion, in a plan view. As shown in FIG. 10 , each second portion 62 is arranged on the insulating layers 221 to 223. Each second portion 62 is arranged from the upper layer to the lower layer of the semiconductor layer 231. The lower end of each second portion 62 is located between the first substrate 21 and the insulating layer 222 on which the semiconductor layer 231 is provided.

[0057] 11 is a plan view corresponding to the line B3-B3 in FIG. 5. As shown in FIGS. 5, 10, and 11, the fifth portion 63 of the first light-shielding portion 6 is connected to the first portion 61 and the two second portions 62, and is disposed above the first portion 61 and the two second portions 62. The fifth portion 63 overlaps the first portion 61 and the two second portions 62 so as to cover them in a plan view. The fifth portion 63 overlaps the lightly doped drain region 231d in a plan view.

[0058] The first light-shielding part 6 has a fifth part 63 that overlaps with the low-concentration drain region 231d, which is the boundary part, in a plan view. Therefore, the first light-shielding part 6 can reduce the risk of light entering the low-concentration drain region 231d from above the low-concentration drain region 231d, in addition to the side of the low-concentration drain region 231d.

[0059] 12 is an enlarged view showing the positional relationship between the semiconductor layer 231 and the first light-shielding portion 6 shown in FIG. 5. As shown in FIG. 12, the upper surface of the insulating layer 221 has a step. The insulating layer 221 has a thick portion and a thin portion along the Z axis. Specifically, the insulating layer 221 has a thick portion 2211, a thin portion 2212, and an intermediate portion 2213.

[0060] The thick portion 2211 is the portion of the insulating layer 221 that is thickest along the Z axis. In plan view, the thick portion 2211 overlaps the channel region 231c, the lightly doped drain region 231d, and the lightly doped source region 231e. In FIG. 8, the thick portion 2211 is the region surrounded by a two-dot chain line.

[0061] The thin portion 2212 is the portion of the insulating layer 221 that has the thinnest thickness along the Z axis. The thin portion 2212 overlaps the drain region 231a and the source region 231b in a plan view. In this embodiment, the entire insulating layer 221 except for the thick portion 2211 and the intermediate portion 2213 is the thin portion 2212. Therefore, the thin portion 2212 is provided so as to surround the thick portion 2211 in a plan view.

[0062] The intermediate portion 2213 is a portion located between the thick portion 2211 and the thin portion 2212 in plan view. In FIG. 8, the intermediate portion 2213 is a portion of the region surrounded by the dashed-dotted line excluding the region surrounded by the dashed-two-dotted line. The intermediate portion 2213 is frame-shaped surrounding the thick portion 2211 in plan view. As shown in FIG. 12, the thickness of the intermediate portion 2213 along the Z axis gradually decreases from the thick portion 2211 toward the thin portion 2212. The upper surface of the intermediate portion 2213 is an inclined surface. The lower surface of the insulating layer 221 is a flat surface.

[0063] The semiconductor layer 231 provided on the insulating layer 221 has irregularities that correspond to the irregularities on the upper surface of the insulating layer 221. Therefore, the semiconductor layer 231 has steps.

[0064] 12, in the semiconductor layer 231, the channel region 231c, the low-concentration drain region 231d, and the low-concentration source region 231e are located in the Z1 direction further from portions of the drain region 231a and the source region 231b. The channel region 231c, the low-concentration drain region 231d, and the low-concentration source region 231e overlap the thick portion 2211 in a planar view. Further, portions of the drain region 231a and the source region 231b overlap the thin portion 2212 in a planar view. Further, the drain region 231a near the low-concentration drain region 231d and the source region 231b near the low-concentration source region 231e overlap the intermediate portion 2213 in a planar view and are inclined with respect to the Z axis.

[0065] 12, the drain region 231a has a contact portion 230. The contact portion 230 is in contact with the first portion 61, which serves as a "drain connection portion," and overlaps with the first portion 61 in a planar view. The contact portion 230 and the first portion 61 are in contact with each other as long as they are directly or indirectly connected to each other and electrically connected. The contact portion 230 overlaps the thin portion 2212 in a planar view. In FIG. 12, the type of hatching for the contact portion 230 in the drain region 231a is different from that for the other portions to make it easier to understand the arrangement of the contact portion 230.

[0066] 13 corresponds to the cross section taken along C1-C1 in FIG. 8. FIG. 14 corresponds to the cross section taken along C2-C2 in FIG. 8. As shown in FIG. 12, the channel region 231c and the lightly doped drain region 231d are at the same position on the Z axis. Therefore, as shown in FIGS. 12 and 14, the third distance D3 between the channel region 231c and the first substrate 21 is equal to the second distance D2 between the lightly doped drain region 231d and the first substrate 21.

[0067] 12 to 14, the contact portion 230 is located further in the Z2 direction than the lightly doped drain region 231d. Therefore, the first distance D1, which is the distance between the contact portion 230 and the first substrate 21, is shorter than the second distance D2.

[0068] The first distance D1, the second distance D2, and the third distance D3 are each a distance along the Z-axis direction. The distance to the first substrate 21 is considered to be the distance to the second light-shielding portion 8 that is flush with the first substrate 21, but may also be considered to be the distance to the bottom of the recess 21H.

[0069] Because the first distance D1 is shorter than the second distance D2, it is easy to arrange the first light-shielding portion 6 from the upper layer to the lower layer of the lightly doped drain region 231d. This makes it possible to improve the light-shielding properties on the sides of the lightly doped drain region 231d. This increases the effect of the first light-shielding portion 6 in suppressing light from entering the sides of the lightly doped drain region 231d. This makes it possible to more effectively suppress malfunctions and the like caused by photocurrent in the transistor 23 than ever before.

[0070] In this embodiment, the "boundary" between the drain region 231a and the channel region 231c corresponds to the lightly doped drain region 231d. The lightly doped drain region 231d is the region in the semiconductor layer 231 where light leakage is most likely to occur. Therefore, by arranging the first light-shielding portion 6 so as to suppress light from entering the lightly doped drain region 231d, it is possible to particularly effectively suppress malfunctions and the like caused by photocurrent in the transistor 23.

[0071] In this embodiment, the transistor 23 has the lightly doped drain region 231d, but the lightly doped drain region 231d may be omitted. For example, when the semiconductor layer 231 is composed of the drain region 231a, the source region 231b, and the channel region 231c, the first light-shielding portion 6 and the third light-shielding portion 7 are provided so as to surround the boundary between the drain region 231a and the channel region 231c.

[0072] 13, the first portion 61 is provided from the lower layer to the upper layer of the lightly doped drain region 231d. Therefore, the first portion 61 overlaps with the lightly doped drain region 231d, which is the boundary between the lightly doped drain region 231d and the channel region 231c, when viewed in the direction along the Y-axis, which is the "first direction."

[0073] The first portion 61 overlaps the lightly doped drain region 231d when viewed along the Y-axis, thereby enhancing the effect of suppressing light from entering the lightly doped drain region 231d from the side. As described above, since the first distance D1 is shorter than the second distance D2, the first portion 61 can be disposed so as to overlap the lightly doped drain region 231d when viewed along the Y-axis.

[0074] As described above, the two second portions 62 are provided to sandwich the lightly doped drain region 231d. Although not shown in detail, each second portion 62 overlaps with the lightly doped drain region 231d, which is the boundary portion, when viewed in the direction along the X-axis. This further enhances the effect of suppressing light from entering the lightly doped drain region 231d from the side.

[0075] 12, the semiconductor layer 231 has an inclined portion 239. The inclined portion 239 is located between the low-concentration drain region 231d and the contact portion 230. The inclined portion 239 is inclined with respect to the direction along the Z axis, which is the thickness direction of the first substrate 21. The portions of the semiconductor layer 231 other than the inclined portion 239 are parallel to the XY plane, and the inclined portion 239 is inclined with respect to the XY plane. The inclined portion 239 is a part of the drain region 231a.

[0076] The presence of the inclined portion 239 makes it easier to realize a structure in which the contact portion 230 can be located lower than the low-concentration drain region 231d. The inclination angle of the inclined portion 239 with respect to the Z axis is not limited and is determined appropriately depending on, for example, the manufacturing method. In the example of FIG. 12, the inclination angle of the inclined portion 239 is constant, but it does not have to be constant and may have, for example, an inflection point.

[0077] As described above, the second light-shielding portion 8 is disposed between the first substrate 21 and the semiconductor layer 231. The second light-shielding portion 8 overlaps the lightly doped drain region 231d in plan view. By disposing the second light-shielding portion 8 below the semiconductor layer 231, it is possible to suppress the incidence of light from below the semiconductor layer 231 into the lightly doped drain region 231d.

[0078] Furthermore, the second light-shielding portion 8 is at a gate potential. Therefore, the second light-shielding portion 8 can be used as a back gate. Furthermore, the first light-shielding portion 6 and the second light-shielding portion 8 have different potentials. Although the two second portions 62 of the first light-shielding portion 6 overlap with the second light-shielding portion 8 in a plan view, they do not necessarily have to overlap.

[0079] Furthermore, as described above, the second light-shielding portion 8 is disposed in the recess 21H provided in the first substrate 21. By disposing the second light-shielding portion 8 in the recess 21H, it is easy to planarize the upper surface of the second light-shielding portion 8, for example, by CMP (Chemical Mechanical Polishing). This makes it easy to form a second light-shielding portion 8 with few irregularities on the upper surface. This reduces the risk of insufficient light-shielding properties due to the irregularities. This makes it easy to form a second light-shielding portion 8 with excellent light-shielding properties for the recess 21H.

[0080] 5, 6, and 10, the third light-shielding portion 7 has a three-dimensional structure that covers the lightly doped drain region 231d. The third light-shielding portion 7 includes a third portion 71 and two fourth portions 72.

[0081] As shown in FIGS. 6 and 8 , the third portion 71 of the third light-shielding portion 7 is a portion located above the gate electrode 232. The third portion 71 is disposed on the insulating layers 223 and 224. The third portion 71 overlaps with the gate electrode 232 in plan view. The third portion 71 extends along the X-axis. As shown in FIG. 6 , the third portion 71 is disposed on the insulating layers 223 and 224. The third portion 71 is located between two fourth portions 72.

[0082] As shown in FIG. 11 , each of the two fourth portions 72 extends in the Y2 direction from the third portion 71 in a plan view. As shown in FIG. 9 , each fourth portion 72 includes a portion extending from the third portion 71 along the X-axis. This portion is connected to the portion extending in the Y2 direction. The two fourth portions 72 are spaced apart from each other and arranged to sandwich the low-concentration drain region 231d, which is the boundary portion, from both sides in the width direction along the X-axis in a plan view. The two fourth portions 72 are spaced apart from the low-concentration drain region 231d, which is the boundary portion, in a plan view. The two fourth portions 72 are located outside the two second portions 62 in a plan view. As shown in FIG. 10 , each fourth portion 72 is arranged on the insulating layers 221 to 224. The fourth portions 72 are arranged from the upper layer to the lower layer of the semiconductor layer 231. The upper end of each fourth portion 72 is connected to the scanning line 241. The lower end of each fourth portion 72 is connected to the second light-shielding portion 8.

[0083] As shown in Figure 8, the presence of the third light-shielding portion 7 having the above-mentioned third portion 73 and two fourth portions 74, and the first light-shielding portion 6 having the above-mentioned first portion 61 and second portion 62 allows the first light-shielding portion 6 and the third light-shielding portion 7 to surround the low-concentration drain region 231d.

[0084] Furthermore, the two fourth portions 72 are located outside the two second portions 62 in a planar view, thereby reducing the risk that the fourth portions 72, which are the gate potential, will affect the low-concentration drain region 231d.

[0085] Additionally, the two second portions 62 and the two fourth portions 72 overlap with the lightly doped drain region 231d when viewed along the X-axis. Furthermore, parts of the two second portions 62 and parts of the two fourth portions 72 overlap with each other in the direction along the X-axis, which is the width direction of the semiconductor layer 231. This effectively suppresses light from entering from the side of the lightly doped drain region 231d.

[0086] Furthermore, each of the two second portions 62 is linear in the Y1 direction, which is the extending direction of the semiconductor layer 231, in a plan view. Therefore, the light-shielding region A12 where the first light-shielding portion 6 is arranged can be narrowed compared to when each second portion 62 is bent or curved. This allows the opening region A11 to be enlarged, i.e., the aperture ratio to be improved.

[0087] Similarly, each of the two fourth portions 72 is linear in the Y1 direction, which is the extending direction of the semiconductor layer 231, in a plan view. Therefore, the light-shielding region A12 where the third light-shielding portion 7 is arranged can be narrowed compared to when each fourth portion 72 is bent or curved. This allows the opening region A11 to be enlarged, i.e., the aperture ratio to be improved.

[0088] 5, a connection portion 70 of the third light-shielding portion 7 with the gate electrode 232 is located on the drain region 231a side of the gate electrode 232 in plan view. By arranging the connection portion 70 in this manner, it is possible to narrow the light-shielding region A12 where the third light-shielding portion 7 is arranged. This makes it possible to enlarge the opening region A11, i.e., improve the aperture ratio.

[0089] 11, the gate electrode 232 has a first gate portion 2321 and a second gate portion 2322. The second gate portion 2322 is located farther from the drain region 231a than the first gate portion 2321 in a plan view. The length of the second gate portion 2322 along the X axis is shorter than the length of the first gate portion 2321 along the X axis. The first gate portion 2321 is located at an intersection of the light-shielding region A12. The third light-shielding portion 7 is connected to the first gate portion 2321.

[0090] Such a configuration of the gate electrode 232 and the arrangement of the third light-shielding portion 7 facilitates narrowing of the light-shielding region A12, thereby enabling the expansion of the opening region A11, that is, the improvement of the aperture ratio.

[0091] Fig. 15 is a plan view corresponding to the line B4-B4 in Fig. 5. As shown in Fig. 15, the scanning lines 241 are located above the first light-shielding portions 6 and overlap the first light-shielding portions 6 in plan view. Therefore, the scanning lines 241 in addition to the first light-shielding portions 6 can more effectively reduce the risk of light entering the lightly doped drain region 231d from above.

[0092] Furthermore, no wiring or electrode is interposed between the first light-shielding portion 6 and the lightly doped drain region 231d. This allows the first light-shielding portion 6 to be placed very close to the lightly doped drain region 231d. This allows the first light-shielding portion 6 to suppress light from entering the lightly doped drain region 231d from the Z1 direction.

[0093] 2. Second embodiment In the second embodiment, the elements having the same functions as those in the first embodiment will be designated by the same reference numerals as those used in the description of the first embodiment, and detailed description thereof will be omitted as appropriate.

[0094] Fig. 16 is a cross-sectional view showing the second light-shielding portion 8 of the second embodiment. As shown in Fig. 16, in the second embodiment, the first substrate 21 does not have the recess 21H of the first embodiment, and the second light-shielding portion 8 is disposed on the flat upper surface of the first substrate 21. Therefore, the second light-shielding portion 8 protrudes from the first substrate 21 in the Z1 direction.

[0095] Furthermore, the second light-shielding portion 8 overlaps the low-concentration drain region 231d, the low-concentration source region 231e, and the channel region 231c in plan view, but does not overlap the drain region 231a and the source region 231b.

[0096] Since the second light-shielding portion 8 protrudes from the first substrate 21, the insulating layer 221 having a step on its upper surface can be easily formed by devising the arrangement in a plan view as described above. Therefore, the semiconductor layer 231 having a step can be easily formed.

[0097] 3. Variations The above-described exemplary embodiments may be modified in various ways. Specific modifications that may be applied to the above-described embodiments are exemplified below. Two or more aspects arbitrarily selected from the following examples may be combined as appropriate to the extent that they are not mutually inconsistent.

[0098] In the above-described embodiments, the electro-optical device 100 is an active matrix type, but the driving method of the electro-optical device 100 is not limited to this, and may be, for example, a passive matrix type.

[0099] The driving method of the "electro-optical device" is not limited to the vertical electric field method, but may be a horizontal electric field method. The horizontal electric field method may be, for example, an in-plane switching (IPS) mode. The vertical electric field method may be, for example, a twisted nematic (TN) mode, a vertical alignment (VA) mode, a PVA mode, or an optically compensated bend (OCB) mode.

[0100] In the above description, the third light-shielding portion 7 is connected to the second light-shielding portion 8, but it is not necessary for them to be connected. Also, the second light-shielding portion 8 may be omitted.

[0101] 4.Electronic equipment The electro-optical device 100 can be used in various electronic devices.

[0102] 17 is a perspective view showing a personal computer 2000, which is an example of an electronic device. The personal computer 2000 has an electro-optical device 100 that displays various images, a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed, and a control unit 2003. The control unit 2003 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0103] 18 is a plan view showing a smartphone 3000, which is an example of an electronic device. The smartphone 3000 has an operation button 3001, an electro-optical device 100 that displays various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 changes in response to an operation of the operation button 3001. The control unit 3002 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0104] FIG. 19 is a schematic diagram showing a projector, which is an example of an electronic device. The projection display device 4000 is, for example, a three-plate projector. The electro-optical device 1r is an electro-optical device 100 corresponding to the red display color, the electro-optical device 1g is an electro-optical device 100 corresponding to the green display color, and the electro-optical device 1b is an electro-optical device 100 corresponding to the blue display color. In other words, the projection display device 4000 has three electro-optical devices 1r, 1g, and 1b corresponding to the red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0105] The illumination optical system 4001 supplies a red component r of light emitted from an illumination device 4002, which is a light source, to an electro-optical device 1r, a green component g to an electro-optical device 1g, and a blue component b to an electro-optical device 1b. Each of the electro-optical devices 1r, 1g, and 1b functions as an optical modulator such as a light valve that modulates each monochromatic light supplied from the illumination optical system 4001 in accordance with a display image. The projection optical system 4003 combines the light emitted from the electro-optical devices 1r, 1g, and 1b and projects the combined light onto a projection surface 4004.

[0106] The above electronic devices include the electro-optical device 100 and the control unit 2003, 3002, or 4005. The electro-optical device 100 has excellent light-blocking properties in the semiconductor layer 231, which prevents the operation of the transistor 23 from becoming unstable. This reduces the risk of display defects. Therefore, the inclusion of the electro-optical device 100 can improve the display quality of the personal computer 2000, smartphone 3000, or projection display device 4000.

[0107] Electronic devices to which the electro-optical device of the present invention can be applied are not limited to the devices exemplified above, and examples thereof include PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation systems, in-vehicle displays, electronic organizers, electronic paper, calculators, word processors, workstations, videophones, and POS (Point of Sale) terminals. Furthermore, examples of electronic devices to which the present invention can be applied include printers, scanners, copiers, video players, and devices equipped with touch panels.

[0108] Although the present invention has been described above based on preferred embodiments, the present invention is not limited to the above-described embodiments. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above-described embodiments, and any configuration can be added.

[0109] In the above description, a liquid crystal display device has been described as an example of the electro-optical device of the present invention, but the electro-optical device of the present invention is not limited to this. For example, the electro-optical device of the present invention can also be applied to an image sensor, etc. [Explanation of symbols]

[0110] 2...element substrate, 3...opposite substrate, 4...sealing member, 5...liquid crystal layer, 6...first light-shielding portion, 7...third light-shielding portion, 8...second light-shielding portion, 21...first substrate (substrate), 22...laminated body, 23...transistor, 24...capacitor element, 25...pixel electrode, 29...first alignment film, 31...second substrate, 32...inorganic insulating layer, 33...common electrode, 34...second alignment film, 61...first portion, 62...second portion, 63...fifth portion, 70...connecting portion, 71...third portion, 72...fourth portion, 73...third portion, 74...fourth portion, 100...electro-optical device position, 221 to 299...insulating layer, 231...semiconductor layer, 231a...drain region, 231b...source region, 231c...channel region, 231d...lightly doped drain region, 231e...lightly doped source region, 232...gate electrode, 233...gate insulating film, 241...scanning line, 242...signal line, 2321...first gate portion, 2322...second gate portion, 2401...electrode, 2402...electrode, 2403...dielectric layer, A10...display region, A11...opening region, A12...light-shielding region, A20...peripheral region, P...pixel.

Claims

1. A substrate; A pixel electrode; a transistor disposed between the substrate and the pixel electrode, the transistor comprising a semiconductor layer having a source region, a drain region, and a channel region, and a gate electrode; a first light-shielding portion disposed between the semiconductor layer and the pixel electrode; the first light-shielding portion has a drain connection portion connected to the drain region, the semiconductor layer has a boundary between the channel region and the drain region, the drain region has a contact portion that is in contact with the first light-shielding portion and overlaps the first light-shielding portion in a plan view; a first distance between the contact portion and the substrate is shorter than a second distance between the boundary portion and the substrate; Electro-optical device characterized by:

2. the semiconductor layer extends in a first direction, the drain connection portion overlaps with the boundary portion when viewed in the first direction. The electro-optical device according to claim 1 .

3. the drain connection portion overlaps the drain region in a plan view, the first light-shielding portion has two portions extending in the first direction from the drain region in a plan view and provided so as to sandwich the lightly doped drain region of the semiconductor layer; each of the two portions overlaps with the boundary portion when viewed in a second direction that is a width direction of the semiconductor layer and intersects with the first direction; The electro-optical device according to claim 2 .

4. the semiconductor layer further includes a lightly doped drain region disposed between the drain region and the channel region; The lightly doped drain region corresponds to the boundary portion. The electro-optical device according to claim 1 .

5. the semiconductor layer has an inclined portion inclined with respect to the thickness direction of the substrate between the boundary portion and the contact portion; The electro-optical device according to claim 1 .

6. a second light-shielding portion disposed between the substrate and the semiconductor layer; the second light-shielding portion overlaps the boundary portion in a plan view; The electro-optical device according to claim 1 .

7. the second light-shielding portion is disposed in a recess provided in the substrate; 7. The electro-optical device according to claim 6.

8. the second light-shielding portion is disposed on a flat upper surface of the substrate; 7. The electro-optical device according to claim 6.

9. The second light-shielding portion is a gate potential.

7. The electro-optical device according to claim 6.

10. The electro-optical device according to any one of claims 1 to 9; and a control unit that controls the operation of the electro-optical device.

Images