Data input device and method for processing input data

Abstract

This invention provides a data input device capable of high-speed data transmission and a method for processing input data. [Solution] The detection circuit is connected to the input circuit and the training circuit and is used to set a second delay setting based on a first delay setting and the clock cycle of a first clock signal, the second delay setting includes a second data delay amount and a second clock delay amount, the data delay line is connected to the input circuit and the detection circuit and outputs a second data signal based on a first data signal and a second data delay amount, and the clock delay line is connected to the input circuit and the detection circuit and outputs a second clock signal based on a first clock signal and a second clock delay amount.

Description

Technical Field

[0001] The present invention relates to a data input device and a method for processing input data, and particularly to a data input device capable of high-speed transmission and a method for processing input data.

Background Art

[0002] In a circuit such as a memory circuit, a clock signal is usually used as an operation timing reference.

Summary of the Invention

Problems to be Solved by the Invention

[0003] However, the phase of the clock signal may shift due to changes in temperature, voltage, etc., and as a result, the error rate of the memory circuit when sampling input data may increase.

Means for Solving the Problems

[0004] In view of the above problems, the present invention has the following configuration. That is, in a data input device including an input circuit, a training circuit, a detection circuit, a data delay line, and a clock delay line, the input circuit is used to receive a first data signal and a first clock signal, the training circuit is connected to the input circuit and is used to set a first delay setting based on the first data signal and the first clock signal. The first delay setting includes a first data delay amount and a first clock delay amount, the detection circuit is connected to the input circuit and the training circuit and is used to set a second delay setting based on the first delay setting and the clock cycle of the first clock signal. The second delay setting includes a second data delay amount and a second clock delay amount, the data delay line is connected to the input circuit and the detection circuit and outputs a second data signal based on the first data signal and the second data delay amount, The clock delay line is connected to the input circuit and the detection circuit, and outputs a second clock signal based on the first clock signal and the second clock delay amount.

[0005] Furthermore, the clock cycle includes a plurality of delay unit time grids, and the detection circuit sets the second delay setting based on the first delay setting and the number of the plurality of delay unit time grids included in the clock cycle.

[0006] Furthermore, when the setting of the first delay setting is completed, the detection circuit detects the number of the plurality of delay unit time grids included in the clock cycle at that time and records it as the first number. In addition, the detection circuit subsequently detects the number of the plurality of delay unit time grids included in the clock cycle in real time. If the detection circuit finds that the number of the plurality of delay unit time grids included in the clock cycle is different from the first number, the detection circuit sets the recorded and detected number of the plurality of delay unit time grids included in the clock cycle as the second number, and sets the second delay setting based on the first delay setting, the first number, and the second number.

[0007] Furthermore, the first data delay amount, the first clock delay amount, the second data delay amount, and the second clock delay amount each include a plurality of the delay unit time grids. The detection circuit adjusts the number of delay unit time grids of the first data delay amount based on the first number and the second number in order to obtain the second data delay amount, and the detection circuit adjusts the number of delay unit time grids of the first clock delay amount based on the first number and the second number in order to obtain the second clock delay amount.

[0008] Furthermore, the detection circuit adjusts the number of the multiple delay unit time grids of the first data delay amount in order to obtain the second data delay amount based on the ratio of the second number to the first number. The detection circuit adjusts the number of delay unit time grids of the first clock delay amount based on the ratio of the second number to the first number in order to obtain the second clock delay amount.

[0009] Furthermore, the detection circuit obtains the second data delay amount by multiplying the number of delay unit time grids of the first data delay amount by the ratio of the second number to the first number, and the detection circuit obtains the second clock delay amount by multiplying the number of delay unit time grids of the first clock delay amount by the ratio of the second number to the first number.

[0010] Furthermore, the delay unit time grid corresponds to a delay unit, and the delay unit is a buffer.

[0011] Furthermore, it receives the first data signal and the first clock signal. Based on the first data signal and the first clock signal, a first delay setting is set, the first delay setting includes a first data delay amount and a first clock delay amount. Based on the first delay setting and the clock cycle of the first clock signal, a second delay setting is set, the second delay setting includes a second data delay amount and a second clock delay amount. Based on the first data signal and the second data delay amount, a second data signal is output. A second clock signal is output based on the first clock signal and the second clock delay amount.

[0012] Furthermore, the clock cycle includes a plurality of delay unit time grids, and the step of setting the second delay setting based on the first delay setting and the clock cycle of the first clock signal is: This includes setting a second delay setting based on the first delay setting and the number of the plurality of delay unit time grids included in the clock cycle.

[0013] Furthermore, the step of setting the second delay setting based on the first delay setting and the clock cycle of the first clock signal is: When the setting of the first delay setting is completed, the number of the multiple delay unit time grids included in the clock cycle at that time is detected and recorded as the first number. In addition, the number of the multiple delay unit time grids included in the clock cycle is then detected in real time. When the number of delay unit time grids included in the clock cycle differs from the first number, the number of delay unit time grids included in the clock cycle that is recorded and detected is set as the second number. This includes setting a second delay setting based on the first delay setting, the first number, and the second number.

[0014] Furthermore, the first data delay amount, the first clock delay amount, the second data delay amount, and the second clock delay amount each include a plurality of the delay unit time grids. The step of setting the second delay setting based on the first delay setting, the first number, and the second number is: In order to obtain the second data delay amount, the number of the plurality of delay unit time grids of the first data delay amount is adjusted based on the first number and the second number, To obtain the second clock delay amount, the method includes adjusting the number of delay unit time grids of the first clock delay amount based on the first number and the second number.

[0015] Furthermore, the step of setting the second delay setting based on the first delay setting, the first number, and the second number is: To obtain the second data delay amount, the number of the multiple delay unit time grids of the first data delay amount is adjusted based on the ratio of the second number to the first number. To obtain the second clock delay amount, it includes adjusting the number of the plurality of delay unit time grids of the first clock delay amount based on the ratio of the second number to the first number.

[0016] Also, the step of setting the second delay setting based on the first delay setting, the first number, and the second number is To obtain the second data delay amount, multiplying the number of the plurality of delay unit time grids of the first data delay amount by the ratio of the second number to the first number To obtain the second clock delay amount, it includes multiplying the number of the plurality of delay unit time grids of the first clock delay amount by the ratio of the second number to the first number.

[0017] Also, the delay unit time grid corresponds to a delay unit, and the delay unit is a buffer.

Brief Description of Drawings

[0018] [Figure 1] It is a schematic diagram of an embodiment of a data input device and an output circuit. [Figure 2] It is a flowchart for explaining an embodiment of a method for processing input data according to the present invention. [Figure 3A] It is a schematic diagram of an embodiment when an output circuit outputs a first data signal and a first clock signal. [Figure 3B] It is a schematic diagram of an embodiment when an input circuit receives a first data signal and a first clock signal. [Figure 4A] It is a schematic diagram of an embodiment of a training process of a training circuit. [Figure 4B] It is a schematic diagram of an embodiment of a training process of a training circuit. [Figure 4C] It is a schematic diagram of an embodiment of a training process of a training circuit. [Figure 5]This is a schematic diagram of an embodiment of the first data signal and the first clock signal after the training process and after being affected by temperature and voltage. [Figure 6] This is a schematic diagram of an embodiment of the clock cycle. [Figure 7] This is a flowchart of the embodiment in step S03. [Modes for carrying out the invention]

[0019] The detailed features and advantages of this application will be described in detail in the following embodiments. Furthermore, the content will be sufficient for those skilled in the art to understand the technical content of this application and implement it accordingly. Based on the content described in the specification, scope, and drawings of this application, those skilled in the art will readily understand the purposes and advantages related to this application.

[0020] Embodiments of the present invention will be described with reference to Figure 1. The data input device 1 includes an input circuit 10, a training circuit 11, a detection circuit 12, a data delay line 13, and a clock delay line 14.

[0021] The training circuit 11 is connected to the input circuit 10, the detection circuit 12, the data delay line 13, and the clock delay line 14. The detection circuit 12 is connected to the input circuit 10, the training circuit 11, the data delay line 13, and the clock delay line 14.

[0022] Furthermore, in several embodiments, the data input device 1 may be applied to a transmission interface. Examples include, but are not limited to, memory transmission interfaces such as dynamic random access memory (DRAM) and die-to-die transmission interfaces, and the data input device 1 can be applied to any transmission interface. In addition, the data input device 1 can be realized in the form of a chip through an integrated circuit manufacturing process.

[0023] Next, we will explain with reference to Figures 1 and 2. Here, Figure 2 is a flowchart illustrating an embodiment of the input data processing method according to the present invention. The input circuit 10 is used to receive a first data signal D1 and a first clock signal CK from the output circuit 2 (step S01). Next, we will explain with reference to Figure 3A. Here, Figure 3A is a schematic diagram of an embodiment in which the output circuit outputs the first data signal and the first clock signal. In some embodiments, the first data signal D1 includes multiple data.

[0024] For the sake of explanation, in Figure 3A, the first data signal D1 is assumed to contain only three data points: D01, D11, and D21. However, the number of data points included in the first data signal D1 is not limited to these.

[0025] In this embodiment, when the first data signal D1 and the first clock signal CK are output from the output circuit 2, the positive edge and / or negative edge of the first clock signal CK are located at (hit) the center position of each data contained in the first data signal D1.

[0026] Figure 3A shows an embodiment in which the positive edge of the first clock signal CK is located at the center position of each data contained in the first data signal D1.

[0027] The explanation will be given with reference to Figure 3B. Here, Figure 3B is a schematic diagram of an embodiment in which the input circuit receives the first data signal and the first clock signal. In some embodiments, when the input circuit 10 receives the first data signal D1 and the first clock signal CK, a skew T1 occurs between the first data signal D1 and the first clock signal CK.

[0028] Skew T1 prevents the positive edge of the first clock signal CK from accurately hitting the center position of each data contained in the first data signal D1. In the embodiment of Figure 3B, skew T1 causes the first data signal D1 to be faster than the first clock signal CK, and the first positive edge of the first clock signal CK hits data D11 instead of the expected data D01.

[0029] In some embodiments, the output circuit 2 may be a memory circuit. In other embodiments, the output circuit 2 may be a volatile storage medium, a non-volatile storage medium, or a combination thereof.

[0030] Volatile memory media include random access memories such as random access memory (RAM), static random access memory (SRAM), or dynamic random access memory (DRAM).

[0031] Non-volatile storage media include ROM, programmable read-only memory (PROM), EPROM, EEPROM, one-time PROM (OTPROM), or flash memory. The type of output circuit 2 is not limited.

[0032] In some embodiments, the first clock signal CK may be a global clock generated by a clock source (such as an oscillator, but not limited thereto). Furthermore, the first clock signal CK may be delayed through a clock tree, but the present invention is not limited to this.

[0033] In some embodiments, the transmission speed of the first data signal D1 and the first clock signal CK may be 16 Gbps or 32 Gbps, but is not limited to these.

[0034] In this embodiment, the skew T1 is caused by the physical metal wire between the output circuit 2 and the input circuit 10.

[0035] In several embodiments, the training circuit 11 is used to perform a training process in which a first delay setting A (step S02) is set based on a first data signal D1 and a first clock signal CK in order to correct the skew T1.

[0036] The first delay setting A includes a first data delay amount A1 and a first clock delay amount A2. See Figures 4A to 4C. Here, Figures 4A to 4C are schematic diagrams of embodiments of the training process of the training circuit, respectively.

[0037] In several embodiments, during the training process of the training circuit 11, as shown in Figure 4C, to cause the positive or negative edge of the first clock signal CK to hit the center position of the current data D01 of the first data signal D1, the data input device 1 can detect the relationship between the first data signal D1 and the first clock signal CK using the training circuit 11, and set the first data delay amount A1 and the first clock delay amount A2 accordingly.

[0038] Of these, the data pattern of the first data signal D1 input to the training process is known to the training circuit 11.

[0039] For example, if the data pattern of the first data signal D1 is "010" and the current data D01 is "1", the relationship between the first data signal D1 and the first clock signal CK can be shown in Figure 4A.

[0040] First, the training circuit 11 may adjust the left index G1 and the right index G2 respectively up to the boundary of the current data D01.

[0041] Of these, the training circuit 11 can determine whether the current data D01 has been adjusted to the left boundary based on whether the data sampled by the left index G1 is "0". It also determines whether the current data D01 has been adjusted to the right boundary based on whether the data sampled by the right index G2 is "0".

[0042] After the left index G1 and the right index G2 are adjusted to match the boundaries of the current data D01, the training circuit 11 can obtain the data width of the current data D01 based on the distance between the left index G1 and the right index G2, and determine the center position of the current data D01 based on that data width, as shown in Figure 4B.

[0043] Subsequently, the training circuit 11 completes the training process of the data input device 1 by setting the first data delay amount A1 and the first clock delay amount A2 based on the determined center position.

[0044] Here, the training circuit 11 increases the delay amount of the first data signal D1 (first data delay amount A1), as shown in Figure 4(c). In some embodiments, the initial values ​​of the first data delay amount A1 and the first clock delay amount A2 are both 0 seconds (s).

[0045] In Figures 3B and 4A-4C, the first data signal D1 is faster than the skew T1 of the first clock signal CK, but the present invention is not limited to this.

[0046] In some embodiments, the skew T1 may cause the first clock signal CK to be faster than the first data signal D1.

[0047] In some embodiments, if the skew T1 causes the first clock signal CK to be faster than the first data signal D1, the training circuit 11 increases the delay amount of the first clock signal CK (i.e., the first clock delay amount A2).

[0048] By executing the training process via the training circuit 11, the training circuit 11 can determine the time length of the skew T1, and in addition, the first data delay amount A1 or the first clock delay amount A2 increases according to the time length of the skew T1.

[0049] For example, if the time length of the skew T1 shown in Figure 3B is 200 picoseconds (ps), then the first data signal D1 is faster than the first clock signal CK. Therefore, when the training circuit 11 executes the training process, the training circuit 11 sets the first data delay A1 to 200 ps.

[0050] In some embodiments, after the training circuit 11 obtains a first delay setting A, the training circuit 11 transmits a first data delay amount A1 to the data delay line 13 and a first clock delay amount A2 to the clock delay line 14.

[0051] The data delay line 13 outputs the first data signal D1 to a data processing unit (not shown) after increasing the delay amount based on the first data delay amount A1, based on the first data signal D1 and the first data delay amount A1.

[0052] The clock delay line 14 outputs the first clock signal CK to the data processing unit after increasing the delay amount according to the first clock delay amount A2, based on the first clock signal CK and the first clock delay amount A2.

[0053] At this time, the positive and / or negative edges of the first clock signal CK output by the clock delay line 14 precisely coincide with the center position of each data contained in the first data signal D1 output by the data delay line 13.

[0054] However, in several embodiments, during the operation of the data input device 1, after the skew T1 is corrected by the training circuit 11, the generated first clock signal CK and the first clock signal CK may generate a new skew T2 due to the influence of fluctuations in temperature, voltage, etc.

[0055] Next, we will explain with reference to Figure 5. Here, Figure 5 is a schematic diagram of an embodiment of the first data signal and the first clock signal after the training process and after being affected by temperature and voltage. When there is skew T2, the positive edge of the first clock signal CK, corrected for skew T1, no longer correctly hits the center position of each data in the first data signal D1, corrected for skew T1.

[0056] In the embodiment shown in Figure 5, the skew T2 causes the first clock signal CK, after correcting for the skew T1, to be faster than the first data signal D1, after correcting for the skew T1. As a result, the positive edge of the first clock signal CK, after correcting for the skew T1, cannot correctly reach the expected data.

[0057] In other words, the first data delay A1 and the first clock delay A2 set by the training circuit 11 to compensate for the skew T1 at this time cannot cope with the effects generated by the skew T2.

[0058] In several embodiments, the detection circuit 12 is used to set a second delay setting B (step S03) based on a first delay setting A and the clock cycle T of the first clock signal CK in order to compensate for the skew T2.

[0059] The second delay setting B includes a second data delay amount B1 and a second clock delay amount B2. See Figure 6, which is a schematic diagram of an embodiment of the clock cycle.

[0060] In this embodiment, the clock cycle T includes a plurality of delay unit time grids d. The detection circuit 12 is used to set a second delay setting B based on the first delay setting A and the number of delay unit time grids d included in the clock cycle T.

[0061] In some embodiments, the delay unit time grid d corresponds to a delay unit.

[0062] The number of delay unit time grids d included in a clock cycle T represents the time required for a signal to pass through multiple delay units, which are determined by the number of delay unit time grids d included in the clock cycle T.

[0063] For example, suppose the number of delay unit time grids d included in a clock cycle T is 100. The length of the clock cycle T is the time required for a signal to pass through 100 delay units. In some embodiments, the delay units are buffers.

[0064] Next, we will explain with reference to Figure 7. In some embodiments, when the detection circuit 12 executes step S03, the detection circuit 12 first completes the first delay setting A in the training circuit 11, and at that time detects the number of multiple delay unit time grids d included in the clock cycle T and records it as a first number (step S031). Then, the number of multiple delay unit time grids d included in the clock cycle T is detected in real time.

[0065] When the detection circuit 12 detects that the number of delay unit time grids d included in the clock cycle T is different from the first number, the detection circuit 12 records that the detected number of delay unit time grids d included in the clock cycle T is the second number (step S032).

[0066] Next, the detection circuit 12 sets a second delay setting B based on the first delay setting A, the first number, and the second number (step S033).

[0067] For example, assuming that the training circuit 11 has completed the first delay setting A, the number of delay unit time grids d included in the clock cycle T is 100, and the detection circuit 12 detects and records 100 as the first value. After recording 100 as the first number, it then detects the number of delay unit time grids d included in the clock cycle T in real time.

[0068] When the detection circuit 12 detects that the number of delay unit time grids d included in the clock cycle T is 80, it records that the detected 80 is the second number because 80 is different from the first number (i.e., 100).

[0069] The detection circuit 12 then sets a second delay setting B based on a first delay setting A, a first number (i.e., 100), and a second number (i.e., 80).

[0070] The number of delay unit time grids d included in a clock cycle T differs from time to time (i.e., the values ​​of the first and second numbers are different) because the delay units are affected by fluctuations in temperature, voltage, etc.

[0071] For example, if we assume the first number is 100 and the second number is 80, this means that the length of the clock cycle T changes from the time it takes for the signal to pass through 100 delay units to the time it takes for the signal to pass through 80 delay units.

[0072] In other words, this means that the time required for a signal to pass through a single delay unit increases, and the reason why it takes time for a signal to pass through a single delay unit is that the delay unit is affected by changes in temperature, voltage, etc.

[0073] If the length of the clock cycle T at this time is 200 ps, ​​then because the time length of the clock cycle T is fixed, the time required for the signal to pass through a single delay unit is 2 ps (200 ps / 100 = 2 ps) when the number of delay unit time grids d included in the clock cycle T is the first number, and the time required for the signal to pass through a single delay unit is 2.5 ps (200 ps / 80 = 2.5 ps) when the number of delay unit time grids d included in the clock cycle T is the second number.

[0074] In some embodiments, the first data delay A1, the first clock delay A2, the second data delay B1, and the second clock delay B2 also include a plurality of delay unit time grids d.

[0075] Similarly, the number of delay unit time grids d included in the first data delay A1, the first clock delay A2, the second data delay B1, and the second clock delay B2 represents the time required for the signal to pass through multiple delay units corresponding to the number of delay unit time grids d included in the first data delay A1, the first clock delay A2, the second data delay B1, and the second clock delay B2.

[0076] In some embodiments, the training circuit 11 sets the first data delay amount A1 and the first clock delay amount A2 by setting the number of delay unit time grids d included in the first data delay amount A1 and the first clock delay amount A2.

[0077] Taking Figure 3B as an example, if the time length of the skew T1 shown in Figure 3B is 200 ps, ​​then the first data signal D1 is faster than the first clock signal CK. Therefore, after the training circuit 11 executes the training process, if the time required for the signal to pass through one delay unit is 2 ps, the training circuit 11 sets the number of delay unit time grids d included in the first data delay amount A1 to 100. Thus, the time length of the first data delay amount A1 becomes 200 ps.

[0078] In particular, when a delay unit is affected by fluctuations in temperature, voltage, etc., the time required for a signal to pass through a single delay unit changes, and the skew generated by the number of delay unit time grids d included in the first data delay amount A1 and the first clock delay amount A2 set by the training circuit 11 becomes skew T2.

[0079] Similar to the example above, when the delay unit is affected by fluctuations in temperature, voltage, etc., and the time required for a signal to pass through a single delay unit increases from 2 ps to 2.5 ps, the number of delay unit time grids d included in the first data delay amount A1 is 100. Therefore, the time length of the first data delay amount A1 becomes 250 ps (2.5 ps × 100 = 250 ps) instead of the originally planned 200 ps. As a result, the first data signal D1 after correction by skew T1 is delayed too much, and the first clock signal CK after correction by skew T1 is 50 ps faster than the first data signal D1 after correction by skew T1. Here, the 50 ps difference caused by changes in temperature, voltage, etc. is the skew T2.

[0080] In some embodiments, when the detection circuit 12 performs step S033, the detection circuit 12 adjusts the number of delay unit time grids d of the first data delay amount A1 based on a first number and a second number to obtain a second data delay amount B1.

[0081] Then, the detection circuit 12 adjusts the number of delay unit time grids d of the first clock delay amount A2 based on the first and second numbers to obtain the second clock delay amount B2.

[0082] For example, if the first number is 100, the second number is 80, the clock cycle T time length is 200 ps, ​​and the number of delay unit time grids d in the first data delay A1 is 100, then the time required for a signal to pass through one delay unit increases from 2 ps (200 ps / 100 = 2 ps) to 2.5 ps (200 ps / 80 = 2.5 ps). Therefore, if the number of delay unit time grids d included in the first data delay A1 is 100, the length of the first data delay A1 becomes 250 ps (2.5 ps × 100 = 250 ps) instead of the originally planned 200 ps.

[0083] Therefore, in order to maintain the time length of the delay amount at 200 ps, ​​the detection circuit 12 adjusts the number of delay unit time grids d of the first data delay amount A1 to 80, and the first data delay amount A1 in which the number of delay unit time grids d included is 80 is the second data delay amount B1.

[0084] In some embodiments, when the detection circuit 12 performs step S033, the detection circuit 12 adjusts the number of delay unit time grids d of the first data delay amount A1 based on the ratio of the second number to the first number to obtain a second data delay amount B1.

[0085] Then, the detection circuit 12 adjusts the number of delay unit time grids d of the first clock delay amount A2 based on the ratio of the second number to the first number, thereby obtaining the second clock delay amount B2.

[0086] In some embodiments, the detection circuit 12 obtains a second data delay amount B1 by multiplying the number of delay unit time grids d of the first data delay amount A1 by the ratio of the second number to the first number.

[0087] The detection circuit 12 then obtains the second clock delay amount B2 by multiplying the number of delay unit time grids d of the first clock delay amount A2 by the ratio of the second number to the first number.

[0088] For example, if we assume the first number is 100 and the second number is 80, and the number of delay unit time grids d included in the first data delay amount A1 is 100, then the detection circuit 12 obtains a second data delay amount B1 with a number of delay unit time grids d included in the first data delay amount A1 of 80 (100 × 0.8 = 80) by multiplying the number of delay unit time grids d included in the first data delay amount A1 (i.e., 100) by the ratio of the second number to the first number (i.e., 0.8).

[0089] In Figure 5, the first data signal D1 after correction for skew T1 is excessively delayed due to skew T2, so the first clock signal CK after correction for skew T1 is faster than the first data signal D1 after correction for skew T1. However, the present invention is not limited to this.

[0090] In several embodiments, the skew T2 may cause the first clock signal CK, after correcting for the skew T1, to be excessively delayed, while the first data signal D1, after correcting for the skew T1, is faster than the first clock signal CK, after correcting for the skew T1.

[0091] In several embodiments, the data delay line 13 is used to output a second data signal D2, which is provided to a data processing unit (not shown), based on a first data signal D1 and a second data delay amount B1 (step S04).

[0092] The clock delay line 14 is used to output a second clock signal CK2 to be supplied to the data processing unit, based on the first clock signal CK and the second clock delay amount B2 (step S05).

[0093] At this time, the positive and / or negative edges of the second clock signal CK2 output by the clock delay line 14 precisely hit the center position of each data contained in the second data signal D2 output by the data delay line 13.

[0094] In short, the data input device 1 of the present invention can perform an input data processing method according to any embodiment on a first data signal D1 and a first clock signal CK, and the positive edge and / or negative edge of the second clock signal CK2 can be at the center position of each data included in the second data signal D2.

[0095] Furthermore, even if there is a skew T2 due to changes in temperature, voltage, etc., the data input device 1 that executes the input data processing method of this embodiment can correct the skew T2 without interrupting data transmission, thereby enabling high-speed data transmission.

[0096] As described above, the technical content of this application has been explained with reference to preferred embodiments. However, these embodiments are not intended to limit the technical scope of this application. Any minor changes or modifications made by those skilled in the art without departing from the spirit of this application should be interpreted as being included in the technical scope, and the technical scope of this application shall be determined based on the claims. [Explanation of Symbols]

[0097] 1. Data input device 2 Output Circuits 10 Input Circuits 11 Training Circuits 12 Detection Circuit 13 Data delay line 14 Clock delay line A First delay setting B. Second delay setting A1 First data delay amount A2 First clock delay amount B1 Second data delay amount B2 Second clock delay amount D1 First data signal CK First clock signal D2 Second data signal CK2 Second clock signal Steps S01-S05, S031-S033 D01, D11, D21 data T1, T2 Skew G1, G2 indicators T Clock cycle d Delay unit time grid

Claims

1. In a data input device including an input circuit, a training circuit, a detection circuit, a data delay line, and a clock delay line, The input circuit is used to receive a first data signal and a first clock signal. The training circuit is connected to the input circuit and is used to set a first delay setting based on the first data signal and the first clock signal, the first delay setting includes a first data delay amount and a first clock delay amount. The detection circuit is connected to the input circuit and the training circuit and is used to set a second delay setting based on the first delay setting and the clock cycle of the first clock signal, the second delay setting includes a second data delay amount and a second clock delay amount. The data delay line is connected to the input circuit and the detection circuit, and outputs a second data signal based on the first data signal and the second data delay amount. The clock delay line is connected to the input circuit and the detection circuit, and the data input device outputs a second clock signal based on the first clock signal and the second clock delay amount.

2. The data input device according to claim 1, wherein the clock cycle includes a plurality of delay unit time grids, and the detection circuit sets a second delay setting based on the first delay setting and the number of the plurality of delay unit time grids included in the clock cycle.

3. When the setting of the first delay setting is completed, the detection circuit detects the number of the plurality of delay unit time grids included in the clock cycle at that time and records it as the first number, and thereafter detects the number of the plurality of delay unit time grids included in the clock cycle in real time, and when the detection circuit finds that the number of the plurality of delay unit time grids included in the clock cycle is different from the first number, the detection circuit sets the number of the plurality of delay unit time grids included in the clock cycle that it has recorded and detected as the second number, and thereafter sets the second delay setting based on the first delay setting, the first number, and the second number, as described in claim 2.

4. The data input device according to claim 3, wherein the first data delay amount, the first clock delay amount, the second data delay amount, and the second clock delay amount each include a plurality of delay unit time grids, the detection circuit adjusts the number of the plurality of delay unit time grids of the first data delay amount based on the first number and the second number in order to obtain the second data delay amount, and the detection circuit adjusts the number of the plurality of delay unit time grids of the first clock delay amount based on the first number and the second number in order to obtain the second clock delay amount.

5. The detection circuit adjusts the number of the plurality of delay unit time grids of the first data delay amount in order to obtain the second data delay amount based on the ratio of the second number to the first number, and the detection circuit adjusts the number of the plurality of delay unit time grids of the first clock delay amount in order to obtain the second clock delay amount based on the ratio of the second number to the first number, the data input device according to claim 4.

6. The data input device according to claim 5, wherein the detection circuit multiplies the number of delay unit time grids of the first data delay amount by the ratio of the second number to the first number in order to obtain the second data delay amount, and the detection circuit multiplies the number of delay unit time grids of the first clock delay amount by the ratio of the second number to the first number in order to obtain the second clock delay amount.

7. The data input device according to claim 6, wherein the delay unit time grid corresponds to a delay unit, and the delay unit is a buffer.

8. The first data signal and the first clock signal are received. Based on the first data signal and the first clock signal, a first delay setting is set, the first delay setting includes a first data delay amount and a first clock delay amount. Based on the first delay setting and the clock cycle of the first clock signal, a second delay setting is set, the second delay setting includes a second data delay amount and a second clock delay amount. Based on the first data signal and the second data delay amount, a second data signal is output. A method for processing input data to output a second clock signal based on the first clock signal and the second clock delay amount.

9. The step of setting the second delay setting based on the first delay setting and the clock cycle of the first clock signal, wherein the clock cycle includes a plurality of delay unit time grids, The input data processing method according to claim 8, comprising setting a second delay setting based on the first delay setting and the number of the plurality of delay unit time grids included in the clock cycle.

10. The step of setting the second delay setting based on the first delay setting and the clock cycle of the first clock signal is: When the setting of the first delay setting is completed, the number of the plurality of delay unit time grids included in the clock cycle at that time is detected and recorded as the first number, and thereafter the number of the plurality of delay unit time grids included in the clock cycle is detected in real time, When the number of delay unit time grids included in the clock cycle is different from the first number, the number of delay unit time grids included in the clock cycle that is recorded and detected is set to the second number. The method for processing input data according to claim 9, comprising setting a second delay setting based on the first delay setting, the first number, and the second number.

11. The first data delay amount, the first clock delay amount, the second data delay amount, and the second clock delay amount each include a plurality of the delay unit time grids, The step of setting the second delay setting based on the first delay setting, the first number, and the second number is: In order to obtain the second data delay amount, the number of the plurality of delay unit time grids of the first data delay amount is adjusted based on the first number and the second number, The input data processing method according to claim 10, comprising adjusting the number of delay unit time grids of the first clock delay amount based on the first number and the second number in order to obtain the second clock delay amount.

12. The step of setting the second delay setting based on the first delay setting, the first number, and the second number is: In order to obtain the second data delay amount, the number of delay unit time grids of the first data delay amount is adjusted based on the ratio of the second number to the first number. The input data processing method according to claim 11, comprising adjusting the number of delay unit time grids of the first clock delay amount based on the ratio of the second number to the first number in order to obtain the second clock delay amount.

13. The step of setting the second delay setting based on the first delay setting, the first number, and the second number is: In order to obtain the second data delay amount, the number of delay unit time grids of the first data delay amount is multiplied by the ratio of the second number to the first number. The input data processing method according to claim 12, comprising multiplying the number of delay unit time grids of the first clock delay amount by the ratio of the second number to the first number in order to obtain the second clock delay amount.

14. The method for processing input data according to claim 13, wherein the delay unit time grid corresponds to a delay unit, and the delay unit is a buffer.

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