Isolator

Abstract

The objective is to provide an isolator that can be miniaturized. [Solution] The isolator of the embodiment comprises a substrate, a first chip, and a second chip. The substrate has an insulating layer and a pair of coils. The pair of coils face each other in the thickness direction via the insulating layer. The first chip is positioned facing one side of the substrate. The first chip is connected to one of the pair of coils. The second chip is positioned facing the other side of the substrate. The second chip is connected to the other of the pair of coils.

Description

Technical Field

[0001] Embodiments of the present invention relate to isolators.

Background Art

[0002] An isolator that transmits a signal from a transmission-side circuit to a reception-side circuit in an insulated state between the transmission-side circuit and the reception-side circuit is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide an isolator that can be miniaturized.

Means for Solving the Problems

[0005] The isolator of the embodiment has a substrate portion, a first chip, and a second chip. The substrate portion has an insulating layer and a pair of coils. The pair of coils face each other in the thickness direction through the insulating layer. The first chip is disposed to face one surface of the substrate portion. The first chip is connected to one of the pair of coils. The second chip is disposed to face the other surface of the substrate portion. The second chip is connected to the other of the pair of coils.

Brief Description of the Drawings

[0006] [Figure 1] Plan view of the isolator of the embodiment. [Figure 2] Cross-sectional view of the isolator package according to the isolator of the embodiment. [Figure 3] Perspective view of the substrate portion according to the isolator of the embodiment. [Figure 4] A perspective view of the substrate portion of the isolator according to the embodiment. [Figure 5] Cross-sectional view of the substrate portion relating to the isolator of the embodiment. [Figure 6] Cross-sectional view of the substrate portion of the modified isolator. [Modes for carrying out the invention]

[0007] The isolator of the embodiment will be described below with reference to the drawings.

[0008] (First embodiment) The configuration of the isolator 10 in the first embodiment will be described below. Figure 1 is a plan view showing an example of the planar layout of the isolator 10 according to the embodiment. Figure 2 is a cross-sectional view of the isolator package 1 according to the embodiment.

[0009] As shown in Figure 2, the isolator package 1 comprises an isolator 10 and a package member 50. The package member 50 is made of, for example, an insulating resin material. The package member 50 seals the isolator 10 and protects it from the outside.

[0010] The isolator 10 is a so-called digital isolator. The isolator 10 comprises a plurality of first terminal sections 11, a plurality of second terminal sections 12, a first semiconductor chip (first chip) 21, a second semiconductor chip (second chip) 22, and a substrate section 40.

[0011] The circuit board 40 is plate-shaped. The circuit board 40 is a module that functions as a digital isolator. A transformer is mounted on the circuit board 40. The circuit board 40 is configured to transmit signals while insulating the transmitting circuit (primary circuit) and the receiving circuit (secondary circuit) using the transformer. Details of the configuration of the circuit board 40 will be described later.

[0012] Hereinafter, the plane parallel to the surface of the substrate portion 40 will be defined as the XY plane. The directions that intersect each other perpendicularly within the XY plane will be defined as the X-axis direction and the Y-axis direction. In particular, in the isolator 10, the direction in which the terminal portions 11 and 12 extend will be defined as the X-axis direction. Furthermore, the direction that intersects the XY plane will be defined as the Z-axis direction. The Z-axis direction coincides with the thickness direction of the substrate portion 40. In addition, the Z-axis direction coincides with the thickness direction of the first semiconductor chip 21, the second semiconductor chip 22, and the substrate portion 40.

[0013] In the following description, the side of the substrate 40 on which the second semiconductor chip 22 is placed will be referred to as the upper side (+Z), and the opposite side on which the first semiconductor chip 21 is placed will be referred to as the lower side (-Z). Note that the orientation of the isolator package 1 when in use is not limited to the above-mentioned vertical direction.

[0014] The substrate portion 40 has an upper surface 40b facing upward (+Z) and a lower surface 40a facing downward (-Z). The second semiconductor chip 22 is fixed to the upper surface 40b of the substrate portion 40 via an insulating adhesive 32. The first semiconductor chip 21 is fixed to the lower surface 40a of the substrate portion 40 via an insulating adhesive 31. The insulating adhesives 31 and 32 temporarily fix the first semiconductor chip 21 and the second semiconductor chip 22 to the substrate portion 40 until the isolator 10 is wrapped in the package member 50 and fixed in place during the manufacturing process.

[0015] The substrate portion 40 is electrically connected to the first semiconductor chip 21 and the second semiconductor chip 22 via bump portions BP. The substrate portion 40 and the first semiconductor chip 21 and the second semiconductor chip 22 are connected, for example, by flip-chip bonding. The bump portions BP are formed, for example, by soldering.

[0016] As shown in Figure 1, the first semiconductor chip 21 and the second semiconductor chip 22 overlap each other when viewed from the thickness direction (Z-axis direction) of the substrate portion 40. The substrate portion 40 is sandwiched between the first semiconductor chip 21 and the second semiconductor chip 22.

[0017] As shown in FIG. 2, a plurality of first terminal portions 11 and a plurality of second terminal portions 12 are connected to the lower surface 40a of the substrate portion 40 via solder portions SD. Thereby, the substrate portion 40 is electrically connected to the plurality of first terminal portions 11 and the plurality of second terminal portions 12.

[0018] A circuit 21a is formed on the first semiconductor chip 21. The circuit 21a includes a signal transmission / reception circuit and a modulation / demodulation circuit. The circuit 21a is electrically connected to the substrate portion 40 via bump portions BP connected to the upper surface of the first semiconductor chip 21.

[0019] A circuit 22a is formed on the second semiconductor chip 22. The circuit 22a includes a signal transmission / reception circuit and a modulation / demodulation circuit. The circuit 22a is electrically connected to the substrate portion 40 via bump portions BP connected to the lower surface of the second semiconductor chip 22.

[0020] The plurality of first terminal portions 11 and the plurality of second terminal portions 12 are plate-like metal members extending along the XY plane. The plurality of first terminal portions 11 and the plurality of second terminal portions 12 are connected to the substrate portion 40 on their upper surfaces respectively. The plurality of first terminal portions 11 and the plurality of second terminal portions 12 are made of a single plate material. The plurality of first terminal portions 11 and the plurality of second terminal portions 12 are divided from each other by cutting off the relay portions after being connected to the substrate portion 40 respectively.

[0021] As shown in FIG. 1, the solder portions SD for connecting the first terminal portions 11 to the substrate portion 40 and the solder portions SD for connecting the second terminal portions 12 to the substrate portion 40 are arranged at the opposite ends of the substrate portion 40 in the X-axis direction. The solder portions SD for connecting the first terminal portions 11 to the substrate portion 40 and the solder portions SD for connecting the second terminal portions 12 to the substrate portion 40 are arranged at positions different from those of the first semiconductor chip 21 and the second semiconductor chip 22 when viewed from the thickness direction (Z-axis direction) of the substrate portion 40.

[0022] Figure 3 is a perspective view of the substrate portion 40 of this embodiment, viewed from diagonally above. Figure 4 is a perspective view of the substrate portion 40 of this embodiment, viewed from diagonally below. Figure 5 is a cross-sectional view of the substrate portion 40. In Figures 3 and 4, the insulating layer covering the first coil 43 and the second coil 44 is shown transparently to make the configuration of the first coil 43 and the second coil 44 easier to understand. Also, in Figure 5, the insulating adhesives 31 and 32 that fix the substrate portion 40 to the first semiconductor chip 21 and the second semiconductor chip 22 are not shown.

[0023] As shown in Figures 3 and 4, the substrate portion 40 of this embodiment is composed of a single substrate 41. The substrate 41 of this embodiment is a flexible substrate. However, the substrate 41 may be a rigid substrate. Alternatively, the substrate 41 may be a rigid-flexible substrate. The shape of the substrate 41 may be, for example, rectangular, but is not limited to rectangular, and any shape may be applied.

[0024] As shown in Figure 5, the substrate 41 is provided with a first coil 43, a second coil 44, a first wiring section 45, a second wiring section 46, and a plurality of pads P1, P2, P3, P4, P5, P6, P7, and P8. The first coil 43, the second coil 44, the first wiring section 45, the second wiring section 46, and the pads P1, P2, P3, P4, P5, P6, P7, and P8 are formed, for example, from copper foil or copper plating and are conductive.

[0025] The outer shape of the substrate 41 is formed by stacking multiple insulating layers 41a, 41b, 41c, 41d, 41e, 41f, and 41g. The multiple insulating layers 41a, 41b, 41c, 41d, 41e, 41f, and 41g are arranged from bottom to top in the order of the first insulating layer 41a, the second insulating layer 41b, the third insulating layer 41c, the fourth insulating layer 41d, the fifth insulating layer 41e, the sixth insulating layer 41f, and the sixth insulating layer 41g.

[0026] Of the multiple pads P1, P2, P3, P4, P5, P6, P7, and P8, the first pad P1, the second pad P2, the third pad P3, the fourth pad P4, and the fifth pad P5 (hereinafter referred to as the first to fifth pads) are provided inside the second insulating layer 41b, and the sixth pad P6, the seventh pad P7, and the eighth pad P8 (hereinafter referred to as the sixth to eighth pads P6, P7, and P8) are provided inside the sixth insulating layer 41f.

[0027] Of the first insulating layer 41a below the second insulating layer 41b, the portion that overlaps with the first to fifth pads P1, P2, P3, P4, and P5 when viewed in the thickness direction (Z-axis direction) has been removed. As a result, the first to fifth pads P1, P2, P3, P4, and P5 are exposed on the underside of the substrate portion 40. The first pad P1 is electrically connected to the first terminal portion 11 via the solder portion SD. Similarly, the fifth pad P5 is electrically connected to the second terminal portion 12 via the solder portion SD. The second pad P2, the third pad P3, and the fourth pad P4 are each electrically connected to the first semiconductor chip 21 via the bump portion BP.

[0028] As shown in Figure 4, the third pad P3 is electrically connected to the central end of the first coil 43. The fourth pad P4 is electrically connected to the outer peripheral end of the first coil 43. The third pad P3 and the fourth pad P4 have, for example, a rounded rectangular shape when viewed in the thickness direction (Z-axis direction). However, the shape of the third pad P3 and the fourth pad P4 is not limited to this.

[0029] As shown in Figure 5, the portion of the seventh insulating layer 41g above the sixth insulating layer 41f that overlaps with the sixth to eighth pads P6, P7, and P8 in the thickness direction (Z-axis direction) has been removed. As a result, the sixth to eighth pads P6, P7, and P8 are exposed on the upper side of the substrate portion 40. The sixth to eighth pads P6, P7, and P8 are electrically connected to the second semiconductor chip 22 via bump portions BP.

[0030] As shown in Figure 3, the sixth pad P6 is electrically connected to the central end of the second coil 44. The seventh pad P7 is electrically connected to the outer peripheral end of the second coil 44. The sixth pad P6 and the seventh pad P7 may have different shapes and sizes from, for example, the third pad P3 and the fourth pad P4 when viewed in the thickness direction (Z-axis direction). More specifically, if each of the third pad P3 and the fourth pad P4 is rectangular, each of the sixth pad P6 and the seventh pad P7 may be, for example, circular, and may be larger than each of the third pad P3 and the fourth pad P4.

[0031] The third pad P3 and the sixth pad P6 are positioned to overlap each other when viewed in the thickness direction (Z-axis direction). The fourth pad P4 and the seventh pad P7 are positioned to overlap each other when viewed in the thickness direction (Z-axis direction).

[0032] As shown in Figure 3, a dummy pad Pdm may be provided on the substrate portion 40. The dummy pad Pdm is provided inside the sixth insulating layer 41f, similar to the sixth to eighth pads P6, P7, and P8. The dummy pad Pdm may also be provided on the same layer as the first to fifth pads P1, P2, P3, P4, and P5.

[0033] The dummy pad Pdm is positioned, for example, symmetrically to the seventh pad P7 with respect to the sixth pad P6 when viewed from the thickness direction (Z-axis direction) of the substrate portion 40. The position and size of the dummy pad Pdm can be determined, for example, based on the center of gravity of the substrate portion 40, in order to make it easier to keep the substrate portion 40 horizontal with respect to the XY plane when mounting the substrate portion 40. The substrate 41 may also contain multiple dummy pads Pdm.

[0034] As shown in Figure 5, the first coil 43 is provided within the third insulating layer 41c. In this embodiment, the upper surface of the first coil 43 is located below, for example, the upper surface of the third insulating layer 41c. However, the upper surface of the first coil 43 may be flush with the upper surface of the third insulating layer 41c. The lower part of the first coil 43 may be plated. Furthermore, the first coil 43 may be composed of, for example, two or more layers of copper foil.

[0035] As shown in Figure 4, when the substrate portion 40 is viewed in the thickness direction (Z-axis direction), the first coil 43 has a spiral winding shape and a predetermined inductance. The first coil 43 is also called the primary coil. The first coil 43 serves as the path for electrical signals between the bump portion BP connected to the third pad P3 and the bump portion BP connected to the fourth pad P4.

[0036] As shown in Figure 5, the second coil 44 is provided within the fifth insulating layer 41e. In this embodiment, the lower surface of the second coil 44 is located above, for example, the lower surface of the fifth insulating layer 41e. However, the lower surface of the second coil 44 may be flush with the lower surface of the fifth insulating layer 41e. The upper part of the second coil 44 may be plated. The second coil 44 may also be composed of, for example, two or more layers of copper foil.

[0037] As shown in Figure 3, when the substrate portion 40 is viewed in the thickness direction (Z-axis direction), the second coil 44 has a spiral winding shape and a predetermined inductance. The second coil 44 is also called the secondary coil. The second coil 44 serves as the path for electrical signals between the bump portion BP connected to the sixth pad P6 and the bump portion BP connected to the seventh pad P7.

[0038] With the above configuration, the substrate portion 40 of this embodiment is provided with an insulating layer 41d and a pair of coils 43 and 44 facing each other in the thickness direction (Z-axis direction) via the insulating layer 41d. That is, the first coil 43 and the second coil 44 are arranged to face each other, separated from each other in the thickness direction (Z-axis direction).

[0039] In this embodiment, a portion of the third insulating layer 41c, a portion of the fourth insulating layer 41d, and a portion of the fifth insulating layer 41e are sandwiched between the first coil 43 and the second coil 44.

[0040] The thickness D of the insulating layers 41c, 41d, and 41e placed between the first coil 43 and the second coil 44 is preferably 25 μm or more. Generally, materials with a dielectric strength of 100 kV / mm or more, such as polyimide, are used as the materials constituting the insulating layers 41c, 41d, and 41e placed between the first coil 43 and the second coil 44. In this case, by setting the thickness D to 25 μm or more, the dielectric strength between the first coil 43 and the second coil 44 can be set to 2.5 kV or more. Furthermore, the thickness D of the insulating layers 41c, 41d, and 41e placed between the first coil 43 and the second coil 44 is preferably 100 μm or less. By setting the thickness D to 100 μm or less, the distance between the first coil 43 and the second coil 44 can be brought closer, and the transmission efficiency of electrical signals between the first coil 43 and the second coil 44 can be increased. For similar reasons, the thickness D is more preferably 50 μm or less.

[0041] In this embodiment, the insulating layer placed between the pair of coils 43 and 44 is composed of multiple layers (insulating layers 41c, 41d, and 41e), but the insulating layer placed between the pair of coils 43 and 44 may be a single layer. For example, if the upper surface of the first coil 43 and the upper surface of the third insulating layer 41c are flush, and the lower surface of the second coil 44 and the lower surface of the fifth insulating layer 41e are flush, then the insulating layer placed between the pair of coils 43 and 44 will be a single layer (fourth insulating layer 41d). In this case, the thickness D of the insulating layer placed between the pair of coils 43 and 44 will be the same as the thickness of the fourth insulating layer 41d.

[0042] As shown in Figure 5, the first wiring section 45 is provided within the third insulating layer 41c. In this embodiment, the first wiring section 45 is arranged in the same layer as the first coil 43. However, the first wiring section 45 may be arranged in a different layer from the first coil 43.

[0043] One end of the first wiring section 45 is connected to the first pad P1, and the other end of the first wiring section 45 is connected to the second pad P2. As described above, the first pad P1 is connected to the first terminal section 11 via the solder section SD. The second pad P2 is connected to the first semiconductor chip 21 via the bump section BP. Therefore, the first wiring section 45 electrically connects the first terminal section 11 and the first semiconductor chip 21, bridging the gap between them.

[0044] The second wiring section 46 has a first section 46a, a second section 46b, and a third section 46c. The first section 46a is provided within the fifth insulating layer 41e. In this embodiment, the first section 46a is arranged in the same layer as the second coil 44. However, the first section 46a may be arranged in a different layer from the second coil 44. One end of the first section 46a is connected to the eighth pad P8. The other end of the first section 46a is connected to the second section 46b. The second section 46b penetrates the third insulating layer 41c, the fourth insulating layer 41d, and the fifth insulating layer 41e.

[0045] The second portion 46b is formed, for example, by copper plating the inner surface of the through-hole. The upper end of the second portion 46b connects to the first portion 46a. The lower end of the second portion 46b connects to the third portion 46c.

[0046] The third portion 46c is provided within the third insulating layer 41c. In this embodiment, the third portion 46c is arranged in the same layer as the first coil 43 and the first wiring section 45. However, the third portion 46c may be arranged in a different layer from the first coil 43 and the first wiring section 45. One end of the third portion 46c is connected to the second portion 46b. The other end of the third portion 46c is connected to the fifth pad P5.

[0047] Therefore, one end of the second wiring section 46 is connected to the eighth pad P8, and the other end of the second wiring section 46 is connected to the fifth pad P5. As described above, the eighth pad P8 is connected to the second semiconductor chip 22 via the bump section BP. The fifth pad P5 is connected to the second terminal section 12 via the solder section SD. Therefore, the second wiring section 46 electrically connects the second semiconductor chip 22 and the second terminal section 12, bridging the gap between them.

[0048] In the substrate portion 40, the first coil 43, the first wiring portion 45, and the third portion 46c of the second wiring portion 46 are formed in the same layer. Similarly, in the substrate portion 40, the second coil 44 and the first portion 46a of the second wiring portion 46 are arranged in the same layer. According to this embodiment, patterns of conductive metals having different functions are arranged in the same layer. This makes it possible to reduce the thickness of the substrate portion 40 compared to the case where patterns of conductive metals with different functions are arranged in different layers. Furthermore, according to this embodiment, it is possible to reduce the number of layers of the substrate 41 that constitutes the substrate portion 40, making it possible to manufacture the substrate portion 40 at a lower cost.

[0049] Furthermore, in the substrate 41, patterns of conductive metals with different functions may be arranged on different layers. In this case, when viewing the substrate 40 from the thickness direction (Z-axis direction), the dimensions of the isolator 10 can be made smaller by partially overlapping the wiring and coils.

[0050] Next, the path of electrical signals to the isolator 10 will be described. The electrical signal input from the first terminal section 11 is input to the first semiconductor chip 21 via the solder section SD, the first pad P1, the first wiring section 45 of the substrate section 40, the second pad P2, and the bump section BP. This electrical signal is then input from the circuit section of the first semiconductor chip 21 to the first coil 43 of the substrate section 40 via the bump section BP, pads P3 and P4.

[0051] The first coil 43 converts the input electrical signal into magnetic energy. The second coil 44 receives the magnetic energy converted by the first coil 43 and converts it back into electrical energy. The isolator 10 isolates the first semiconductor chip 21 connected to the first coil 43 and the second semiconductor chip 22 connected to the second coil 44 by converting the input electrical signal into magnetic energy between the first coil 43 and the second coil 44.

[0052] The electrical signal flowing through the second coil 44 is input to the second semiconductor chip 22 via pads P6 and P7 and bump BP. This electrical signal flows from the circuit section of the second semiconductor chip 22 through the solder section SD, the second wiring section 46 of the substrate section 40, the fifth pad P5, and the solder section SD to the second terminal section 12.

[0053] In this embodiment, the isolator 10 receives an electrical signal from the first terminal 11, which travels through the substrate 40 to the first semiconductor chip 21. The electrical signal from the circuit of the first semiconductor chip 21 flows through a pair of coils 43 and 44 on the substrate 40 to the circuit of the second semiconductor chip 22. The electrical signal from the circuit of the second semiconductor chip 22 is then output from the second terminal 12 via the substrate 40.

[0054] The isolator 10 of this embodiment includes a substrate portion 40, a first semiconductor chip 21, and a second semiconductor chip 22. The substrate portion 40 has insulating layers 41c, 41d, 41e, and a pair of coils 43, 44 facing each other in the thickness direction via the insulating layers 41c, 41d, 41e. The first semiconductor chip 21 is positioned opposite one surface (bottom surface 40a) of the substrate portion 40. The first semiconductor chip 21 is connected to one of the pair of coils 43, 44 (first coil 43). The second semiconductor chip 22 is positioned opposite the other surface (top surface 40b) of the substrate portion 40. The second semiconductor chip 22 is connected to the other of the pair of coils 43, 44 (second coil 44).

[0055] According to this embodiment, a first semiconductor chip 21 and a second semiconductor chip 22 are stacked vertically on a substrate portion 40 that functions as an isolator module having a pair of coils 43 and 44. Therefore, when viewing the isolator 10 from the thickness direction (Z-axis direction), the substrate portion 40, the first semiconductor chip 21, and the second semiconductor chip 22 can be arranged overlapping each other. As a result, the dimensions of the isolator 10 when viewed from the thickness direction (Z-axis direction) can be reduced. In other words, the dimensions of the isolator 10 in the X-axis direction or the Y-axis direction can be reduced.

[0056] Furthermore, according to this embodiment, an isolator module consisting of a pair of coils 43 and 44 and insulating layers 41c, 41d, and 41e located between them is formed inside the substrate portion 40. Therefore, compared to the case where the isolator module is formed inside the semiconductor chip, it is easier to adjust the thickness D of the insulating layers 41c, 41d, and 41e, and it is easier to improve the insulating performance of the isolator module. Moreover, by forming the isolator module inside the substrate portion 40, the isolator 10 can be manufactured at a low cost.

[0057] Furthermore, according to this embodiment, the first semiconductor chip 21 and the second semiconductor chip 22 are stacked on the substrate 40 in the thickness direction (Z-axis direction). Therefore, the first semiconductor chip 21 and the second semiconductor chip 22 and the substrate 40 can be electrically connected by flip-chip bonding. According to this embodiment, the wire bonding connection process can be omitted from the manufacturing process of the isolator 10, making it possible to manufacture the isolator 10 at a low cost. In addition, connection by flip-chip bonding is more reliable than connection by wire bonding. According to this embodiment, a highly reliable isolator 10 can be provided.

[0058] The isolator 10 of this embodiment has a first terminal portion 11. The first terminal portion 11 is connected to a substrate portion 40. The substrate portion 40 has a first wiring portion 45. The first wiring portion 45 electrically connects the first terminal portion 11 and the first semiconductor chip 21.

[0059] With this configuration, the first terminal portion 11 and the first semiconductor chip 21 can be connected via the first wiring portion 45 of the substrate portion 40 without directly connecting them. Therefore, there is no need to connect the first semiconductor chip 21 and the first terminal portion 11 by wire bonding, making it possible to provide an inexpensive and highly reliable isolator 10.

[0060] The isolator 10 of this embodiment has a second terminal portion 12. The second terminal portion 12 is connected to the substrate portion 40. The substrate portion 40 has a second wiring portion 46. The second wiring portion 46 electrically connects the second terminal portion 12 and the second semiconductor chip 22. Both the first terminal portion 11 and the second terminal portion 12 are arranged facing each other on one side (bottom surface 40a) of the substrate portion 40.

[0061] With this configuration, the second terminal portion 12 and the second semiconductor chip 22 can be connected via the second wiring portion 46 of the substrate portion 40 without direct connection. Therefore, there is no need to connect the second semiconductor chip 22 and the second terminal portion 12 by wire bonding, making it possible to provide an inexpensive and highly reliable isolator 10. Furthermore, according to this embodiment, the first terminal portion 11 and the second terminal portion 12 are arranged on the same side of the substrate portion 40. Therefore, it is possible to connect the first terminal portion 11 and the second terminal portion 12 to the substrate portion 40 simultaneously from the same direction, which simplifies the manufacturing process of the isolator 10.

[0062] In the isolator 10 of this embodiment, the thickness D of the insulating layers 41c, 41d, and 41e placed between the pair of coils 43 and 44 is 25 μm or more. With this configuration, it is possible to provide a highly reliable isolator 10 by ensuring sufficient dielectric strength between the coils 43 and 44.

[0063] In the isolator 10 of this embodiment, it is preferable that at least a portion of the substrate portion 40 be a flexible substrate. With a flexible substrate, it is easier to make the thickness D of the insulating layers 41c, 41d, and 41e between the coils 43 and 44 thinner. More specifically, it is easier to make the thickness D of the insulating layers 41c, 41d, and 41e between 25 μm and 50 μm. For this reason, by making the region of the substrate portion 40 in which the pair of coils 43 and 44 are provided a flexible substrate, the insulating layers 41c, 41d, and 41e between the pair of coils 43 and 44 can be made thinner. As a result, it becomes possible to arrange the pair of coils 43 and 44 closer to each other, and the transmission efficiency of the isolator 10 can be improved.

[0064] In the isolator 10 of this embodiment, it is preferable that at least a portion of the substrate portion 40 is a rigid substrate. Rigid substrates can be manufactured at a lower cost compared to flexible substrates. Therefore, by making at least a portion of the substrate portion 40 a rigid substrate, it is possible to manufacture it at a lower cost compared to manufacturing the entire structure from a flexible substrate.

[0065] In the isolator 10 of this embodiment, the substrate portion is composed of a single substrate 41 on which one and the other of a pair of coils 43 and 44 are formed in different layers, respectively.

[0066] This configuration makes it possible to suppress the complexity of the manufacturing process compared to the case where a substrate containing a first coil and a substrate containing a second coil are bonded together to form the substrate (a modified example described later). More specifically, when a substrate containing a first coil and a substrate containing a second coil are bonded together to form the substrate, misalignment of the first and second coils during the bonding process can occur, which can lead to deterioration of the characteristics of the isolator module. For this reason, the manufacturing process can become complicated in order to suppress the occurrence of misalignment of the first and second coils. According to this embodiment, since both the first coil 43 and the second coil 44 are provided within the same substrate 41, the coils 43 and 44 are less likely to misalign in a plane perpendicular to the thickness direction, thus suppressing deterioration of characteristics while also suppressing the complexity of the manufacturing process.

[0067] (modified version) Next, a modified substrate portion 140 that can be adopted in this embodiment will be described based on Figure 6. The substrate portion 140 of this modified embodiment differs from the embodiment described above mainly in that it is formed by bonding a plurality of substrates 141 and 142 in the thickness direction. Components that are the same as those in the embodiment described above are denoted by the same reference numerals and their descriptions are omitted.

[0068] In this modified example, the substrate portion 140 functions as an isolator module positioned between the first semiconductor chip 21 and the second semiconductor chip 22 in the isolator 10, similar to the substrate portion 40 in the embodiment described above. Note that the multiple pads provided on the substrate portion 140 are not shown in Figure 6.

[0069] In this modified example, the substrate portion 40 includes an adhesive layer (insulating layer) 149, a first substrate 141, and a second substrate 142. In this modified example, both the first substrate 141 and the second substrate 142 are flexible substrates. However, either or both of the first substrate 141 and the second substrate 142 may be rigid substrates, or rigid-flexible substrates.

[0070] A first coil 43 is provided inside the first substrate 141. The outer shape of the first substrate 141 is formed by stacking multiple insulating layers 141a, 141b, 141c, and 141d. The first coil 43 is embedded inside the insulating layer 141c. Although some parts are not shown in the illustration, the first substrate 141 is provided with a first wiring section 45, a part of the second wiring section 46, and multiple pads P1, P2, P3, P4, and P5, similar to the embodiment described above.

[0071] A second coil 44 is provided inside the second substrate 142. The outer shape of the second substrate 142 is formed by laminating multiple insulating layers 142a, 142b, 142c, and 142d. The second coil 44 is embedded inside the insulating layer 142c. Although some parts are not shown in the illustration, the inside of the second substrate 142 is provided with a first wiring section 45, a part of the second wiring section 46, and multiple pads P5, P6, P7, and P8, similar to the embodiment described above.

[0072] The adhesive layer 149 is made of an insulating adhesive. The adhesive layer 149 is placed between the first substrate 141 and the second substrate 142. The adhesive layer 149 adheres the uppermost insulating layer 141d of the first substrate 141 and the lowermost insulating layer 142d of the second substrate 142. In this way, the adhesive layer 149 integrates the first substrate 141 and the second substrate 142.

[0073] The substrate portion 140 of this modified example has a first substrate 141 and a second substrate 142. The first substrate 141 and the second substrate 142 are laminated in the thickness direction (Z-axis direction) via an adhesive layer (insulating layer) 149. One of a pair of coils 43, 44 (first coil 43) is formed on the first substrate 141. The other of the pair of coils 43, 44 (second coil 44) is formed on the second substrate 142.

[0074] According to this modified example, the substrate portion 140 is formed by bonding a first substrate 141 containing the first coil 43 and a second substrate 142 containing the second coil 44. Therefore, the thickness of the adhesive layer 149 during bonding can be easily controlled. This makes it possible to adjust the voltage withstand capability and transmission efficiency of the isolator 10.

[0075] Furthermore, according to this modified example, the process of bonding the first substrate 141 and the second substrate 142 together can be adopted after connecting the first substrate 141 to the first semiconductor chip 21 and the second substrate 142 to the second semiconductor chip 22. This simplifies the flip-chip bonding processes between the first substrate 141 and the first semiconductor chip 21, and between the second substrate 142 and the second semiconductor chip 22.

[0076] According to at least one embodiment described above, an isolator 10 can be provided that has a substrate portion 40 having a pair of coils facing each other separated by an insulating layer, and a first semiconductor chip 21 and a second semiconductor chip 22 sandwiching the substrate portion 40 from both sides in the thickness direction (Z-axis direction), thereby enabling miniaturization of the planar dimensions.

[0077] This embodiment includes the following appended aspects. (Note 1) A substrate portion having an insulating layer and a pair of coils facing each other in the thickness direction via the insulating layer, A first chip is positioned opposite one side of the substrate portion and connected to one of the pair of coils, The substrate portion comprises a second chip positioned opposite the other surface and connected to the other of the pair of coils, Isolator. (Note 2) It includes a first terminal section connected to the aforementioned substrate section, The substrate portion has a first wiring portion that electrically connects the first terminal portion and the first chip. The isolator described in Appendix 1. (Note 3) It includes a second terminal portion connected to the aforementioned substrate portion, The substrate portion has a second wiring portion that electrically connects the second terminal portion and the second chip, The first terminal portion and the second terminal portion are both arranged facing one side of the substrate portion. The isolator described in Appendix 2. (Note 4) The thickness of the insulating layer is 25 μm or more. The isolator described in any of the appendices 1-3. (Note 5) At least a portion of the substrate is a flexible substrate. The isolator described in any of the appendices 1-4. (Note 6) At least a portion of the substrate is a rigid substrate. An isolator as described in any of the appendices 1-5. (Note 7) The substrate portion is composed of a single substrate on which one and the other of the pair of coils are formed in different layers, respectively. An isolator as described in any of the appendices 1-6. (Note 8) The substrate portion has a first substrate and a second substrate that are laminated in the thickness direction via the insulating layer, One of the pair of coils is formed on the first substrate. The other of the pair of coils is formed on the second substrate. An isolator as described in any of the appendices 1-6.

[0078] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0079] 10...Isolator, 11...First terminal section, 11...Terminal section, 12...Second terminal section, 21...First semiconductor chip (first chip), 22...Second semiconductor chip (second chip), 40, 140...Substrate section, 41, 141...Substrate, 41a, 41c, 41d, 141a, 141c, 141d, 142a, 142c...Insulating layer, 43...Coil, 45...First wiring section, 46...Second wiring section, 141...First substrate, 142...Second substrate, 149...Adhesive layer (insulating layer), D...Thickness

Claims

1. A substrate portion having an insulating layer and a pair of coils facing each other in the thickness direction via the insulating layer, A first chip is positioned opposite one side of the substrate portion and connected to one of the pair of coils, The substrate portion comprises a second chip positioned opposite the other surface and connected to the other of the pair of coils, Isolator.

2. It includes a first terminal portion connected to the aforementioned substrate portion, The substrate portion has a first wiring portion that electrically connects the first terminal portion and the first chip. The isolator according to claim 1.

3. It includes a second terminal portion connected to the aforementioned substrate portion, The substrate portion has a second wiring portion that electrically connects the second terminal portion and the second chip, The first terminal portion and the second terminal portion are both arranged facing one side of the substrate portion. The isolator according to claim 2.

4. The thickness of the insulating layer is 25 μm or more. The isolator according to claim 1.

5. At least a portion of the substrate is a flexible substrate. The isolator according to claim 1.

6. At least a portion of the substrate is a rigid substrate. The isolator according to claim 1.

7. The substrate portion is composed of a single substrate on which one and the other of the pair of coils are formed in different layers, respectively. The isolator according to claim 1.

8. The substrate portion has a first substrate and a second substrate that are laminated in the thickness direction via the insulating layer, One of the pair of coils is formed on the first substrate. The other of the pair of coils is formed on the second substrate. The isolator according to claim 1.

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