Control circuits, drive circuits, and semiconductor circuits

Abstract

The objective is to provide a control circuit, a drive circuit, and a semiconductor circuit that can suppress damage to switching elements. [Solution] The control circuit of the embodiment is a control circuit provided in a drive circuit that drives a bridge circuit having a plurality of switching elements by controlling each of the plurality of switching elements with a plurality of control circuits. The control circuit of the embodiment receives a first control signal for controlling a first switching element that it controls among the plurality of switching elements, and a second control signal for controlling a second switching element that is controlled by the other control circuits among the plurality of switching elements.

Description

Technical Field

[0001] Embodiments of the present invention relate to a control circuit, a drive circuit, and a semiconductor circuit.

Background Art

[0002] There is known a drive circuit that controls a plurality of switching elements by a plurality of control circuits. In a conventional drive circuit, each control circuit could not determine whether it was malfunctioning. Therefore, each control circuit started an operation to protect each switching element it controls after an abnormality such as an overcurrent occurring in each switching element was detected by an external device. Therefore, the protection of the switching element was delayed, and there was a risk that the switching element would be damaged.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a control circuit, a drive circuit, and a semiconductor circuit that can suppress damage to a switching element.

Means for Solving the Problems

[0005] The control circuit of the embodiment is a control circuit provided in a drive circuit that drives a bridge circuit having a plurality of switching elements by controlling each of the plurality of switching elements with a plurality of control circuits. The control circuit of the embodiment receives a first control signal for controlling a first switching element that it controls among the plurality of switching elements, and a second control signal for controlling a second switching element that is controlled by the other control circuits among the plurality of switching elements. [Brief explanation of the drawing]

[0006] [Figure 1] A circuit diagram showing a semiconductor circuit of the first embodiment. [Figure 2] A circuit diagram showing the control circuit of the first embodiment. [Figure 3] A circuit diagram showing a semiconductor circuit of the second embodiment. [Figure 4] A circuit diagram showing the control circuit of the second embodiment. [Figure 5] A circuit diagram showing a semiconductor circuit of the third embodiment. [Figure 6] A circuit diagram showing the control circuit of the fourth embodiment. [Figure 7] A circuit diagram showing the control circuit of the fifth embodiment. [Figure 8] A circuit diagram showing the control circuit of the sixth embodiment. [Figure 9] A circuit diagram showing the control circuit of the seventh embodiment. [Figure 10] A circuit diagram showing a semiconductor circuit of the eighth embodiment. [Figure 11] A circuit diagram showing a semiconductor circuit of the ninth embodiment. [Figure 12] A circuit diagram showing a semiconductor circuit of the tenth embodiment. [Figure 13] A circuit diagram showing a semiconductor circuit of the 11th embodiment. [Figure 14] A circuit diagram showing a semiconductor package according to the 11th embodiment. [Figure 15] A circuit diagram showing a semiconductor circuit of the twelfth embodiment. [Modes for carrying out the invention]

[0007] The control circuit, drive circuit, and semiconductor circuit of the embodiment will be described below with reference to the drawings.

[0008] (First embodiment) Figure 1 is a circuit diagram showing a semiconductor circuit 100 of a first embodiment. The semiconductor circuit 100 shown in Figure 1 is a circuit that controls electronic equipment such as a motor. The semiconductor circuit 100 is a circuit formed on a wiring board by power devices such as switching elements 61 and 62 (described later), control circuits 10A and 10B (described later), which are semiconductor packages, isolators 83a and 83b (described later), and other circuits, and is, for example, part of an inverter device. The semiconductor circuit 100 comprises a bridge circuit 60, a drive circuit 80, and a controller 90. The bridge circuit 60 is connected to the electronic equipment controlled by the semiconductor circuit 100 and supplies power to drive the electronic equipment. The drive circuit 80 drives the bridge circuit 60 based on a control signal input from the controller 90.

[0009] The bridge circuit 60 has multiple switching elements. In the first embodiment, the bridge circuit 60 has two switching elements 61 and 62. Switching elements 61 and 62 are connected to each other. In the first embodiment, the two switching elements 61 and 62 are transistors. More specifically, the two switching elements 61 and 62 are N-channel field-effect transistors (FETs). The two switching elements 61 and 62 are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Switching element 61 is the high-side switching element. Switching element 62 is the low-side switching element. The source terminal of switching element 61 is connected to the drain terminal of switching element 62. Note that the two switching elements 61 and 62 can be any type of switching element. The bridge circuit 60 may be a half-bridge circuit or a full-bridge circuit. The bridge circuit 60 may be, for example, an inverter circuit.

[0010] The controller 90 inputs control signals to the drive circuit 80 for controlling the bridge circuit 60. In the first embodiment, the controller 90 has a CPU 91. The CPU 91 inputs control signals to the drive circuit 80.

[0011] In the first embodiment, the drive circuit 80 is a gate drive circuit. The drive circuit 80 includes a first drive unit 81, a second drive unit 82, and isolators 83a and 83b. The first drive unit 81 drives the switching element 61. The second drive unit 82 drives the switching element 62. The first drive unit 81 and the second drive unit 82 have similar configurations except that they drive different switching elements. Therefore, in the following description, the first drive unit 81 will be described as a representative of the first drive unit 81 and the second drive unit 82, and the description of the second drive unit 82 may be omitted.

[0012] The first drive unit 81 has a control circuit 10A. The second drive unit 82 has a control circuit 10B. Thus, in the first embodiment, the drive circuit 80 has two control circuits 10A and 10B as a plurality of control circuits. The control circuit 10A is a control circuit that controls one of the two switching elements 61 and 62, i.e., the switching element 61. The control circuit 10B is a control circuit that controls the other of the two switching elements 61 and 62, i.e., the switching element 62. That is, the plurality of switching elements 61 and 62 are respectively controlled by the plurality of control circuits 10A and 10B. In the control circuit 10A, the switching element 61 is the "first switching element" controlled by the control circuit 10A itself among the plurality of switching elements, and the switching element 62 is the "second switching element" controlled by the other control circuit 10B among the plurality of switching elements. In the control circuit 10B, the switching element 62 is the "first switching element" controlled by the control circuit 10B itself among the plurality of switching elements, and the switching element 61 is the "second switching element" controlled by the other control circuit 10A among the plurality of switching elements. In the following description, the control circuit 10A will be described as a representative of the control circuits 10A and 10B, and the description of the control circuit 10B may be omitted. Also, in the following description, when the control circuit 10A and the control circuit 10B are not particularly distinguished, they may be collectively referred to as the control circuit 10.

[0013] The control circuit 10 is an integrated circuit (IC). In the first embodiment, the control circuit 10 is an insulated gate drive IC. In the first embodiment, the control circuit 10A and the control circuit 10B are different semiconductor packages from each other. Each of the control circuit 10A and the control circuit 10B is configured by packaging each element such as a semiconductor chip and an infrared light-emitting diode.

[0014] FIG. 2 is a circuit diagram showing the control circuit 10A. As shown in FIG. 2, the control circuit 10A includes a first input terminal 11a, a second input terminal 11b, a fault output terminal 11c, a ground terminal 11d, a positive power supply terminal 11e, an output terminal 11f, a third input terminal 11g, a negative power supply terminal 11h, a determination unit 20, and an isolation transfer unit 50.

[0015] As shown in FIG. 1, a first control signal S1 is input from the controller 90 to the first input terminal 11a. The first control signal S1 is a control signal for controlling the switching element 61. A resistor element R1a is arranged between the first input terminal 11a and the controller 90. The first control signal S1 is input to the first input terminal 11a via the resistor element R1a. The first control signal S1 is, for example, a signal that goes high when turning on the switching element 61 and goes low when turning off the switching element 61.

[0016] In the circuit of the present disclosure, "another element is arranged between a certain element and another element" means that the another element is provided on the circuit from one of the certain element and the another element to the other until traced.

[0017] A second control signal S2 is input from the controller 90 to the second input terminal 11b. The second control signal S2 is a control signal for controlling the switching element 62. A resistor element R2a is arranged between the second input terminal 11b and the controller 90. The second control signal S2 is input to the second input terminal 11b via the resistor element R2a. The second control signal S2 is, for example, a signal that goes high when turning on the switching element 62 and goes low when turning off the switching element 62.

[0018] The fault output terminal 11c is a terminal that outputs the fault signal / FS1. The fault signal / FS1 is input to the controller 90. The fault signal / FS1 is a signal that changes based on the result of the abnormality detection operation described later. The fault signal / FS1 is a negative logic signal that is low when an abnormality is determined to have occurred in the abnormality detection operation, and high when no abnormality is determined to have occurred in the abnormality detection operation. In this specification, the " / " written before a symbol indicates that the signal indicated by that symbol is an inverted negative logic signal. In the drawings and tables, instead of writing " / ", an overline is drawn over the symbol of a negative logic signal. A resistor R3a is placed between the fault output terminal 11c and the power supply terminal of the controller 90 to which the positive power supply voltage VDD is applied.

[0019] The ground terminal 11d is connected to ground GND. The positive power supply terminal 11e is supplied with a positive power supply voltage VCC1 by power supply E1. The negative power supply terminal 11h is supplied with a negative power supply voltage VEE1 by power supply E1. A capacitor C1 is placed between the positive power supply terminal 11e and the negative power supply terminal 11h. Power supply E1 includes a floating power supply.

[0020] Output terminal 11f is a terminal that outputs a first output voltage V1. The first output voltage V1 is applied to the gate terminal of the switching element 61. The first output voltage V1 is high when the first control signal S1 is high, and low when the first control signal S1 is low. A resistor R5a is placed between output terminal 11f and the gate terminal of the switching element 61.

[0021] The second output voltage / V2 is input to the third input terminal 11g. The second output voltage / V2 is a voltage output from the isolator 83a based on the second output voltage V2 output from the output terminal 11f of the control circuit 10B. The second output voltage / V2 is a negative logic signal that is low when the second output voltage V2 is high and high when the second output voltage V2 is low. In other words, the second output voltage V2 is inverted via the isolator 83a and input to the third input terminal 11g as the second output voltage / V2. In the first embodiment, the second output voltage / V2 corresponds to "element information" indicating the state of the switching element 62. Since the second output voltage V2 output from the output terminal 11f of the control circuit 10B is applied to the gate terminal of the switching element 62, the state of the switching element 62 can be determined from the value of the second output voltage / V2 based on the second output voltage V2. In the first embodiment, the second output voltage / V2 is information based on the gate voltage (drive voltage) applied to the switching element 62.

[0022] The isolator 83a is an optical coupler having a light-emitting diode and a phototransistor. The second output voltage V2 output from the output terminal 11f of the control circuit 10B is input to the isolator 83a. A resistor R6b is placed between the input terminal of the isolator 83a and the output terminal 11f of the control circuit 10B. A resistor R4a is placed between the output terminal of the isolator 83a and the positive power supply terminal 11e of the control circuit 10A. When the input second output voltage V2 is high, the isolator 83a lowers the second output voltage / V2 input to the third input terminal 11g of the control circuit 10A. When the input second output voltage V2 is low, the isolator 83a lowers the second output voltage / V2 input to the third input terminal 11g of the control circuit 10A.

[0023] As shown in Figure 2, the isolated transmission unit 50 transmits signals in isolation between the first input terminal 11a, the second input terminal 11b, and the fault output terminal 11c and the determination unit 20. The isolated transmission unit 50 includes a first transmission unit 51, a second transmission unit 52, a third transmission unit 53, a shielding film 55, and a conversion unit 50a. The shielding film 55 is a component that removes noise in the first transmission unit 51, the second transmission unit 52, and the third transmission unit 53.

[0024] The first transmission unit 51 transmits the first control signal S1 input to the first input terminal 11a to the determination unit 20 via isolation. In other words, in the first embodiment, the first control signal S1 is transmitted via isolation transmission unit 50. The first transmission unit 51 is an optical coupler having a light-emitting diode 51a and a photodiode 51b. When the first control signal S1 is high, current flows through the light-emitting diode 51a and the light-emitting diode 51a emits light. When the light emitted from the light-emitting diode 51a is received by the photodiode 51b, current flows through the photodiode 51b. The current flowing through the photodiode 51b is converted into a voltage by the conversion unit 50a and output to the determination unit 20 as the first control signal S1. As a result, the first control signal S1 is transmitted via isolation to the determination unit 20 via the light emitted from the light-emitting diode 51a. The conversion unit 50a is connected to the positive power supply terminal 11e and the negative power supply terminal 11h. The ground (reference potential) in the determination unit 20 and the ground (reference potential) in the conversion unit 50a are common to each other and are the negative power supply voltage VEE1 applied to the negative power supply terminal 11h.

[0025] The second transmission unit 52 transmits the second control signal S2 input to the second input terminal 11b to the determination unit 20 via isolation. In other words, in the first embodiment, the second control signal S2 is transmitted via isolation transmission unit 50. The second transmission unit 52 is an optical coupler having a light-emitting diode 52a and a photodiode 52b. When the second control signal S2 is high, the second transmission unit 52 transmits the second control signal S2 to the determination unit 20 via light emitted from the light-emitting diode 52a via isolation, similar to the first transmission unit 51.

[0026] The third transmission unit 53 transmits the fault signal FS1, which is input from the fault determination unit 40 (described later) of the determination unit 20, to the fault output terminal 11c in isolation. The third transmission unit 53 is an optical coupler having a light-emitting diode 53a and a phototransistor 53b. When the fault signal FS1 is high, current flows through the light-emitting diode 53a and the light-emitting diode 53a lights up. The light emitted from the light-emitting diode 53a is received by the phototransistor 53b, causing the phototransistor 53b to turn ON. In this case, the fault output terminal 11c is connected to the ground terminal 11d via the phototransistor 53b, and the fault signal / FS1 output from the fault output terminal 11c becomes low. On the other hand, when the fault signal FS1 is low, the light-emitting diode 53a does not light up, and the phototransistor 53b turns OFF. In this case, a positive power supply voltage VDD is applied to the fault output terminal 11c via the resistor R3a, and the fault signal / FS1 becomes high. In other words, the fault signal FS1 output from the fault detection unit 40 is inverted by the third transmission unit 53 and output as fault signal / FS1 from the fault output terminal 11c to the controller 90. In this embodiment, the light-emitting diodes 51a, 52a, and 53a are infrared light-emitting diodes. Note that the light-emitting diodes 51a, 52a, and 53a may be light-emitting diodes that emit any type of light, for example, they may be blue light-emitting diodes or white light-emitting diodes. Note that other light-emitting diodes described herein may also be light-emitting diodes that emit any type of light, for example, they may be infrared light-emitting diodes, blue light-emitting diodes or white light-emitting diodes.

[0027] The determination unit 20 is a circuit unit that makes a determination based on the input signal and outputs a signal based on the determination result. The determination unit 20 is mounted on a semiconductor chip provided in the control circuit 10. The determination unit 20 includes an output determination unit 30 and a fault determination unit 40.

[0028] The output determination unit 30 determines whether to set the output of the first output voltage V1 to high or low. The output determination unit 30 has an AND circuit 31. The AND circuit 31 receives three signals: a first control signal S1 input via the buffer circuit 26, a second control signal S2 inverted via the NOT circuit 21, and a second output voltage V2 input via the buffer circuit 23. The AND circuit 31 sets its output value to high if all three input signals are high. The AND circuit 31 sets its output value to low if at least one of the three input signals is low. The output value output from the AND circuit 31 is the first output voltage V1, and is output to the output terminal 11f via the buffer circuit 22.

[0029] The fault detection unit 40 determines whether to set the output of the fault signal / FS1 to high or low. The fault detection unit 40 includes an AND circuit 41, an AND circuit 42, and a NOR circuit 43. The AND circuit 41 receives three signals: a first control signal / S1 inverted via a NOT circuit 27, a second control signal S2 input via a buffer circuit 25, and a second output voltage V2 inverted via a NOT circuit 24. The AND circuit 41 sets its output value to high if all three input signals are high. The AND circuit 41 sets its output value to low if at least one of the three input signals is low.

[0030] The AND gate 42 receives three signals: a first control signal / S1 inverted via the NOT gate 27, a second control signal / S2 inverted via the NOT gate 21, and a second output voltage / V2 input via the buffer gate 23. The AND gate 42 outputs high when all three input signals are high. The AND gate 42 outputs low when at least one of the three input signals is low.

[0031] The NOR gate 43 receives three input signals: the first output voltage V1 from the AND gate 31, the output from the AND gate 41, and the output from the AND gate 42. The NOR gate 43 outputs a fault signal FS1. The NOR gate 43 sets the fault signal FS1 high when all three input signals are low. The NOR gate 43 sets the fault signal FS1 low when at least one of the three input signals is high. When the fault signal FS1 is high, the light-emitting diode 53a lights up, the phototransistor 53b turns ON, and the fault signal FS1 becomes low. When the fault signal FS1 is low, the light-emitting diode 53a does not light up, the phototransistor 53b turns OFF, and the fault signal FS1 becomes high.

[0032] The determination unit 20 is capable of performing an abnormality determination operation to determine whether or not there is an abnormality in the control state of the two switching elements 61 and 62. An abnormality in the control state of the two switching elements 61 and 62 includes an abnormality in the control signal for controlling the two switching elements 61 and 62, i.e., an input abnormality, and an abnormality in the ON / OFF state of the two switching elements 61 and 62, i.e., an output abnormality.

[0033] In the first embodiment, the abnormality determination operation includes determining whether or not an abnormality has occurred in the control state of the two switching elements 61 and 62 based on the first control signal S1, the second control signal S2, and the second output voltage / V2. Table 1 is a table showing the first control signal S1, the second control signal S2, the second output voltage / V2, the first output voltage V1, the fault signal / FS1, and the determination result of the abnormality determination operation.

[0034] [Table 1]

[0035] In Table 1, a "Pass" result indicates a normal state, while a "Fail" result indicates an abnormal state. When the first control signal S1 is high, in a normal state, the second control signal S2 is low, the first output voltage V1 becomes high based on the first control signal S1, and the second output voltage V2 becomes low based on the second control signal S2. Therefore, the second output voltage V2, which is inverted and input to the control circuit 10A, becomes high. In other words, the state shown in Table 1 [1] is a normal state.

[0036] When the second control signal S2 is high, under normal conditions, the first control signal S1 is low, the first output voltage V1 becomes low based on the first control signal S1, and the second output voltage V2 becomes high based on the second control signal S2. Therefore, the second output voltage V2, which is inverted and input to the control circuit 10A, becomes low. In other words, the state shown in Table 1 [5] is a normal state.

[0037] When both the first control signal S1 and the second control signal S2 are low, under normal conditions, both the first output voltage V1 and the second output voltage V2 will also be low, and the second output voltage V2, which is inverted and input to the control circuit 10A, will be high. In other words, [7] shown in Table 1 is a normal condition.

[0038] In normal conditions where the judgment result is "Pass," as shown in Table 1 [1], [5], and [7], the fault signal / FS1 is high. On the other hand, conditions where the judgment result is "Fail," as shown in Table 1 [2], [3], [4], [6], and [8], are all abnormal conditions. In the abnormal conditions of [2], [3], [4], [6], and [8], the fault signal / FS1 is low.

[0039] In the first embodiment, the determination unit 20 determines whether or not there is an abnormality in the control state of the two switching elements 61 and 62, based on the output determination unit 30 and fault determination unit 40 described above. For example, in the case of [1] shown in Table 1, the first control signal S1 is high, the second control signal S2 is low, and the second output voltage / V2 is high. In this case, all three signals S1, / S2, and / V2 input to the AND circuit 31 of the output determination unit 30 are high. Therefore, the AND circuit 31 outputs the first output voltage V1 as high. Outputting the first output voltage V1 as high when the first control signal S1 is high is normal operation.

[0040] In case [1], all three signals / S1, / S2, and / V2 input to the AND circuit 41 in the fault detection unit 40 are low. Therefore, the output of the AND circuit 41 is low. In case [1], of the three signals / S1, / S2, and / V2 input to the AND circuit 42 in the fault detection unit 40, the first control signal / S1 is low. Therefore, the output of the AND circuit 42 is also low. The NOR circuit 43 receives low signals from the two AND circuits 41 and 42, but the first output voltage V1 input from the AND circuit 31 of the output detection unit 30 is high. Therefore, the fault signal FS1 output from the NOR circuit 43 is low. Consequently, the fault signal / FS1 output from the fault output terminal 11c is high. In other words, the state of the fault signal / FS1 indicates that no abnormality has been detected.

[0041] As described above, in the case of [1] in Table 1, the determination unit 20 determines that the control state of the two switching elements 61 and 62 is normal through abnormality determination operation. As a result, the control circuit 10A outputs a first output voltage V1 that is high based on the first control signal S1 that is high, and also outputs a fault signal / FS1 that is high, indicating that it is in a normal state.

[0042] For example, in the case of [2] shown in Table 1, the first control signal S1 is high, the second control signal S2 is high, and the second output voltage / V2 is low. In the switching operation of the two switching elements 61 and 62, it is not possible to turn both switching elements 61 and 62 ON at the same time. Therefore, under normal circumstances, the first control signal S1 and the second control signal S2 will not both be high. Thus, in the case of [2], there is an abnormality in the control signals that control the two switching elements 61 and 62. In this case, two of the three signals S1, / S2, and / V2 input to the AND circuit 31 of the output determination unit 30, / S2 and / V2, become low. Therefore, the AND circuit 31 outputs the first output voltage V1 as low. Under normal circumstances, when the first control signal S1 is high, the AND circuit 31 outputs the first output voltage V1 as high. However, in case [2], an abnormality has occurred, so the output determination unit 30 determines that there is an abnormality in the control state of the two switching elements 61 and 62 and outputs the first output voltage V1 as low. In other words, the output determination unit 30 determines that the two switching elements 61 and 62 are in a short-circuit state and outputs the first output voltage V1 as low. As a result, even if the switching element 62 is turned ON by the high second output voltage V2, the first output voltage V1 is turned low and the switching element 61 is turned OFF. Therefore, a short circuit caused by both switching elements 61 and 62 being turned ON is avoided, and the bridge circuit 60 can be protected. Thus, when the control circuit 10A determines that the two switching elements 61 and 62 are in a short-circuit state during the abnormality determination operation, it turns the switching element 61 OFF.

[0043] In case [2], the first control signal / S1 of the three signals / S1, / S2, and / V2 input to the AND circuit 41 in the fault detection unit 40 becomes low. Therefore, the output of the AND circuit 41 becomes low. In case [2], all three signals / S1, / S2, and / V2 input to the AND circuit 42 in the fault detection unit 40 become low. Therefore, the output of the AND circuit 42 also becomes low. In addition, the first output voltage V1 input to the NOR circuit 43 from the AND circuit 31 of the output detection unit 30 also becomes low. Therefore, the fault signal FS1 output from the NOR circuit 43 becomes high. Consequently, the fault signal / FS1 output from the fault output terminal 11c becomes low. In other words, the state of the fault signal / FS1 indicates that an abnormality has been detected.

[0044] As described above, in the case of [2] in Table 1, the determination unit 20 determines that the control state of the two switching elements 61 and 62 is abnormal through abnormality determination operation. As a result, even when the control circuit 10A receives a high first control signal S1, it protects the bridge circuit 60 by setting the first output voltage V1 low and outputs a fault signal / FS1 in a low state to indicate an abnormal condition.

[0045] In the case of [2], the second control signal S2 is high, while the second output voltage V2 is low, meaning the second output voltage V2 is high. It is normal for the second output voltage V2 to be high when the second control signal S2 is high. Therefore, in the case of [2], there is an abnormality in the input of the control signal, but the output of the second output voltage V2 in response to the second control signal S2 is normal.

[0046] For example, in the case of [6] shown in Table 1, the first control signal S1 is low, the second control signal S2 is high, and the second output voltage / V2 is high. In this case, under normal circumstances, the second output voltage V2 would be high based on the second control signal S2, so the second output voltage / V2 would be low. However, because the second output voltage / V2 is high, in the case of [6], the control circuit 10B is unable to output a normal second output voltage V2 in response to the second control signal S2, meaning that the control circuit 10B is not operating normally. In this case, two of the three signals S1, / S2, and / V2 input to the AND circuit 31 of the output determination unit 30, S1 and / S2, become low. Therefore, the AND circuit 31 outputs the first output voltage V1 as low. The fact that the first output voltage V1 is output as low because the first control signal S1 is low is itself normal operation.

[0047] On the other hand, in the case of [6], the second output voltage V2 of the three signals / S1, S2, and V2 input to the AND circuit 41 in the fault detection unit 40 becomes low. Therefore, the output of the AND circuit 41 becomes low. In the case of [6], the second control signal / S2 of the three signals / S1, / S2, and / V2 input to the AND circuit 42 in the fault detection unit 40 becomes low. Therefore, the output of the AND circuit 42 also becomes low. In addition, the first output voltage V1 input to the NOR circuit 43 from the AND circuit 31 of the output detection unit 30 also becomes low. Therefore, the fault signal FS1 output from the NOR circuit 43 becomes high. Consequently, the fault signal / FS1 output from the fault output terminal 11c becomes low. In other words, the state of the fault signal / FS1 indicates that an abnormality has been detected.

[0048] As described above, in the case of [6] in Table 1, the determination unit 20 determines through abnormality determination operation that the control state of the two switching elements 61 and 62 is abnormal. As a result, the control circuit 10A outputs a fault signal / FS1 as low, indicating an abnormal state. Based on the first control signal S1 which is low for the first output voltage V1, the control circuit 10A outputs a low, which is a normal output. In this case, the two switching elements 61 and 62 are turned OFF, and the bridge circuit 60 is protected.

[0049] In the cases of [3], [4], [5], [7], and [8] in Table 1, the control circuit 10A performs an abnormality determination operation by the determination unit 20, similar to the cases of [1], [2], and [6], and outputs the first output voltage V1 and fault signal / FS1 based on the determination result.

[0050] As shown in Figure 1, in the control circuit 10B of the second drive unit 82, the second control signal S2 is input to the first input terminal 11a via the resistor R1b, and the first control signal S1 is input to the second input terminal 11b via the resistor R2b. In the control circuit 10B, the second output voltage V2 is output from the output terminal 11f. The output terminal 11f of the control circuit 10B is connected to the gate terminal of the switching element 62 via the resistor R5b. As a result, the second output voltage V2 is applied to the gate terminal of the switching element 62. The positive power supply terminal 11e of the control circuit 10B is supplied with a positive power supply voltage VCC2 by the power supply E2. The positive power supply voltage VCC2 may be the same as or different from the positive power supply voltage VCC1. The negative power supply terminal 11h of the control circuit 10B is supplied with a negative power supply voltage VEE2 by the power supply E2. The negative power supply voltage VEE2 may be the same as or different from the negative power supply voltage VEE1. In the control circuit 10B, a capacitor C2 is placed between the positive power supply terminal 11e and the negative power supply terminal 11h.

[0051] The third input terminal 11g of the control circuit 10B receives the first output voltage / V1. The first output voltage / V1 is the voltage output from the isolator 83b based on the first output voltage V1 output from the output terminal 11f of the control circuit 10A. The first output voltage / V1 is a negative logic signal that is low when the first output voltage V1 is high, and high when the first output voltage V1 is low. In other words, the first output voltage V1 is inverted via the isolator 83b and input to the third input terminal 11g of the control circuit 10B as the first output voltage / V1. In the first embodiment, the first output voltage / V1 corresponds to "element information" indicating the state of the switching element 61. Since the first output voltage V1 output from the output terminal 11f of the control circuit 10A is applied to the gate terminal of the switching element 61, the state of the switching element 61 can be determined from the value of the first output voltage / V1 based on the first output voltage V1. In the first embodiment, the first output voltage / V1 is information based on the gate voltage (drive voltage) applied to the switching element 61.

[0052] The isolator 83b is an optical coupler having a light-emitting diode and a phototransistor. The first output voltage V1 output from the output terminal 11f of the control circuit 10A is input to the isolator 83b. A resistor R6a is placed between the input terminal of the isolator 83b and the output terminal 11f of the control circuit 10A. A resistor R4b is placed between the output terminal of the isolator 83b and the positive power supply terminal 11e of the control circuit 10B. When the input first output voltage V1 is high, the isolator 83b lowers the first output voltage / V1 input to the third input terminal 11g of the control circuit 10B. When the input first output voltage V1 is low, the isolator 83b lowers the first output voltage / V1 input to the third input terminal 11g of the control circuit 10B. Control circuit 10B performs abnormality detection operations in the same way as control circuit 10A, except that it uses the first output voltage / V1 instead of the second output voltage / V2, and the output from output terminal 11f is the second output voltage V2.

[0053] The semiconductor circuit 100 includes an overcurrent detection circuit 12. The overcurrent detection circuit 12 includes a resistor 12a and a logic gate 12b. One end of the resistor 12a is connected to the source terminal of the switching element 62. The other end of the resistor 12a is connected to a wiring to which a negative power supply voltage VEE2 is applied. The logic gate 12b is supplied with the voltage from the source terminal of the switching element 62 and the negative power supply voltage VEE2. The logic gate 12b outputs a fault signal / FS1 to the controller 90. The logic gate 12b sets the fault signal / FS1 low if the value of the current flowing through the resistor 12a is greater than or equal to a predetermined value, and sets the fault signal / FS1 high if the value of the current flowing through the resistor 12a is less than the predetermined value. As a result, even if the two switching elements 61 and 62 are short-circuited and an overcurrent flows through them, the overcurrent detection circuit 12 sends a fault signal / FS1 indicating an abnormality to the controller 90. Therefore, based on the fault signal / FS1 sent from the overcurrent detection circuit 12, the controller 90 can send a signal to the control circuits 10A and 10B to turn off at least one of the two switching elements 61 and 62, thereby protecting the bridge circuit 60. Although not shown, the fault signal / FS1 output from the logic gate 12b may also be output to the controller 90 via an isolated signal transmission unit separate from the isolated transmission unit 50.

[0054] According to the first embodiment, the control circuit 10A is a control circuit provided in a drive circuit 80 that drives a bridge circuit 60 having a plurality of switching elements 61, 62 by controlling the plurality of switching elements 61, 62 by a plurality of control circuits 10A, 10B. The control circuit 10A receives a first control signal S1 for controlling the switching element 61 (first switching element) that it controls among the plurality of switching elements 61, 62, and a second control signal S2 for controlling the switching element 62 (second switching element) that is controlled by the other control circuits 10B among the plurality of switching elements 61, 62. Therefore, the control circuit 10A can compare the first control signal S1 for controlling the switching element 61 that it controls and the second control signal S2 for controlling the switching element 62 that is controlled by the other control circuits 10B. This makes it possible for the control circuit 10A to determine whether or not there is an abnormality in the control signals that control the two switching elements 61, 62. Therefore, for example, the control circuit 10A can determine that an abnormality has occurred when both the first control signal S1 and the second control signal S2 are high, and can turn off the switching element 61 that the control circuit 10A controls, regardless of the state of the first control signal S1. As a result, short circuits between the two switching elements 61 and 62 can be suppressed, and overcurrents flowing through the bridge circuit 60 can be suppressed. This prevents damage to the switching elements 61 and 62.

[0055] Conventionally, for example, the overcurrent detection circuit 12 described above was used alone to detect when the two switching elements 61 and 62 were short-circuited, thereby protecting the bridge circuit 60. However, in this case, there was a problem in that it was not possible to detect that there was an abnormality in the control state of the two switching elements 61 and 62 until the two switching elements 61 and 62 were short-circuited and an overcurrent flowed through the resistor element 12a. In contrast, according to the first embodiment, by comparing two control signals for controlling the two switching elements 61 and 62, the control circuit 10A can detect the possibility of the two switching elements 61 and 62 being short-circuited before an overcurrent occurs. Therefore, the control circuit 10A can determine that an abnormality has occurred before the two switching elements 61 and 62 are actually short-circuited, and can turn off the switching element 61. This makes it possible to more effectively suppress the flow of overcurrent through the bridge circuit 60. According to the first embodiment, compared to the case where abnormality detection is performed solely by the overcurrent detection circuit 12, abnormalities can be detected more quickly, for example, by 10 ns (nanoseconds) or more and several hundred ns (nanoseconds) or less.

[0056] Furthermore, since the control circuit 10A receives two control signals, a first control signal S1 and a second control signal S2, for controlling the two switching elements 61 and 62, it is possible to determine whether or not there is an abnormality in the dead time when the two switching elements 61 and 62 are in the OFF state by comparing the state of the first control signal S1 and the state of the second control signal S2.

[0057] According to the first embodiment, the control circuit 10A is capable of performing an abnormality determination operation to determine whether or not there is an abnormality in the control state of the two switching elements 61 and 62. The control circuit 10A receives a second output voltage / V2 as element information indicating the state of the other switching element 62. The abnormality determination operation includes determining whether or not there is an abnormality in the control state of the two switching elements 61 and 62 based on the first control signal S1, the second control signal S2, and the second output voltage / V2 (element information). Therefore, even if the switching element 62 malfunctions for some reason when the first control signal S1 and the second control signal S2 are normal, the control circuit 10A can detect that the state of the switching element 62 is abnormal based on the second output voltage / V2. As a result, the control circuit 10A can quickly detect an abnormality, for example, when the second control signal S2 is low and the switching element 62 is in the ON state, and quickly turn the switching element 61 to the OFF state. Therefore, damage to the two switching elements 61 and 62 can be further suppressed. In addition, a case in which the switching element 62 malfunctions for any reason is, for example, when the switching element 62 self-turns on, causing the gate voltage of the switching element 62 to rise and the second output voltage V2 to go high.

[0058] According to the first embodiment, the element information indicating the state of the other switching element 62 includes information based on the gate voltage (drive voltage) applied to the other switching element 62, i.e., the second output voltage V2. Therefore, the control circuit 10A can more easily and accurately detect the state of the switching element 62 based on this information. In the first embodiment, this information is the second output voltage / V2.

[0059] According to the first embodiment, the abnormality detection operation includes determining whether the two switching elements 61 and 62 are in a short-circuit state. If the control circuit 10A determines in the abnormality detection operation that the two switching elements 61 and 62 are in a short-circuit state, it turns one of the switching elements 61 OFF. Therefore, it is possible to suppress the two switching elements 61 and 62 from being in a short-circuit state, and thus suitably suppress damage to the switching elements 61 and 62. In the first embodiment, in the cases of [2] and [3] in Table 1, the control circuit 10A determines that the two switching elements 61 and 62 are in a short-circuit state. Therefore, in the cases of [2] and [3], the control circuit 10A turns the first output voltage V1 low, turning the switching element 61 OFF.

[0060] According to the first embodiment, if the control circuit 10A determines during the abnormality detection operation that an abnormality has occurred in the control state of the two switching elements 61 and 62, it outputs a signal indicating that an abnormality has occurred. Specifically, if the control circuit 10A determines during the abnormality detection operation that an abnormality has occurred in the control state of the two switching elements 61 and 62, it outputs a fault signal / FS1 that is low. Therefore, when an abnormality occurs in the control state of the two switching elements 61 and 62, the control circuit 10A can input that an abnormality has occurred to the controller 90 via the fault signal / FS1.

[0061] Furthermore, the effects obtained by the control circuit 10A described above can also be obtained similarly with the control circuit 10B.

[0062] According to the first embodiment, the drive circuit 80 is a drive circuit that drives a bridge circuit 60 having two switching elements 61 and 62 connected to each other. The drive circuit 80 comprises two control circuits 10A and 10B. The two control circuits 10A and 10B control the two switching elements 61 and 62, respectively. Therefore, control circuit 10A and control circuit 10B can monitor each other's control signals input to the other control circuit and output voltages output from the other control circuit, and can perform abnormality detection operations as described above. As a result, the drive circuit 80, which comprises the two control circuits 10A and 10B, can detect its own malfunction. Therefore, the drive circuit 80 can detect abnormalities in the bridge circuit 60 more quickly than in the conventional case where an abnormality occurring in the bridge circuit 60 is detected by an external circuit such as an overcurrent detection circuit 12. Therefore, the bridge circuit 60 can be protected more quickly, and damage to the switching elements 61 and 62 can be more suppressed.

[0063] (Second embodiment) The second embodiment differs from the first embodiment in the configuration of the control circuits 210A and 210B. In the following description, components similar to those in the above-described embodiment may be omitted from the description by using the same reference numerals as appropriate.

[0064] Figure 3 is a circuit diagram showing a semiconductor circuit 200 of the second embodiment. As shown in Figure 3, the controller 290 of the semiconductor circuit 200 has two CPUs 291 and 292. Each CPU 291 and 292 has the same configuration as the CPU 91 of the first embodiment. The controller 290 controls the drive circuit 280 by CPU 291 when both CPUs 291 and 292 are operating normally, and controls the drive circuit 280 by CPU 292 when CPU 291 fails. The controller 290 may, for example, control the first drive unit 281 of the drive circuit 280 by CPU 291 and control the second drive unit 282 of the drive circuit 280 by CPU 292. In this case, if one of the two CPUs 291 and 292 fails, the other CPU may control both the first drive unit 281 and the second drive unit 282.

[0065] The drive circuit 280 includes a first drive unit 281 that drives the switching element 61, a second drive unit 282 that drives the switching element 62, and isolators 83a, 83b, 284a, and 284b. The first drive unit 281 and the second drive unit 282 have similar configurations except that they drive different switching elements. Therefore, in the following description, the first drive unit 281 will be described as a representative, and the description of the second drive unit 282 may be omitted. The first drive unit 281 has a control circuit 210A. The second drive unit 282 has a control circuit 210B. In the following description, the control circuit 210A will be described as a representative of the control circuits 210A and 210B, and the description of the control circuit 210B may be omitted.

[0066] Figure 4 is a circuit diagram showing the control circuit 210A of the second embodiment. As shown in Figure 4, the control circuit 210A includes a first input terminal 11a, a second input terminal 11b, a fault output terminal 11c, a ground terminal 11d, a positive power terminal 11e, an output terminal 11f, a third input terminal 11g, a negative power terminal 11h, a second fault output terminal 211c, a second output terminal 211i, a fourth input terminal 211j, a determination unit 220, and an isolation transmission unit 250.

[0067] The second fault output terminal 211c is a terminal that outputs the second fault signal / FS2. The second fault signal / FS2 is input to the controller 290. The second fault signal / FS2 is a signal that changes based on the result of the abnormality detection operation. The second fault signal / FS2 changes according to the state of the enable signal / VS2, which will be described later. The second fault signal / FS2 is high when the enable signal / VS2 is high, and low when the enable signal / VS2 is low. As shown in Figure 3, a resistor R3b is placed between the second fault output terminal 211c and the power supply terminal of the controller 290 to which the positive power supply voltage VDD is applied.

[0068] The second output terminal 211i is a terminal that outputs the enable signal VS1. The enable signal VS1 is a signal that turns on the switching element 62 controlled by the other control circuit 210B. The enable signal VS1 is input to the isolator 284b via the resistor R8a. The enable signal VS1 is inverted by isolation transmission in the isolator 284b to become the enable signal / VS1, which is input to the fourth input terminal 211j of the control circuit 210B. The isolator 284b has the same configuration as the isolator 83b. A resistor R7b is placed between the output terminal of the isolator 284b and the positive power supply terminal 11e of the control circuit 210B. When the enable signal VS1 is high, that is, when the enable signal / VS1 is low, the second output voltage V2 output from the control circuit 210B becomes high when the enable signal / VS1 is input to the control circuit 210B, and the switching element 62 is turned on.

[0069] The fourth input terminal 211j of the control circuit 210A receives the enable signal / VS2. The enable signal / VS2 is input from the control circuit 210B via the isolator 284a. The enable signal / VS2 is the signal obtained by inverting the enable signal VS2 output from the second output terminal 211i of the control circuit 210B through the isolator 284a. The enable signal VS2 is the signal output from the other control circuit 210B and is a signal to turn on the switching element 61 controlled by the control circuit 210A. The enable signal VS2 output from the second output terminal 211i is input to the isolator 284a via the resistor R8b. The enable signal VS2 is inverted by isolation transmission in the isolator 284a to become the enable signal / VS2, which is then input to the fourth input terminal 211j of the control circuit 210A. The isolator 284a has the same configuration as the isolator 83a. A resistor R7a is placed between the output terminal of the isolator 284a and the positive power supply terminal 11e of the control circuit 210A. When the enable signal VS2 is high, that is, when the enable signal / VS2 is low, the first output voltage V1 output from the control circuit 210A becomes high when the enable signal / VS2 is input to the control circuit 210A, and the switching element 61 is turned ON.

[0070] As shown in Figure 4, the isolation transmission unit 250 includes a first transmission unit 51, a second transmission unit 52, a third transmission unit 53, a fourth transmission unit 254, a shielding film 55, and a conversion unit 50a. The fourth transmission unit 254 isolates and transmits the enable signal VS2 input from the NOT circuit 244 of the determination unit 220 (described later) to the second fault output terminal 211c. The fourth transmission unit 254 is an optical coupler having a light-emitting diode 254a and a phototransistor 254b. The structure of the fourth transmission unit 254 is the same as that of the third transmission unit 53. The enable signal VS2 output from the NOT circuit 244 is inverted by the fourth transmission unit 254 and output as a second fault signal / FS2 from the second fault output terminal 211c to the controller 290. The other configurations of the isolation transmission unit 250 are the same as the other configurations of the isolation transmission unit 50 in the first embodiment.

[0071] The determination unit 220 includes an output determination unit 230 and a fault determination unit 240. In the second embodiment, the output determination unit 230 includes an AND circuit 31, an OR circuit 233, and an enable output determination unit 270. The OR circuit 233 receives two signals: the output from the AND circuit 31 and the enable signal VS2 inverted by the NOT circuit 244 of the fault determination unit 240. The OR circuit 233 outputs a first output voltage V1 to the output terminal 11f based on the two input signals. The OR circuit 233 sets the first output voltage V1 high when at least one of the output from the AND circuit 31 and the enable signal VS2 is high. The OR circuit 233 sets the first output voltage V1 low when both the output from the AND circuit 31 and the enable signal VS2 are low.

[0072] The enable output determination unit 270 changes the state of the enable signal VS1 to be output based on the first control signal / S1, the second control signal S2, and the second output voltage / V2. The enable output determination unit 270 has an AND circuit 271. The AND circuit 271 receives three signals: the first control signal / S1 inverted via the NOT circuit 27, the second control signal S2 input via the buffer circuit 25, and the second output voltage / V2 input via the buffer circuit 23. The AND circuit 271 sets its output value to high when all three input signals are high. The AND circuit 271 sets its output value to low when at least one of the three input signals is low. The output value output from the AND circuit 271 is output to the second output terminal 211i as the enable signal VS1. The other configurations of the output determination unit 230 are the same as the other configurations of the output determination unit 30 of the first embodiment.

[0073] In the second embodiment, the fault determination unit 240 determines whether to set the output of the fault signal / FS1 and the second fault signal / FS2 to high or low. The fault determination unit 240 includes an AND circuit 41, an AND circuit 42, a NOR circuit 43, and a NOT circuit 244. The NOT circuit 244 receives the enable signal / VS2 as input. The NOT circuit 244 inverts the enable signal / VS2 and outputs it as the enable signal VS2. The enable signal VS2 is input to the isolation transmission unit 250 and the OR circuit 233. When the enable signal VS2 is high, the light-emitting diode 254a of the fourth transmission unit 254 lights up, and the phototransistor 254b turns ON. As a result, the second fault signal / FS2 output from the second fault output terminal 211c becomes low. In other words, the second fault signal / FS2 indicates an abnormal state. When the enable signal VS2 is low, the second fault signal / FS2 output from the second fault output terminal 211c becomes high. The other configurations of the fault determination unit 240 are the same as those of the fault determination unit 40 in the first embodiment.

[0074] Table 2 shows the first control signal S1, the second control signal S2, the second output voltage / V2, the enable signal VS1, the first output voltage V1, the fault signal / FS1, and the result of the abnormality detection operation in the second embodiment.

[0075] [Table 2]

[0076] The combinations of the first control signal S1, the second control signal S2, and the second output voltage / V2 in Table 2 [1] to [8] are the same as the combinations of the first control signal S1, the second control signal S2, and the second output voltage / V2 in Table 1 [1] to [8] of the first embodiment. All items in Table 2 except the enable signal VS1 are the same as in Table 1.

[0077] For example, in the normal case shown in Table 2 [1], two of the three signals / S1, S2, and / V2 input to the AND circuit 271 of the enable output determination unit 270, / S1 and S2, are low. Therefore, the output of the AND circuit 271 is low, and the enable signal VS1 is low.

[0078] For example, in Table 2, when an abnormality occurs in the input control signal [2], two of the three signals / S1, S2, and / V2 input to the AND circuit 271 of the enable output determination unit 270, / S1 and / V2, become low. Therefore, the output of the AND circuit 271 becomes low, and the enable signal VS1 becomes low. In this case, although an abnormality has occurred, it is an input abnormality in the control signal, so the enable signal VS1 is fixed at low.

[0079] For example, in [6] in Table 2, since the second control signal S2 is high, under normal circumstances the second output voltage V2 should also be high, and the second output voltage / V2 should be low. However, in the case of [6], the second output voltage / V2 is high, and the control circuit 210B is not operating normally. Therefore, the other switching element 62 does not enter a normal state. In this case, all three signals / S1, S2, and / V2 input to the AND circuit 271 of the enable output determination unit 270 are high. Therefore, the output of the AND circuit 271 becomes high, and the enable signal VS1 becomes high. As a result, the enable signal / VS1 input to the fourth input terminal 211j of the control circuit 210B becomes low, and the high enable signal VS1 inverted by the NOT circuit 244 is input to the OR circuit 233 of the control circuit 210B. Consequently, the output of the OR circuit 233 of the control circuit 210B, which was low, becomes high, and the second output voltage V2 output from the control circuit 210B becomes high. This allows the switching element 62 to be switched to a normal state.

[0080] Thus, in the second embodiment, the determination unit 220 determines whether the state of the other switching element 62 is normal based on the first control signal S1, the second control signal S2, and the second output voltage / V2. If it determines that the state of the other switching element 62 is not normal, it outputs a signal to set the state of the other switching element 62 to normal, i.e., an enable signal VS1. When the enable signal / VS1 is low in the control circuit 210B, the second fault signal / FS2 output from the second fault output terminal 211c of the control circuit 210B is low. Therefore, the state of the switching element 62 is switched to a normal state by the enable signal / VS1 input from the control circuit 210A, while the second fault signal / FS2, indicating that the control state of the switching element 62 in the control circuit 210B is abnormal, is input to the controller 290.

[0081] The other configurations of the control circuit 210A are the same as those of the control circuit 10A in the first embodiment. The control circuit 210B is the same as the control circuit 210A, except that the input and output signals differ as appropriate due to the different switching elements being controlled. The other configurations of the semiconductor circuit 200 are the same as those of the semiconductor circuit 100 in the first embodiment.

[0082] According to the second embodiment, the abnormality determination operation in the control circuit 210A includes determining whether the state of the other switching element 62 is normal based on the first control signal S1, the second control signal S2, and the second output voltage / V2 (element information). If the control circuit 210A determines in the abnormality determination operation that the state of the other switching element 62 is not normal, it outputs an enable signal VS1 to bring the state of the other switching element 62 back to normal. Therefore, if the switching element 62 controlled by the other control circuit 210B is not operating normally, the control circuit 210A can switch the other switching element 62 back to normal. Thus, even if an abnormality occurs, the bridge circuit 60 can continue to operate.

[0083] According to the second embodiment, in the control circuit 210A, a signal to bring the other switching element 62 to a normal state is output to the control circuit 210B that controls the other switching element 62. Therefore, the control circuit 210A can operate the control circuit 210B based on this signal to switch the other switching element 62 to a normal state. Specifically, in the second embodiment, if the other switching element 62 is in the OFF state at a timing when it should be in the ON state, the control circuit 210A outputs an enable signal VS1 to the control circuit 210B to turn the switching element 62 ON. As a result, the control circuit 210B outputs a second output voltage V2 to turn the switching element 62 ON, and the switching element 62 is turned ON.

[0084] Furthermore, the effects obtained by the control circuit 210A described above can also be obtained similarly with the control circuit 210B.

[0085] In the example described above, an enable signal VS1 is output from one control circuit 210A to turn on the other switching element 62 when it should be in the ON state but is in the OFF state. However, this is not the only example. For example, a disable signal may be output from one control circuit 210A to turn off the other switching element 62 when it should be in the OFF state but is in the ON state. The same applies to control circuit 210B. For example, if the disable signal output from control circuit 210A is high, the switching element 62 controlled by control circuit 210B is switched to the OFF state. In this case, the disable signal is high in cases [2], [3], and [8] in Table 2, and low in cases [1], [4], [5], [6], and [7].

[0086] (Third embodiment) The third embodiment differs from the second embodiment in that a buffer drive unit 385 is provided. In the following description, components similar to those in the embodiments described above may be omitted from the description by using the same reference numerals as appropriate.

[0087] Figure 5 is a circuit diagram showing a semiconductor circuit 300 of a third embodiment. As shown in Figure 5, the drive circuit 380 of the semiconductor circuit 300 has a buffer drive unit 385. In this embodiment, the buffer drive unit 385 is provided in the first drive unit 381. The first drive unit 381 is the same as the first drive unit 281 in the second embodiment, except that it has the buffer drive unit 385. The buffer drive unit 385 has a NOT circuit 385a and an OR circuit 385b. The NOT circuit 385a inverts the enable signal / VS2 input from the isolator 284a to the fourth input terminal 211j and inputs it to the OR circuit 385b as the enable signal VS2.

[0088] The OR circuit 385b is positioned between the output terminal 11f of the control circuit 210A and the resistor R5a. The OR circuit 385b receives the enable signal VS2, which has been inverted by the NOT circuit 385a, and the first output voltage V1, which is output from the output terminal 11f. Based on the enable signal VS2 and the first output voltage V1, the OR circuit 385b outputs a first output voltage V1a, which is output to the gate terminal of the switching element 61. The OR circuit 385b sets the first output voltage V1a high when at least one of the enable signal VS2 and the first output voltage V1 is high. The OR circuit 385b sets the first output voltage V1a low when both the enable signal VS2 and the first output voltage V1 are low. In the third embodiment, the resistor R9a is positioned between the output terminal 11f and the wiring to which the negative power supply voltage VEE1 is applied. The resistor R9b is positioned between the output terminal of the NOT circuit 385a and the wiring to which the negative power supply voltage VEE1 is applied.

[0089] For example, if the control circuit 210A stops due to a malfunction or other reason, the first output voltage V1 output from the output terminal 11f of the control circuit 210A will always be low. In this case, the first output voltage V1 input to the control circuit 210B will be high, so at the timing when the switching element 61 is normally turned ON, the enable signal VS2 output from the control circuit 210B will be high, and the enable signal VS2 input to the control circuit 210A via the isolator 284a will be low. If the control circuit 210A is operating, the enable signal VS2 input to the control circuit 210A will switch the switching element 61 to the ON state as described in the second embodiment. However, since the control circuit 210A has stopped operating, the first output voltage V1 output from the control circuit 210A will not be high, and the switching element 61 cannot be turned ON. In contrast, in the third embodiment, the enable signal VS2 output from the control circuit 210B is also input to the buffer drive unit 385. The buffer drive unit 385 outputs a high first output voltage V1a applied to the switching element 61 if the enable signal VS2, which has been inverted by the NOT circuit 385a, is high. As a result, even if the control circuit 210A is stopped, the control circuit 210B can turn on the switching element 61.

[0090] Thus, according to the third embodiment, if the other control circuit 210A stops, the control circuit 210B controls the switching element 61 that was controlled by the other control circuit 210A, taking over from the other control circuit 210A. Therefore, even if the control circuit 210A stops, the bridge circuit 60 can continue to be driven.

[0091] The buffer drive unit 385 described above is a circuit that allows the control circuit 210B to control the switching element 61 when the control circuit 210A stops, but it is not limited to this. The buffer drive unit 385 may also be provided for the control circuit 210B in the same way as for the control circuit 210A. In this case, even if the control circuit 210B stops, the control circuit 210A can control the switching element 62. For example, if the drive circuit 380 has three or more control circuits, at least one of the three or more control circuits may take over the control of the switching element that was being controlled by the other control circuits when the other control circuits stop. At least one of the three or more control circuits may take over the control of the switching element that was being controlled by two or more other control circuits when two or more of the other control circuits stop.

[0092] (Fourth embodiment) The fourth embodiment differs from the second embodiment in the configuration of the insulating transmission section 450. In the following description, components similar to those in the embodiments described above may be omitted from the description by using the same reference numerals as appropriate.

[0093] Figure 6 is a circuit diagram showing the control circuit 410A of the fourth embodiment. As shown in Figure 6, the isolated transmission unit 450 of the control circuit 410A has a first transmission unit 451, a second transmission unit 452, a third transmission unit 453, and a fourth transmission unit 454. In the fourth embodiment, the first transmission unit 451, the second transmission unit 452, the third transmission unit 453, and the fourth transmission unit 454 transmit signals isolated by magnetic coupling. The first transmission unit 451, the second transmission unit 452, the third transmission unit 453, and the fourth transmission unit 454 have the same functions as the first transmission unit 51, the second transmission unit 52, the third transmission unit 53, and the fourth transmission unit 254 of the second embodiment described above, except that the transmission method is different. The first transmission unit 451 receives a first control signal S1 via a buffer circuit 440a. The second transmission unit 452 receives the second control signal S2 via the buffer circuit 440b. The signal output from the third transmission unit 453 is inverted by the NOT circuit 440c and output as a fault signal / FS1 from the fault output terminal 11c. The signal output from the fourth transmission unit 454 is inverted by the NOT circuit 440d and output as a second fault signal / FS2 from the second fault output terminal 211c.

[0094] The other configurations of the control circuit 410A are the same as those of the control circuit 210A in the second embodiment. The isolators 83a, 83b, 284a, and 284b in the above-described embodiments may also be isolators that transmit signals in isolation by magnetic coupling, similar to the isolation transmission unit 450.

[0095] (Fifth embodiment) The fifth embodiment differs from the fourth embodiment in that it includes an input determination unit 582. In the following description, components similar to those in the embodiments described above may be omitted from the description by using the same reference numerals as appropriate.

[0096] Figure 7 is a circuit diagram showing the control circuit 510A of the fifth embodiment. As shown in Figure 7, the control circuit 510A has an input determination unit 582. The input determination unit 582 is a circuit that determines whether or not there is an abnormality in the first control signal S1 and the second control signal S2 input to the control circuit 510A. The input determination unit 582 is located between the first input terminal 11a and the second input terminal 11b and the isolation transmission unit 450. The input determination unit 582 has AND circuits 582a, 582d, NAND circuits 582b, 582c, and a NOR circuit 582e.

[0097] The AND gate 582a receives two signals: a first control signal S1 and the output of the NAND gate 582b. The AND gate 582a outputs a first control signal S1 that is high when both input signals are high, and outputs a first control signal S1 that is low when at least one of the two input signals is low.

[0098] The NAND gate 582b receives two signals: a first control signal S1 and a second control signal S2. The NAND gate 582b outputs a low output value when both input signals are high, and a high output value when at least one of the two input signals is low. The output of the NAND gate 582b is input to the AND gate 582a and the NOR gate 582e.

[0099] The NAND gate 582c receives two signals: a first control signal S1 and a second control signal S2. The NAND gate 582c outputs a low value when both input signals are high, and outputs a high value when at least one of the two input signals is low. The output of the NAND gate 582c is input to the AND gate 582d.

[0100] The AND gate 582d receives two signals: the second control signal S2 and the output of the NAND gate 582c. The AND gate 582d outputs a second control signal S2 that is high when both input signals are high, and outputs a second control signal S2 that is low when at least one of the two input signals is low.

[0101] The NOR circuit 582e receives the output from the NAND circuit 582b and the output from the buffer circuit 540c. The output from the buffer circuit 540c is the fault signal FS1 output from the NOR circuit 43 of the determination unit 220, which is transmitted in isolation by the third transmission unit 453. The output from the NAND circuit 582b is inverted and input to the NOR circuit 582e. The NOR circuit 582e outputs a fault signal / FS1 that is low if at least one of the two input signals is high, and outputs a fault signal / FS1 that is high if both input signals are low.

[0102] As described above, the NAND circuits 582b and 582c output a low output value when both input signals are high, and a high output value otherwise. In other words, the NAND circuits 582b and 582c output a low output value only when both the first control signal S1 and the second control signal S2 are high. Since the condition in which both the first control signal S1 and the second control signal S2 are high does not occur when the bridge circuit 60 is normally driven, when the NAND circuits 582b and 582c output a low output value, there is an abnormality in the control signals output from the controller 290. The AND circuits 582a and 582d each receive the outputs from the NAND circuits 582b and 582c, respectively, so when the outputs of the NAND circuits 582b and 582c are low, the values ​​output from each AND circuit 582a and 582d will also be low. As a result, if an abnormality occurs in which both the first control signal S1 and the second control signal S2 become high, the input determination unit 582 converts both the first control signal S1 and the second control signal S2 to low before they are input to the isolation transmission unit 450. Therefore, the input determination unit 582 can perform an abnormality determination operation faster than the determination unit 220 can, and it is possible to detect that an abnormality has occurred in the control state of the two switching elements 61 and 62. Furthermore, if the input determination unit 582 determines that an abnormality has occurred, it sets both the first control signal S1 and the second control signal S2 to low to prevent the two switching elements 61 and 62 from becoming ON simultaneously and short-circuiting. Therefore, the control circuit 510A can protect the two switching elements 61 and 62 more quickly, and damage to the two switching elements 61 and 62 can be more effectively suppressed.

[0103] Thus, according to the fifth embodiment, the abnormality determination operation performed by the input determination unit 582 includes determining whether or not an abnormality has occurred in the control state of the two switching elements 61 and 62 based on the first control signal S1 and the second control signal S2. Therefore, as described above, an abnormality in the input control signals can be determined immediately after the first control signal S1 and the second control signal S2 are input to the first input terminal 11a and the second input terminal 11b, allowing for more rapid detection of abnormalities. Consequently, damage to the two switching elements 61 and 62 can be more effectively suppressed.

[0104] When the output from the NAND circuit 582b is low, the NOR circuit 582e receives a value that inverts that output to high. Therefore, regardless of the output from the buffer circuit 540c, the fault signal / FS1 output from the NOR circuit 582e is low. In other words, when both the first control signal S1 and the second control signal S2 are high, regardless of the output from the fault detection unit 240, the fault signal / FS1 output from the fault output terminal 11c is low, indicating that an abnormality has occurred. Consequently, when an abnormality occurs in which both the first control signal S1 and the second control signal S2 are high, the fault signal / FS1 indicating that the abnormality has occurred is input to the controller 290.

[0105] In the example described above, the input determination unit 582 determined that an abnormality had occurred in the input and turned off the two switching elements 61 and 62 when both the first control signal S1 and the second control signal S2 were high. However, the input determination unit 582 may also determine that an abnormality has occurred in the input and turn off the two switching elements 61 and 62 when the interval between the timing when the first control signal S1 is high and the timing when the second control signal S2 is high, i.e., the dead time, becomes shorter than or equal to a set predetermined value.

[0106] (Sixth embodiment) The sixth embodiment differs from the fourth embodiment in the configuration of the insulating transmission section 650. In the following description, components similar to those in the embodiments described above may be omitted from the description by using the same reference numerals as appropriate.

[0107] Figure 8 is a circuit diagram showing the control circuit 610A of the sixth embodiment. As shown in Figure 8, the isolated transmission section 650 of the control circuit 610A has a first transmission section 651, a second transmission section 652, a third transmission section 653, and a fourth transmission section 654. In the sixth embodiment, the first transmission section 651, the second transmission section 652, the third transmission section 653, and the fourth transmission section 654 transmit signals isolated by capacitive coupling. The first transmission section 651, the second transmission section 652, the third transmission section 653, and the fourth transmission section 654 are each capacitors. The first transmission section 651, the second transmission section 652, the third transmission section 653, and the fourth transmission section 454 have the same functions as the first transmission section 451, the second transmission section 452, the third transmission section 453, and the fourth transmission section 454 of the fourth embodiment described above, except that the transmission method is different.

[0108] The other configurations of the control circuit 610A are the same as those of the control circuit 410A in the fourth embodiment. The isolators 83a, 83b, 284a, and 284b in the embodiments described above may also be isolators that transmit signals in isolation by capacitive coupling, similar to the isolation transmission unit 650.

[0109] (Seventh Embodiment) The seventh embodiment differs from the fifth embodiment in the configuration of the input determination unit 782. In the following description, components similar to those in the embodiments described above may be omitted from the description by using the same reference numerals as appropriate.

[0110] Figure 9 is a circuit diagram showing the control circuit 710A of the seventh embodiment. As shown in Figure 9, the isolation transmission unit of the control circuit 710A is the isolation transmission unit 650 in the sixth embodiment. The control circuit 710A has a third output terminal 711k to which a first control signal S1 is output. The first control signal S1 output from the third output terminal 711k is input to the second input terminal 11b of the other control circuit (not shown). The second control signal S2 input to the second input terminal 11b in the seventh embodiment is the second control signal S2 output from the third output terminal 711k of the other control circuit (not shown).

[0111] The input determination unit 782 of the control circuit 710A includes AND circuits 782a and 782d, a NAND circuit 782b, a NOR circuit 782e, a delay circuit 783, and a switching circuit 784. Two signals, a first control signal S1 and a second control signal S2, are input to the AND circuit 782a. The output value of the AND circuit 782a is high when both the first control signal S1 and the second control signal S2 are high, and low when at least one of the first control signal S1 and the second control signal S2 is low. The output value of the AND circuit 782a is input to the switching circuit 784 as a set signal.

[0112] The NAND gate 782b receives two signals: a first control signal S1 and a second control signal S2. The output value of the NAND gate 782b is low when both the first control signal S1 and the second control signal S2 are high, and high when at least one of the first control signal S1 and the second control signal S2 is low.

[0113] The AND circuit 782d receives two signals: the output from the NAND circuit 782b and the second control signal S2. The AND circuit 782d outputs a second control signal S2 that is high when both input signals are high, and outputs a second control signal S2 that is low when at least one of the two input signals is low. The second control signal S2 output from the AND circuit 782d is input to the determination unit 220 via the buffer circuit 440b and the second transmission unit 652.

[0114] The NOR gate 782e receives the output from the NAND gate 782b and the output from the buffer gate 540c, i.e., the fault signal FS1. The output from the NAND gate 782b is inverted and input to the NOR gate 782e. The NOR gate 782e outputs a fault signal / FS1 that is low if at least one of the two input signals is high, and outputs a fault signal / FS1 that is high if both input signals are low.

[0115] The delay circuit 783 includes a clock generation unit 783a and a plurality of D-type flip-flops 783b. The plurality of D-type flip-flops 783b are connected in series. The clock generation unit 783a inputs a clock signal to the plurality of D-type flip-flops 783b. The delay circuit 783 receives the first control signal S1 input to the first input terminal 11a. The first control signal S1 input to the delay circuit 783 is delayed by the plurality of D-type flip-flops 783b and input to the switching circuit 784 as a B signal. The delay of the first control signal S1 input to the delay circuit 783 increases as the number of D-type flip-flops 783b through which it passes increases. The number of D-type flip-flops 783b through which the first control signal S1 passes may be predetermined or may be changed as appropriate depending on the control state of the bridge circuit 60, etc. The number of D-type flip-flops 783b through which the first control signal S1 passes may be appropriately changed based on the first control signal S1 and the second control signal S2.

[0116] The switching circuit 784 receives the first control signal S1 input to the first input terminal 11a, the output from the AND circuit 782a, and the output from the delay circuit 783. The first control signal S1 from the first input terminal 11a input to the switching circuit 784 is input to the switching circuit 784 as the A signal. The switching circuit 784 is a circuit that switches the output Y between the A signal and the B signal according to the input from the AND circuit 782a, which is input as the set signal. When the set signal input from the AND circuit 782a is low, the switching circuit 784 outputs the A signal, that is, the undelayed first control signal S1 input to the first input terminal 11a, as the output Y. On the other hand, when the set signal input from the AND circuit 782a is high, the switching circuit 784 outputs the B signal, that is, the delayed first control signal S1 input from the delay circuit 783, as the output Y. The first control signal S1 output from the switching circuit 784 is input to the determination unit 220 via the buffer circuit 440a and the first transmission unit 651, and is also output from the third output terminal 711k to the other control circuit (not shown).

[0117] For example, if the first control signal S1 input to the first input terminal 11a is high and the second control signal S2 input to the second input terminal 11b is low, the output from the AND circuit 782a will be low, and the switching circuit 784 will output the first control signal S1 without delay. In this case, the second control signal S2 output from the AND circuit 782d will also remain low. In other words, the first control signal S1 input to the first input terminal 11a and the second control signal S2 input to the second input terminal 11b are directly input to the determination unit 220 via the isolation transmission unit 650. This is also true when the first control signal S1 input to the first input terminal 11a is low and the second control signal S2 input to the second input terminal 11b is high, and when both the first control signal S1 input to the first input terminal 11a and the second control signal S2 input to the second input terminal 11b are low.

[0118] On the other hand, when both the first control signal S1 input to the first input terminal 11a and the second control signal S2 input to the second input terminal 11b are high, the output from the AND circuit 782a is high, and the switching circuit 784 outputs the first control signal S1 delayed by the delay circuit 783. Also, in this case, the output from the NAND circuit 782b is low, so even though the second control signal S2 is high, the second control signal S2 output from the AND circuit 782d is low. Until the delayed signal input from the delay circuit 783 in the switching circuit 784 becomes high, that is, until the delay time in the delay circuit 783 has elapsed, the first control signal S1 output from the switching circuit 784 is low. Therefore, immediately after the first control signal S1 and the second control signal S2, both of which are high, are input to the first input terminal 11a and the second input terminal 11b respectively, the isolation transmission unit 650 receives both the first control signal S1 and the second control signal S2 in a low state. Subsequently, after the time delayed by the delay circuit 783 has elapsed, the delayed first control signal S1 is output from the switching circuit 784 in a high state. In other words, the time during which both the first control signal S1 and the second control signal S2 are low can be made equal to the time during which the first control signal S1 is delayed by the delay circuit 783. The time during which both the first control signal S1 and the second control signal S2 are low is equal to the time during which both switching elements 61 and 62 are in the OFF state, i.e., the dead time. Therefore, by delaying the first control signal S1 with the delay circuit 783, the dead time can be made equal to the time during which the first control signal S1 is delayed by the delay circuit 783. In this way, the control circuit 710A of the seventh embodiment can generate dead time with the delay circuit 783.

[0119] The state in which both the first control signal S1 and the second control signal S2 are high means that there is no dead time. Therefore, by comparing the first control signal S1 and the second control signal S2, it is possible to determine whether or not there is an abnormality in the dead time. In other words, in the seventh embodiment, the abnormality determination operation performed by the input determination unit 782 includes determining whether or not there is an abnormality in the dead time in which both switching elements 61 and 62 are in the OFF state. Furthermore, if the input determination unit 782 determines in the abnormality determination operation that both the first control signal S1 and the second control signal S2 are high and that there is an abnormality in the dead time, it generates a predetermined dead time using the delay circuit 783 described above, and outputs the first control signal S1 and the second control signal S2 based on the generated dead time to the determination unit 220 via the isolation transmission unit 650.

[0120] As described above, according to the seventh embodiment, the abnormality determination operation performed by the control circuit 710A includes determining whether or not an abnormality has occurred in the dead time when both switching elements 61 and 62 are in the OFF state. If the control circuit 710A determines in the abnormality determination operation that an abnormality has occurred in the dead time, it generates a predetermined dead time and controls one of the switching elements 61 based on the generated dead time. Therefore, even if an abnormality occurs in the dead time, an appropriate dead time can be generated to continue driving both switching elements 61 and 62. Furthermore, it is possible to suppress both switching elements 61 and 62 from being in the ON state, and to suppress short circuits between the two switching elements 61 and 62. Thus, damage to the two switching elements 61 and 62 can be further suppressed.

[0121] Furthermore, in the seventh embodiment, the first control signal S1 output from the switching circuit 784 is output from the third output terminal 711k and input to the second input terminal 11b of the other control circuit (not shown). Therefore, if the first control signal S1 is delayed as described above, the delayed first control signal S1 is input to the other control circuit (not shown). As a result, the other control circuit (not shown) can also drive the switching element 62 based on the dead time generated by the delay circuit 783.

[0122] When the two switching elements 61 and 62 are driven by the dead time generated as described above, the first control signal S1 and the second control signal S2 input to the first input terminal 11a and the second input terminal 11b, respectively, are both high. As a result, the signal output from the NAND circuit 782b becomes low, and the signal input from the NAND circuit 782b to the NOR circuit 782e is inverted and becomes high. Consequently, the fault signal / FS1 output from the NOR circuit 782e to the fault output terminal 11c becomes low, indicating an abnormal state. Therefore, when an abnormality occurs in which both the first control signal S1 and the second control signal S2 become high, the fault signal / FS1 indicating that the abnormality has occurred is input to the controller 290.

[0123] In the example described above, a dead time is generated when both the first control signal S1 and the second control signal S2 are high, i.e., when no dead time is provided. However, the example is not limited to this. The input determination unit 782 may also operate to change the dead time to the generated dead time when the dead time becomes shorter than or equal to a set predetermined value.

[0124] (Eighth embodiment) The eighth embodiment differs from the second embodiment in that the two control circuits 810A and 810B are mounted in a single semiconductor package. In the following description, components similar to those in the embodiments described above may be omitted from the description by using the same reference numerals as appropriate.

[0125] Figure 10 is a circuit diagram showing a semiconductor circuit 800 of the eighth embodiment. As shown in Figure 10, the drive circuit 880 in the semiconductor circuit 800 comprises a semiconductor package 800a, power supplies E1 and E2, resistors R1a, R1b, R3a, R3b, R3c, R5a, R5b, and capacitors C1 and C2. The semiconductor package 800a has a control circuit 810A and a control circuit 810B. The semiconductor package 800a also incorporates an isolation transmission section having the same function as the isolators 83a, 83b, 284a, and 284b in the second embodiment. In Figure 10, the isolation transmission section having the same function as the isolators 83a, 83b, 284a, and 284b is indicated by the same reference numerals as the isolators 83a, 83b, 284a, and 284b in the second embodiment. Furthermore, each isolation transmission unit incorporated into the semiconductor package 800a is not limited to isolation transmission units using optical coupling, such as the isolators 83a, 83b, 284a, and 284b in the second embodiment, but may also be an isolation transmission unit using magnetic coupling, such as the isolation transmission unit 450 in the fourth embodiment, or an isolation transmission unit using capacitive coupling, such as the isolation transmission unit 650 in the sixth embodiment. The semiconductor package 800a is configured by packaging, for example, the isolation transmission unit, a semiconductor chip on which the control circuit 810A is mounted, and a semiconductor chip on which the control circuit 810B is mounted. The drive circuit 880 may, instead of the semiconductor package 800a, include a semiconductor chip on which the isolation transmission unit and the control circuits 810A and 810B are mounted.

[0126] In this embodiment, each of the control circuits 810A and 810B is a semiconductor chip having portions corresponding to the determination unit 220, the conversion unit 50a, and the photodiodes 51b and 52b in the second embodiment. The portions of the control circuits 210A and 210B in the second embodiment that correspond to portions other than the determination unit 220, the conversion unit 50a, and the photodiodes 51b and 52b are provided separately in a semiconductor package 800a and function in the same way as in the second embodiment. Note that each of the control circuits 810A and 810B may also have portions corresponding to portions other than the determination unit 220, the conversion unit 50a, and the photodiodes 51b and 52b in the second embodiment.

[0127] Capacitor C1 and resistor R5a may be mounted on the semiconductor chip of the control circuit 810A, which is built into the semiconductor package 800a. Capacitor C2 and resistor R5b may be mounted on the semiconductor chip of the control circuit 810B, which is built into the semiconductor package 800a. If the element that isolates and transmits each fault signal among the elements built into the semiconductor package 800a is a digital isolator, then resistors R1a, R1b, R3a, R3b, and R3c may be built into the semiconductor package 800a. In other words, all elements of the drive circuit 880 except for the power supplies E1 and E2 may be provided in the semiconductor package 800a.

[0128] The semiconductor package 800a has a third fault output terminal 811c and a disable terminal 811m. The third fault output terminal 811c and the disable terminal 811m are connected to the control circuit 810B.

[0129] A third fault signal / FS3, based on the detection result of the overcurrent detection circuit 12, is output from the third fault output terminal 811c. The third fault signal / FS3 is input to the controller 890. When the third fault signal / FS3 is low, the controller 890 inputs control signals to the control circuits 810A and 810B, respectively, to turn off the two switching elements 61 and 62. A resistor R3c is placed between the third fault output terminal 811c and the power supply terminal of the controller 890 to which the positive power supply voltage VDD is applied.

[0130] The output of the logic gate 12b of the overcurrent detection circuit 12 is input to the disable terminal 811m. When an overcurrent flows through the resistor element 12a of the overcurrent detection circuit 12 and the output from the logic gate 12b input to the disable terminal 811m becomes low, the third fault signal / FS3 output from the third fault output terminal 811c becomes low. This transmits to the controller 890 that an overcurrent has occurred in the bridge circuit 60, and the controller 890 inputs control signals to the control circuits 810A and 810B, respectively, to turn off the two switching elements 61 and 62. In the eighth embodiment, the fault signal / FS1 does not include a signal based on the detection result of the overcurrent detection circuit 12. The controller 890 is the same as the controller 290 of the second embodiment, except that the input fault signals are different.

[0131] The other configurations of the control circuits 810A and 810B are the same as the other configurations of the control circuits 210A and 210B in the second embodiment. The other configurations of the drive circuit 880 are the same as the other configurations of the drive circuit 280 in the second embodiment. The other configurations of the semiconductor circuit 800 are the same as the other configurations of the semiconductor circuit 200 in the second embodiment.

[0132] (Ninth embodiment) The ninth embodiment differs from the eighth embodiment in that various protective functions have been added. In the following description, components similar to those in the embodiments described above may be omitted from the description by using the same reference numerals as appropriate.

[0133] Figure 11 is a circuit diagram showing a semiconductor circuit 900 of the ninth embodiment. As shown in Figure 11, the drive circuit 980 in the semiconductor circuit 900 comprises a semiconductor package 900a having two control circuits 910A and 910B, similar to the eighth embodiment. The semiconductor package 900a has a DESAT terminal 911p, an AMC terminal 911r, and a second negative power supply terminal 911s. There are two of each of the DESAT terminal 911p, AMC terminal 911r, and second negative power supply terminal 911s. One DESAT terminal 911p, one AMC terminal 911r, and one second negative power supply terminal 911s are connected to control circuit 910A. The other DESAT terminal 911p, the other AMC terminal 911r, and the other second negative power supply terminal 911s are connected to control circuit 910B. In the following explanation, control circuit 910A will be described as a representative of control circuit 910A and 910B, and the explanation of control circuit 910B may be omitted.

[0134] A negative power supply voltage VEE1 is applied to the second negative power supply terminal 911s, which is connected to the control circuit 910A. A capacitor C3 is placed between the DESAT terminal 911p and the second negative power supply terminal 911s. The gate terminal of the switching element 61 is connected to the AMC terminal 911r, which is connected to the control circuit 910A.

[0135] Furthermore, the semiconductor circuit 900 may be provided with a gate negative bias power supply to bring the gate terminals of each switching element 61, 62 to a negative potential in order to prevent the switching elements 61, 62 from being accidentally turned ON when they are OFF. In this case, the second negative power supply terminal 911s may be disconnected from the negative power supply voltage VEE1 and connected to the negative terminal of the power supply E1 and the positive terminal of the gate negative bias power supply. Alternatively, in this case, the negative power supply voltage VEE1 may be applied to the negative terminal of the gate negative bias power supply.

[0136] The drive circuit 980 includes a DESAT circuit section 986, a UVLO circuit section 987, and an AMC circuit section 988. The DESAT circuit section 986, the UVLO circuit section 987, and the AMC circuit section 988 are connected to two control circuits 910A and 910B, respectively. The DESAT circuit section 986 connected to control circuit 910B has the same configuration as the DESAT circuit section 986 connected to control circuit 910A, except that it is connected to control circuit 910B. The UVLO circuit section 987 connected to control circuit 910B has the same configuration as the UVLO circuit section 987 connected to control circuit 910A, except that it is connected to control circuit 910B. The AMC circuit section 988 connected to control circuit 910B has the same configuration as the AMC circuit section 988 connected to control circuit 910A, except that it is connected to control circuit 910B. Therefore, in the following explanation, we will describe the DESAT circuit section 986, UVLO circuit section 987, and AMC circuit section 988 connected to the control circuit 910A, which controls the switching element 61, as representatives of each DESAT circuit section 986, UVLO circuit section 987, and AMC circuit section 988 connected to each control circuit 910A, 910B.

[0137] The DESAT circuit section 986 is a circuit that has a DESAT function that stops the output when the input voltage becomes higher than a predetermined value. The DESAT circuit section 986 includes a diode 986a, a resistor 986b, a DESAT determination unit 986c, a soft turn-off circuit section 986d, a current source 986e, and a capacitor C3. The anode of the diode 986a is connected to the DESAT terminal 911p via the resistor 986b. The cathode of the diode 986a is connected to the drain terminal of the switching element 61.

[0138] The DESAT determination unit 986c, the soft turn-off circuit unit 986d, and the current source 986e are integrated into the semiconductor package 900a. The DESAT determination unit 986c receives input from the DESAT terminal 911p and input from the second negative power supply terminal 911s. The current source 986e is positioned between the wiring connecting the DESAT determination unit 986c and the DESAT terminal 911p and the wiring to which the positive power supply voltage VCC1 is applied. The DESAT determination unit 986c determines whether the drain voltage generated based on the drain current flowing through the switching element 61 is higher than a predetermined value. The output of the DESAT determination unit 986c is input to the soft turn-off circuit unit 986d. The soft turn-off circuit unit 986d is positioned between the DESAT determination unit 986c and the output terminal 11f. When the DESAT determination unit 986c receives a determination result that the drain voltage generated by the switching element 61 is higher than a predetermined value, the soft turn-off circuit unit 986d gradually reduces the first output voltage V1 output from the output terminal 11f, thereby soft-turning off the switching element 61. This protects the switching element 61 by turning it OFF when the drain voltage generated by the switching element 61 becomes higher than a predetermined value.

[0139] The UVLO circuit 987 is a circuit that has an undervoltage lockout (UVLO) function to prevent malfunctions due to low voltage. The UVLO circuit 987 is built into the semiconductor package 900a. The UVLO circuit 987 receives the positive power supply voltage VCC1 and the voltage applied to the second negative power supply terminal 911s as input. When the positive power supply voltage VCC1 falls below a predetermined value, the UVLO circuit 987 turns off the switching element 61. This prevents excessive heat generation in the switching element 61.

[0140] The AMC circuit 988 is a circuit that has an active Miller clamp function. The AMC circuit 988 is built into the semiconductor package 900a. The AMC circuit 988 is connected to the AMC terminal 911r and the wiring to which the negative power supply voltage VEE1 is applied. When the voltage at the gate terminal of the switching element 61 rises and the switching element 61 is about to self-turn on, the AMC circuit 988 short-circuits the gate terminal of the switching element 61 to the wiring to which the negative power supply voltage VEE1 is applied, thereby suppressing the self-turn-on of the switching element 61. This prevents the bridge circuit 60 from malfunctioning.

[0141] Thus, the protection function based on the abnormality detection operation performed in the control circuits described in each of the embodiments above can be used in conjunction with other protection functions such as the DESAT circuit section 986, the UVLO circuit section 987, and the AMC circuit section 988 described above.

[0142] The other configurations of the control circuits 910A and 910B are the same as those of the control circuits 810A and 810B in the eighth embodiment. The other configurations of the drive circuit 980 are the same as those of the drive circuit 880 in the eighth embodiment. The other configurations of the semiconductor circuit 900 are the same as those of the semiconductor circuit 800 in the eighth embodiment.

[0143] (Tenth embodiment) The tenth embodiment is an embodiment in which the semiconductor circuit 1000 is a circuit that drives a three-phase motor 1000m. In the following description, the same components as in the embodiments described above may be omitted from the description by using the same reference numerals as appropriate.

[0144] Figure 12 is a circuit diagram showing a semiconductor circuit 1000 of the tenth embodiment. As shown in Figure 12, the semiconductor circuit 1000 comprises a controller 1090, drive circuits 880U, 880V, and 880W, and a bridge circuit 1060. The three drive circuits 880U, 880V, and 880W each have the same configuration as the drive circuit 880 of the eighth embodiment. The three drive circuits 880U, 880V, and 880W are controlled by the controller 1090 in the same way as in each of the embodiments described above. The configuration of the controller 1090 can be the same as the controller of each of the embodiments described above.

[0145] The bridge circuit 1060 is a three-phase inverter circuit. The bridge circuit 1060 has three legs 1060U, 1060V, and 1060W connected in parallel with each other. Leg 1060U has two switching elements 61U and 62U connected to each other. Leg 1060V has two switching elements 61V and 62V connected to each other. Leg 1060W has two switching elements 61W and 62W connected to each other. Switching elements 61U, 61V, and 61W are the same as switching element 61 in each of the embodiments described above. Switching elements 62U, 62V, and 62W are the same as switching element 62 in each of the embodiments described above.

[0146] Leg 1060U is driven by drive circuit 880U. Leg 1060V is driven by drive circuit 880V. Leg 1060W is driven by drive circuit 880W. The 3-phase motor 1000m is supplied with the U-phase current Iu output from Leg 1060U, the V-phase current Iv output from Leg 1060V, and the W-phase current Iw output from Leg 1060W. The U-phase current Iu, V-phase current Iv, and W-phase current Iw are currents that are out of phase with respect to each other. The 3-phase motor 1000m is driven by the supply of the U-phase current Iu, V-phase current Iv, and W-phase current Iw.

[0147] (11th embodiment) The eleventh embodiment is an embodiment that includes a non-isolated gate drive IC. In the following description, components similar to those in the embodiments described above may be omitted from description by using the same reference numerals as appropriate.

[0148] Figure 13 is a circuit diagram showing the semiconductor circuit 1100 of the 11th embodiment. Figure 14 is a circuit diagram showing the semiconductor package 1100a of the 11th embodiment. As shown in Figure 13, the drive circuit 1180 in the semiconductor circuit 1100 includes the semiconductor package 1100a. As shown in Figure 14, the semiconductor package 1100a has two control circuits 1110A and 1110B, similar to the eighth embodiment. The semiconductor package 1100a is a non-isolated gate drive IC. The semiconductor package 1100a is an HVIC (High Voltage IC).

[0149] The control circuit 1110A has a determination unit 1120A. The determination unit 1120A has an output determination unit 30, a fault determination unit 40, and an enable output determination unit 270. The semiconductor package 1100a has two second input terminals 11b and 11m. As shown in Figure 13, the second control signal S2 output from the controller 1190 is input to the second input terminal 11m via the isolator 1183a. The controller 1190 is the same as the controller 290 of the second embodiment, except that it has one CPU 91. The isolator 1183a is a digital isolator that isolates and transmits signals by capacitive coupling. The positive power supply voltage VDD is input to the isolator 1183a via the regulator 89b as the power supply on the side to which the second control signal S2 is input. The regulator 89b steps down the positive power supply voltage VDD. The isolator 1183a receives a positive power supply voltage VCC1 via regulator 89a as the power supply for the side that outputs the second control signal S2. As shown in Figure 14, the second control signal S2 input to the second input terminal 11m is inverted via buffer circuit 28 and NOT circuit 21 to become the second control signal / S2, which is then input to the AND circuit 31 of the output determination unit 30 and the AND circuit 42 of the fault determination unit 40. The second control signal S2 input to the second input terminal 11m is input via buffer circuit 28 to the AND circuit 41 of the fault determination unit 40 and the AND circuit 271 of the enable output determination unit 270.

[0150] The first output voltage V1 output from the AND circuit 31 of the output determination unit 30 is input to the OR circuit 385b of the buffer drive unit 385c from the output terminal 11f, as shown in Figure 13. The buffer drive unit 385c is the same as the buffer drive unit 385 in the third embodiment, except that it does not have a NOT circuit 385a. The enable signal VS2 output from the second output terminal 11p is input to the OR circuit 385b via the isolator 1183b. The isolator 1183b is a digital isolator that isolates and transmits signals by capacitive coupling. The positive power supply voltage VDD is input to the isolator 1183b via the regulator 89b as the power supply on the side to which the enable signal VS2 is input. The positive power supply voltage VCC1 is input to the isolator 1183b via the regulator 89a as the power supply on the side to which the enable signal VS2 is output. The regulator 89a steps down the positive power supply voltage VCC1. The first output voltage V1a, output from the OR circuit 385b, is input to the gate terminal of the switching element 61 via the buffer circuit 86a and the resistor R5a. The buffer circuit 86a is supplied with a positive power supply voltage VCC1 generated by the bootstrap circuit 87. The positive power supply voltage VCC1 is a voltage with a negative power supply voltage VEE1 as its reference potential, which is the same potential as the source terminal of the switching element 61.

[0151] The bootstrap circuit 87 includes a bootstrap diode 87a, a bootstrap capacitor 87b, and a resistor 87c. The anode of the bootstrap diode 87a is connected to the wiring to which the positive power supply voltage VDD is applied. The cathode of the bootstrap diode 87a is connected to one end of the resistor 87c. The other end of the resistor 87c is connected to one electrode of the bootstrap capacitor 87b. The other electrode of the bootstrap capacitor 87b is connected to the wiring connected to the negative power supply terminal 11h. In the bootstrap circuit 87, the bootstrap capacitor 87b is charged by the switching operation of the bridge circuit 60. The charging of the bootstrap capacitor 87b generates the positive power supply voltage VCC1. Since the reference potential of the bootstrap capacitor 87b is the same as the potential of the source terminal of the switching element 61, when the switching element 61 is turned on, i.e., when the switching element 62 is turned off, a positive power supply voltage VCC1 is generated in the bootstrap capacitor 87b as a gate voltage even higher than the source terminal of the switching element 61, where a high potential of several hundred volts is generated, and this positive power supply voltage VCC1 is used as a gate drive power supply to drive the switching element 61.

[0152] The semiconductor package 1100a has two fault output terminals 11c and 11n. Fault output terminal 11n is a terminal that outputs the fault signal FS1. As shown in Figure 14, the fault signal FS1 output from the NOR circuit 43 of the fault determination unit 40 is output from fault output terminal 11n. As shown in Figure 13, the fault signal FS1 output from fault output terminal 11n is inverted by the isolator 1183a to become fault signal / FS1 and is input to the controller 1190.

[0153] As shown in Figure 14, the enable signal VS1 output from the AND circuit 271 of the enable output determination unit 270 is output from the second output terminal 211i. As shown in Figure 13, the enable signal VS1 output from the second output terminal 211i is input to the buffer drive unit 385d via the isolator 1183b. The buffer drive unit 385d has an OR circuit 385e. The OR circuit 385e is input to the enable signal VS1 and the second output voltage V2 output from the output terminal 11k. The OR circuit 385e outputs a second output voltage V2a which is output to the gate terminal of the switching element 62 based on the enable signal VS1 and the second output voltage V2. The OR circuit 385e sets the second output voltage V2a high when at least one of the enable signal VS1 and the second output voltage V2 is high. The OR circuit 385e sets the second output voltage V2a low when both the enable signal VS1 and the second output voltage V2 are low. The second output voltage V2a, output from the OR circuit 385e, is input to the gate terminal of the switching element 62 via the buffer circuit 86b and the resistor R5b. The positive power supply voltage VDD is applied to the buffer circuit 86b. The enable signal VS1 output from the isolator 1183b is inverted by the NOT circuit 88a to become the second fault signal / FS2, which is input to the controller 1190.

[0154] As shown in Figure 14, the control circuit 1110A includes a level shift circuit 72, a pulse generator 73, and a flip-flop 74. The level shift circuit 72 includes two switching elements 72a and 72b and two resistive elements 72c and 72d. The two switching elements 72a and 72b are transistors. More specifically, the two switching elements 72a and 72b are N-channel field-effect transistors. The two switching elements 72a and 72b are MOSFETs. The source terminals of the two switching elements 72a and 72b are connected to ground GND. One end of the resistive element 72c is connected to the drain terminal of the switching element 72a. The other end of the resistive element 72c is connected to the positive power supply terminal 11e. The drain terminal of the switching element 72a is connected to the set terminal of the flip-flop 74 via a NOT gate 75a. The voltage at the drain terminal of switching element 72a is inverted by the NOT gate 75a and input to the flip-flop 74 as a set signal. One end of resistor element 72d is connected to the drain terminal of switching element 72b. The other end of resistor element 72d is connected to the positive power supply terminal 11e. The drain terminal of switching element 72b is connected to the reset terminal of flip-flop 74 via the NOT gate 75b. The voltage at the drain terminal of switching element 72b is inverted by the NOT gate 75b and input to the flip-flop 74 as a reset signal.

[0155] The pulse generator 73 receives the first control signal S1 input to the first input terminal 11a via the Schmitt trigger 76a. The pulse generator 73 outputs a pulse voltage to the gate terminal of the switching element 72a when the input first control signal S1 changes from low to high. The pulse generator 73 also outputs a pulse voltage to the gate terminal of the switching element 72b when the input first control signal S1 changes from high to low.

[0156] When a pulse voltage is input from the pulse generator 73 to the gate terminal of switching element 72a, switching element 72a turns ON, and the voltage at the drain terminal of switching element 72a goes low. Therefore, the set signal input to flip-flop 74 becomes high. When a pulse voltage is input from the pulse generator 73 to the gate terminal of switching element 72b, switching element 72b turns ON, and the voltage at the drain terminal of switching element 72b goes low. Therefore, the reset signal input to flip-flop 74 becomes high.

[0157] When switching element 72a is in the ON state, the voltage at the drain terminal of switching element 72a is determined according to the magnitude of the resistance value of resistor element 72c and the magnitude of the on-resistance of switching element 72a. When switching element 72b is in the ON state, the voltage at the drain terminal of switching element 72b is determined according to the magnitude of the resistance value of resistor element 72d and the magnitude of the on-resistance of switching element 72b. Therefore, the voltages of the set signal and reset signal output from the level shift circuit 72 can be made to be based on the magnitudes of the resistance values ​​of resistor elements 72c and 72d and the magnitudes of the on-resistances of switching elements 72a and 72b. As a result, the level shift circuit 72 can convert the voltage level of the first control signal S1 input to the first input terminal 11a. In the eleventh embodiment, the level shift circuit 72 levels up (shifts up), i.e., boosts, the voltage level of the first control signal S1.

[0158] The flip-flop 74 sets the output signal high when the set signal is high and the reset signal is low. The flip-flop 74 sets the output signal low when the set signal is low and the reset signal is high. The flip-flop 74 maintains the state of the output signal in the state it was in before when both the set signal and the reset signal are low. The signal output from the flip-flop 74 is the first control signal S1, whose voltage level has been converted in the level shift circuit 72. The first control signal S1 output from the flip-flop 74 is input to the AND circuit 31 of the output determination unit 30. The first control signal S1 output from the flip-flop 74 is inverted by the NOT circuit 27 to become the first control signal / S1, which is input to the AND circuits 41 and 42 of the fault determination unit 40 and the AND circuit 271 of the enable output determination unit 270.

[0159] In the semiconductor package 1100a of the 11th embodiment, the region including the determination unit 1120A, the flip-flop 74, the NOT circuits 75a, 75b, and the resistors 72c, 72d is the high-voltage well 1100b.

[0160] The control circuit 1110B includes a determination unit 1120B and a delay circuit 77. The determination unit 1120B includes an output determination unit 30b, a fault determination unit 40b, and an enable output determination unit 270b. The output determination unit 30b includes an AND circuit 31b. Three signals are input to the AND circuit 31b: a second control signal S2, a first control signal S1, and a first output voltage V1. In the control circuit 1110B, the output determination unit 30b functions similarly to the output determination unit 30 in the control circuit 1110A. The AND circuit 31b of the output determination unit 30b outputs a second output voltage V2. The second output voltage V2 output from the AND circuit 31b is delayed by the delay circuit 77 and output from the output terminal 11k. As shown in Figure 13, the second output voltage V2 output from the output terminal 11k is input to the OR circuit 385e of the buffer drive unit 385d. The second output voltage V2 output from output terminal 11k is inverted by isolator 1183b to become the second output voltage / V2, which is then input to the third input terminal 11g.

[0161] In the control circuit 1110B, the fault detection unit 40b functions similarly to the fault detection unit 40 in the control circuit 1110A. As shown in Figure 14, the fault detection unit 40b includes an AND circuit 41b, an AND circuit 42b, and an OR circuit 43b. Three signals are input to the AND circuit 41b: a first control signal S1, a second control signal S2, and a first output voltage V1. The first control signal S1, input to the first input terminal 11a, is input to the AND circuit 41b via a Schmitt trigger 76a. The second control signal S2, which is inverted by being input to the NOT circuit 29b via the Schmitt trigger 76b from the second input terminal 11b, is input to the AND circuit 41b. The first output voltage V1, input to the third input terminal 11q, is inverted by the NOT circuit 29c to become the first output voltage V1 and is input to the AND circuit 41b. The third input terminal 11q receives the first output voltage / V1, which is obtained by inverting the first output voltage V1 output from the output terminal 11f by the isolator 1183b. The AND gate 41b sets its output value high when all three input signals are high. The AND gate 41b sets its output value low when at least one of the three input signals is low.

[0162] The AND gate 42b receives three signals: a first control signal / S1, a second control signal / S2, and a first output voltage / V1. The first control signal / S1, which is inverted after being input to the NOT gate 29a via a Schmitt trigger 76a from the first input terminal 11a, is input to the AND gate 42b. The second control signal / S2, which is inverted after being input to the NOT gate 29b via a Schmitt trigger 76b from the second input terminal 11b, is input to the AND gate 42b. The first output voltage / V1, which is input to the third input terminal 11q, is input to the AND gate 42b. The AND gate 42b outputs high when all three input signals are high. The AND gate 42b outputs low when at least one of the three input signals is low.

[0163] The OR circuit 43b receives three signals: the signal output from AND circuit 41b, the signal output from AND circuit 42b, and the signal output from AND circuit 31b. The OR circuit 43b outputs a fault signal / FS1. The OR circuit 43b sets the fault signal / FS1 high if at least one of the three input signals is high. The OR circuit 43b sets the fault signal / FS1 low if all three input signals are low. The fault signal / FS1 output from the OR circuit 43b is input to the controller 1190 via the fault output terminal 11c.

[0164] In control circuit 1110B, the enable output determination unit 270b functions similarly to the enable output determination unit 270 in control circuit 1110A. The enable output determination unit 270b has an AND circuit 271b. Three signals are input to the AND circuit 271b: a first control signal S1, a second control signal S2, and a first output voltage V1. The first control signal S1 is input to the AND circuit 271b from the first input terminal 11a via a Schmitt trigger 76a. The second control signal S2, which has been input to the NOT circuit 29b and inverted, is input to the AND circuit 271b from the second input terminal 11b via a Schmitt trigger 76b. The first output voltage V1, which is input to the third input terminal 11q, is input to the AND circuit 271b. The AND circuit 271b outputs an enable signal VS2 to the second output terminal 11p. The AND circuit 271b sets the enable signal VS2 high when all three input signals are high. The AND gate 271b sets the enable signal VS2 low if at least one of the three input signals is low.

[0165] One end of resistor Raa is connected to the wiring connecting the first input terminal 11a and the Schmitt trigger 76a. The other end of resistor Raa is connected to ground (GND). One end of resistor Rab is connected to the wiring connecting the second input terminal 11b and the Schmitt trigger 76b. The other end of resistor Rab is connected to ground (GND). A positive power supply voltage VDD is input to the semiconductor package 1100a from the power supply terminal 11r. The positive power supply voltage VDD input to the power supply terminal 11r is used within the semiconductor package 1100a via an internal voltage regulator 78. The internal voltage regulator 78 steps down the positive power supply voltage VDD. As shown in Figure 13, a capacitor C4 is placed between the wiring connected to the power supply terminal 11r from outside the semiconductor package 1100a and the wiring connected to the ground terminal 11d from outside the semiconductor package 1100a.

[0166] In the eleventh embodiment, the isolators 1183a and 1183b are not particularly limited as long as they can transmit signals in isolation, and may be isolators other than digital isolators, such as photocouplers. Furthermore, the isolators 1183a and 1183b may be digital isolators that transmit signals in isolation by magnetic coupling. Also, the isolators 1183a and 1183b may not be provided at all. In this case, the voltage level may be adjusted by providing a level shift circuit inside the semiconductor package 1100a, for example, in addition to the level shift circuit 72.

[0167] (12th embodiment) The twelfth embodiment is an embodiment in which the bridge circuit 1260 is a multilevel inverter circuit. In the following description, components similar to those in the embodiments described above may be omitted from description by using the same reference numerals as appropriate.

[0168] Figure 15 is a circuit diagram showing a semiconductor circuit 1200 of the twelfth embodiment. As shown in Figure 15, the semiconductor circuit 1200 comprises a controller 1290, drive circuits 1280U, 1280V, 1280W, and a bridge circuit 1260. The controller 1290 has control ICs 1291U, 1291V, 1291W, 1292U, 1292V, and 1292W. Control ICs 1291U and 1292U control the drive circuit 1280U. Control ICs 1291V and 1292V control the drive circuit 1280V. Control ICs 1291W and 1292W control the drive circuit 1280W.

[0169] Note that drive circuits 1280U, 1280V, and 1280W have similar configurations, except that the phase of the legs of the bridge circuit 1260 is different. Therefore, Figure 15 omits the diagrams showing the connections between control circuits 1211V to 1214V within drive circuit 1280V, the connections between control circuits 1211W to 1214W within drive circuit 1280W, the connections between drive circuit 1280V and control ICs 1291V and 1292V, and the connections between drive circuit 1280W and control ICs 1291W and 1292W.

[0170] The bridge circuit 1260 is a three-phase multilevel inverter circuit. The bridge circuit 1260 has three legs 1260U, 1260V, and 1260W connected in parallel with each other. Leg 1260U has four switching elements 1261U, 1262U, 1263U, and 1264U connected in series. Leg 1260V has four switching elements 1261V, 1262V, 1263V, and 1264V connected in series. Leg 1260W has four switching elements 1261W, 1262W, 1263W, and 1264W connected in series. Each switching element in the bridge circuit 1260 is a transistor. More specifically, each switching element in the bridge circuit 1260 is an N-channel field-effect transistor. Each switching element in the bridge circuit 1260 is a MOSFET.

[0171] The drain terminal of switching element 1261U is connected to the positive terminal of power supply E3. The source terminal of switching element 1261U is connected to the drain terminal of switching element 1262U. The source terminal of switching element 1262U is connected to the drain terminal of switching element 1263U. The source terminal of switching element 1263U is connected to the drain terminal of switching element 1264U. The source terminal of switching element 1264U is connected to the negative terminal of power supply E3. A U-phase current Iu is output from the wiring connecting switching element 1262U and switching element 1263U.

[0172] Switching elements 1261V to 1264V are connected in the same way as switching elements 1261U to 1264U. The V-phase current Iv is output from the wiring connecting switching element 1262V and switching element 1263V. Switching elements 1261W to 1264W are connected in the same way as switching elements 1261U to 1264U. The W-phase current Iw is output from the wiring connecting switching element 1262W and switching element 1263W.

[0173] The bridge circuit 1260 has two capacitors C5 and C6 connected in series. One electrode of capacitor C5 is connected to the positive terminal of power supply E3. The other electrode of capacitor C5 is connected to one electrode of capacitor C6. The other electrode of capacitor C6 is connected to the negative terminal of power supply E3.

[0174] The bridge circuit 1260 has clamp diodes 1278U, 1278V, 1278W, 1279U, 1279V, and 1279W. The anode of clamp diode 1278U is connected to the neutral point O between capacitors C5 and C6. The cathode of clamp diode 1278U is connected to the wiring connecting switching elements 1261U and 1262U. The anode of clamp diode 1279U is connected to the wiring connecting switching elements 1263U and 1264U. The cathode of clamp diode 1279U is connected to the neutral point O between capacitors C5 and C6.

[0175] The anode of clamp diode 1278V is connected to the neutral point O between capacitors C5 and C6. The cathode of clamp diode 1278V is connected to the wiring connecting switching elements 1261V and 1262V. The anode of clamp diode 1279V is connected to the wiring connecting switching elements 1263V and 1264V. The cathode of clamp diode 1279V is connected to the neutral point O between capacitors C5 and C6.

[0176] The anode of clamp diode 1278W is connected to the neutral point O between capacitors C5 and C6. The cathode of clamp diode 1278W is connected to the wiring connecting switching elements 1261W and 1262W. The anode of clamp diode 1279W is connected to the wiring connecting switching elements 1263W and 1264W. The cathode of clamp diode 1279W is connected to the neutral point O between capacitors C5 and C6.

[0177] The drive circuit 1280U includes control circuits 1211U, 1212U, 1213U, and 1214U. Each of the control circuits 1211U to 1214U is an integrated circuit having the same configuration as the control circuit 10 in the first embodiment. Control circuit 1211U is a control circuit that controls the switching element 1261U. Control circuit 1212U is a control circuit that controls the switching element 1262U. Control circuit 1213U is a control circuit that controls the switching element 1263U. Control circuit 1214U is a control circuit that controls the switching element 1264U.

[0178] In the twelfth embodiment, switching elements 1261U and 1263U are alternately switched to the ON state. Switching elements 1262U and 1264U are alternately switched to the ON state. In the bridge circuit 1260, which is a multilevel inverter circuit, the switching operation of the leg 1260U is a switching operation in which the state is sequentially switched between a first state, a second state and a third state. The first state is when switching elements 1261U and 1262U are ON, and switching elements 1263U and 1264U are OFF. The second state is when switching elements 1262U and 1263U are ON, and switching elements 1261U and 1264U are OFF. The third state is when switching elements 1263U and 1264U are ON, and switching elements 1261U and 1262U are OFF. Each control circuit 1211U to 1214U controls each switching element 1261U to 1264U based on a command from the controller 1290 so that the state of leg 1260U is sequentially switched between the first state, the second state, and the third state. The switching operation of leg 1260V and leg 1260W are the same as the switching operation of leg 1260U, except that the timing is different.

[0179] The control circuit 1211U receives control signals from the controller IC 1291U of the controller 1290 for controlling the switching element 1261U and for controlling the switching element 1263U. The output voltage output from the control circuit 1213U to the gate terminal of the switching element 1263U is input to the control circuit 1211U in an inverted state via the isolator 83c. The isolator 83c is, for example, an optical coupler having a light-emitting diode and a phototransistor. The isolator 83c can have any configuration as long as it can isolate and transmit signals. In the control circuit 1211U, the switching element 1261U is the "first switching element" controlled by the control circuit 1211U itself, and the switching element 1263U is the "second switching element" controlled by another control circuit 1213U.

[0180] The control circuit 1213U receives control signals from the controller IC 1291U of the controller 1290 for controlling the switching element 1263U and for controlling the switching element 1261U. The output voltage output from the control circuit 1211U to the gate terminal of the switching element 1261U is input to the control circuit 1213U in an inverted state via the isolator 83d. The isolator 83d is, for example, an optical coupler having a light-emitting diode and a phototransistor. The isolator 83d can have any configuration as long as it can transmit signals in isolation. In the control circuit 1213U, the switching element 1263U is the "first switching element" controlled by the control circuit 1213U itself, and the switching element 1261U is the "second switching element" controlled by another control circuit 1211U.

[0181] Control circuits 1211U and 1213U monitor each other's control signals and output voltages, similar to how control circuits 10A and 10B in the first embodiment monitor each other's control signals and output voltages. The operation of control circuit 1211U is the same as the operation of control circuit 10A in the first embodiment. The operation of control circuit 1213U is the same as the operation of control circuit 10B in the first embodiment.

[0182] The control circuit 1212U receives control signals from the controller IC 1290's control IC 1292U for controlling the switching element 1262U and control signals for controlling the switching element 1264U. The output voltage output from the control circuit 1214U to the gate terminal of the switching element 1264U is input to the control circuit 1212U in an inverted state via the isolator 83e. The isolator 83e is, for example, an optical coupler having a light-emitting diode and a phototransistor. The isolator 83e can have any configuration as long as it can isolate and transmit signals. In the control circuit 1212U, the switching element 1262U is the "first switching element" controlled by the control circuit 1212U itself, and the switching element 1264U is the "second switching element" controlled by another control circuit 1214U.

[0183] The control circuit 1214U receives control signals from the controller IC 1292U of the controller 1290 for controlling the switching element 1264U and for controlling the switching element 1262U. The output voltage output from the control circuit 1212U to the gate terminal of the switching element 1262U is input to the control circuit 1214U in an inverted state via the isolator 83f. The isolator 83f is, for example, an optical coupler having a light-emitting diode and a phototransistor. The isolator 83f can have any configuration as long as it can isolate and transmit signals. In the control circuit 1214U, the switching element 1264U is the "first switching element" controlled by the control circuit 1214U itself, and the switching element 1262U is the "second switching element" controlled by another control circuit 1212U.

[0184] Control circuits 1212U and 1214U monitor each other's control signals and output voltages, similar to how control circuits 10A and 10B in the first embodiment monitor each other's control signals and output voltages. The operation of control circuit 1212U is the same as the operation of control circuit 10A in the first embodiment. The operation of control circuit 1214U is the same as the operation of control circuit 10B in the first embodiment.

[0185] The drive circuit 1280V has control circuits 1211V, 1212V, 1213V, and 1214V. Each of the control circuits 1211V to 1214V is an integrated circuit having the same configuration as control circuit 10 in the first embodiment. Control circuit 1211V is a control circuit that controls switching element 1261V. Control circuit 1212V is a control circuit that controls switching element 1262V. Control circuit 1213V is a control circuit that controls switching element 1263V. Control circuit 1214V is a control circuit that controls switching element 1264V. The drive circuit 1280V operates similarly to the drive circuit 1280U, except that it drives the V-phase leg 1260V. Control circuits 1211V and 1213V monitor each other's control signals and output voltages, similar to how control circuits 10A and 10B in the first embodiment monitor each other's control signals and output voltages. Control circuits 1212V and 1214V monitor each other's control signals and output voltages, similar to how control circuits 10A and 10B in the first embodiment monitor each other's control signals and output voltages.

[0186] The drive circuit 1280W includes control circuits 1211W, 1212W, 1213W, and 1214W. Each of the control circuits 1211W to 1214W is an integrated circuit having the same configuration as the control circuit 10 in the first embodiment. Control circuit 1211W is a control circuit that controls the switching element 1261W. Control circuit 1212W is a control circuit that controls the switching element 1262W. Control circuit 1213W is a control circuit that controls the switching element 1263W. Control circuit 1214W is a control circuit that controls the switching element 1264W. The drive circuit 1280W operates similarly to the drive circuit 1280U, except that it drives the W-phase leg 1260W. Control circuits 1211W and 1213W monitor each other's control signals and output voltages, similar to how control circuits 10A and 10B in the first embodiment monitor each other's control signals and output voltages. Control circuits 1212W and 1214W monitor each other's control signals and output voltages, similar to how control circuits 10A and 10B in the first embodiment monitor each other's control signals and output voltages.

[0187] According to at least one embodiment described above, the control circuit is provided in a drive circuit that drives a bridge circuit having a plurality of switching elements by controlling each of the plurality of switching elements with a plurality of control circuits. The control circuit receives a first control signal for controlling a first switching element that it controls among the plurality of switching elements, and a second control signal for controlling a second switching element that is controlled by the other control circuits among the plurality of switching elements. As a result, the control circuit can compare the first control signal for controlling the first switching element that it controls with the second control signal for controlling the second switching element that the other control circuits control, and can determine whether or not there is an abnormality in the control signals. Therefore, it is possible to suppress short circuits between the plurality of switching elements and to suppress the flow of overcurrent in the bridge circuit. As a result, it is possible to suppress damage to the switching elements.

[0188] The control circuit of the embodiment may have any configuration and may operate in any way, as long as it receives a first control signal for controlling a first switching element controlled by the control circuit itself, and a second control signal for controlling a second switching element controlled by another control circuit. The number of switching elements included in the bridge circuit is not particularly limited, as long as there are two or more. If the bridge circuit has three or more switching elements, the control circuit of the embodiment may receive multiple second control signals for controlling multiple second switching elements, each controlled by multiple other control circuits. Furthermore, the second control signals input to the control circuit of the embodiment may be control signals for controlling any of the multiple switching elements included in the bridge circuit other than the switching element controlled by the control circuit itself. For example, if the bridge circuit has U-phase legs, V-phase legs, and W-phase legs, as in the bridge circuit 1060 in the 10th embodiment, the control circuit of the embodiment may receive some or all of the five second control signals for controlling the five switching elements other than the switching element controlled by the control circuit itself. For example, a control circuit that controls a switching element in a leg of one of the U-phase, V-phase, and W-phase may receive a first control signal for controlling the switching element in the leg of the phase it controls, and a second control signal for controlling the switching elements in one or more other legs of the other phases. For example, each control circuit that controls the high-side switching element in a leg of the U-phase and the low-side switching element in a leg of the W-phase may receive a first control signal for controlling one of the high-side switching elements in the U-phase and the low-side switching element in the W-phase that it controls (the first switching element), and a second control signal for controlling the other of the high-side switching element in the U-phase and the low-side switching element in the W-phase (the second switching element).Furthermore, for example, each control circuit that controls the high-side switching element of the U-phase leg, the low-side switching element of the V-phase leg, and the low-side switching element of the W-phase leg may receive a first control signal for controlling the switching element it controls (the first switching element) and two second control signals for controlling two other switching elements (the second switching elements) controlled by the other two control circuits. The number of second control signals input to each control circuit is not particularly limited, as long as there is one or more. The control circuits, drive circuits, and semiconductor circuits of this embodiment may be used for any application.

[0189] Each function in the control circuit of the above-described embodiment, including the abnormality detection operation, may be implemented by any method that enables the implementation of the function. At least a part of each function of the control circuit may be implemented, for example, by a processor such as a CPU executing a program, i.e., software, stored in a memory unit not shown; or by hardware including circuit units such as LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array), and GPU (Graphics Processing Unit); or by the cooperation of software and hardware. The memory unit not shown may be implemented by storage media such as RAM (Random Access Memory), ROM (Read Only Memory), HDD (hard disk drive), and flash memory.

[0190] In the embodiments described above, an isolation transmission unit and an isolator are provided to ensure that signal transmission from the controller to each control circuit, and signal transmission between two control circuits, is performed using isolation transmission. However, the system is not limited to this configuration. Each signal may be transmitted directly without isolation transmission. Furthermore, the isolation transmission methods for signals described in each embodiment may be combined as appropriate in each embodiment, or may be replaced with isolation transmission methods from other embodiments as appropriate.

[0191] The control circuit, drive circuit, and semiconductor circuit of the embodiment include the following appended embodiments. (Note 1) A control circuit provided in a drive circuit that drives a bridge circuit having a plurality of switching elements by controlling each of the plurality of switching elements with a plurality of control circuits, A control circuit that receives a first control signal for controlling a first switching element among the plurality of switching elements that it controls, and a second control signal for controlling a second switching element among the plurality of switching elements that is controlled by the other control circuits. (Note 2) An abnormality determination operation can be performed to determine whether or not an abnormality has occurred in the control state of the first switching element and the control state of the second switching element. The control circuit according to Appendix 1, wherein the abnormality determination operation includes determining whether or not an abnormality has occurred in the control state of the first switching element and the control state of the second switching element based on the first control signal and the second control signal. (Note 3) Element information indicating the state of the second switching element is input, The control circuit described in Appendix 2, wherein the abnormality determination operation includes determining whether or not an abnormality has occurred in the control state of the first switching element and the control state of the second switching element based on the first control signal, the second control signal, and the element information. (Note 4) The control circuit described in Appendix 3 includes the element information, which is based on the drive voltage applied to the second switching element. (Note 5) The abnormality determination operation includes determining whether the state of the second switching element is normal based on the first control signal, the second control signal, and the element information. The control circuit described in Appendix 4, which, when it is determined in the abnormality determination operation that the state of the second switching element is not in a normal state, outputs a signal to bring the state of the second switching element back to a normal state. (Note 6) The control circuit described in Appendix 5 outputs a signal to the control circuit that controls the second switching element, which is used to return the second switching element to a normal state. (Note 7) The abnormality determination operation includes determining whether the first switching element and the second switching element are in a short-circuit state. The control circuit described in any one of the appendices 2 to 6, wherein, in the abnormality detection operation, it is determined that the first switching element and the second switching element are in a short-circuit state, the first switching element is turned OFF. (Note 8) The abnormality determination operation includes determining whether an abnormality has occurred during the dead time when both the first switching element and the second switching element are in the OFF state. A control circuit according to any one of Appendix 2 to 7, which, when it is determined in the abnormality determination operation that an abnormality has occurred in the dead time, generates a predetermined dead time and controls the first switching element based on the generated dead time. (Note 9) The control circuit described in any one of Appendix 2 to Appendix 8, which, when it is determined in the abnormality determination operation that an abnormality has occurred in the control state of the first switching element and the control state of the second switching element, outputs a signal indicating that an abnormality has occurred. (Note 10) A drive circuit for driving a bridge circuit having multiple switching elements, A plurality of control circuits according to any one of claims 1 to 9, The plurality of control circuits are drive circuits that control each of the plurality of switching elements. (Note 11) The drive circuit described in Appendix 10, wherein at least one of the plurality of control circuits controls the switching element that was being controlled by the other control circuit when the other control circuit stops. (Note 12) The drive circuit described in Appendix 10 or Appendix 11, The aforementioned bridge circuit, A semiconductor circuit equipped with the following features.

[0192] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0193] 10, 10A, 10B, 210A, 210B, 410A, 510A, 610A, 710A, 810A, 810B, 910A, 910B, 1110A, 1110B, 1211U, 1212U, 1213U, 1214U, 1211V, 1212V, 1213V, 1214V, 1211W, 1212W, 1213W, 1214W…control circuits, 60, 1060, 1260…bridge circuits, 61, 61U, 61V, 61W, 62, 62U, 62V, 62W, 1261U, 1261V, 1261W, 1262U, 1262V, 1262 W, 1263U, 1263V, 1263W, 1264U, 1264V, 1264W… Switching elements (first switching element, second switching element), 80, 280, 380, 880, 880U, 880V, 880W, 980, 1180, 1280U, 1280V, 1280W… Drive circuits, 100, 200, 300, 800, 900, 1000, 1100, 1200… Semiconductor circuits, S1, / S1… First control signal, S2, / S2… Second control signal, / V1… First output voltage (element information), / V2… Second output voltage (element information)

Claims

1. A control circuit provided in a drive circuit that drives a bridge circuit having a plurality of switching elements by controlling each of the plurality of switching elements with a plurality of control circuits, A control circuit that receives a first control signal for controlling a first switching element among the plurality of switching elements that it controls, and a second control signal for controlling a second switching element among the plurality of switching elements that is controlled by the other control circuits.

2. An abnormality determination operation can be performed to determine whether or not an abnormality has occurred in the control state of the first switching element and the control state of the second switching element. The control circuit according to claim 1, wherein the abnormality determination operation includes determining whether or not an abnormality has occurred in the control state of the first switching element and the control state of the second switching element based on the first control signal and the second control signal.

3. Element information indicating the state of the second switching element is input, The control circuit according to claim 2, wherein the abnormality determination operation includes determining whether or not an abnormality has occurred in the control state of the first switching element and the control state of the second switching element based on the first control signal, the second control signal, and the element information.

4. The control circuit according to claim 3, wherein the element information includes information based on the drive voltage applied to the second switching element.

5. The abnormality determination operation includes determining whether the state of the second switching element is normal based on the first control signal, the second control signal, and the element information. The control circuit according to claim 4, which, when it is determined in the abnormality determination operation that the state of the second switching element is not in a normal state, outputs a signal to bring the state of the second switching element back to a normal state.

6. The control circuit according to claim 5, wherein a signal for restoring the second switching element to a normal state is output to a control circuit that controls the second switching element.

7. The abnormality determination operation includes determining whether the first switching element and the second switching element are in a short-circuit state. The control circuit according to claim 2, wherein if the abnormality determination operation determines that the first switching element and the second switching element are in a short-circuit state, the first switching element is turned OFF.

8. The abnormality determination operation includes determining whether or not an abnormality has occurred during the dead time when both the first switching element and the second switching element are in the OFF state. The control circuit according to claim 2, wherein, in the abnormality determination operation, it is determined that an abnormality has occurred in the dead time, a predetermined dead time is generated, and the first switching element is controlled based on the generated dead time.

9. The control circuit according to claim 2, which, when it is determined in the abnormality determination operation that an abnormality has occurred in the control state of the first switching element and the control state of the second switching element, outputs a signal indicating that an abnormality has occurred.

10. A drive circuit for driving a bridge circuit having multiple switching elements, A plurality of control circuits according to any one of claims 1 to 9 are provided, The plurality of control circuits are drive circuits that control each of the plurality of switching elements.

11. The drive circuit according to claim 10, wherein at least one of the plurality of control circuits controls a switching element that was being controlled by the other control circuit when the other control circuit stops.

12. The drive circuit according to claim 10, The aforementioned bridge circuit, A semiconductor circuit equipped with the following features.

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