Switching power supply

Abstract

The objective is to provide a switching power supply that operates in combination with PFM control and PWM control, and that can reduce the on-loss of the FET in the region where the output voltage is lower in PWM control. [Solution] The problem is solved by a switching power supply device comprising a DC-DC converter equipped with a switching circuit for performing power conversion at input and output, and a pulse signal generation unit that generates pulse signals for driving the switching elements of the switching circuit, wherein the pulse signal generation unit performs PFM control in the high voltage output region and switches between and performs phase shift control and symmetric PWM control in the low voltage output region.

Description

Technical Field

[0001] The present invention relates to a switching power supply device that operates in combination with a plurality of switching methods, more specifically, PFM control and PWM control.

Background Art

[0002] For example, as shown in Patent Document 1, there is known a switching power supply device that operates by combining PFM control and phase shift control in an LLC converter.

Prior Art Documents

Patent Documents

[0003] / / 这里原内容为空行,翻译后也保留空行

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The switching power supply device described in Patent Document 1 reduces the output voltage by executing PFM control on an LLC converter to increase the switching frequency. Here, when the switching frequency is increased and becomes higher than the resonance frequency of the series resonance circuit, due to the frequency characteristics of the LLC circuit, the output voltage can no longer be lowered, and the desired voltage cannot be output. To solve this problem, the switching power supply device described in Patent Document 1 switches the LLC converter from PFM control to phase shift control, or from phase shift control to PFM control, with the point where the switching frequency becomes the resonance frequency as the boundary value, thereby expanding the range of the output gain. Note that the output gain is an index corresponding to the voltage output by the DC-DC converter, and the relationship between the output gain and the output voltage is positively correlated.

[0005] However, when phase shift control is applied to an LLC converter to lower the output voltage, the on-dissipation of the FET increases in the region where the output voltage is lower, and the amount of heat generated by the FET increases. Therefore, in order to prevent the FET from being destroyed due to exceeding its heat resistance, it is necessary to take measures to reduce the loss in the low-voltage output region where the loss is large, but Patent Document 1 does not address this at all. The reason why the on-dissipation of the FET increases in the region where the output voltage is lower will be explained in detail using Figures 1 and 2.

[0006] An LLC converter is a converter that has bridge circuits on the primary and secondary sides of a transformer. Figure 1(a) is an equivalent circuit of an LLC converter, showing only the primary side. Figure 1(b) is a graph showing the frequency-gain characteristics when driving the LLC converter with PFM control, where the horizontal axis is the switching frequency and the vertical axis is the output gain. However, after the switching frequency is increased and the output gain becomes 1, it switches to fixed-frequency phase-shift control. For this reason, the solid line showing the operating region is drawn to slope downwards vertically, while the output gain in the low-voltage output region is drawn as a dashed line to show a gradual decrease. However, in the region where the output voltage is lower in phase-shift control, the on-loss of the FET, specifically the on-loss of FET3, becomes significant. The reason will be explained using Figure 1(a), while also referring to Figure 2, which shows the voltage and current waveforms of each switch of the LLC converter.

[0007] The phase shift control state consists of four periods: period (1) when FET4 and FET2 are ON, period (2) when FET3 and FET2 are ON, period (3) when FET3 and FET1 are ON, and period (4) when FET4 and FET1 are ON. Here, the state of period (1) and period (2) is the issue.

[0008] First, during the period (1) when FET4 and FET2 are ON, the switch that is turned ON in the previous period (4) switches from FET1 to FET2. As shown in the waveform of FET4Ids in Figure 2, a back electromotive force is generated due to the transformer's leakage inductance, and a current flows in the reverse direction in the latter half of period (1). Moreover, this current is large. Even when transitioning to the period (2) when FET4 is OFF, the situation of reverse current flowing due to parasitic inductance is maintained. In this situation, when FET3 is turned ON, this reverse current and the forward current of FET3 are superimposed, causing a sudden large current to flow between the drain and source of FET3, as shown in the waveform of FET3Ids in Figure 2. In the region where the output gain is close to 1, the loss reduction effect of soft switching works to a certain extent, so the ON loss of FET3 is not so serious. However, as the output gain decreases, the ON loss of FET3 exceeds the loss reduction effect of soft switching. Switching losses in this situation could lead to serious problems such as switch failure or fire.

[0009] The present invention has been made in view of these circumstances, and its objective is to provide a switching power supply that operates in combination with PFM control and PWM control, and that can reduce the on-loss of the FET in the region where the output voltage becomes lower in PWM control. [Means for solving the problem]

[0010] To achieve this objective, the technical means according to the present invention is a switching power supply device having at least the following configuration.

[0011] A switching power supply device comprising a DC-DC converter equipped with a switching circuit for power conversion at input and output, and a pulse signal generation unit for generating pulse signals to drive the switching elements of the switching circuit, wherein the pulse signal generation unit performs PFM control in the high-voltage output region and switches between and performs phase shift control and symmetric PWM control in the low-voltage output region. Here, the "pulse signal generation unit" can be constructed with a digital controller such as a microcontroller. Furthermore, "symmetric PWM control" is conceived in contrast to "phase shift control," and it is not necessary for the phase difference applied to each switch to be exactly 180 degrees. [Effects of the Invention]

[0012] Having these characteristics, according to the present invention, in a switching power supply device that operates in combination with PFM control and PWM control, the on-loss of the FET in the region where the output voltage is lower in PWM control can be reduced. [Brief explanation of the drawing]

[0013] [Figure 1] The following diagrams and graphs illustrate the LLC converter. Figure 1(a) is a circuit diagram of the primary side equivalent circuit of the LLC converter, and Figure 1(b) is a graph showing the frequency-gain characteristics of the LLC converter. [Figure 2] This graph shows the drain-to-source voltage waveform, current waveform, and on-dissipation for FET3 and FET4 in the primary-side equivalent circuit of the LLC converter. [Figure 3] This is a circuit diagram showing the DC-DC converter portion, which is the main part of the switching power supply device according to an embodiment of the present invention. [Figure 4] This figure shows the drive waveform of a switching power supply device according to an embodiment of the present invention. [Figure 5]Figure 5(a) shows the waveform in phase shift control mode, and Figure 5(b) shows the waveform in symmetric PWM control mode. [Figure 6] This waveform diagram shows the output voltage and output current of a switching power supply, including the switching timing from symmetric PWM control to phase shift control. [Modes for carrying out the invention]

[0014] The following describes an example of an embodiment of the switching power supply device according to the present invention, based on the drawings. The following drawings are created for illustrative purposes, and in order to make them easier to understand, some components that are not necessary for the explanation may be intentionally omitted. In the following explanation, the same reference numerals in different figures indicate parts with the same function, and redundant explanations in each figure will be omitted as appropriate.

[0015] (Configuration of a switching power supply) Figure 3 is a circuit diagram showing the DC-DC converter portion, which is the main part of a switching power supply device according to an embodiment of the present invention. The DC-DC converter is generally a full-bridge LLC converter composed of a power switch, a resonant circuit, a transformer, and a rectifier / smoothing circuit. The switch circuit consists of a left leg in which MOSFETs FET1 and FET2 are connected in series, and a right leg in which MOSFETs FET3 and FET4 are connected in series. By inputting control signals generated by a digital controller (not shown) to the gates of the MOSFETs in the switch circuit, the switching power supply device performs switching control using either a PFM control method or a PWM control method. More specifically, the PFM control method is used in the high-voltage output region, and the PWM control method is used in the low-voltage output region. Furthermore, in the low-voltage output region, two methods, a phase-shift control method and a symmetrical PWM control method, are switched and used.

[0016] The digital controller not shown monitors the output gain given by the connected load fluctuations and functions as a pulse signal generation unit that generates a control signal for the switching power supply device. Specifically, when the output gain is 1 or more, it generates a switching pulse for the PFM control method, and is programmed to generate a switching pulse for the PWM control method when the output gain is less than 1. The digital controller can employ appropriate means such as a microcomputer, FPGA, ASIC, etc.

[0017] Also, when the digital controller as the pulse signal generation unit is in the low voltage output region, if the on-loss of the switching element exceeds the loss reduction effect by soft switching, it outputs a drive pulse for executing symmetric PWM control on the switching power supply device, and if the loss reduction effect by soft switching exceeds the on-loss of the switching element, it outputs a drive pulse for executing phase shift control on the switching power supply device.

[0018] Specifically, the digital controller as the pulse signal generation unit is programmed to output a drive pulse for switching to phase shift control when the output gain exceeds a first threshold during the execution of symmetric PWM control, and to output a drive pulse for switching to symmetric PWM control when the output gain falls below a second threshold smaller than the first threshold during the execution of phase shift control. Here, the first threshold and the second threshold are output gains smaller than 1, and their values are made different to provide hysteresis so that hunting does not occur.

[0019] Also, as a modification of the switching control, instead of monitoring the output gain, the heat generation amount of the FET may be monitored by a temperature sensor. That is, the digital controller as the pulse signal generation unit may be configured to output a drive pulse for switching to phase shift control when the monitored temperature exceeds a first threshold during the execution of symmetric PWM control, and to output a drive pulse for switching to symmetric PWM control when the monitored temperature falls below a second threshold smaller than the first threshold during the execution of phase shift control.

[0020] Figure 4 is a diagram showing the drive waveforms of the switching power supply device according to an embodiment of the present invention, that is, a drive pulse waveform diagram showing how the drive pulses generated and output by a digital controller as a pulse signal generation unit are applied to FET1 to FET4. Figure 4(a) shows the drive pulse waveform during PFM control, Figure 4(b) shows the drive pulse waveform during phase shift control, and Figure 4(c) shows the drive pulse waveform during symmetric PWM control.

[0021] During PFM control, the switching frequency of the drive pulse changes from a low frequency region to a high frequency region. Also, the phase difference between the set of FET3 and FET4 with respect to the set of FET1 and FET2 is fixed at 180 degrees as shown in Figure 4(a). Furthermore, the duty ratio, which is the pulse width per cycle, is also fixed at 50% as shown in Figure 4(a).

[0022] During phase shift control, the switching frequency of the drive pulse is fixed at the resonance frequency. On the other hand, the phase difference between the set of FET3 and FET4 with respect to the set of FET1 and FET2 gradually shifts from 180 degrees to X degrees as shown in Figure 4(b). The duty ratio, which is the pulse width per cycle, is fixed at 50%.

[0023] During symmetric PWM control, the switching frequency of the drive pulse is fixed at the resonance frequency. Also, the phase difference between the set of FET3 and FET4 with respect to the set of FET1 and FET2 is fixed at 180 degrees as shown in Figure 4(c). On the other hand, the duty ratio, which is the pulse width per cycle, is set to Y%.

[0024] (Regarding the switching loss of the switching power supply device) Figure 5 is a graph showing the voltage waveform, current waveform, and on-loss between the drain and source of FET3 and FET4 of the switching power supply device according to an embodiment of the present invention. Figure 5(a) shows the waveform in the phase shift control mode, and Figure 5(b) shows the waveform in the symmetric PWM control mode.

[0025] As shown in Figure 5(a), when the switching power supply is in phase-shift control mode, the effect of the transformer leakage inductance shown in the circuit diagram of Figure 3 is negligible at the timing of switching from the ON state of FET2 to the ON state of FET1. Since the reverse current observed as FET2Ids, which is the current of FET2, is steep, no large on-loss occurs in FET1. However, at the timing of switching from the ON state of FET4 to the ON state of FET3, the effect of the parasitic inductance of the pattern wiring becomes significant, and a large reverse current is superimposed with the forward current of FET3, causing a sudden large current to flow between the drain and source of FET3. Thus, in the circuit shown in Figure 3, the burden is concentrated on FET3, which constitutes the right leg. However, in the region where the output gain is close to 1, the loss reduction effect of soft switching works to a certain extent, so the on-loss of FET3 is not so serious. However, as the output gain decreases, the on-loss of FET3 exceeds the loss reduction effect of soft switching and becomes negligible.

[0026] Therefore, in the switching power supply device according to the embodiment of the present invention, if the on-loss of the switching element exceeds the loss reduction effect due to soft switching, the drive pulse is configured to switch from phase shift control mode to symmetric PWM control mode. As shown in Figure 5(b), when the switching power supply device is in symmetric PWM control mode, there is a period when all FETs are off, so the influence of the leakage inductance of the transformer shown in the circuit diagram of Figure 3 is limited, and the on-loss of FET1 and the on-loss of FET3 are equalized. As a result of verification, the on-loss of FET3 and FET4 were reduced by 25% each, and the thermal establishment conditions were sufficiently relaxed.

[0027] (Regarding the output waveform of a switching power supply) As described above, the switching power supply according to the embodiment of the present invention can reduce the on-loss of the FET in the low-voltage output region by switching the drive pulse from a phase-shift control mode to a symmetric PWM control mode. Furthermore, it has been confirmed that the output of the switching power supply remains very stable even at the switching timing between the two modes. This will be explained with reference to Figure 6.

[0028] Figure 6 is a waveform diagram showing the output voltage and output current of a switching power supply, including the switching timing from symmetric PWM control to phase shift control. In the graph shown above, the output voltage waveform, output current waveform, and mode transition of the switching power supply are shown from top to bottom. Mode "0" indicates symmetric PWM control, and mode "1" indicates shift control. The graph shown below shows the switching waveforms of FET1 to FET4, but only the period of slightly more than one cycle before and after the mode switch is shown in an enlarged view.

[0029] As mentioned earlier, the digital controller, acting as a pulse signal generator, outputs a drive pulse to switch to phase shift control when the output gain exceeds a first threshold during symmetric PWM control. As can be seen from Figure 6, even when the mode is switched, the output voltage waveform of the switching power supply increases smoothly and gradually. Furthermore, no significant disturbances are observed in the output current waveform of the switching power supply. Thus, according to the embodiment of the present invention, it is possible to smoothly switch the output voltage and output current of the switching power supply without large fluctuations occurring when the control mode of the switching power supply is switched. In addition, the control mode switching is performed with hysteresis by setting two thresholds as the output voltage threshold: a first threshold and a second threshold that is smaller than the first threshold. This further suppresses disturbances in the output voltage and output current of the switching power supply.

[0030] Although the switching power supply devices according to embodiments of the present invention have been described in detail above, the specific configuration is not limited to these embodiments, and any design changes, etc., that do not depart from the gist of the present invention are also included. For example, the topology of the embodiments was such that a MOSFET switch was arranged only on the primary side, but a dual active bridge (DAB) converter in which MOSFET switches are arranged on both the primary and secondary sides is also acceptable. It should be correctly recognized that the present invention is based on the technical idea of ​​realizing a safe switching power supply device while expanding the output gain by assuming that there is a first switching mode and a second switching mode, eliminating the concentration of load in the low output region in the second switching mode and equalizing the on-loss between the left and right legs.

Claims

1. A switching power supply device comprising a DC-DC converter equipped with a switching circuit for performing power conversion at input and output, and a pulse signal generation unit for generating pulse signals to drive the switching elements of the switching circuit, The pulse signal generation unit performs PFM control in the high-voltage output region, and switches between phase shift control and symmetric PWM control in the low-voltage output region. A switching power supply device characterized by the following features.

2. The pulse signal generation unit performs symmetric PWM control in the low-voltage output region if the on-loss of the switch element exceeds the loss reduction effect of soft switching, and performs phase shift control if the loss reduction effect of soft switching exceeds the on-loss of the switch element. The switching power supply device according to feature 1.

3. The pulse signal generation unit switches to phase shift control and executes control when the output gain exceeds a first threshold during symmetric PWM control, and switches to symmetric PWM control and executes control when the output gain falls below a second threshold which is smaller than the first threshold during phase shift control. The switching power supply device according to feature 1.

4. The pulse signal generation unit switches to PFM control and executes the control when the output gain exceeds a third threshold, which is greater than the first threshold, during the execution of phase shift control. The switching power supply device according to feature 3.

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