Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can improve yield. [Solution] The semiconductor device comprises a substrate having a first surface and a second surface opposite to the first surface, a first nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface, with a recess formed on the fourth surface, a second nitride semiconductor layer provided in the recess, and a first metal layer provided on the second nitride semiconductor layer, wherein through holes are formed in the substrate, the first nitride semiconductor layer and the second nitride semiconductor layer, penetrating the substrate, the first nitride semiconductor layer and the second nitride semiconductor layer and reaching the first metal layer, and the second metal layer is in contact with the first metal layer and covers the first surface and the inner wall surface of the through holes, the first metal layer contains cobalt, and the second nitride semiconductor layer contains 1.0 × 10 18 cm -3 It contains impurity atoms at the above concentrations.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] A semiconductor device is known in which a metal layer is formed as an etching stopper on a semiconductor layer containing a high concentration of carriers, the metal layer making ohmic contact with the semiconductor layer, through holes are formed in the semiconductor layer that reach the etching stopper, and electrodes that contact the etching stopper are formed within the through holes. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2024-092747 [Overview of the project] [Problems that the invention aims to solve]

[0004] In conventional semiconductor devices, the contact resistance between the metal layer and the semiconductor layer can increase, leading to a decrease in yield.

[0005] This disclosure aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can improve yield. [Means for solving the problem]

[0006] The semiconductor device of this disclosure comprises a substrate having a first surface and a second surface opposite to the first surface; a first nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface, with a recess formed on the fourth surface; a second nitride semiconductor layer provided in the recess; and a first metal layer provided on the second nitride semiconductor layer. Through holes are formed in the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer, penetrating the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer and reaching the first metal layer. The second metal layer is in contact with the first metal layer and covers the first surface and the inner wall surface of the through holes. The first metal layer contains cobalt, and the second nitride semiconductor layer contains 1.0 × 10¹⁶ 18 cm -3 It contains impurity atoms at the above concentrations. [Effects of the Invention]

[0007] According to this disclosure, yield can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows the layout of the gate electrode, source wiring, and drain wiring in a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 3] Figure 3 shows the band structure of the semiconductor layer (regrowth layer). [Figure 4] Figure 4 is a cross-sectional view (part 1) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a cross-sectional view (part 2) showing a first example of a semiconductor device manufacturing method according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 3) showing a first example of a semiconductor device manufacturing method according to the first embodiment. [Figure 7] Figure 7 is a cross-sectional view (part 4) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 5) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 6) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 7) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. <0​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​Figure 23 is a cross-sectional view (part 3) showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 24] Figure 24 is a cross-sectional view (part 4) showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 25] Figure 25 is a cross-sectional view (part 5) showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 26] Figure 26 is a cross-sectional view (part 6) showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 27] Figure 27 is a cross-sectional view (part 7) showing a method for manufacturing a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0009] [Description of Embodiments in this Disclosure] First, the embodiments of this disclosure will be listed and described.

[0010] [1] A semiconductor device according to one aspect of the present disclosure comprises a substrate having a first surface and a second surface opposite to the first surface, a first nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface, with a recess formed on the fourth surface, a second nitride semiconductor layer provided in the recess, and a first metal layer provided on the second nitride semiconductor layer, wherein through holes are formed in the substrate, the first nitride semiconductor layer and the second nitride semiconductor layer, penetrating the substrate, the first nitride semiconductor layer and the second nitride semiconductor layer and reaching the first metal layer, and the second metal layer is in contact with the first metal layer and covers the first surface and the inner wall surface of the through holes, the first metal layer contains cobalt, and the second nitride semiconductor layer contains 1.0 × 10 18 cm -3 It contains impurity atoms at the above concentrations.

[0011] A second nitride semiconductor layer is formed in a recess formed on the fourth surface of the first nitride semiconductor layer, and the second nitride semiconductor layer is 1.0 × 10 18 cm -3The material contains impurity atoms at the above concentrations. As a result, ohmic contact is achieved between the second nitride semiconductor layer and the first metal layer. Furthermore, the first metal layer containing cobalt has high resistance to materials that may come into contact with the first metal layer between the formation of through holes and the formation of the second metal layer. Consequently, the electrical resistance between the second metal layer and the first nitride semiconductor layer is stable, and the yield can be improved.

[0012] [2] In [1], a third metal layer is provided covering the first metal layer, and the electrical resistance of the third metal layer may be lower than that of the first metal layer. In this case, the electrical resistance of the source electrode including the first metal layer and the third metal layer can be kept low.

[0013] [3] In [2], the third metal layer may include at least one selected from the group consisting of gold, copper, and aluminum. In this case, the electrical resistance of the third metal layer is easily lowered.

[0014] [4] In any of [1] to [3], the second nitride semiconductor layer may be a gallium nitride layer. In this case, it is easier to obtain a low electrical resistance in the second nitride semiconductor layer.

[0015] [5] In any of [1] to [4], the Fermi level in the second nitride semiconductor layer may be higher than the energy of the lower end of the conduction band. In this case, ohmic contact is easily obtained between the second nitride semiconductor layer and the first metal layer.

[0016] [6] In any of [1] to [5], the carrier density in the second nitride semiconductor layer may be higher than the carrier density in the first nitride semiconductor layer. In this case, the electrical resistance of the second nitride semiconductor layer is easily reduced.

[0017] 〔7〕In any one of 〔1〕 to 〔6〕, it has a gate electrode that makes a Schottky contact with the first nitride semiconductor layer, the gate electrode has a fourth metal layer that directly contacts the first nitride semiconductor layer, and the fourth metal layer may contain cobalt. In this case, the first metal layer and the fourth metal layer can be formed simultaneously. Also, by the fourth metal layer containing cobalt, it is easy to obtain a high Schottky barrier for the gate electrode.

[0018] 〔8〕In 〔7〕, the fourth metal layer may contain cobalt in an amorphous state. Such a fourth metal layer can make it difficult to generate gate leakage.

[0019] 〔9〕In 〔8〕, the fourth metal layer may contain hydrogen atoms, carbon atoms, nitrogen atoms, and oxygen atoms. In this case, it is easy to make the fourth metal layer amorphous.

[0020] 〔10〕A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes a step of forming a first nitride semiconductor layer having a third surface that contacts the second surface and a fourth surface that is opposite to the third surface on a substrate having a first surface and a second surface opposite to the first surface, a step of forming a recess in the fourth surface, a step of forming a second nitride semiconductor layer in the recess, a step of forming a first metal layer on the second nitride semiconductor layer, a step of forming a through hole that penetrates the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer and reaches the first metal layer in the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer, and a step of forming a second metal layer that contacts the first metal layer and covers the first surface and the inner wall surface of the through hole. The first metal layer contains cobalt, and the second nitride semiconductor layer contains impurity atoms at a concentration of 1.0×10 18 cm -3 or more.

[0021] A recess is formed in the fourth surface of the first nitride semiconductor layer, a second nitride semiconductor layer is formed in the recess, and the second nitride semiconductor layer has a concentration of 1.0×10 18 cm -3The material contains impurity atoms at the above concentrations. Furthermore, the first metal layer containing cobalt has high resistance to substances that may come into contact with it between the formation of through holes and the formation of the second metal layer. Therefore, the electrical resistance between the second metal layer and the first nitride semiconductor layer is stable, and the yield can be improved.

[0022]

[11] In

[10] , the step of forming the first metal layer comprises the steps of forming a fifth metal layer containing amorphous cobalt on the first nitride semiconductor layer and the second nitride semiconductor layer by atomic layer deposition, and patterning the fifth metal layer, wherein a fourth metal layer in direct contact with the first nitride semiconductor layer may be formed in the step of patterning the fifth metal layer. In this case, the first metal layer and the fourth metal layer can be formed simultaneously.

[0023]

[12] In

[11] , the raw material for the fifth metal layer may include bis-diisopropylbutaneamidinate cobalt. In this case, the fifth metal layer is more likely to form in an amorphous state.

[0024]

[13] In the step of forming the fifth metal layer in

[12] , at least one gas selected from the group consisting of hydrogen gas and ammonia gas may be supplied into the furnace along with the raw materials. In this case, it is particularly easy to form the fifth metal layer in an amorphous state.

[0025]

[14] In any of

[11] to

[13] , the process includes a step of performing a reduction treatment at a first temperature at which the native oxide film on the surface of the first nitride semiconductor layer is decomposed, prior to the step of forming the fifth metal layer, and the fifth metal layer may be formed at a second temperature lower than the first temperature. In this case, good Schottky properties are easily obtained between the gate electrode and the first nitride semiconductor layer.

[0026]

[15] In

[14] , the reduction treatment step and the fifth metal layer formation step may be carried out in the same furnace without opening to the atmosphere. In this case, it is easy to obtain particularly excellent cleanliness on the surface of the first nitride semiconductor layer.

[0027]

[16] In

[14] , the reduction treatment step and the fifth metal layer formation step may be carried out in different furnaces without opening to the atmosphere. In this case, the temperature in the furnace where the reduction treatment is performed and the temperature in the furnace where the fifth metal layer is formed can be controlled independently of each other, making it easier to obtain high throughput.

[0028]

[17] In any of

[14] to

[16] , hydrogen gas and ammonia gas may be used in the reduction treatment. In this case, oxygen atoms are removed from the native oxide film by hydrogen gas, and nitrogen vacancies in the first nitride semiconductor layer are compensated for by ammonia gas.

[0029] [Details of the embodiments of this disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited thereto. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant descriptions. In the following description, the XYZ Cartesian coordinate system will be used, but this coordinate system is defined for illustrative purposes only and is not limited to the orientation of the semiconductor device. Also, from any point, the +Z side may be referred to as up, upper, or top, and the -Z side may be referred to as down, lower, or bottom.

[0030] (First Embodiment) A first embodiment will be described. The first embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT).

[0031] [Structure of a semiconductor device] The structure of the semiconductor device according to the first embodiment will now be described. Figure 1 is a diagram showing the layout of the gate electrode, source wiring, and drain wiring in the semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. Figure 2 corresponds to a cross-sectional view along the line II-II in Figure 1.

[0032] As shown in Figures 1 and 2, the semiconductor device 100 according to the embodiment includes a substrate 11, a semiconductor layer 12, a semiconductor layer 21S, a semiconductor layer 21D, a gate electrode 30G, a source electrode 30S, a drain electrode 30D, a source wiring 52S, a drain wiring 52D, and a back electrode 51.

[0033] The substrate 11 is, for example, a silicon carbide (SiC) substrate. The substrate 11 has a first surface 11A and a second surface 11B opposite to the first surface 11A. The second surface 11B is located above (on the +Z side of) the first surface 11A.

[0034] The semiconductor layer 12 is provided on the substrate 11. The semiconductor layer 12 has a third surface 12C that is in contact with the second surface 11B, and a fourth surface 12D opposite to the third surface 12C. The fourth surface 12D is above (on the +Z side of) the third surface 12C. The semiconductor layer 12 is, for example, a nitride semiconductor layer containing gallium (Ga). The nitride semiconductor layer constitutes part of a high electron mobility transistor, such as an electron transport layer (channel layer) and an electron supply layer (barrier layer), and contains a two-dimensional electron gas (2DEG). The semiconductor layer 12 is an example of a first nitride semiconductor layer.

[0035] Multiple recesses 13S and multiple recesses 13D are formed on the fourth surface 12D. The recesses 13S and 13D extend parallel to the Y-axis and are arranged alternately along the X-axis. For example, the recesses 13S and 13D reach the electron transport layer (channel layer). The bottom surfaces of the recesses 13S and 13D may be in the electron transport layer.

[0036] The semiconductor device 100 has an insulating film 61. The insulating film 61 covers the fourth surface 12D of the semiconductor layer 12. For example, the insulating film 61 is a nitride film such as a silicon nitride (SiN) film. Multiple openings 61S, multiple openings 61D, and multiple openings 61G are formed in the insulating film 61. The openings 61S, 61D, and 61G penetrate the insulating film 61. The openings 61S, 61D, and 61G extend parallel to the Y axis. The opening 61S is connected to the recess 13S, and the opening 61D is connected to the recess 13D. The opening 61G is provided between adjacent openings 61S and 61D along the X axis.

[0037] The semiconductor layer 21S is provided in the recess 13S, and the semiconductor layer 21D is provided in the recess 13D. A portion of the semiconductor layer 21S may be inside the opening 61S, and a portion of the semiconductor layer 21D may be inside the opening 61D. For example, the semiconductor layers 21S and 21D are n-type gallium nitride (GaN) layers. The semiconductor layers 21S and 21D are regrowth layers. The carrier density in the semiconductor layers 21S and 21D is higher than the carrier density in the semiconductor layer 12. The semiconductor layers 21S and 21D have a carrier density of 1.0 × 10⁻⁶ 18 cm -3 The above concentrations contain n-type impurity atoms. Semiconductor layers 21S and 21D are, for example, degenerate semiconductor layers. n-type impurities are, for example, silicon (Si) or germanium (Ge). Semiconductor layer 21S is an example of a second nitride semiconductor layer.

[0038] The gate electrode 30G extends parallel to the Y-axis. The gate electrode 30G is in Schottky contact with the semiconductor layer 12 through an opening 61G. The gate electrode 30G has a metal layer 31G, a metal layer 32G, and a metal layer 33G. The metal layer 31G is in direct contact with the semiconductor layer 12. The metal layer 32G covers the metal layer 31G. The metal layer 33G is between the metal layer 31G and the metal layer 32G. The metal layer 31G is on the semiconductor layer 12 and the insulating film 61, the metal layer 33G is on the metal layer 31G, and the metal layer 32G is on the metal layer 33G. The metal layer 31G contains cobalt (Co). The metal layer 31G is, for example, an amorphous cobalt (Co) layer. The thickness of the metal layer 31G is, for example, between 3 nm and 50 nm. The electrical resistance of the metal layer 32G is lower than the electrical resistance of the metal layer 31G. The metal layer 32G is, for example, a gold (Au) layer. The thickness of the metal layer 32G is, for example, between 300 nm and 1000 nm. The metal layer 33G enhances the adhesion between the metal layer 31G and the metal layer 32G. The metal layer 33G is, for example, a titanium (Ti) layer. The thickness of the metal layer 33G is, for example, between 2 nm and 20 nm. The metal layer 31G is an example of a fourth metal layer. As shown in Figure 1, multiple gate electrodes 30G are connected to the gate common connection part 15.

[0039] The source electrode 30S extends parallel to the Y-axis. The source electrode 30S has a metal layer 31S, a metal layer 32S, and a metal layer 33S. Metal layer 31S is in direct contact with the semiconductor layer 21S. Metal layer 32S covers metal layer 31S. Metal layer 33S is between metal layer 31S and metal layer 32S. Metal layer 31S is on top of the semiconductor layer 21S and the insulating film 61, metal layer 33S is on top of metal layer 31S, and metal layer 32S is on top of metal layer 33S. Metal layer 31S contains cobalt (Co). Metal layer 31S is, for example, an amorphous cobalt (Co) layer. The thickness of metal layer 31S is, for example, 3 nm to 50 nm. The electrical resistance of metal layer 32S is lower than the electrical resistance of metal layer 31S. Metal layer 32S is, for example, a gold (Au) layer. The thickness of metal layer 32S is, for example, between 300 nm and 1000 nm. Metal layer 33S enhances the adhesion between metal layer 31S and metal layer 32S. Metal layer 33S is, for example, a titanium (Ti) layer. The thickness of metal layer 33S is, for example, between 2 nm and 20 nm. Metal layer 31S is an example of a first metal layer. Metal layer 32S is an example of a third metal layer.

[0040] The drain electrode 30D extends parallel to the Y-axis. The drain electrode 30D has a metal layer 31D, a metal layer 32D, and a metal layer 33D. Metal layer 31D is in direct contact with the semiconductor layer 21D. Metal layer 32D covers metal layer 31D. Metal layer 33D is between metal layer 31D and metal layer 32D. Metal layer 31D is on top of the semiconductor layer 21D and the insulating film 61, metal layer 33D is on top of metal layer 31D, and metal layer 32D is on top of metal layer 33D. Metal layer 31D contains cobalt (Co). Metal layer 31D is, for example, an amorphous cobalt (Co) layer. The thickness of metal layer 31D is, for example, 3 nm to 50 nm. The electrical resistance of metal layer 32D is lower than the electrical resistance of metal layer 31D. Metal layer 32D is, for example, a gold (Au) layer. The thickness of metal layer 32D is, for example, between 300 nm and 1000 nm. Metal layer 33D enhances the adhesion between metal layer 31D and metal layer 32D. Metal layer 33D is, for example, a titanium (Ti) layer. The thickness of metal layer 33D is, for example, between 2 nm and 20 nm.

[0041] The semiconductor device 100 has an insulating film 62. The insulating film 62 covers the source electrode 30S, the drain electrode 30D, the gate electrode 30G, and the insulating film 61. For example, the insulating film 62 is a nitride film such as a silicon nitride (SiN) film. Multiple openings 62S and multiple openings 62D are formed in the insulating film 62. The openings 62S and 62D extend parallel to the Y axis. The openings 62S reach the source electrode 30S, and the openings 62D reach the drain electrode 30D.

[0042] The source wiring 52S is located above the source electrode 30S. The source wiring 52S is provided on the insulating film 62. The source wiring 52S is in contact with the source electrode 30S through the opening 62S. The drain wiring 52D is located above the drain electrode 30D. The drain wiring 52D is provided on the insulating film 62. The drain wiring 52D is in contact with the drain electrode 30D through the opening 62D. The source wiring 52S and drain wiring 52D have, for example, a seed layer and a plating layer on the seed layer. For example, the seed layer includes a titanium (Ti) layer and the plating layer includes a gold (Au) layer. As shown in Figure 1, a plurality of drain wirings 52D may be connected to a drain pad 55, and a plurality of source wirings 52S may be connected to each other.

[0043] The semiconductor device 100 has an insulating film 63. The insulating film 63 covers the source wiring 52S, the drain wiring 52D, and the insulating film 62. For example, the insulating film 63 is a nitride film such as a silicon nitride (SiN) film.

[0044] Although not shown in the diagram, an opening reaching the gate common connection portion 15 is formed in the insulating film 62, and a gate pad is formed on the insulating film 62 that contacts the gate common connection portion 15 through this opening. In addition, an opening reaching the gate pad and an opening reaching the drain pad 55 are formed in the insulating film 63.

[0045] Through-holes 50 are formed in the substrate 11, semiconductor layer 12, and semiconductor layer 21S, penetrating the substrate 11, semiconductor layer 12, and semiconductor layer 21S. The through-holes 50 reach the source electrode 30S. At least one through-hole 50 is formed for each of the source electrodes 30S. Multiple through-holes 50 may be formed for each of the source electrodes 30S.

[0046] The back electrode 51 is formed on the lower surface of the source electrode 30S, the inner wall surface of the through hole 50, and the lower surface (first surface 11A) of the substrate 11. The back electrode 51 is in contact with the source electrode 30S and covers the first surface 11A and the inner wall surface of the through hole 50. The back electrode 51 has, for example, a seed layer and a plating layer. For example, the seed layer includes a titanium (Ti) layer, a nickel (Ni) layer, a nickel-chromium (NiCr) alloy layer, or a tantalum (Ta) layer, and the plating layer includes a gold (Au) layer. The back electrode 51 is an example of a second metal layer.

[0047] In the semiconductor device 100, a semiconductor layer 21S is formed in the recess 13S of the semiconductor layer 12, and the semiconductor layer 21S is 1.0 × 10 18 cm -3 The semiconductor layer 21S contains impurity atoms at the above concentration. In such a semiconductor layer 21S, the distance between impurity atoms is short, and as shown in Figure 3, the impurity level (E D A binding band is formed between the interacting elements, connecting to the conduction band 26. At this time, the Fermi level (E F ) exists within the conduction band, that is, the Fermi level (E F ) is the energy at the lower end of the conduction band (E C Because it is higher than ), the semiconductor layer 21S exhibits properties similar to those of a metal. In other words, the semiconductor layer 21S functions as a degenerate semiconductor layer. Therefore, ohmic contact is obtained between the semiconductor layer 21S and the source electrode 30S. Figure 3 shows the band structure of the semiconductor layer 21S. E in Figure 3 V This indicates the energy at the upper end of the valence band 27.

[0048] [First example of a semiconductor device manufacturing method] Next, a first example of a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 4 to 14 are cross-sectional views showing a first example of a method for manufacturing the semiconductor device 100 according to the first embodiment.

[0049] In the first example, as shown in Figure 4, a semiconductor layer 12 is formed on a substrate 11, for example, by metal-organic chemical vapor deposition (MOCVD). The substrate 11 has a first surface 11A and a second surface 11B opposite to the first surface 11A. The semiconductor layer 12 has a third surface 12C that is in contact with the second surface 11B and a fourth surface 12D opposite to the third surface 12C. Next, an insulating film 61 is formed on the semiconductor layer 12. The insulating film 61 can be formed, for example, by plasma CVD. The insulating film 61 covers the fourth surface 12D of the semiconductor layer 12.

[0050] Next, as shown in Figure 5, openings 61S and 61D are formed in the insulating film 61, and recesses 13S and 13D are formed in the semiconductor layer 12. For the formation of the openings 61S and 61D, reactive ion etching (RIE) of the insulating film 61 is performed, for example, using a resist pattern as a mask. For the RIE of the insulating film 61, a reactive gas containing fluorine (F), for example, is used. For the formation of the recesses 13S and 13D, RIE of the semiconductor layer 12 is performed, using the resist pattern used to form the openings 61S and 61D as a mask. For the RIE of the semiconductor layer 12, a reactive gas containing chlorine (Cl), for example, is used.

[0051] Next, as shown in Figure 6, a semiconductor layer 21S is formed in the recess 13S and a semiconductor layer 21D is formed in the recess 13D. In the formation of semiconductor layers 21S and 21D, for example, crystal growth of the semiconductor layer is performed by MOCVD, molecular beam epitaxy (MBE), or sputtering using a growth mask, and then the growth mask is removed. Semiconductor layers 21S and 21D are so-called regrowth layers.

[0052] Next, as shown in Figure 7, an opening 61G is formed in the insulating film 61. For the formation of the opening 61G, for example, RIE is performed using a resist pattern as a mask. For etching the insulating film 61, for example, a reactive gas containing fluorine (F) is used.

[0053] Next, as shown in Figure 8, a metal layer 31 is formed by atomic layer deposition (ALD). The metal layer 31 is formed on the insulating film 61, on the inner walls of each of the openings 61S, 61D, and 61G, on the semiconductor layer 21S, on the semiconductor layer 21D, and on the portion of the semiconductor layer 12 exposed from opening 61G. The metal layer 31 contains amorphous cobalt (Co). When forming a Co layer as the metal layer 31, for example, bis(diisopropylbutanamidinate)cobalt is supplied to the ALD furnace as a raw material for Co. In addition, at least one gas selected from the group consisting of hydrogen (H2) gas and ammonia (NH3) gas is supplied to the ALD furnace for the decomposition of the Co raw material. As a carrier gas, an inert gas such as nitrogen (N2) gas or argon (Ar) gas may be used. The metal layer 31 is an example of a fifth metal layer.

[0054] In forming the metal layer 31, as shown in Figure 15, for example, the temperature inside the ALD furnace is raised from room temperature to 200°C, and the metal layer 31 is deposited at 200°C. After the metal layer 31 is deposited, the temperature inside the ALD furnace is lowered back down to room temperature. Figure 15 shows an example of the temperature change when forming the metal layer 31.

[0055] Next, as shown in Figure 9, a laminate of metal layers 32G and 33G, a laminate of metal layers 32S and 33S, and a laminate of metal layers 32D and 33D are formed on the metal layer 31. These laminates can be formed, for example, by vapor deposition and lift-off.

[0056] Next, as shown in Figure 10, the portion of the metal layer 31 exposed from the above-mentioned laminate is removed. That is, the metal layer 31 is patterned. This patterning forms metal layers 31G, 31S, and 31D from the metal layer 31. Metal layer 31G is in direct contact with the semiconductor layer 12, metal layer 31S is in direct contact with the semiconductor layer 21S, and metal layer 31D is in direct contact with the semiconductor layer 21D. This patterning is performed by wet etching or milling. Next, annealing is performed in a nitrogen (N2) gas atmosphere at a temperature of 350°C to 450°C for 10 to 50 minutes. As a result, a gate electrode 30G comprising metal layers 31G, 32G, and 33G, a source electrode 30S comprising metal layers 31S, 32S, and 33S, and a drain electrode 30D comprising metal layers 31D, 32D, and 33D are formed. Annealing may be performed before patterning of the metal layer 31.

[0057] Next, as shown in Figure 11, an insulating film 62 is formed on the source electrode 30S, drain electrode 30D, gate electrode 30G, and insulating film 61. The insulating film 62 can be formed, for example, by plasma CVD. The insulating film 62 covers the source electrode 30S, drain electrode 30D, gate electrode 30G, and insulating film 61.

[0058] Next, as shown in Figure 12, openings 62S and 62D are formed in the insulating film 62. For the formation of openings 62S and 62D, for example, a RIE of the insulating film 62 is performed using a resist pattern as a mask. When performing the RIE of the insulating film 62, a reactive gas containing fluorine (F), for example, is used. Next, a source wiring 52S that contacts the source electrode 30S through opening 62S and a drain wiring 52D that contacts the drain electrode 30D through opening 62D are formed on the insulating film 62.

[0059] Next, as shown in Figure 13, an insulating film 63 is formed on top of the insulating film 62. The insulating film 63 can be formed, for example, by plasma CVD. The insulating film 63 covers the source wiring 52S, the drain wiring 52D, and the insulating film 62.

[0060] Next, as shown in Figure 14, through-holes 50 are formed in the substrate 11, semiconductor layer 12, and semiconductor layer 21S, penetrating the substrate 11, semiconductor layer 12, and semiconductor layer 21S. The through-holes 50 are formed so as to reach the source electrode 30S. The lower surface of the source electrode 30S is exposed through the through-holes 50. In forming the through-holes 50, the substrate 11 is etched first, followed by etching of the semiconductor layers 12 and 21S. When etching the semiconductor layers 12 and 21S, a reactive gas containing chlorine (Cl), for example, is used. The metal layer 31S containing cobalt (Co) has high resistance to etching using a reactive gas containing chlorine (Cl). Therefore, the metal layer 31S functions as an etching stopper. When etching the substrate 11 to form the through-holes 50, a mask is formed on the first surface 11A, and the mask is removed after etching the substrate 11. In addition, the inside of the through-holes 50 is cleaned after the formation of the through-holes 50.

[0061] Next, the back electrode 51 is formed (see Figure 2). The back electrode 51 contacts the source electrode 30S and covers the first surface 11A and the inner wall surface of the through hole 50.

[0062] In this way, the semiconductor device 100 according to the first embodiment can be manufactured.

[0063] [Second example of a semiconductor device manufacturing method] Next, a second example of a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 16 to 18 are cross-sectional views showing a second example of a method for manufacturing the semiconductor device 100 according to the first embodiment.

[0064] In the second example, the process up to the formation of the metal layer 31 is carried out using the same procedure as in the first example (see Figures 4 to 8). Next, as shown in Figure 16, a metal layer 33 is formed on top of the metal layer 31, and a metal layer 32A is formed on top of the metal layer 33. For example, the metal layer 33 is a titanium (Ti) layer, and the metal layer 32A is a gold (Au) layer. The metal layers 33 and 32A are formed, for example, by sputtering.

[0065] Next, as shown in Figure 17, metal layers 32GB, 32SB, and 32DB are formed on metal layer 32A. Metal layer 32GB is formed in the region where metal layer 32G will be formed, metal layer 32SB is formed in the region where metal layer 32S will be formed, and metal layer 32DB is formed in the region where metal layer 32D will be formed. Each of the metal layers 32GB, 32SB, and 32DB is formed to a thickness such that the sum of the thickness of the metal layer 32GB and the thickness of metal layer 32A matches the thickness of metal layers 32G, 32S, and 32D. Metal layers 32GB, 32SB, and 32DB can be formed, for example, by a plating method using metal layer 32A as a seed layer and a plating resist as a mask.

[0066] Next, as shown in Figure 18, the portions of metal layers 32A, 33, and 31 that are exposed from metal layers 32GB, 32SB, and 32DB are removed. That is, metal layers 32A, 33, and 31 are patterned. Through this patterning, metal layers 32GA, 32SA, and 32DA are formed from metal layer 32A, metal layers 33G, 33S, and 33D are formed from metal layer 33, and metal layers 31G, 31S, and 31D are formed from metal layer 31. Metal layer 31G is in direct contact with semiconductor layer 12, metal layer 31S is in direct contact with semiconductor layer 21S, and metal layer 31D is in direct contact with semiconductor layer 21D. In addition, metal layer 32G is obtained from metal layers 32GA and 32GB, metal layer 32S is obtained from metal layers 32SA and 32SB, and metal layer 32D is obtained from metal layers 32DA and 32DB. This patterning is performed by wet etching or milling. Next, annealing is performed in a nitrogen (N2) gas atmosphere at a temperature of 350°C to 450°C for 10 to 50 minutes. As a result, a gate electrode 30G with metal layers 31G, 32G, and 33G, a source electrode 30S with metal layers 31S, 32S, and 33S, and a drain electrode 30D with metal layers 31D, 32D, and 33D are formed. Annealing may be performed before patterning of metal layers 32A, 33, and 31.

[0067] Subsequently, the process from the formation of the insulating film 62 onward is carried out using the same procedure as in the first example (see Figures 11 to 14 and Figure 2).

[0068] In this way, the semiconductor device 100 according to the first embodiment can be manufactured.

[0069] In the semiconductor device 100, the back electrode 51 is in contact with the source electrode 30S, and the source electrode 30S and the semiconductor layer 21S are in ohmic contact. As a result, the electrical resistance between the semiconductor layer 12, which includes 2DEG, and the back electrode 51 is low. Therefore, according to the semiconductor device 100, the stability of the electrical resistance between the back electrode 51 and the semiconductor layer 12 is good, and the yield can be improved.

[0070] While it is conceivable to use a nickel (Ni) layer as the metal layer 31S, nickel can react with substances used to remove the mask after etching the substrate 11 and substances used to clean the through-holes 50. Therefore, if a nickel (Ni) layer is used as the metal layer 31S, a portion of the metal layer 31S may be lost, increasing the contact resistance between the source electrode 30S and the semiconductor layer 21S, and potentially reducing the yield. On the other hand, in the semiconductor device 100, the metal layer 31S contains cobalt (Co), and the metal layer 31S has high resistance to substances used to remove the mask after etching the substrate 11 and substances used to clean the through-holes 50. Therefore, the increase in contact resistance that occurs when a nickel (Ni) layer is used does not occur, and the yield can be improved.

[0071] Because the semiconductor layer 21S is a GaN layer, it is easy to obtain low electrical resistance in the semiconductor layer 21S.

[0072] The higher carrier density in semiconductor layers 21S and 21D compared to semiconductor layer 12 makes it easier to reduce the electrical resistance of the semiconductor device 100. Specifically, it makes it easier to reduce the electrical resistance between the back electrode 51 and the drain wiring 52D.

[0073] The semiconductor layer 21S is 1.0 × 10 19 cm -3 It may contain n-type impurity atoms at the above concentrations, 1.0 × 10 20 cm -3The semiconductor layer 21D may contain n-type impurity atoms at the above concentrations. The higher the concentration of n-type impurity atoms in the semiconductor layer 21S, the easier it is to obtain ohmic contact with the source electrode 30S. Similarly, the semiconductor layer 21D may contain 1.0 × 10⁻⁶ impurity atoms. 19 cm -3 It may contain n-type impurity atoms at the above concentrations, 1.0 × 10 20 cm -3 The semiconductor layer 21D may contain n-type impurity atoms at the above concentrations. The higher the concentration of n-type impurity atoms in the semiconductor layer 21D, the easier it is to obtain ohmic contact with the drain electrode 30D. The concentration of impurity atoms can be measured by secondary ion mass spectrometry (SIMS).

[0074] In the semiconductor device 100, metal layers 31G, 31S, and 31D can be formed simultaneously. Since the metal layer 31G contains amorphous cobalt, the metal layer 31G can be made less prone to gate leakage. Therefore, gate leakage can be reduced with the semiconductor device 100. In addition, since the work function of cobalt (Co) is relatively large, a high Schottky barrier can be easily obtained at the gate electrode 30G. In particular, if the surface exposed from the opening 61G of the semiconductor layer 12 is reduced before the formation of the metal layer 31, an even higher Schottky barrier can be easily obtained.

[0075] When the metal layer 31G contains hydrogen, carbon, nitrogen, and oxygen, the metal layer 31G is more likely to be in an amorphous state. The proportion of hydrogen (H) atoms, carbon (C) atoms, nitrogen (N) atoms, and oxygen (O) atoms in the metal layer 31G is, for example, between 2 atomic percent and 25 atomic percent. The proportion of each of the hydrogen, carbon, nitrogen, and oxygen atoms can be measured by SIMS. The hydrogen and nitrogen atoms originate from the raw materials and carrier gas of the metal layer 31. The carbon and oxygen atoms originate from the raw materials of the metal layer 31.

[0076] The thickness of the metal layer 31G is, as described above, for example, 3 nm to 50 nm. If the thickness of the metal layer 31G is less than 3 nm, it may become difficult to reduce gate leakage. If the thickness of the metal layer 31G is greater than 50 nm, the electrical resistance of the gate electrode 30G may become too high. The thickness of the metal layer 31G may be 5 nm to 30 nm, or 7 nm to 20 nm.

[0077] The thickness of the metal layer 31G can be measured using a transmission electron microscope (TEM) or a scanning transmission electron microscope (STEM). In this disclosure, the thickness of the metal layer 31G is the minimum dimension along the Z-axis perpendicular to the fourth surface 12D of the semiconductor layer 12 inside the aperture 61G.

[0078] The electrical resistance of the gate electrode 30G can be lowered by including a metal layer 32G in the gate electrode 30G, and having a lower electrical resistance in the metal layer 32G than in the metal layer 31G. The electrical resistance of the source electrode 30S can be lowered by including a metal layer 32S in the source electrode 30S, and having a lower electrical resistance in the metal layer 32S than in the metal layer 31S. The electrical resistance of the drain electrode 30D can be lowered by including a metal layer 32D in the drain electrode 30D, and having a lower electrical resistance in the metal layer 32D than in the metal layer 31D. The metal layers 32G, 32S, and 32D are not limited to gold (Au) layers. The metal layers 32G, 32S, and 32D may include at least one selected from the group consisting of gold (Au), copper (Cu), and aluminum (Al).

[0079] The gate electrode 30G has a metal layer 33G between the metal layer 31G and the metal layer 32G, which provides good adhesion between the metal layer 31G and the metal layer 32G. The source electrode 30S has a metal layer 33S between the metal layer 31S and the metal layer 32S, which provides good adhesion between the metal layer 31S and the metal layer 32S. The drain electrode 30D has a metal layer 33D between the metal layer 31D and the metal layer 32D, which provides good adhesion between the metal layer 31D and the metal layer 32D. When the metal layers 33G, 33S, and 33D contain titanium, good adhesion is easily obtained.

[0080] Since the cobalt-containing metal layer 31 is formed by the ALD method, the metal layer 31 is easily made amorphous. The fact that the raw material for the metal layer 31 contains bis-diisopropylbutaneamidinate cobalt makes it easy to form an amorphous metal layer 31. In addition, when forming the metal layer 31, supplying at least one gas selected from the group consisting of hydrogen (H2) gas and ammonia (NH3) gas along with the raw material into the ALD furnace makes it easier to decompose the raw material, and thus particularly easy to form an amorphous metal layer 31. Note that if either hydrogen gas or ammonia gas is supplied to the ALD furnace along with the raw material, the other gas does not need to be supplied. The supply of at least one gas is sufficient to decompose the raw material.

[0081] Before forming the metal layer 31, as shown in Figure 19, a reduction treatment is performed at a first temperature at which the native oxide film on the surface of the semiconductor layer 12 is decomposed, thereby obtaining good Schottky properties between the gate electrode 30G and the semiconductor layer 12. For example, a high Schottky barrier is obtained, the threshold voltage of the high electron mobility transistor is increased, and the voltage applied to the gate electrode 30G can be increased. For example, the native oxide film is a gallium oxide (Ga2O3) film, and the first temperature is between 400°C and 500°C. The metal layer 31 is formed at a second temperature lower than the first temperature, for example between 150°C and 250°C. Figure 19 shows another example of temperature variation when forming the metal layer 31.

[0082] For the reduction treatment, for example, hydrogen (H2) gas and ammonia (NH3) gas are used. In this case, hydrogen gas removes oxygen atoms from the native oxide film, and ammonia gas fills in nitrogen vacancies in the semiconductor layer 12. In the reduction treatment, for example, the flow rate of H2 gas is set to be between 1 standard cubic centimeter (sccm) and 500 sccm, and the flow rate of NH3 gas is set to be between 1 sccm and 500 sccm.

[0083] When a reduction treatment is performed, the reduction treatment and the formation of the metal layer 31 are carried out in the same furnace without opening to the atmosphere, i.e., the treatment is performed continuously in situ, resulting in particularly excellent cleanliness of the surface of the semiconductor layer 12. Therefore, it is easier to obtain better Schottky properties. The supply of hydrogen gas and ammonia gas can be continued from the reduction treatment to the formation of the metal layer 31.

[0084] Furthermore, when a reduction treatment is performed, by carrying out the reduction treatment and the formation of the metal layer 31 in separate furnaces without opening to the atmosphere, the temperature in the furnace where the reduction treatment is performed and the temperature in the furnace where the metal layer 31 is formed can be controlled independently of each other, making it easier to obtain a high throughput.

[0085] The distance between the source electrode 30S and the gate electrode 30G is, for example, 0.5 μm or more and 2 μm or less. If the distance between the source electrode 30S and the gate electrode 30G is less than 0.5 μm, the breakdown voltage may be low. If the distance between the source electrode 30S and the gate electrode 30G is greater than 2 μm, the sheet resistance may be high. The distance between the source electrode 30S and the gate electrode 30G may also be 0.5 μm or more and 1 μm or less.

[0086] (Second Embodiment) A second embodiment will now be described. The second embodiment differs from the first embodiment mainly in the configuration of the insulating film, gate electrode, source electrode, and drain electrode.

[0087] [Structure of a semiconductor device] The structure of a semiconductor device according to the second embodiment will now be described. Figure 20 is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0088] As shown in Figure 20, in the semiconductor device 200 according to the second embodiment, an insulating film 262 is placed on the insulating film 61, semiconductor layer 21S, and semiconductor layer 21D instead of the insulating film 62. The insulating film 262 is softer than the insulating film 61. The thickness of the insulating film 262 is, for example, 200 nm or more and 300 nm or less. Openings 262G, 262S, and 262D are formed in the insulating film 262. In a plan view, opening 262G overlaps with opening 61G and extends parallel to the Y axis. In a plan view, opening 61G is inside opening 262G. Opening 262G reaches the insulating film 61. In a plan view, opening 262S overlaps with opening 61S and extends parallel to the Y axis. In a plan view, opening 262S is inside opening 61S. Opening 262S reaches the semiconductor layer 21S. In a plan view, opening 262D overlaps with opening 61D and extends parallel to the Y axis. In a plan view, the aperture 262D is located inside the aperture 61D. The aperture 262D reaches the semiconductor layer 21D.

[0089] The gate electrode 30G is located inside the openings 61G and 262G. The gate electrode 30G has metal layers 31G, 33G, and 32G, as in the first embodiment. The source electrode 30S is located inside the opening 262S. The source electrode 30S has metal layers 31S, 33S, and 32S, as in the first embodiment. The drain electrode 30D is located inside the opening 262D. The drain electrode 30D has metal layers 31D, 33D, and 32D, as in the first embodiment.

[0090] The upper surface (+Z side) is flush with the insulating film 262, gate electrode 30G, source electrode 30S, and drain electrode 30D. The insulating film 63 is located on top of the insulating film 262, gate electrode 30G, source electrode 30S, and drain electrode 30D.

[0091] The source wiring 52S is located above the source electrode 30S. The source wiring 52S is provided on the source electrode 30S and the insulating film 262. The source wiring 52S is in contact with the source electrode 30S. The drain wiring 52D is located above the drain electrode 30D. The drain wiring 52D is provided on the drain electrode 30D and the insulating film 262. The drain wiring 52D is in contact with the drain electrode 30D.

[0092] The other components of the semiconductor device 200 are the same as those of the semiconductor device 100.

[0093] [Manufacturing method for semiconductor devices] Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. Figures 21 to 27 are cross-sectional views showing the method for manufacturing the semiconductor device 200 according to the second embodiment.

[0094] The process up to the formation of semiconductor layers 21S and 21D is carried out using the same procedure as in the first example of the first embodiment (see Figures 4 to 6). Next, as shown in Figure 21, an insulating film 262 is formed on semiconductor layer 21S, semiconductor layer 21D and insulating film 61. The insulating film 262 can be formed, for example, by plasma CVD. The insulating film 262 covers semiconductor layer 21S, semiconductor layer 21D and insulating film 61.

[0095] Next, as shown in Figure 22, openings 262S and 262D are formed in the insulating film 262. In forming openings 262S and 262D, for example, a resist pattern is used as a mask during the RIE of the insulating film 262. During the RIE of the insulating film 262, for example, a reactive gas containing fluorine (F) is used.

[0096] Next, as shown in Figure 23, an opening 262G is formed in the insulating film 262 and an opening 61G is formed in the insulating film 61. For the formation of the openings 262G and 61G, for example, a resist pattern is used as a mask during the RIE of the insulating films 262 and 61. For example, a reactive gas containing fluorine (F) is used during the RIE of the insulating films 262 and 61.

[0097] Next, as shown in Figure 24, a metal layer 31 is formed by the ALD method. The metal layer 31 can be formed under the same conditions as in the first embodiment.

[0098] Next, as shown in Figure 25, a metal layer 33 is formed on top of metal layer 31, and a metal layer 32 is formed on top of metal layer 33. For example, metal layer 33 is a titanium (Ti) layer, and metal layer 32 is a gold (Au) layer. Metal layers 33 and 32 are formed by, for example, vapor deposition, sputtering, or plating.

[0099] Next, as shown in Figure 26, chemical mechanical polishing (CMP) is performed to make the upper surfaces of the insulating film 262, metal layer 32, metal layer 33, and metal layer 31 flush. Through CMP, metal layers 32G, 32S, and 32D are formed from metal layer 32, metal layers 33G, 33S, and 33D are formed from metal layer 33, and metal layers 31G, 31S, and 31D are formed from metal layer 31. As a result, a gate electrode 30G with metal layers 31G, 32G, and 33G, a source electrode 30S with metal layers 31S, 32S, and 33S, and a drain electrode 30D with metal layers 31D, 32D, and 33D are formed.

[0100] Next, as shown in Figure 27, source wiring 52S is formed on the insulating film 262 and source electrode 30S, and drain wiring 52D is formed on the insulating film 262 and drain electrode 30D. Then, insulating film 63 is formed on the insulating film 262, gate electrode 30G, source wiring 52S and drain wiring 52D.

[0101] Subsequently, the process from the formation of the through hole 50 onward is carried out using the same procedure as in the first embodiment (see Figures 14 and 20).

[0102] In this way, the semiconductor device 200 according to the second embodiment can be manufactured.

[0103] The second embodiment also allows for improved yield, similar to the first embodiment.

[0104] The metal layers 31S and 31D do not have to be in an amorphous state; they may contain crystalline cobalt (Co). For example, after forming metal layers 31S and 31D containing crystalline cobalt (Co), a metal layer 31G containing amorphous cobalt (Co) may be formed.

[0105] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims. [Explanation of Symbols]

[0106] 11 circuit boards 11A 1st page 11B 2nd side 12 Semiconductor layer 12C 3rd page 12D 4th side 13D, 13S recess 15 Gate Common Connection Section 21D, 21S semiconductor layer 26 Conduction band 27 valence band 30D drain electrode 30G gate 30S Source Electrode 31, 31D, 31G, 31S metal layer 32, 32A, 32D, 32DA, 32DB, 32G, 32GA, 32GB, 32S, 32SA, 32SB Metal layer 33, 33D, 33G, 33S metal layer 50 Through holes 51 Backside electrode 52D Drain Wiring 52S Source Wiring 55 Drain Pad 61, 62, 63, 262 insulating film 61D, 61G, 61S, 62D, 62S, 262D, 262G, 262S opening 100, 200 semiconductor equipment

Claims

1. A substrate having a first surface and a second surface opposite to the first surface, A first nitride semiconductor layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface, with a recess formed on the fourth surface, A second nitride semiconductor layer provided in the recess, A first metal layer provided on the second nitride semiconductor layer, It has, The substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer have through-holes that penetrate the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer and reach the first metal layer. The first metal layer has a second metal layer that is in contact with the first metal layer and covers the first surface and the inner wall surface of the through hole, The first metal layer contains cobalt, The second nitride semiconductor layer is 1.0 × 10 １８ cm －３ A semiconductor device containing impurity atoms at the above concentration.

2. Having a third metal layer covering the first metal layer, The semiconductor device according to claim 1, wherein the electrical resistance of the third metal layer is lower than the electrical resistance of the first metal layer.

3. The semiconductor device according to claim 2, wherein the third metal layer comprises at least one selected from the group consisting of gold, copper, and aluminum.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second nitride semiconductor layer is a gallium nitride layer.

5. The semiconductor device according to any one of claims 1 to 3, wherein in the second nitride semiconductor layer, the Fermi level is higher than the energy of the lower end of the conduction band.

6. The semiconductor device according to any one of claims 1 to 3, wherein the carrier density in the second nitride semiconductor layer is higher than the carrier density in the first nitride semiconductor layer.

7. The gate electrode has Schottky contact with the first nitride semiconductor layer, The gate electrode has a fourth metal layer that is in direct contact with the first nitride semiconductor layer. The semiconductor device according to any one of claims 1 to 3, wherein the fourth metal layer contains cobalt.

8. The semiconductor device according to claim 7, wherein the fourth metal layer contains amorphous cobalt.

9. The semiconductor device according to claim 8, wherein the fourth metal layer comprises hydrogen atoms, carbon atoms, nitrogen atoms, and oxygen atoms.

10. A step of forming a first nitride semiconductor layer on a substrate having a first surface and a second surface opposite to the first surface, the layer having a third surface in contact with the second surface and a fourth surface opposite to the third surface. The process of forming a recess on the aforementioned fourth surface, The process of forming a second nitride semiconductor layer in the recess, A step of forming a first metal layer on the second nitride semiconductor layer, The process of forming through holes in the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer, which penetrate the substrate, the first nitride semiconductor layer, and the second nitride semiconductor layer and reach the first metal layer, A step of forming a second metal layer that contacts the first metal layer and covers the first surface and the inner wall surface of the through hole, It has, The first metal layer contains cobalt, The second nitride semiconductor layer is 1.0 × 10 １８ cm －３ A method for manufacturing a semiconductor device containing impurity atoms at the above concentration.

11. The step of forming the first metal layer is: A step of forming a fifth metal layer containing amorphous cobalt on the first nitride semiconductor layer and the second nitride semiconductor layer by atomic layer deposition, The process of patterning the fifth metal layer, It has, The method for manufacturing a semiconductor device according to claim 10, wherein a fourth metal layer that is in direct contact with the first nitride semiconductor layer is formed in the step of patterning the fifth metal layer.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the raw material for the fifth metal layer contains bis-diisopropylbutaneamidinate cobalt.

13. The method for manufacturing a semiconductor device according to claim 12, wherein in the step of forming the fifth metal layer, at least one gas selected from the group consisting of hydrogen gas and ammonia gas is supplied into the furnace along with the raw materials.

14. Prior to the step of forming the fifth metal layer, the process includes a step of performing a reduction treatment at a first temperature at which the native oxide film on the surface of the first nitride semiconductor layer is decomposed. The method for manufacturing a semiconductor device according to any one of claims 11 to 13, wherein the fifth metal layer is formed at a second temperature lower than the first temperature.

15. The method for manufacturing a semiconductor device according to claim 14, wherein the reduction treatment step and the fifth metal layer formation step are performed in the same furnace without opening to the atmosphere.

16. The method for manufacturing a semiconductor device according to claim 14, wherein the step of performing the reduction treatment and the step of forming the fifth metal layer are carried out in different furnaces without opening to the atmosphere.

17. The method for manufacturing a semiconductor device according to claim 14, wherein hydrogen gas and ammonia gas are used in the reduction treatment.

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