Power factor correction circuit

Abstract

This invention provides a power factor correction circuit that can suppress the surge voltage generated between the drain and source of a switching element during the first switching of each half-cycle. [Solution] The power factor correction circuit 1 comprises a high-frequency leg 11 connected to the AC voltage Vin via an inductor L, and a commercial leg 12 directly connected to the AC voltage Vin. The power factor correction circuit 1 converts the AC voltage Vin to a DC voltage Vo by controlling the on / off state of the commercial leg 12 at the frequency of the AC voltage Vin, and the on / off state of the high-frequency leg 12 at a frequency higher than the frequency of the AC voltage Vin. The power factor correction circuit 1 sets the turn-on switching speed of the commercial leg 12 to be slower than that of the high-frequency leg 11, and turns on the commercial leg 12 before the high-frequency leg 11 at the start of half a cycle of the AC voltage Vin.

Description

Technical Field

[0001] The present invention relates to a power factor improvement circuit having a high-frequency leg and a commercial leg.

Background Art

[0002] A power factor improvement circuit having a high-frequency leg and a commercial leg is called a totem-pole type PFC (Totem-Pole Bridgeless PFC) circuit. The commercial leg is composed of a pair of switching elements connected in series that perform a switching operation at the frequency of the input AC voltage. The high-frequency leg is composed of another pair of switching elements connected in series that perform a switching operation at a frequency higher than the frequency of the input AC voltage. In such a power factor improvement circuit, the switching element of the high-frequency leg performs ZVS (zero voltage switching) turn-on, thereby suppressing the switching loss and stress generated in the switching element and realizing high efficiency (see, for example, Non-Patent Document 1).

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in totem-pole type PFC circuits, the large surge voltage generated between the drain and source of the switching elements during the first switching of each half-cycle can exceed the voltage rating of the switching elements. Furthermore, large surge voltages simultaneously generate significant EMI noise.

[0005] One aspect of the present invention provides a power factor correction circuit that can suppress the surge voltage generated between the drain and source of a switching element during the first switching of each half-cycle. [Means for solving the problem]

[0006] A power factor correction circuit according to one aspect of the present invention comprises a high-frequency leg connected to an AC voltage via an inductor and a commercial leg directly connected to the AC voltage. The power factor correction circuit converts the AC voltage to a DC voltage by controlling the commercial leg to turn on and off at the frequency of the AC voltage, and the high-frequency leg to turn on and off at a frequency higher than the frequency of the AC voltage. The power factor correction circuit sets the turn-on switching speed of the commercial leg to be slower than that of the high-frequency leg 11, and turns on the commercial leg before the high-frequency leg at the start of half a cycle of the AC voltage. [Effects of the Invention]

[0007] According to one aspect of the present invention, surge voltage generated between the drain and source of a switching element during the first switching of each half-cycle can be suppressed, thereby suppressing EMI noise. [Brief explanation of the drawing]

[0008] [Figure 1] This diagram shows the circuit configuration of an embodiment of the power factor correction circuit. [Figure 2] This figure shows the AC voltage, inductor current, and drive signal. [Figure 3] This diagram shows the current path of the inductor current iL. [Figure 4] This diagram shows the charge and discharge operation at the start of a half-cycle. [Figure 5]There is a diagram showing the surge voltage associated with charging and discharging operations. [Figure 6] There is a diagram showing suppressed surge voltage. [Figure 7] This figure shows another example. [Modes for carrying out the invention]

[0009] The embodiments of the present invention will now be described in detail with reference to the figures. In the following embodiments, components that have the same function are denoted by the same reference numerals and their descriptions are omitted as appropriate.

[0010] The power factor correction circuit 1 of this embodiment is a totem-pole type PFC circuit that converts an AC voltage Vin to a DC voltage Vo. Referring to Figure 1, the power factor correction circuit 1 comprises an inductor L, a high-frequency leg 11, a commercial-frequency leg 12, and a capacitor Co.

[0011] The high-frequency leg 11 comprises a pair of high-frequency upper switching elements SW1 (hereinafter referred to as high-frequency upper SW1) and a high-frequency lower switching element SW2 (hereinafter referred to as high-frequency lower SW2) connected in series. The connection point between the high-frequency upper SW1 and the high-frequency lower SW2 of the high-frequency leg 11 is connected to an AC voltage Vin via an inductor L.

[0012] The commercial leg 12 comprises a pair of commercial-powered switching elements SW3 (hereinafter referred to as commercial-powered SW3) and commercial-powered switching elements SW4 (hereinafter referred to as commercial-powered SW4) connected in series. The connection point between commercial-powered SW3 and commercial-powered SW4 of the commercial leg 12 is directly connected to the AC voltage Vin.

[0013] In the power factor correction circuit 1, both ends of the high-frequency leg 11 and both ends of the commercial-voltage leg 12 are connected in parallel to both ends of the capacitor Co, and a DC voltage Vo is obtained from the capacitor Co.

[0014] The power factor improvement circuit 1 includes a control circuit 20. The control circuit 20 generates and outputs respective drive signals (gate signals) G3 and G4 for turning on and off the commercial upper SW3 and the commercial lower SW4 at the frequency of the AC voltage Vin. The drive signal G3 (G4) is supplied to the gate terminal of the commercial upper SW3 (commercial lower SW4) via a driver 33 (34) and a gate resistor R3 (R4). The control circuit 20 generates and outputs respective drive signals (gate signals) G1 and G2 for turning on and off the high-frequency upper SW1 and the high-frequency lower SW2 at a frequency higher than the frequency of the AC voltage Vin. The drive signal G1 (G2) is supplied to the gate terminal of the high-frequency upper SW1 (high-frequency lower SW2) via a driver 31 (32) and a gate resistor R1 (R2).

[0015] FIG. 2 shows the inductor current i and the drive signals G1 to G4 in the positive half-cycle of the AC voltage Vin. L FIG. 3 shows the current path of the inductor current i in the positive half-cycle. L Referring to FIG. 2, the control circuit 20 controls the commercial upper SW3 to be in the off state and the commercial lower SW4 to be in the on state respectively in the positive half-cycle.

[0016] The control circuit 20 complementarily turns on and off the high-frequency upper SW1 and the high-frequency lower SW2 at a frequency higher than the frequency of the AC voltage Vin in the positive half-cycle. When the high-frequency lower SW2 turns on from the off state (dead time) of the high-frequency upper SW1 and the high-frequency lower SW2, as shown in FIG. 3(a), it becomes the excitation period in which the inductor L is charged. Next, when the high-frequency lower SW2 turns off and the high-frequency upper SW1 turns on across the dead time, as shown in FIG. 3(b), it becomes the regeneration period in which the inductor L is discharged. After that, if the high-frequency upper SW1 continues to be on even after the timing when the current of the inductor L becomes zero, as shown in FIG. 3(c), the polarity of the current is reversed and it becomes the reverse current period. When the high-frequency upper SW1 turns off during this reverse current period, as shown in FIG. 3(d), the body diode of the high-frequency upper SW2 conducts. By turning on the high-frequency lower SW2 at this timing, ZVS (zero voltage switching) turn-on is realized.

[0017] The high-frequency upper SW1, high-frequency lower SW2, commercial upper SW3, and commercial lower SW4 are composed of switching elements such as GaN devices and SiC (Silicon Carbide) devices (for example, a metal-oxide-semiconductor field-effect transistor (MOSFET)). Therefore, parasitic capacitances exist in the high-frequency upper SW1, high-frequency lower SW2, commercial upper SW3, and commercial lower SW4. Among these parasitic capacitances, the output capacitance Coss is charged and discharged between 0V and the DC voltage Vo during the switching operation.

[0018] FIG. 4(a) shows the charging state of the output capacitance Coss at the dead time at the start of the positive half-cycle. The output capacitances Coss of the high-frequency lower SW2 and the commercial lower SW4 are charged to the DC voltage Vo. The high-frequency lower SW2 and the commercial lower SW4 are turned on from the state where the output capacitance Coss is charged to the DC voltage Vo.

[0019] When the high-frequency lower SW2 in the high-frequency leg 11 is first turned on, as shown by the solid-line arrow in FIG. 4(b), the output capacitance Coss of the high-frequency lower SW2 is short-circuited and discharged, and the output capacitance Coss of the high-frequency upper SW1 is directly charged from the DC voltage Vo. Since the charging and discharging current of the high-frequency leg 11 is steep, that is, di / dt is large, in the drain-source voltage Vds of the high-frequency upper SW1, as shown in FIG. 5(a), a large surge voltage (L s (di / dt)) is generated by the parasitic inductance L existing in the current path. Subsequently, ringing occurs in the drain-source voltage Vds of the high-frequency upper SW1 due to the resonance of the output capacitance Coss and the parasitic inductance. s

[0020] As shown by the dotted-line arrow in FIG. 4(b), the output capacitance Coss of the commercial upper SW3 is charged, and the output capacitance Coss of the commercial lower SW4 is discharged. Since the charging and discharging current of the commercial leg 12 passes through the inductor L, di / dt is relatively small, and a large surge voltage does not occur in the drain-source voltage Vds of the commercial upper SW3.

[0021] ​When the commercial-under SW4 of commercial leg 12 is first turned on, as shown by the solid arrow in Figure 4(c), the output capacitance Coss of the commercial-under SW4 is short-circuited and discharged, and the output capacitance Coss of the commercial-upper SW3 is directly charged from the DC voltage Vo. The charge / discharge current of commercial leg 12 is steep, i.e., di / dt is large, so at the drain-source voltage Vds of the commercial-upper SW3, a large surge voltage (L) is generated due to the parasitic inductance present in the current path, as shown in Figure 5(b). s di / dt) occurs. At the drain-source voltage Vds of SW3, ringing subsequently occurs due to resonance between the output capacitance Coss and the parasitic inductance.

[0022] As shown by the dotted arrows in Figure 4(c), the output capacitance Coss of the high-frequency upper SW1 is charged, and the output capacitance Coss of the high-frequency lower SW1 is discharged. Since the charge / discharge current of the high-frequency leg 11 is mediated through the inductor L, the di / dt is relatively small, and no large surge voltage occurs in the drain-source voltage Vds of the high-frequency upper SW1. Thus, regardless of whether the high-frequency leg 11 or the commercial leg 12 is turned on first from the dead time at the start of the half-cycle, a large surge voltage will occur.

[0023] Therefore, the power factor correction circuit 1 of this embodiment sets the turn-on switching speed of the commercial leg 12 to be slower than that of the high-frequency leg 11, and starts switching of the commercial leg 12 earlier than that of the high-frequency leg 11 from the dead time at the start of the half-cycle. By setting the turn-on switching speed of the commercial leg 12 to be slower than that of the high-frequency leg 11, the charge / discharge current of the output capacitance Coss becomes smaller in di / dt, and as shown in Figure 6, the surge voltage (L s This suppresses the occurrence of di / dt. While delaying the turn-on time increases switching losses, the switching frequency of commercial leg 12 is the frequency of the AC voltage (50Hz or 60Hz), so the increase in switching losses is not a problem.

[0024] To slow down the turn-on switching speed of the commercial leg 12 compared to the high-frequency leg 11, the gate resistors R3 and R4 used in the commercial leg 12 are set to have larger resistance values ​​than the gate resistors R1 and R2 used in the high-frequency leg 11. In this embodiment, while the gate resistors R1 and R2 of the high-frequency leg 11 are set to 47Ω, the gate resistors R3 and R4 of the commercial leg 12 are set to 270Ω, which is more than five times larger than the gate resistors R1 and R2.

[0025] If you do not want to slow down the switching speed during turn-off, you can provide a series circuit consisting of diode D1 and resistors R31 and R41 in parallel with gate resistors R3 and R4, as shown in Figure 7(a), so that the combined resistance of gate resistors R3 and R4 and resistors R31 and R41 acts during turn-off.

[0026] In the commercial upper SW3 and commercial lower SW4 of commercial leg 12, as shown in Figure 7(b), a capacitor C1 may be provided between the gate and source to set the turn-on switching speed of commercial leg 12 to be slower than that of high-frequency leg 11.

[0027] Furthermore, the power factor correction circuit 1 of this embodiment only needs to be equipped with a commercial leg 12, and can also be used in an interleaved configuration with multiple high-frequency legs 11.

[0028] (summary) (1) Each embodiment of the present invention comprises a power factor correction circuit 1, a high-frequency leg 11 connected to an AC voltage Vin via an inductor L, and a commercial leg 12 directly connected to the AC voltage Vin. The power factor correction circuit 1 converts the AC voltage Vin to a DC voltage Vo by controlling the commercial leg 12 to turn on and off at the frequency of the AC voltage Vin, and the high-frequency leg 11 to turn on at a frequency higher than the frequency of the AC voltage Vin. The power factor correction circuit 1 sets the turn-on switching speed of the commercial leg 12 to be slower than that of the high-frequency leg 11, and turns on the commercial leg 12 before the high-frequency leg 11 at the start of half a cycle of the AC voltage Vin.

[0029] According to the power factor correction circuit 1 described in (1) above, surge voltages generated between the drain and source of the switching elements (high frequency upper SW1, high frequency lower SW2, commercial power upper SW3, commercial power lower SW4) during the first switching of each half-cycle can be suppressed, thereby suppressing EMI noise.

[0030] (2) In the power factor correction circuit 1 described in (1) above, the gate resistors R3 and R4 used for the switching elements of the commercial leg 12 (commercial upper SW3, commercial lower SW4) are greater than the gate resistors R1 and R2 used for the switching elements of the high-frequency leg 11 (high-frequency upper SW1, high-frequency lower SW2).

[0031] According to the power factor correction circuit 1 described in (2) above, the switching speed of the commercial leg 12 turn-on can be set slower than that of the high-frequency leg 11 with a simple configuration.

[0032] (3) In the power factor correction circuit 1 described in (2) above, the gate resistors R3 and R4 used for the switching elements of the commercial leg 12 are five times or more the gate resistors R1 and R2 used for the switching elements of the high-frequency leg 11.

[0033] According to the power factor correction circuit 1 described in (3) above, a reliable surge voltage suppression effect can be obtained.

[0034] (4) In the power factor correction circuit 1 described in (2) or (3) above, the switching element of the commercial leg 12 has a capacitor C1 connected between the gate and source.

[0035] According to the power factor correction circuit 1 described in (4) above, the switching speed of the commercial leg 12 turn-on can be set slower than that of the high-frequency leg 11 with a simple configuration.

[0036] Although the present invention has been described above with reference to specific embodiments, it goes without saying that these embodiments are merely examples and can be modified and implemented without departing from the spirit of the present invention. [Explanation of Symbols]

[0037] 1. Power Factor Correction Circuit 11 High-frequency legs 12 Commercial Legs 20 Control circuits 31-34 Drivers C1, Co capacitor Coss output capacity D1 diode L Inductor R1~R4 Gate Resistors R31, R41 resistors SW1 High-Frequency Switching Element SW2 High-Frequency Switching Element SW3 Commercial Switching Element SW4 Commercial Switching Element Vin AC voltage Vo DC voltage

Claims

1. A power factor correction circuit comprising a high-frequency leg connected to an AC voltage via an inductor and a commercial leg directly connected to the AC voltage, wherein the commercial leg is switched on and off at the frequency of the AC voltage and the high-frequency leg at a frequency higher than the frequency of the AC voltage, thereby converting the AC voltage to a DC voltage, A power factor correction circuit that sets the switching speed of the commercial leg to turn on slower than that of the high-frequency leg, and turns on the commercial leg before the high-frequency leg at the start of half a cycle of the AC voltage.

2. The power factor correction circuit according to claim 1, wherein the gate resistance used in the switching element of the commercial leg is greater than the gate resistance used in the switching element of the high-frequency leg.

3. The power factor correction circuit according to claim 2, wherein the gate resistance used in the switching element of the commercial leg is five times or more the gate resistance used in the switching element of the high-frequency leg.

4. The power factor correction circuit according to claim 1, wherein the switching element of the commercial leg has a capacitor connected between the gate and source.

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