Semiconductor light-emitting element and method for manufacturing a semiconductor light-emitting element

Abstract

To improve the reliability of semiconductor light-emitting elements. [Solution] The semiconductor light-emitting element 10 includes a p-side contact electrode 30 provided on a p-type semiconductor layer 28, a p-side current diffusion layer 34 provided on the p-side contact electrode 30, a first protective layer 38 having a pad opening provided on the p-side current diffusion layer 34 and covering the p-type semiconductor layer 28 and the p-side current diffusion layer 34 at locations different from the pad opening, and a p-side pad electrode 42 that contacts the p-side current diffusion layer 34 at the pad opening. The p-side current diffusion layer 34 includes a lower TiN layer 50 that contacts the conductive oxide material of the p-side contact electrode 30 and an upper TiN layer 54 that contacts the dielectric material of the first protective layer 38. In RGB measurement values ​​expressed as values ​​between 0 and 255, the difference between the R value and B value of the lower TiN layer 50 is 25 or more, and the difference between the R value and B value of the upper TiN layer 54 is less than 25.

Description

[Technical Field]

[0001] This invention relates to a semiconductor light-emitting element and a method for manufacturing a semiconductor light-emitting element. [Background technology]

[0002] A semiconductor light-emitting element has an n-type semiconductor layer, an active layer, and a p-type semiconductor layer stacked on a substrate, with an n-side electrode provided on the n-type semiconductor layer and a p-side electrode provided on the p-type semiconductor layer. In addition, a protective layer made of a dielectric material such as silicon oxide or silicon nitride is provided on the surface of the semiconductor light-emitting element (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2016-171141 [Overview of the project] [Problems that the invention aims to solve]

[0004] It is preferable to further improve the reliability of the semiconductor light-emitting element.

[0005] This invention has been made in view of these problems, and aims to provide a technology for improving the reliability of semiconductor light-emitting devices. [Means for solving the problem]

[0006] A semiconductor light-emitting element according to one aspect of the present invention comprises an n-type semiconductor layer, an active layer provided on the n-type semiconductor layer, a p-type semiconductor layer provided on the active layer, a contact electrode provided on the p-type semiconductor layer and comprising a conductive oxide material, a current diffusion layer provided on the contact electrode, a protective layer provided on the current diffusion layer having a pad opening, covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer and the current diffusion layer at locations different from the pad opening, and made of a dielectric material, and a pad electrode provided on the protective layer outside the pad opening and in contact with the current diffusion layer at the pad opening. The current diffusion layer includes a lower TiN layer in contact with the conductive oxide material of the contact electrode and an upper TiN layer in contact with the dielectric material of the protective layer. The lower TiN layer is made of titanium nitride in which the difference between the R value and the B value is 25 or more in an RGB measurement value expressed as a numerical value between 0 and 255, and the upper TiN layer is made of titanium nitride in which the difference between the R value and the B value is less than 25 in an RGB measurement value expressed as a numerical value between 0 and 255.

[0007] Another aspect of the present invention is a method for manufacturing a semiconductor light-emitting element. This method comprises the steps of: forming an active layer on an n-type semiconductor layer; forming a p-type semiconductor layer on the active layer; forming a contact electrode comprising a conductive oxide material on the p-type semiconductor layer; forming a current diffusion layer on the contact electrode; forming a protective layer made of a dielectric material that covers the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current diffusion layer; removing the protective layer on the current diffusion layer to form a pad opening; and forming a pad electrode that contacts the current diffusion layer at the pad opening and is provided on the protective layer outside the pad opening. The step of forming the current diffusion layer includes the steps of forming a lower TiN layer that contacts the conductive oxide material of the contact electrode and forming an upper TiN layer that contacts the dielectric material of the protective layer. The lower TiN layer is formed by reactive sputtering under the condition that the flow rate ratio of nitrogen gas to argon gas is 9% or more, and the upper TiN layer is formed by reactive sputtering under the condition that the flow rate ratio of nitrogen gas to argon gas is 8% or less. [Effects of the Invention]

[0008] According to the present invention, the reliability of the semiconductor light-emitting device can be improved.

Brief Description of the Drawings

[0009] [Figure 1] It is a cross-sectional view schematically showing the configuration of the semiconductor light-emitting device according to the embodiment. [Figure 2] It is a cross-sectional view schematically showing the configuration of the p-side contact electrode, the p-side current diffusion layer, and the p-side pad electrode. [Figure 3] It is a cross-sectional view schematically showing the configuration of the n-side contact electrode, the n-side current diffusion layer, and the n-side pad electrode. [Figure 4] It is a graph showing an example of the film formation conditions of titanium nitride. [Figure 5] It is a graph showing an example of the RGB measurement values of titanium nitride. [Figure 6] It is a table showing an example of the RGB measurement values and the sealing property of the upper TiN layer. [Figure 7] It is a table showing an example of the RGB measurement values and the adhesion property of the lower TiN layer. [Figure 8] It is a diagram schematically showing the manufacturing process of the semiconductor light-emitting device. [Figure 9] It is a diagram schematically showing the manufacturing process of the semiconductor light-emitting device. [Figure 10] It is a diagram schematically showing the manufacturing process of the semiconductor light-emitting device. [Figure 11] It is a diagram schematically showing the manufacturing process of the semiconductor light-emitting device. [Figure 12] It is a diagram schematically showing the manufacturing process of the semiconductor light-emitting device. [Figure 13] It is a diagram schematically showing the manufacturing process of the semiconductor light-emitting device. [Figure 14] It is a diagram schematically showing the manufacturing process of the semiconductor light-emitting device. [Figure 15] It is a diagram schematically showing the manufacturing process of the semiconductor light-emitting device.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments for implementing the present invention will be described in detail with reference to the drawings. In the description, the same elements are denoted by the same reference numerals, and duplicate descriptions will be omitted as appropriate. Also, for the sake of understanding the description, the dimensional ratios of the respective components in each drawing do not necessarily match the dimensional ratios of the actual light-emitting elements.

[0011] The semiconductor light-emitting element according to this embodiment is configured to emit "deep ultraviolet light" with a central wavelength λ of about 360 nm or less, and is a so-called DUV-LED (Deep UltraViolet-Light Emitting Diode) chip. In order to output deep ultraviolet light of such a wavelength, an aluminum gallium nitride (AlGaN)-based semiconductor material with a bandgap of about 3.4 eV or more is used. In this embodiment, particularly, the case of emitting deep ultraviolet light with a central wavelength λ of about 240 nm to 320 nm is shown.

[0012] In this specification, the "AlGaN-based semiconductor material" refers to a semiconductor material containing at least aluminum nitride (AlN) and gallium nitride (GaN), and includes semiconductor materials containing other materials such as indium nitride (InN). Therefore, the "AlGaN-based semiconductor material" referred to in this specification can be represented by a composition of In 1-x-y Al x Ga y N (0 < x + y ≤ 1, 0 < x < 1, 0 < y < 1), and includes AlGaN or InAlGaN. The "AlGaN-based semiconductor material" in this specification has, for example, a molar fraction of each of AlN and GaN of 1% or more, preferably 5% or more, 10% or more, or 20% or more.

[0013] Also, in order to distinguish materials that do not contain AlN, they may be referred to as "GaN-based semiconductor materials". "GaN-based semiconductor materials" include GaN and InGaN. Similarly, in order to distinguish materials that do not contain GaN, they may be referred to as "AlN-based semiconductor materials". "AlN-based semiconductor materials" include AlN and InAlN.

[0014] Figure 1 is a schematic cross-sectional view showing the configuration of a semiconductor light-emitting element 10 according to an embodiment. The semiconductor light-emitting element 10 comprises a substrate 20, a base layer 22, an n-type semiconductor layer 24, an active layer 26, a p-type semiconductor layer 28, a p-side contact electrode 30, an n-side contact electrode 32, a p-side current diffusion layer 34, an n-side current diffusion layer 36, a first protective layer 38, a second protective layer 40, a p-side pad electrode 42, an n-side pad electrode 44, a p-side junction layer 46, and an n-side junction layer 48.

[0015] In Figure 1, the direction indicated by arrow A is sometimes referred to as the "up-down direction" or "thickness direction." Also, when viewed from the substrate 20, the direction away from the substrate 20 is sometimes referred to as the "upper side," and the direction towards the substrate 20 is sometimes referred to as the "lower side."

[0016] The substrate 20 has a first main surface 20a and a second main surface 20b opposite to the first main surface 20a. The first main surface 20a is a crystal growth surface for growing each layer from the base layer 22 to the p-type semiconductor layer 28. The substrate 20 is made of a material that is transparent to deep ultraviolet light emitted by the semiconductor light-emitting element 10, for example, sapphire (Al2O3). A fine uneven pattern with a depth and pitch of submicron (1 μm or less) is formed on the first main surface 20a. Such a substrate 20 is also called a patterned sapphire substrate (PSS). The second main surface 20b is a light extraction surface for extracting deep ultraviolet light emitted by the active layer 26 to the outside. The substrate 20 may be made of AlN or AlGaN. The substrate 20 may also be a normal substrate in which the first main surface 20a is a flat surface that is not patterned.

[0017] The base layer 22 is provided on the first main surface 20a of the substrate 20. The base layer 22 is an underlying layer (template layer) for forming the n-type semiconductor layer 24. The base layer 22 is, for example, an undoped AlN layer, specifically, an AlN (HT-AlN; High Temperature-AlN) layer grown at a high temperature. The base layer 22 may include an undoped AlGaN layer formed on the AlN layer. When the substrate 20 is an AlN substrate or an AlGaN substrate, the base layer 22 may be composed of only an undoped AlGaN layer. That is, the base layer 22 includes at least one of an undoped AlN layer and an AlGaN layer.

[0018] The n-type semiconductor layer 24 is provided on the upper surface 22a of the base layer 22. The n-type semiconductor layer 24 is composed of an n-type AlGaN-based semiconductor material. For example, it is doped with Si as an n-type impurity. The composition ratio of the n-type semiconductor layer 24 is selected so as to transmit the deep ultraviolet light emitted by the active layer 26. For example, the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The n-type semiconductor layer 24 has a bandgap larger than the wavelength of the deep ultraviolet light emitted by the active layer 26. For example, it is configured so that the bandgap is 4.3 eV or more. The n-type semiconductor layer 24 is preferably configured so that the molar fraction of AlN is 80% or less, that is, the bandgap is 5.5 eV or less, and more preferably configured so that the molar fraction of AlN is 70% or less (that is, the bandgap is 5.2 eV or less). The n-type semiconductor layer 24 has a thickness of 1 μm or more and 3 μm or less. For example, it has a thickness of about 2 μm.

[0019] The n-type semiconductor layer 24 has a Si impurity concentration of 1×10 18 / cm 3 or more and 5×10 19 / cm 3 or less. The n-type semiconductor layer 24 is preferably configured so that the Si concentration is 5×10 18 / cm 3 or more and 3×10 19 / cm 3 or less, and more preferably 7×10 18 / cm3 The above 2 x 10 19 / cm 3 It is more preferable that the following configuration be used. In one embodiment, the Si concentration of the n-type semiconductor layer 24 is 1 × 10 19 / cm 3 It is front and back, specifically 8 x 10 18 / cm 3 The above 1.5 × 10 19 / cm 3 The range is as follows:

[0020] The n-type semiconductor layer 24 has a first upper surface 24a and a second upper surface 24b. The first upper surface 24a is the portion where the active layer 26 is formed, and the second upper surface 24b is the portion where the active layer 26 is not formed.

[0021] The active layer 26 is provided on the first upper surface 24a of the n-type semiconductor layer 24. The active layer 26 is composed of an AlGaN-based semiconductor material and is sandwiched between the n-type semiconductor layer 24 and the p-type semiconductor layer 28 to form a double heterostructure. The active layer 26 is configured to have a band gap of 3.4 eV or more in order to output deep ultraviolet light with a wavelength of 355 nm or less. For example, the AlN composition ratio is selected so that it can output deep ultraviolet light with a wavelength of 320 nm or less.

[0022] The active layer 26 has, for example, a single-layer or multi-layer quantum well structure and includes a barrier layer made of an undoped AlGaN semiconductor material and a well layer made of an undoped AlGaN semiconductor material. The active layer 26 includes, for example, a first barrier layer that is in direct contact with the n-type semiconductor layer 24 and a first well layer provided on the first barrier layer. One or more pairs of barrier layers and well layers may be additionally provided between the first well layer and the p-type semiconductor layer 28. Each of the barrier layer and well layer has a thickness of 1 nm to 20 nm, for example, a thickness of 2 nm to 10 nm.

[0023] An electron blocking layer may be further provided between the active layer 26 and the p-type semiconductor layer 28. The electron blocking layer is composed of an undoped AlGaN-based semiconductor material, for example, configured such that the mole fraction of AlN is 40% or more, preferably 50% or more. The electron blocking layer may be configured such that the mole fraction of AlN is 80% or more, or it may be composed of an AlN-based semiconductor material that does not contain GaN. The electron blocking layer has a thickness of 1 nm to 10 nm, for example, a thickness of 2 nm to 5 nm.

[0024] The p-type semiconductor layer 28 is formed on the active layer 26. The p-type semiconductor layer 28 is a p-type AlGaN-based semiconductor material layer or a p-type GaN-based semiconductor material layer, for example, an AlGaN layer or GaN layer doped with magnesium (Mg) as a p-type impurity. The p-type semiconductor layer 28 has a thickness of, for example, 20 nm to 400 nm.

[0025] The p-type semiconductor layer 28 may be composed of multiple layers. For example, the p-type semiconductor layer 28 may have a p-type cladding layer and a p-type contact layer. The p-type cladding layer is a p-type AlGaN layer with a higher AlN ratio compared to the p-type contact layer and is provided to be in direct contact with the active layer 26. The p-type contact layer is a p-type AlGaN layer or a p-type GaN layer with a lower AlN ratio compared to the p-type cladding layer. The p-type contact layer is provided on top of the p-type cladding layer and is provided to be in direct contact with the p-side contact electrode 30. The p-type cladding layer may have a first p-type cladding layer and a second p-side cladding layer.

[0026] The composition ratio of the p-type first cladding layer is selected to transmit deep ultraviolet light emitted by the active layer 26. The p-type first cladding layer is configured such that, for example, the mole fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The AlN ratio of the p-type first cladding layer is, for example, similar to or greater than the AlN ratio of the n-type semiconductor layer 24. The AlN ratio of the p-type cladding layer may be 70% or more or 80% or more. The p-type first cladding layer has a thickness of 10 nm to 100 nm, for example, 15 nm to 70 nm.

[0027] The p-type second cladding layer is provided on the p-type first cladding layer. The p-type second cladding layer is a p-type AlGaN layer with a moderate AlN ratio, lower than that of the p-type first cladding layer and higher than that of the p-type contact layer. The p-type second cladding layer is formed such that, for example, the mole fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The AlN ratio of the p-type second cladding layer is formed such that, for example, it is about ±10% of the AlN ratio of the n-type semiconductor layer 24. The p-type second cladding layer has a thickness of 5 nm to 250 nm, for example, 10 nm to 150 nm. Note that the p-type second cladding layer is not required, and the p-type cladding layer may consist only of the p-type first cladding layer.

[0028] The p-type contact layer is a p-type AlGaN layer or p-type GaN layer with a relatively low AlN ratio. The p-type contact layer is configured to have an AlN ratio of 20% or less in order to obtain good ohmic contact with the p-side contact electrode 30, and is preferably formed to have an AlN ratio of 10% or less, 5% or less, or 0%. In other words, the p-type contact layer can be formed from a p-type GaN-based semiconductor material that is substantially free of AlN. As a result, the p-type contact layer can absorb deep ultraviolet light emitted by the active layer 26. It is preferable that the p-type contact layer be formed thinly in order to reduce the amount of deep ultraviolet light absorbed by the active layer 26. The p-type contact layer has a thickness of 5 nm to 30 nm, for example, 10 nm to 20 nm.

[0029] The p-side contact electrode 30 is provided on the upper surface 28a of the p-type semiconductor layer 28. The p-side contact electrode 30 comprises a conductive oxide material that can make ohmic contact with the p-type semiconductor layer 28 (e.g., the p-type contact layer). The p-side contact electrode 30 is composed of a transparent conductive oxide (TCO) such as zinc oxide (ZnO), magnesium zinc oxide (MgZnO), tin oxide (SnO2), or indium tin oxide (ITO). The thickness of the conductive oxide material of the p-side contact electrode 30 is, for example, 50 nm or more, 100 nm or more, or 150 nm or more, and for example, 500 nm or less, 300 nm or less, or 200 nm or less.

[0030] The n-side contact electrode 32 is provided on the second upper surface 24b of the n-type semiconductor layer 24. The n-side contact electrode 32 includes a first Ti layer, an Al layer, a second Ti layer, and a TiN layer that are stacked in order. Details of the configuration of the n-side contact electrode 32 will be described separately with reference to Figure 3.

[0031] The p-side current diffusion layer 34 is provided on the p-side contact electrode 30. The p-side current diffusion layer 34 is in contact with the p-side contact electrode 30 and may cover the entire p-side contact electrode 30. The p-side current diffusion layer 34 includes a lower TiN layer, an intermediate layer, and an upper TiN layer. The lower TiN layer of the p-side current diffusion layer 34 is in contact with the conductive oxide material of the p-side contact electrode 30. The upper TiN layer of the p-side current diffusion layer 34 is in contact with the dielectric material of the first protective layer 38. The p-side current diffusion layer 34 has a p-side connection opening 34a in which the upper TiN layer is partially removed and the intermediate layer is exposed. Details of the configuration of the p-side current diffusion layer 34 will be described separately with reference to Figure 2.

[0032] The n-side current diffusion layer 36 is provided on the n-side contact electrode 32. The n-side current diffusion layer 36 may be in contact with the n-side contact electrode 32 and may cover the entire n-side contact electrode 32. The n-side current diffusion layer 36 may have a similar configuration to the p-side current diffusion layer 34 and include a lower TiN layer, an intermediate layer, and an upper TiN layer. The lower TiN layer of the n-side current diffusion layer 36 is in contact with the n-side contact electrode 32. The upper TiN layer of the n-side current diffusion layer 36 is in contact with the dielectric material of the first protective layer 38. The n-side current diffusion layer 36 has an n-side connection opening 36a in which the upper TiN layer is partially removed and the intermediate layer is exposed. Details of the configuration of the n-side current diffusion layer 36 will be described separately with reference to Figure 3.

[0033] The first protective layer 38 is provided to cover the entire upper part of the element. The first protective layer 38 covers the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, the p-side current diffusion layer 34, and the n-side current diffusion layer 36. The first protective layer 38 has a first p-side pad opening 38p provided on the p-side current diffusion layer 34 and a first n-side pad opening 38n provided on the n-side current diffusion layer 36. The first protective layer 38 covers the p-side current diffusion layer 34 at a location different from the first p-side pad opening 38p and covers the n-side current diffusion layer 36 at a location different from the first n-side pad opening 38n. The first protective layer 38 is in contact with the base layer 22 on the outer periphery of the n-type semiconductor layer 24. The first protective layer 38 is in contact with the upper surface 22a of the base layer 22, the second upper surface 24b and side surface 24c of the n-type semiconductor layer 24, the side surface 26b of the active layer 26, the upper surface 28a and side surface 28b of the p-type semiconductor layer 28, the p-side current diffusion layer 34, and the n-side current diffusion layer 36.

[0034] The first protective layer 38 is composed of an oxide dielectric material such as silicon oxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO2). Preferably, the first protective layer 38 is composed of SiO2. The thickness of the first protective layer 38 is 300 nm to 1500 nm, for example, 600 nm to 1000 nm.

[0035] The second protective layer 40 is provided to cover the entire upper part of the element and to cover the entire surface of the first protective layer 38. The second protective layer 40 has a second p-side pad opening 40p provided on the p-side current diffusion layer 34 and a second n-side pad opening 40n provided on the n-side current diffusion layer 36. The second protective layer 40 covers the first protective layer 38 at locations different from the second p-side pad opening 40p and the second n-side pad opening 40n. The second protective layer 40 is also provided inside the first p-side pad opening 38p and the first n-side pad opening 38n, respectively. The second protective layer 40 covers the inner circumferential surface 38a of the first protective layer 38 that defines the first p-side pad opening 38p and covers the inner circumferential surface 38b of the first protective layer 38 that defines the first n-side pad opening 38n. The second protective layer 40 is in contact with the base layer 22 on the outer circumference of the first protective layer 38. The second protective layer 40 is in contact with the upper surface 22a of the base layer 22, the inner circumferential surfaces 38a and 38b of the first protective layer 38, the upper surface 34b of the p-side current diffusion layer 34, and the upper surface 36b of the n-side current diffusion layer 36.

[0036] The second protective layer 40 is made of silicon nitride (SiN), a dielectric material with excellent moisture resistance. x It consists of the following. The thickness of the second protective layer 40 is 50 nm or more and 500 nm or less, for example, 100 nm or more and 400 nm or less.

[0037] The p-side pad electrode 42 and the n-side pad electrode 44 are the parts that are joined when the semiconductor light-emitting element 10 is mounted on a submount or the like. The p-side pad electrode 42 and the n-side pad electrode 44 include, for example, a Ni / Au or Ti / Au stacked structure. The p-side pad electrode 42 and the n-side pad electrode 44 may be configured so as not to contain platinum group elements such as ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and platinum (Pt). The thickness of the p-side pad electrode 42 and the n-side pad electrode 44 is 100 nm or more, for example, 200 nm to 1000 nm.

[0038] The p-side pad electrode 42 is provided on the p-side current diffusion layer 34 and contacts the upper surface 34b of the p-side current diffusion layer 34 at the second p-side pad opening 40p. The p-side pad electrode 42 contacts the intermediate layer of the p-side current diffusion layer 34 at the p-side connection opening 34a. The p-side pad electrode 42 is electrically connected to the p-side contact electrode 30 via the p-side current diffusion layer 34. The p-side pad electrode 42 is provided so as to close the second p-side pad opening 40p and is provided on the second protective layer 40 outside the second p-side pad opening 40p.

[0039] The n-side pad electrode 44 is provided on the n-side current diffusion layer 36 and contacts the upper surface 36b of the n-side current diffusion layer 36 at the second n-side pad opening 40n. The n-side pad electrode 44 contacts the intermediate layer of the n-side current diffusion layer 36 at the n-side connection opening 36a. The n-side pad electrode 44 is electrically connected to the n-side contact electrode 32 via the n-side current diffusion layer 36. The n-side pad electrode 44 is provided so as to close the second n-side pad opening 40n and is provided on the second protective layer 40 outside the second n-side pad opening 40n.

[0040] The p-side junction layer 46 and the n-side junction layer 48 are junction layers for bonding the semiconductor light-emitting element 10 to the submount. The p-side junction layer 46 and the n-side junction layer 48 include, for example, Au and Sn. The p-side junction layer 46 and the n-side junction layer 48 may include AuSn, which is a mixed crystal of Au and Sn, or they may include a stacked structure of Au layers and Sn layers.

[0041] Figure 2 schematically shows the configuration of the p-side contact electrode 30, the p-side current diffusion layer 34, and the p-side pad electrode 42. The p-side current diffusion layer 34 includes a lower TiN layer 50, an intermediate layer 52, and an upper TiN layer 54. The p-side pad electrode 42 includes an adhesive layer 42a made of Ni or Ti and an Au layer 42b.

[0042] The lower TiN layer 50 of the p-side current diffusion layer 34 is in contact with the p-side contact electrode 30. The thickness of the lower TiN layer 50 of the p-side current diffusion layer 34 is between 10 nm and 200 nm, for example, between 20 nm and 150 nm.

[0043] The intermediate layer 52 of the p-side current diffusion layer 34 is provided on the lower TiN layer 50. The intermediate layer 52 of the p-side current diffusion layer 34 includes a laminated film in which multiple intermediate TiN layers 56a to 56c and multiple metal layers 58a to 58c are alternately stacked. The intermediate TiN layers 56a to 56c are made of conductive TiN. The thickness of each intermediate TiN layer 56a to 56c is 10 nm to 200 nm, for example, 50 nm to 150 nm. The metal layers 58a to 58c are made of, for example, Rh. The thickness of each metal layer 58a to 58c is 10 nm to 200 nm, for example, 20 nm to 150 nm. In a modified example, multiple Ti layers may be provided instead of multiple intermediate TiN layers 56a to 56c. In this case, the intermediate layer 52 of the p-side current diffusion layer 34 may include a laminated film in which multiple Ti layers and multiple Rh layers are alternately stacked.

[0044] The upper TiN layer 54 of the p-side current diffusion layer 34 is provided on top of the intermediate layer 52. The upper TiN layer 54 is in contact with the metal layer 58c that constitutes the uppermost layer of the intermediate layer 52. The upper TiN layer 54 is made of conductive TiN. The thickness of the upper TiN layer 54 is 10 nm to 200 nm, for example, 50 nm to 150 nm. The upper TiN layer 54 has a p-side connection opening 34a that exposes the metal layer 58c of the uppermost layer of the intermediate layer 52. The p-side connection opening 34a is provided in a position that communicates with the first p-side pad opening 38p.

[0045] The lower TiN layer 50 of the p-side current diffusion layer 34 is composed of titanium nitride having a film quality that provides high adhesion to conductive oxide materials, and is composed of titanium nitride that is yellow or golden in color. On the other hand, the upper TiN layer 54 of the p-side current diffusion layer 34 is composed of titanium nitride having a film quality that provides high adhesion to dielectric materials, and is composed of titanium nitride that is white or gray in color. The upper TiN layer 54 has a lower saturation than the lower TiN layer 50 and is composed of titanium nitride having a film quality that is closer to metallic titanium. When the TiN film is produced by reactive sputtering, the film quality can be controlled by the flow rate of nitrogen gas, which is the reactive gas. For example, by increasing the flow rate of nitrogen gas, titanium nitride with a film quality that provides high adhesion to conductive oxide materials can be produced for the lower TiN layer 50. By decreasing the flow rate of nitrogen gas, titanium nitride with a film quality that provides high adhesion to dielectric materials can be produced for the upper TiN layer 54. The conditions for depositing titanium nitride will be described separately with reference to Figure 4.

[0046] The intermediate TiN layers 56a to 56c of the p-side current diffusion layer 34 may be composed of titanium nitride having a yellow or golden color similar to the lower TiN layer 50, or they may be composed of titanium nitride having a white or gray color similar to the upper TiN layer 54. For example, by using titanium nitride having a yellow or golden color as at least one of the intermediate TiN layers 56a to 56c, the barrier properties of the intermediate layer 52 can be improved. For example, by using titanium nitride having a white or gray color as at least one of the intermediate TiN layers 56a to 56c, adhesion to the dielectric material can be improved, and the sealing performance of the first protective layer 38 can be improved. For example, titanium nitride having a white or gray color can be used as the bottommost intermediate TiN layer 56a of the intermediate layer 52 (for example, the intermediate TiN layer 56a that contacts the lower TiN layer 50). In this case, the remaining intermediate TiN layers 56b and 56c may be composed of titanium nitride having a white or gray color, or they may be composed of titanium nitride having a white or gray color.

[0047] The first protective layer 38 is provided on the p-side current diffusion layer 34 outside the p-side connection opening 34a. The first protective layer 38 is in contact with the upper TiN layer 54 of the p-side current diffusion layer 34. The first protective layer 38 is not provided inside the p-side connection opening 34a and is not in contact with the upper surface 34b of the p-side current diffusion layer 34 that is exposed at the p-side connection opening 34a. The first protective layer 38 is in contact with the side of the p-side current diffusion layer 34 on its outer circumference. The first protective layer 38 is in contact with the lower TiN layer 50, the intermediate layer 52 (for example, a plurality of intermediate TiN layers 56a to 56c and a plurality of metal layers 58a to 58c) and the upper TiN layer 54 on its outer circumference.

[0048] The second protective layer 40 is in contact with the inner circumferential surface 38a of the first protective layer 38 that defines the first p-side pad opening 38p. The second protective layer 40 is in contact with the inner circumferential surface 34c of the p-side current diffusion layer 34 that defines the p-side connection opening 34a. The second protective layer 40 is in contact with the upper surface 34b (i.e., the metal layer 58c) of the p-side current diffusion layer 34 that is exposed inside the p-side connection opening 34a.

[0049] The adhesive layer 42a of the p-side pad electrode 42 is in contact with the p-side current diffusion layer 34 inside the second p-side pad opening 40p. The adhesive layer 42a of the p-side pad electrode 42 is in contact with the metal layer 58c that constitutes the uppermost layer of the intermediate layer 52. The adhesive layer 42a of the p-side pad electrode 42 is not in contact with the upper TiN layer 54 of the p-side current diffusion layer 34. The adhesive layer 42a of the p-side pad electrode 42 is not in contact with the first protective layer 38. The Au layer 42b of the p-side pad electrode 42 is provided on top of the adhesive layer 42a. The p-side bonding layer 46 (not shown in Figure 2) is provided on top of the Au layer 42b of the p-side pad electrode 42.

[0050] Figure 3 schematically shows the configuration of the n-side contact electrode 32, the n-side current diffusion layer 36, and the n-side pad electrode 44. The n-side contact electrode 32 includes a first Ti layer 60, an Al layer 62, a second Ti layer 64, and a TiN layer 66. The n-side current diffusion layer 36 includes a lower TiN layer 70, an intermediate layer 72, and an upper TiN layer 74. The n-side pad electrode 44 includes an adhesive layer 44a made of Ni or Ti and an Au layer 44b.

[0051] The lower TiN layer 70 of the n-side current diffusion layer 36 is in contact with the TiN layer 66 of the n-side contact electrode 32. The thickness of the lower TiN layer 70 of the n-side current diffusion layer 36 is between 10 nm and 200 nm, for example, between 20 nm and 150 nm.

[0052] The intermediate layer 72 of the n-side current diffusion layer 36 is provided on the lower TiN layer 70. The intermediate layer 72 of the n-side current diffusion layer 36 includes a laminated film in which multiple intermediate TiN layers 76a to 76c and multiple metal layers 78a to 78c are alternately stacked. The intermediate TiN layers 76a to 76c are made of conductive TiN. The thickness of each intermediate TiN layer 76a to 76c is 10 nm to 200 nm, for example, 50 nm to 150 nm. The metal layers 78a to 78c are made of, for example, Rh. The thickness of each metal layer 78a to 78c is 10 nm to 200 nm, for example, 20 nm to 150 nm. In a modified example, multiple Ti layers may be provided instead of multiple intermediate TiN layers 76a to 76c. In this case, the intermediate layer 72 of the n-side current diffusion layer 36 may include a laminated film in which multiple Ti layers and multiple Rh layers are alternately stacked.

[0053] The upper TiN layer 74 of the n-side current diffusion layer 36 is provided on top of the intermediate layer 72. The upper TiN layer 74 is in contact with the metal layer 78c that constitutes the uppermost layer of the intermediate layer 72. The upper TiN layer 74 is made of conductive TiN. The thickness of the upper TiN layer 74 is 10 nm to 200 nm, for example, 50 nm to 150 nm. The upper TiN layer 74 has an n-side connection opening 36a that exposes the metal layer 78c of the uppermost layer of the intermediate layer 72. The n-side connection opening 36a is provided in a position that communicates with the first n-side pad opening 38n.

[0054] The TiN layer 66 of the n-side contact electrode 32 and the lower TiN layer 70 of the n-side current diffusion layer 36 are made of titanium nitride having a high barrier film quality and are composed of titanium nitride having a yellow or golden color. On the other hand, the upper TiN layer 74 of the n-side current diffusion layer 36 is made of titanium nitride having a film quality with high adhesion to the dielectric material and is composed of titanium nitride having a white or gray color. The upper TiN layer 74 has a lower saturation than the lower TiN layer 70 and is made of titanium nitride having a film quality relatively close to that of metallic titanium. The film deposition conditions for titanium nitride will be described separately with reference to Figure 4.

[0055] The intermediate TiN layers 76a to 76c of the n-side current diffusion layer 36 may be composed of titanium nitride having a yellow or golden color similar to the lower TiN layer 70, or of titanium nitride having a white or gray color similar to the upper TiN layer 74. For example, by using titanium nitride having a yellow or golden color as at least one of the intermediate TiN layers 76a to 76c, the barrier properties of the intermediate layer 72 can be improved. For example, by using titanium nitride having a white or gray color as at least one of the intermediate TiN layers 76a to 76c, adhesion to the dielectric material can be improved, and the sealing performance of the first protective layer 38 can be improved. For example, titanium nitride having a white or gray color can be used as the bottommost intermediate TiN layer 76a of the intermediate layer 72 (for example, the intermediate TiN layer 76a that contacts the lower TiN layer 70). In this case, the remaining intermediate TiN layers 76b and 76c may be composed of titanium nitride having a white or gray color, or of titanium nitride having a white or gray color.

[0056] The first protective layer 38 is provided on the n-side current diffusion layer 36 outside the n-side connection opening 36a. The first protective layer 38 is in contact with the upper TiN layer 74 of the n-side current diffusion layer 36. The first protective layer 38 is not provided inside the n-side connection opening 36a and is not in contact with the upper surface 36b of the n-side current diffusion layer 36 that is exposed at the n-side connection opening 36a. The first protective layer 38 is in contact with the side of the n-side current diffusion layer 36 on its outer circumference. The first protective layer 38 is in contact with the lower TiN layer 70, the intermediate layer 72 (for example, a plurality of intermediate TiN layers 76a to 76c and a plurality of metal layers 78a to 78c) and the upper TiN layer 74 on the outer circumference of the n-side current diffusion layer 36.

[0057] The second protective layer 40 is in contact with the inner circumferential surface 38b of the first protective layer 38 that defines the first n-side pad opening 38n. The second protective layer 40 is in contact with the inner circumferential surface 36c of the n-side current diffusion layer 36 that defines the n-side connection opening 36a. The second protective layer 40 is in contact with the upper surface 36b (i.e., the metal layer 78c) of the n-side current diffusion layer 36 that is exposed inside the n-side connection opening 36a.

[0058] The adhesive layer 44a of the n-side pad electrode 44 is in contact with the n-side current diffusion layer 36 inside the second n-side pad opening 40n. The adhesive layer 44a of the n-side pad electrode 44 is in contact with the metal layer 78c that constitutes the uppermost layer of the intermediate layer 72. The adhesive layer 44a of the n-side pad electrode 44 is not in contact with the upper TiN layer 74 of the n-side current diffusion layer 36. The adhesive layer 44a of the n-side pad electrode 44 is not in contact with the first protective layer 38. The Au layer 44b of the n-side pad electrode 44 is provided on top of the adhesive layer 44a. The n-side bonding layer 48 (not shown in Figure 3) is provided on top of the Au layer 44b of the n-side pad electrode 44.

[0059] Figure 4 is a graph showing an example of titanium nitride film deposition conditions. Figure 4 shows the conditions for depositing titanium nitride by reactive sputtering, using metallic titanium as the target material, nitrogen (N2) as the reactive gas, and argon (Ar) as the non-reactive gas. Figure 4 shows the deposition rate when the nitrogen gas flow rate is varied while the total flow rate of nitrogen and argon gas is fixed at 90 sccm. As shown in Figure 4, increasing the nitrogen gas flow rate tends to decrease the deposition rate. Furthermore, comparing the first region A1, where the nitrogen gas flow rate is 7 sccm or less, and the second region A2, where the nitrogen gas flow rate is 8 sccm or more, the slope of the change in deposition rate with respect to nitrogen gas flow rate is different. This is thought to be because in the first region A1, titanium-rich TiN, which has a film quality similar to metallic titanium, is deposited, while in the second region A2, titanium-poor TiN, which has a film quality far removed from metallic titanium, is deposited. The TiN deposited in the first region A1 has a white or gray color, with a faint yellow tint, and a relatively low saturation color. On the other hand, the TiN deposited in the second region A2 has a yellow or golden color, with a deep yellow hue and relatively high saturation. As the nitrogen gas flow rate increases, the yellow color of the deposited TiN tends to become deeper and the saturation higher.

[0060] Figure 5 is a graph showing an example of RGB measurement values ​​for titanium nitride. Figure 5 shows RGB measurement values ​​for TiN deposited under the same deposition conditions as in Figure 4. RGB measurement values ​​are expressed as values ​​between 0 and 255, representing the red (R), green (G), and blue (B) values ​​measured using the international standard RGB (sRGB). As shown in Figure 5, in the first region A1, where the nitrogen gas flow rate is 7 sccm or less, the difference between the R, G, and B values ​​is small, indicating a color close to white or gray with low saturation. On the other hand, in the second region A2, where the nitrogen gas flow rate is 8 sccm or more, the difference between the R, G, and B values ​​is large, indicating a color close to yellow with a relatively large R value and a relatively small B value. Saturation is proportional to the difference between the maximum and minimum values ​​of the R, G, and B values. Therefore, by using the difference between the maximum value (R value) and the minimum value (B value) (i.e., R value - B value), the saturation of TiN can be evaluated, and the film quality of TiN can be evaluated based on its saturation.

[0061] Figure 6 is a table showing an example of RGB measurement values ​​and sealing performance of the upper TiN layer. Figure 6 evaluates the sealing performance of the semiconductor light-emitting element 10 shown in Figure 1 when the film quality of the upper TiN layer 54 above the p-side current diffusion layer 34 and the upper TiN layer 74 above the n-side current diffusion layer 36 is changed. Sealing performance is evaluated by the length of the lifespan when the semiconductor light-emitting element 10 is energized and used. If the lifespan is above a predetermined standard value, it is considered OK, and if it is below the predetermined standard value, it is considered NG. As shown in Figure 6, in Examples 1 to 4, where the RB (the difference between the R value and the B value) is less than 25, the sealing performance is OK, whereas in Comparative Examples 1 to 4, where the RB is 25 or more, the sealing performance is NG. This is thought to be because when titanium-rich TiN is deposited in the first region A1, the adhesion between the upper TiN layers 54 and 78 and the first protective layer 38 increases, improving the sealing performance. Therefore, by using titanium nitride with a difference of less than 25 between the R value and B value as the upper TiN layers 54 and 74 of the semiconductor light-emitting element 10, the sealing properties of the semiconductor light-emitting element 10 can be improved, and the reliability of the semiconductor light-emitting element 10 can be enhanced.

[0062] Figure 7 is a table showing an example of RGB measurement values ​​and adhesion of the lower TiN layer. Figure 7 evaluates the electrode adhesion when the film quality of the lower TiN layer 50 below the p-side current diffusion layer 34 is changed in the semiconductor light-emitting element 10 shown in Figure 1. Adhesion is evaluated by visual inspection of the semiconductor light-emitting element 10 to see if delamination of the p-side current diffusion layer 34 from the p-side contact electrode 30 has occurred. If no delamination has occurred, it is considered OK, and if delamination has occurred at least partially, it is considered NG. As shown in Figure 7, in the embodiment where RB, the difference between the R value and the B value, is less than 25, the electrode adhesion is OK, whereas in the comparative example where RB is 25 or more, the electrode adhesion is NG. This is thought to be because when titanium-poor TiN is deposited in the second region A2, the adhesion between the conductive oxide material of the p-side contact electrode 30 and the lower TiN layer 50 increases, suppressing electrode delamination. Therefore, by using titanium nitride with a difference of less than 25 between the R value and B value as the lower TiN layer 50 of the semiconductor light-emitting element 10, electrode peeling in the semiconductor light-emitting element 10 can be suppressed, and the reliability of the semiconductor light-emitting element 10 can be improved.

[0063] As shown in the evaluation results in Figure 6, titanium-rich TiN deposited under the conditions of the first region A1 is preferable to improve adhesion with dielectric materials. On the other hand, as shown in the evaluation results in Figure 7, titanium-poor TiN deposited under the conditions of the second region A2 is preferable to improve adhesion with conductive oxides. In this way, by controlling the film quality of the TiN layer according to the material in contact with the TiN layer, the adhesion of the TiN layer can be improved, and the reliability of the semiconductor light-emitting element 10 can be improved.

[0064] Next, the manufacturing method of the semiconductor light-emitting element 10 will be described. Figures 8 to 15 are schematic diagrams showing the manufacturing process of the semiconductor light-emitting element 10. First, in Figure 8, a base layer 22, an n-type semiconductor layer 24, an active layer 26, and a p-type semiconductor layer 28 are formed in order on the first main surface 20a of the substrate 20.

[0065] The substrate 20 is, for example, a patterned sapphire substrate. The base layer 22 includes, for example, an HT-AlN layer and an undoped AlGaN layer. The n-type semiconductor layer 24, the active layer 26, and the p-type semiconductor layer 28 are semiconductor layers composed of AlGaN-based semiconductor material, AlN-based semiconductor material, or GaN-based semiconductor material, and can be formed using well-known epitaxial growth methods such as metal-organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE).

[0066] Next, as shown in Figure 8, a mask 80 is formed on the upper surface 28a of the p-type semiconductor layer 28, for example, using a known lithography technique. With the mask 80 formed, the p-type semiconductor layer 28 and the active layer 26 in areas not overlapping with the mask 80 are removed by dry etching or the like, exposing the second upper surface 24b of the n-type semiconductor layer 24. This etching process forms the side surface 28b of the p-type semiconductor layer 28, the side surface 26b of the active layer 26, and the second upper surface 24b of the n-type semiconductor layer 24. After that, the mask 80 is removed.

[0067] Next, as shown in Figure 9, a p-side contact electrode 30 is formed on the upper surface 28a of the p-type semiconductor layer 28, for example, using a known lithography technique. The p-side contact electrode 30 is made of a conductive oxide material (e.g., ITO) that is in direct contact with the upper surface 28a of the p-type semiconductor layer 28. The p-side contact electrode 30 is formed, for example, by a vapor deposition method. The p-side contact electrode 30 may include a first electrode layer formed by a vapor deposition method and a second electrode layer formed by a sputtering method. First, a first electrode layer made of a conductive oxide material can be formed, and then a second electrode layer made of a conductive oxide material can be formed on the first electrode layer. When a vapor deposition method and a sputtering method are combined, both the contact resistance and resistivity of the p-side contact electrode 30 can be reduced, and the characteristics of the p-side contact electrode 30 can be improved.

[0068] After the p-side contact electrode 30 is formed, the p-side contact electrode 30 is annealed. The p-side contact electrode 30 is annealed at a temperature of 500°C to 650°C, for example, using the RTA (Rapid Thermal Annealing) method. The annealing treatment of the p-side contact electrode 30 reduces the contact resistance of the p-side contact electrode 30.

[0069] Next, as shown in Figure 9, an n-side contact electrode 32 is formed on the second upper surface 24b of the n-type semiconductor layer 24, for example, using a known lithography technique. The n-side contact electrode 32 includes a first Ti layer 60, an Al layer 62, a second Ti layer 64, and a TiN layer 66 (see Figure 3) that are stacked in order and in contact with the second upper surface 24b of the n-type semiconductor layer 24. The first Ti layer 60, Al layer 62, second Ti layer 64, and TiN layer 66 constituting the n-side contact electrode 32 are formed by sputtering. The TiN layer 66 may be titanium-poor TiN with a difference of 25 or more between its R value and B value. The TiN layer 66 can be formed, for example, under deposition conditions where the nitrogen gas flow rate is 8 sccm or more (e.g., 10 sccm). The TiN layer 66 can be formed, for example, under deposition conditions where the nitrogen gas flow rate ratio to argon gas is 9% or more, 10% or more, or 12% or more.

[0070] After the formation of the n-side contact electrode 32, the n-side contact electrode 32 is annealed. The n-side contact electrode 32 is annealed at a temperature of 500°C to 650°C, for example, using the RTA method. The annealing treatment of the n-side contact electrode 32 reduces the contact resistance of the n-side contact electrode 32.

[0071] Next, as shown in Figure 10, a p-side current diffusion layer 34 is formed on the p-side contact electrode 30 and an n-side current diffusion layer 36 is formed on the n-side contact electrode 32, for example, using a known lithography technique. The p-side current diffusion layer 34 and the n-side current diffusion layer 36 each include a lower TiN layer, an intermediate layer, and an upper TiN layer. The intermediate layer may include a laminated film in which multiple intermediate TiN layers and multiple metal layers are alternately stacked. The p-side current diffusion layer 34 and the n-side current diffusion layer 36 can be formed by sputtering. Note that the p-side current diffusion layer 34 and the n-side current diffusion layer 36 may be formed separately.

[0072] The lower TiN layer of the p-side current diffusion layer 34 and the n-side current diffusion layer 36 is composed of titanium-poor TiN with a difference of 25 or more between the R value and the B value, and can be formed, for example, under deposition conditions where the nitrogen gas flow rate is 8 sccm or more (e.g., 10 sccm). The lower TiN layer can be formed, for example, under deposition conditions where the nitrogen gas flow rate ratio to argon gas is 9% or more, 10% or more, or 12% or more.

[0073] The upper TiN layer of the p-side current diffusion layer 34 and the n-side current diffusion layer 36 is composed of titanium-rich TiN in which the difference between the R value and the B value is less than 25 (for example, 20 or less, 15 or less, 10 or less, or 5 or less), and can be formed under deposition conditions where the nitrogen gas flow rate is 7 sccm or less (for example, 5 sccm). The upper TiN layer can be formed, for example, under deposition conditions where the nitrogen gas flow rate ratio to argon gas is 8% or less, 7% or less, or 6% or less.

[0074] At least one of the multiple intermediate TiN layers in the p-side current diffusion layer 34 and the n-side current diffusion layer 36 is composed of titanium-rich TiN with a difference of less than 25 between the R value and the B value (e.g., 20 or less, 15 or less, 10 or less, or 5 or less), and can be formed under deposition conditions where the nitrogen gas flow rate is 7 sccm or less (e.g., 5 sccm). At least one of the multiple intermediate TiN layers can be formed under deposition conditions where, for example, the nitrogen gas flow rate ratio to argon gas is 8% or less, 7% or less, or 6% or less.

[0075] At least one of the multiple intermediate TiN layers of the p-side current diffusion layer 34 and the n-side current diffusion layer 36 may be composed of titanium-poor TiN with a difference of 25 or more between its R-value and B-value, and may be formed, for example, under deposition conditions where the nitrogen gas flow rate is 8 sccm or more (e.g., 10 sccm). At least one of the multiple intermediate TiN layers may be formed, for example, under deposition conditions where the nitrogen gas flow rate ratio to argon gas is 9% or more, 10% or more, or 12% or more.

[0076] Next, as shown in Figure 11, a mask 82 is formed on the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, the p-side current diffusion layer 34, and the n-side current diffusion layer 36, for example, using known lithography techniques. With the mask 82 formed, the n-type semiconductor layer 24 in the region that does not overlap with the mask 82 is removed by dry etching or the like, exposing the upper surface 22a of the base layer 22. This etching process forms the side surface 24c of the n-type semiconductor layer 24. After that, the mask 82 is removed.

[0077] Next, as shown in Figure 12, a first protective layer 38 is formed to cover the entire upper part of the element. The first protective layer 38 can be made of SiO2 and can be formed using the Plasma Enhanced Chemical Vapor Deposition (PECVD) method. The first protective layer 38 is formed to be in contact with the upper surface 22a of the base layer 22, the second upper surface 24b and side surface 24c of the n-type semiconductor layer 24, the side surface 26c of the active layer 26, the upper surface 28a and side surface 28c of the p-type semiconductor layer 28, the p-side current diffusion layer 34, and the n-side current diffusion layer 36. The first protective layer 38 may be in contact with the upper TiN layer above the p-side current diffusion layer 34 and the n-side current diffusion layer 36. The first protective layer 38 may be in contact with at least one of a plurality of intermediate TiN layers constituting the intermediate layer at the side (or outer periphery) of the p-side current diffusion layer 34 and the n-side current diffusion layer 36.

[0078] Next, as shown in Figure 13, a mask 84 is formed on the first protective layer 38 using, for example, a known lithography technique. The mask 84 is formed excluding the formation area W1p for the first p-side pad opening 38p, the formation area W1n for the first n-side pad opening 38n, and the first outer peripheral area W1a that exposes the upper surface 22a of the base layer 22. With the mask 84 formed, the first protective layer 38 in the area that does not overlap with the mask 84 is removed by dry etching. By removing the first protective layer 38 on the p-side current diffusion layer 34, the first p-side pad opening 38p is formed, exposing the p-side current diffusion layer 34. By removing the first protective layer 38 on the n-side current diffusion layer 36, the first n-side pad opening 38n is formed, exposing the n-side current diffusion layer 36. Also, by removing the outer peripheral portion of the first protective layer 38 in the first outer peripheral area W1a, the upper surface 22a of the base layer 22 is exposed.

[0079] As shown in Figure 13, in the formation range W1p of the first p-side pad opening 38p, the upper TiN layer 54 of the p-side current diffusion layer 34 is removed by dry etching, and a p-side connection opening 34a is formed, exposing the uppermost metal layer 58c. Similarly, in the formation range W1n of the first n-side pad opening 38n, the upper TiN layer 74 of the n-side current diffusion layer 36 is removed by dry etching, exposing the uppermost metal layer 78c, and an n-side connection opening 36a is formed. After that, the mask 84 is removed.

[0080] Next, as shown in Figure 14, a second protective layer 40 is formed to cover the entire upper part of the element. The second protective layer 40 is made of SiN xIt can be composed of the above and can be formed using the PECVD method. The second protective layer 40 is formed so as to be in contact with the upper surface 22a of the base layer 22 and the surface of the first protective layer 38. At the first p-side pad opening 38p, the second protective layer 40 is in contact with the inner circumferential surface 38a of the first protective layer 38 that defines the first p-side pad opening 38p. The second protective layer 40 is in contact with the inner circumferential surface 34c of the p-side current diffusion layer 34 (i.e., the upper TiN layer 54) that defines the p-side connection opening 34a, and is in contact with the upper surface 34b of the p-side current diffusion layer 34 at the p-side connection opening 34a. At the first n-side pad opening 38n, the second protective layer 40 is in contact with the inner circumferential surface 38b of the first protective layer 38 that defines the first n-side pad opening 38n. The second protective layer 40 is in contact with the inner circumferential surface 36c of the n-side current diffusion layer 36 (i.e., the upper TiN layer 74) that defines the n-side connection opening 36a, and is in contact with the upper surface 36b of the n-side current diffusion layer 36 at the n-side connection opening 36a.

[0081] Next, as shown in Figure 15, a mask 86 is formed on the second protective layer 40 using, for example, a known lithography technique. The mask 86 is formed excluding the formation area W2p for the second p-side pad opening 40p, the formation area W2n for the second n-side pad opening 40n, and the second outer peripheral area W2a that exposes the upper surface 22a of the base layer 22. With the mask 86 formed, the second protective layer 40 in areas that do not overlap with the mask 86 is removed by dry etching or the like. By removing the second protective layer 40 on the p-side current diffusion layer 34, a second p-side pad opening 40p is formed, exposing the upper surface 34b of the p-side current diffusion layer 34. By removing the second protective layer 40 on the n-side current diffusion layer 36, a second n-side pad opening 40n is formed, exposing the upper surface 36b of the n-side current diffusion layer 36. Furthermore, by removing the outer peripheral portion of the second protective layer 40 in the second outer peripheral area W2a, the upper surface 22a of the base layer 22 is exposed. The second outer peripheral region W2a becomes an element isolation region for separating the elements by cutting the substrate 20 and the base layer 22. After that, the mask 86 is removed.

[0082] Next, as shown in Figure 1, a p-side pad electrode 42 is formed at the second p-side pad opening 40p, connecting to the p-side current diffusion layer 34, and an n-side pad electrode 44 is formed at the second n-side pad opening 40n, connecting to the n-side current diffusion layer 36, using, for example, a known lithography technique. The p-side pad electrode 42 is formed so as to overlap the second protective layer 40 outside the second p-side pad opening 40p. The n-side pad electrode 44 is formed so as to overlap the second protective layer 40 outside the second n-side pad opening 40n. The p-side pad electrode 42 and the n-side pad electrode 44 can be formed simultaneously, but may also be formed separately. Next, a p-side bonding layer 46 is formed on the p-side pad electrode 42, and an n-side bonding layer 48 is formed on the n-side pad electrode 44, using, for example, a known lithography technique. The p-side bonding layer 46 and the n-side bonding layer 48 can be formed simultaneously, but may also be formed separately.

[0083] Through the above process, the semiconductor light-emitting element 10 shown in Figure 1 is produced.

[0084] According to this embodiment, by making the upper TiN layers 54 and 74 that come into contact with the first protective layer 38 out of titanium-rich titanium nitride, the adhesion with the first protective layer 38 can be improved, and the sealing performance of the semiconductor light-emitting element 10 can be enhanced. As a result, the lifespan of the semiconductor light-emitting element 10 during powered operation can be significantly increased.

[0085] According to this embodiment, by constructing the lower TiN layer 50 that contacts the conductive oxide material of the p-side contact electrode 30 with titanium-poor titanium nitride, adhesion to the p-side contact electrode 30 can be improved, and peeling of the p-side current diffusion layer 34 from the p-side contact electrode 30 can be suppressed. This improves the manufacturing yield of the semiconductor light-emitting element 10.

[0086] According to this embodiment, by making at least one of the intermediate TiN layers 56a-56c and 76a-76c that come into contact with the first protective layer 38 from titanium-rich titanium nitride, the adhesion with the first protective layer 38 can be improved, and the sealing performance of the semiconductor light-emitting element 10 can be enhanced. This further improves the lifespan of the semiconductor light-emitting element 10 when powered on.

[0087] The present invention has been described above based on embodiments. Those skilled in the art will understand that the present invention is not limited to the embodiments described above, that various design changes are possible, and that various modifications are possible, and that such modifications also fall within the scope of the present invention.

[0088] Several embodiments of the present invention will be described below.

[0089] A first aspect of the present invention comprises an n-type semiconductor layer, an active layer provided on the n-type semiconductor layer, a p-type semiconductor layer provided on the active layer, a contact electrode provided on the p-type semiconductor layer and comprising a conductive oxide material, a current diffusion layer provided on the contact electrode, and a protective layer provided on the current diffusion layer having a pad opening, covering the n-type semiconductor layer, the active layer, the p-type semiconductor layer and the current diffusion layer at locations different from the pad opening, and contacting the current diffusion layer at the pad opening, and the pad A semiconductor light-emitting element is provided, comprising: a pad electrode provided on the protective layer outside the opening; the current diffusion layer includes a lower TiN layer that contacts the conductive oxide material of the contact electrode; and an upper TiN layer that contacts the dielectric material of the protective layer; the lower TiN layer is made of titanium nitride in which the difference between the R value and the B value is 25 or more in an RGB measurement value expressed as a numerical value between 0 and 255; and the upper TiN layer is made of titanium nitride in which the difference between the R value and the B value is less than 25 in an RGB measurement value expressed as a numerical value between 0 and 255. According to the first embodiment, by bringing the lower TiN layer, which is made of titanium-poor titanium nitride in which the difference between the R value and the B value is 25 or more, into contact with the conductive oxide material, the adhesion between the contact electrode and the lower TiN layer can be improved, and peeling of the current diffusion layer from the contact electrode can be suppressed. Furthermore, by bringing the upper TiN layer, which is made of titanium-rich titanium nitride with a difference of less than 25 between its R-value and B-value, into contact with the protective layer, the adhesion between the upper TiN layer and the protective layer can be improved, thereby enhancing the sealing performance of the protective layer.

[0090] A second aspect of the present invention is a semiconductor light-emitting element according to the first aspect, wherein the current diffusion layer further includes a metal layer provided between the lower TiN layer and the upper TiN layer, and an intermediate TiN layer provided between the lower TiN layer and the metal layer, and the intermediate TiN layer is made of titanium nitride in which the difference between the R value and the B value is less than 25 in an RGB measurement value expressed as a numerical value between 0 and 255. According to the second aspect, the intermediate TiN layer made of titanium-rich titanium nitride can be brought into contact with the protective layer on the side or outer periphery of the current diffusion layer, thereby further improving the adhesion between the current diffusion layer and the protective layer.

[0091] A third aspect of the present invention is a semiconductor light-emitting element according to the second aspect, wherein the intermediate TiN layer is in contact with the lower TiN layer. According to the third aspect, the adhesion between the current diffusion layer and the protective layer can be improved in the vicinity of the lower TiN layer, and the sealing performance by the protective layer can be improved.

[0092] A fourth aspect of the present invention is a semiconductor light-emitting element according to the first aspect, wherein the current diffusion layer is provided between the lower TiN layer and the upper TiN layer and further comprises a laminated film in which a plurality of intermediate TiN layers and a plurality of metal layers are alternately stacked, and at least one of the plurality of intermediate TiN layers is made of titanium nitride in which the difference between the R value and the B value is less than 25 in an RGB measurement value expressed as a numerical value between 0 and 255. According to the fourth aspect, by making at least one of the plurality of intermediate TiN layers titanium-rich titanium nitride, the adhesion between the current diffusion layer and the protective layer can be improved, and the sealing performance by the protective layer can be improved.

[0093] A fifth aspect of the present invention is a semiconductor light-emitting element according to the first aspect, wherein the current diffusion layer is provided between the lower TiN layer and the upper TiN layer and further comprises a laminated film in which a plurality of intermediate TiN layers and a plurality of metal layers are alternately stacked, and at least one of the plurality of intermediate TiN layers is made of titanium nitride in which the difference between the R value and the B value is 25 or more in an RGB measurement value expressed as a numerical value between 0 and 255. According to the fifth aspect, by making at least one of the plurality of intermediate TiN layers titanium nitride which is titanium poor, the barrier properties of the current diffusion layer can be improved and the reliability of the semiconductor light-emitting element can be improved.

[0094] A sixth aspect of the present invention is a semiconductor light-emitting element according to any one of the first to fifth aspects, wherein the protective layer comprises a first protective layer made of silicon oxide that is in contact with the upper TiN layer, and a second protective layer made of silicon nitride that covers the first protective layer. According to the sixth aspect, by making the first protective layer that is in contact with the upper TiN layer out of silicon oxide, the adhesion between the upper TiN layer and the first protective layer can be improved, and the sealing performance of the protective layer can be improved. Furthermore, by covering the first protective layer with a second protective layer made of silicon nitride, the sealing performance of the protective layer can be improved, and the reliability of the semiconductor light-emitting element can be improved.

[0095] A seventh aspect of the present invention is a semiconductor light-emitting element according to any one of the second to fifth aspects, wherein the protective layer comprises a first protective layer made of silicon oxide that contacts the upper TiN layer and the intermediate TiN layer, and a second protective layer made of silicon nitride that covers the first protective layer. According to the seventh aspect, by making the first protective layer that contacts the upper TiN layer and the intermediate TiN layer out of silicon oxide, the adhesion between the upper TiN layer and the intermediate TiN layer and the first protective layer can be improved, and the sealing performance of the protective layer can be improved. Furthermore, by covering the first protective layer with a second protective layer made of silicon nitride, the sealing performance of the protective layer can be improved, and the reliability of the semiconductor light-emitting element can be improved.

[0096] An eighth aspect of the present invention is a semiconductor light-emitting element according to any one of the second to fifth aspects, wherein the metal layer includes an Rh layer. According to the eighth aspect, by inserting an Rh layer between the lower TiN layer and the upper TiN layer, the barrier properties of the current diffusion layer can be improved, and the reliability of the semiconductor light-emitting element can be improved.

[0097] A ninth aspect of the present invention is a step of forming an active layer on an n-type semiconductor layer, a step of forming a p-type semiconductor layer on the active layer, a step of forming a contact electrode comprising a conductive oxide material on the p-type semiconductor layer, a step of forming a current diffusion layer on the contact electrode, a step of forming a protective layer made of a dielectric material that covers the n-type semiconductor layer, the active layer, the p-type semiconductor layer and the current diffusion layer, a step of removing the protective layer on the current diffusion layer to form a pad opening, and contacting the current diffusion layer at the pad opening, and outside the pad opening, the protective A method for manufacturing a semiconductor light-emitting element, comprising the steps of forming a pad electrode provided on a protective layer, wherein the step of forming the current diffusion layer includes the steps of forming a lower TiN layer that contacts the conductive oxide material of the contact electrode, and forming an upper TiN layer that contacts the dielectric material of the protective layer, wherein the lower TiN layer is formed by reactive sputtering under the condition that the flow rate ratio of nitrogen gas to argon gas is 9% or more, and the upper TiN layer is formed by reactive sputtering under the condition that the flow rate ratio of nitrogen gas to argon gas is 8% or less. According to the ninth aspect, by bringing a lower TiN layer made of titanium-poor titanium nitride, formed under the condition that the flow rate ratio of nitrogen gas is 9% or more, into contact with the conductive oxide material, the adhesion between the contact electrode and the lower TiN layer can be improved and peeling of the current diffusion layer from the contact electrode can be suppressed. Furthermore, by bringing the upper TiN layer, which is made of titanium-rich titanium nitride formed under conditions where the nitrogen gas flow rate ratio is 8% or less, into contact with the protective layer, the adhesion between the upper TiN layer and the protective layer can be improved, thereby improving the sealing performance of the protective layer. [Explanation of Symbols]

[0098] 10... Semiconductor light-emitting element, 24... n-type semiconductor layer, 24a... first upper surface, 24b... second upper surface, 26... active layer, 28... p-type semiconductor layer, 30... p-side contact electrode, 32... n-side contact electrode, 34... p-side current diffusion layer, 36... n-side current diffusion layer, 38... first protective layer, 38a... inner surface, 38p... first p-side pad opening, 38n... first n-side pad opening, 40... second protective layer, 40p... second p-side pad opening, 40n... second n-side pad opening, 42... p-side pad electrode, 44... n-side pad electrode, 50, 70... lower TiN layer, 54, 74... upper TiN layer, 56a~56c, 76a~76c... intermediate TiN layer, 58a~58c, 78a~78c... metal layer.

Claims

1. n-type semiconductor layer, An active layer provided on the n-type semiconductor layer, A p-type semiconductor layer provided on the active layer, A contact electrode provided on the p-type semiconductor layer and comprising a conductive oxide material, A current diffusion layer provided on the contact electrode, A protective layer made of a dielectric material has a pad opening provided on the current diffusion layer, and covers the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current diffusion layer at locations different from the pad opening, The pad electrode is in contact with the current diffusion layer at the pad opening and is provided on the protective layer outside the pad opening. The current diffusion layer includes a lower TiN layer that contacts the conductive oxide material of the contact electrode and an upper TiN layer that contacts the dielectric material of the protective layer. The lower TiN layer is composed of titanium nitride in which the difference between the R value and the B value is 25 or more in an RGB measurement value expressed as a number between 0 and 255. The upper TiN layer is made of titanium nitride, in which the difference between the R value and the B value is less than 25 in an RGB measurement value expressed as a numerical value between 0 and 255. Semiconductor light-emitting element.

2. The current diffusion layer further includes a metal layer provided between the lower TiN layer and the upper TiN layer, and an intermediate TiN layer provided between the lower TiN layer and the metal layer, The aforementioned intermediate TiN layer is made of titanium nitride in which the difference between the R value and the B value is less than 25 in an RGB measurement value expressed as a number between 0 and 255. The semiconductor light-emitting element according to claim 1.

3. The aforementioned intermediate TiN layer is in contact with the aforementioned lower TiN layer. The semiconductor light-emitting element according to claim 2.

4. The current diffusion layer is provided between the lower TiN layer and the upper TiN layer, and further includes a laminated film in which a plurality of intermediate TiN layers and a plurality of metal layers are alternately stacked. At least one of the aforementioned intermediate TiN layers is made of titanium nitride, in which the difference between the R value and the B value is less than 25 in an RGB measurement value expressed as a numerical value between 0 and 255. The semiconductor light-emitting element according to claim 1.

5. The current diffusion layer is provided between the lower TiN layer and the upper TiN layer, and further includes a laminated film in which a plurality of intermediate TiN layers and a plurality of metal layers are alternately stacked. At least one of the aforementioned intermediate TiN layers is made of titanium nitride, in which the difference between the R value and the B value is 25 or more in an RGB measurement value expressed as a numerical value between 0 and 255. The semiconductor light-emitting element according to claim 1.

6. The protective layer comprises a first protective layer made of silicon oxide that is in contact with the upper TiN layer, and a second protective layer made of silicon nitride that covers the first protective layer. The semiconductor light-emitting element according to any one of claims 1 to 5.

7. The protective layer comprises a first protective layer made of silicon oxide that is in contact with the upper TiN layer and the intermediate TiN layer, and a second protective layer made of silicon nitride that covers the first protective layer. The semiconductor light-emitting element according to any one of claims 2 to 5.

8. The aforementioned metal layer includes a Rh layer. The semiconductor light-emitting element according to any one of claims 2 to 5.

9. A step of forming an active layer on an n-type semiconductor layer, The step of forming a p-type semiconductor layer on the active layer, A step of forming a contact electrode comprising a conductive oxide material on the p-type semiconductor layer, The steps include forming a current diffusion layer on the contact electrode, A step of coating the n-type semiconductor layer, the active layer, the p-type semiconductor layer, and the current diffusion layer to form a protective layer made of a dielectric material, A step of removing the protective layer on the current diffusion layer to form a pad opening, The process includes forming a pad electrode that contacts the current diffusion layer at the pad opening and is provided on the protective layer outside the pad opening, The step of forming the current diffusion layer includes the step of forming a lower TiN layer that contacts the conductive oxide material of the contact electrode, and the step of forming an upper TiN layer that contacts the dielectric material of the protective layer. The lower TiN layer is formed by reactive sputtering under the condition that the flow rate ratio of nitrogen gas to argon gas is 9% or more. The upper TiN layer is formed by reactive sputtering under the condition that the flow rate ratio of nitrogen gas to argon gas is 8% or less. A method for manufacturing semiconductor light-emitting elements.

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