Panel-level fan-out package structure and manufacturing method

Abstract

This invention provides a panel-level fan-out package structure and a manufacturing method for it. [Solution] A method for manufacturing a panel-level fan-out package structure 1000 includes the steps of: preparing a panel-level frame 400 having a first dielectric layer 301 and a through-cavity surrounded by the first dielectric layer; and mounting an element 500 in the through-cavity. The terminal surface of the element is flush with the second surface, and the terminal surface includes a first terminal and a second terminal. The method also includes the steps of: forming a second dielectric layer 601 covering the element on the first surface; forming a first redistribution layer 701 on the second surface to fan out the first terminal; forming a third dielectric layer 801 on the first redistribution layer, and forming a second redistribution layer 702 on the third dielectric layer to fan out a second terminal that is electrically connected to the first redistribution layer.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic device technology, and particularly to panel-level fan-out package structures and manufacturing methods.

Background Art

[0002] With the continuous development of electronic information technology, multifunctionality and miniaturization are the main drivers of the product replacement cycle of electronic products. In order to achieve the multifunctionality of electronic products, the design of the main components, integrated circuits and package modules has become increasingly complex. In order to achieve the portability of electronic products, the size of electronic products is required to become smaller and the thickness to become thinner. In view of this, high-density integration is an important development trend of future semiconductor packages, and fan-out package technology is a very important advanced package technology at present.

[0003] The currently maturely applied fan-out package technology is the wafer-level fan-out package (abbreviated as Fan-Out Wafer Level Package, FOWLP). The package dimensions of this technology are often 6 inches and 8 inches. Although the size of the silicon wafer is increasing, the expensive material groups and manufacturing processes still limit the diameter dimension to 12 inches, which also limits the number of fan-out units that can be installed on the wafer. Although 18-inch wafers have attracted wide attention, the required investment, material groups, and related equipment are still unknown. At the same time, due to the limitation of the number of chip support structures processed simultaneously, the unit price of FOWLP has increased, making it too expensive for markets that require highly competitive pricing (such as wireless communication, household appliances, and automotive markets).

[0004] Therefore, there is a need to provide a solution for a fan-out panel package (FOPLP), which uses a panel-level package substrate to achieve fan-out with the chip package, thereby improving package efficiency and reducing processing costs. However, general panel-level package substrates mainly use polymer substrates, which lack effective heat dissipation solutions for the panel. Furthermore, FOPLP lacks the multilayer manufacturing process capability equivalent to FOWLP, making it difficult to achieve fan-out for highly dense I / O chips. [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] In view of this, the object of this disclosure is to provide a panel-level fan-out package structure and a method for manufacturing it. [Means for solving the problem]

[0006] Based on the above objectives, in a first aspect, the present disclosure provides a method for manufacturing a panel-level fan-out package structure. Step (a) of preparing a panel-level frame having a first dielectric layer and a through cavity surrounded by the first dielectric layer, wherein the frame includes a first surface and a second surface, and heat dissipation copper posts that penetrate the first dielectric layer and are exposed on the first surface, (b) a step of mounting the element in the through cavity, wherein the terminal surface of the element is flush with the second surface, and the terminal surface includes a first terminal and a second terminal, and a second dielectric layer covering the element is formed on the first surface, (c) a first rewiring layer is formed on the second surface to fan out the first terminal, The present invention is characterized by comprising the steps (d) of forming a third dielectric layer on the first redistribution layer, forming a second redistribution layer on the third dielectric layer that fans out the second terminal, and electrically connecting the second redistribution layer to the first redistribution layer.

[0007] In some implementations, Step (f) of opening a window in the second dielectric layer to expose the heat dissipation copper post and the back surface of the element, The step (g) of forming a fourth line layer including a heat-dissipating copper surface in the second dielectric layer, further comprising the step (g) of electrically connecting the heat-dissipating copper surface to the heat-dissipating copper post and the back surface of the element.

[0008] In some embodiments, the frame further includes conductive copper posts, the two end faces of the conductive copper posts being exposed to the first surface and the second surface, respectively. Among them, the aforementioned manufacturing method is Step (f') of opening a window in the second dielectric layer to expose the conductive copper post, the heat dissipation copper post, and the back surface of the element, A step (g) of manufacturing a fourth line layer including a functional circuit terminal and a heat dissipation copper surface in the second dielectric layer, further comprising the step (g') of electrically connecting the functional circuit terminal to the conductive copper post and electrically connecting the heat dissipation copper post to the back surface of the element.

[0009] In some implementations, the conductive copper post is further electrically connected to the functional circuit terminal and the first rewiring layer.

[0010] In some implementations, step (a) is: A substep (a1) is to prepare a panel level mounting plate and form heat dissipation copper posts and annular sacrificial copper posts on the mounting plate, wherein the height of the heat dissipation copper posts is smaller than the height of the sacrificial copper posts. A substep (a2) involves forming the first dielectric layer on the mounting plate to expose the sacrificial copper post to the first dielectric layer, The substep (a3) ​​of removing the mounting plate, A substep (a4) is to etch away the sacrificial copper posts to remove the first dielectric layer surrounded by the sacrificial copper posts, thereby forming a frame having heat dissipation copper posts and through cavities, wherein the frame includes a first surface and a second surface, and the heat dissipation copper posts are exposed on the first surface.

[0011] In some implementations, step (a) is: A substep (a1') is to prepare a panel level mounting plate and form conductive copper posts, heat dissipation copper posts and annular sacrificial copper posts on the mounting plate, wherein the height of the heat dissipation copper posts is smaller than the height of the sacrificial copper posts and the conductive copper posts, A substep (a2') is to form the first dielectric layer on the mounting plate, thereby exposing the sacrificial copper post to the first dielectric layer, The substep (a3') of removing the mounting plate, A substep (a4') is to etch and remove the sacrificial copper posts to remove the first dielectric layer surrounded by the sacrificial copper posts and form a frame having conductive copper posts, heat dissipation copper posts and through cavities, wherein the frame includes a first surface and a second surface, the heat dissipation copper posts are exposed on the first surface, and the conductive copper posts are exposed on the first surface and the second surface.

[0012] In some implementations, the height difference between the heat-dissipating copper post and the sacrificial copper post is 20 to 50 μm.

[0013] In some implementations, the sacrificial copper post and the conductive copper post are flush with the second surface.

[0014] In some implementations, step (d) is: A substep (d1) is performed by creating a window in the third dielectric layer using an exposure and development method to expose the second terminal and the first rewiring layer of the element, A substep (d2) of forming a third metal seed layer on the surface of the third dielectric layer, A substep (d3) involves applying a third photoresist layer to the third metal seed layer and patterning the third photoresist layer to form a third characteristic pattern. A substep (d4) involves electroplating the third characteristic pattern to fan out the second terminal and form a second redistribution layer that electrically connects to the first redistribution layer, The process includes a substep (d5) of removing the third photoresist layer and etching the exposed third metal seed layer.

[0015] In some implementations, the manufacturing method is The method further includes step (e) forming a fourth dielectric layer on the second redistribution layer, manufacturing a third redistribution layer on the fourth dielectric layer, and electrically connecting the third redistribution layer to the second redistribution layer.

[0016] In some embodiments, the heat-dissipating copper post constitutes the entire frame except for the cavity and is separated from the cavity by the first dielectric layer, and the heat-dissipating copper surface covers the second surface of the frame.

[0017] In some embodiments, the heat-dissipating copper post constitutes the entire frame except for the cavity and the conductive copper post, and is separated from the cavity and the conductive copper post by the first dielectric layer, and the heat-dissipating copper surface covers the second surface other than the functional circuit terminals.

[0018] In a second aspect, embodiments of the present disclosure provide a panel-level fan-out package structure, including a frame and elements embedded in the frame. The frame includes heat-dissipating copper posts and a first dielectric layer separating the heat-dissipating copper posts from the elements. Among them, the frame has opposite first and second surfaces, and a first rewiring layer, a third dielectric layer, and a second rewiring layer are sequentially disposed on the second surface. The first rewiring layer and the second rewiring layer are conductively connected to fan out the first terminal and the second terminal of the element respectively, and the first rewiring layer is conductively connected to the second rewiring layer.

[0019] In some embodiments, it further includes a fourth dielectric layer in the second rewiring layer and a third rewiring layer in the fourth dielectric layer, and the third rewiring layer is conductively connected to the second rewiring layer.

[0020] In some embodiments, it further includes a second dielectric layer disposed on the first surface of the frame and a fourth wiring layer in the second dielectric layer. Among them, the fourth wiring layer includes a heat-dissipating copper surface, and the heat-dissipating copper surface is conductively connected to the heat-dissipating copper posts and the back surface of the element, and the heat-dissipating copper surface covers the first surface.

[0021] In some embodiments, the frame further includes a conductive copper post separated from the heat-dissipating copper post by the first dielectric layer, a second dielectric layer disposed on the first surface of the frame, and a fourth wiring layer in the second dielectric layer. The fourth wiring layer includes a functional circuit terminal and a heat-dissipating copper surface. Among them, the heat-dissipating copper surface is conductively connected to the heat-dissipating copper posts and the back surface of the element, the heat-dissipating copper surface covers the first surface other than the functional circuit terminal, and both ends of the conductive copper post are conductively connected to the functional circuit terminal and the first rewiring layer respectively.

Advantages of the Invention

[0022] As can be seen from the above, the panel-level fan-out package structure and manufacturing method provided in the embodiments of this disclosure achieve fan-out and epitaxial connection of high-density I / O of elements by fan-out multiple terminals of elements embedded in a metal frame in several steps, solving the problem that conventional panel-level fan-out package manufacturing processes cannot meet the fan-out demand for high-density I / O elements. Furthermore, by installing heat dissipation copper posts and heat dissipation copper surfaces connected electrically to the back surface of the elements over a large area, the heat dissipation problem of high-frequency elements is solved. In addition, by creating a height difference between the heat dissipation copper posts, conductive copper posts and sacrificial copper posts, it is not necessary to polish the heat dissipation copper posts after etching and removing the sacrificial copper posts, saving technology in the manufacturing process and significantly improving the efficiency of the manufacturing process. [Brief explanation of the drawing]

[0023] To more clearly illustrate the technical solutions in this disclosure or related technologies, the following briefly introduces the drawings that may be used in describing the embodiments or related technologies. Clearly, the drawings in the following description are only those of embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these without any creative effort. [Figure 1(a)] The diagram shows a schematic cross-sectional view of an intermediate structure for each step of the manufacturing method of the panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 1(aa)] This is a plan view of Figure 1(a). [Figure 1(b)] The diagram shows a schematic cross-sectional view of an intermediate structure for each step of the manufacturing method of the panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 1(c)] The diagram shows a schematic cross-sectional view of an intermediate structure for each step of the manufacturing method of the panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 1(d)] The diagram shows a schematic cross-sectional view of an intermediate structure for each step of the manufacturing method of the panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 1(e)]The diagram shows a schematic cross-sectional view of an intermediate structure for each step of the manufacturing method of the panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 1(f)] The diagram shows a schematic cross-sectional view of an intermediate structure for each step of the manufacturing method of the panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 1(g)] The diagram shows a schematic cross-sectional view of an intermediate structure for each step of the manufacturing method of the panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 1(h)] The diagram shows a schematic cross-sectional view of an intermediate structure for each step of the manufacturing method of the panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 1(i)] The diagram shows a schematic cross-sectional view of an intermediate structure for each step of the manufacturing method of the panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 1(j)] The diagram shows a schematic cross-sectional view of an intermediate structure for each step of the manufacturing method of the panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 2] A schematic diagram of a panel-level fan-out package structure provided in the embodiments of this disclosure is shown. [Figure 3(a)] This shows a schematic cross-sectional view of an intermediate structure of some steps in the manufacturing method of another panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 3(b)] This shows a schematic cross-sectional view of an intermediate structure of some steps in the manufacturing method of another panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 3(c)] This shows a schematic cross-sectional view of an intermediate structure of some steps in the manufacturing method of another panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 3(d)] This shows a schematic cross-sectional view of an intermediate structure of some steps in the manufacturing method of another panel-level fan-out package structure provided in the embodiments of this disclosure. [Figure 4] A schematic diagram of another panel-level fan-out package structure provided in the embodiments of this disclosure is shown. [Modes for carrying out the invention]

[0024] To further clarify the purpose, technical solutions, and advantages of this disclosure, the disclosure will be described in more detail below with reference to the drawings and in conjunction with specific embodiments.

[0025] Unless otherwise defined, technical or scientific terms used in the embodiments of this disclosure must have the general meaning as understood by a person with general skill in the art to which this disclosure belongs. The terms “first,” “second,” and similar terms used in the embodiments of the present invention do not indicate order, number, or importance, but are used to distinguish different components. Similar terms such as “include” or “incorporate” mean that the part or article appearing before the word covers the part or article and similar items listed after the word, and does not exclude other parts or articles. Similar terms such as “connect” or “link” may include electrical connections, and may be direct or indirect, and are not limited to physical or mechanical connections. Terms such as “up,” “down,” “left,” and “right” are used to indicate relative positional relationships, and if the absolute position of the described object changes, the relative positional relationship changes accordingly.

[0026] An exemplary embodiment of this disclosure provides a method for manufacturing a panel-level fan-out package structure. Figures 1(a) to 1(j) show schematic cross-sectional views of intermediate structures at each step of one embodiment of the method for manufacturing a panel-level fan-out package structure of the present invention. Specifically, the manufacturing method includes the following steps:

[0027] As shown in Figure 1(a), step (a) is to prepare a panel-level mounting plate 100 and form conductive copper posts 201, heat-dissipating copper posts 202, and sacrificial copper posts 203 on the mounting plate 100. The panel-level mounting plate 100 may be circular or rectangular, for example, a rectangle or a square. The dimensions of the panel-level mounting plate 100 can be selected according to actual requirements, for example, 300mm × 300mm, 510mm × 515mm, or 600mm × 600mm. Here, a first metal seed layer 101 can be pre-formed on the mounting plate 100, for example, by using a metal sputtering method on the mounting plate 100 to manufacture the first metal seed layer 101. The material of the first metal seed layer 101 may be copper, titanium, or a combination thereof, with a combination of copper and titanium being preferred.

[0028] In some embodiments, the specific steps for forming the conductive copper post 201, the heat dissipating copper post 202, and the sacrificial copper post 203 may involve first fabricating a circuit pattern on the first metal seed layer 101, then electroplating the circuit pattern, and finally peeling off the film.

[0029] Selectively, the sacrificial copper posts 203 can be chosen from an annular structure or a continuous columnar wall structure. Figure 1(aa) is a plan view of the structure shown in Figure 1(a). Figure 1(aa) exemplifies the case where the sacrificial copper posts 203 are a continuous columnar wall structure. In this case, in a subsequent step, the sacrificial copper posts 203 are etched away to remove the first dielectric layer surrounded by the sacrificial copper posts 203, thereby forming a through-cavity, which facilitates the installation of the element in the subsequent through-cavity.

[0030] The number of sacrificial copper posts 203 is not limited to one, but can be limited based on the required number of package elements (e.g., chips) and panel area, and this disclosure does not limit this.

[0031] Conventional FOPLP solutions lack effective heat dissipation solutions. In view of this, in the embodiments of this disclosure, large-area heat-dissipating copper posts (heat-dissipating blocks) 202 are installed. Normally, after avoiding the sacrificial copper posts 203 and conductive copper posts 201, the heat-dissipating copper posts 202 can be installed to the maximum extent possible to improve the heat dissipation effect. It should be understood that if heat dissipation function is not considered, it is not necessary to manufacture the heat-dissipating copper posts 202.

[0032] Selectively, during electroplating, the thickness (corresponding height) of the heat dissipation copper post 202 is controlled to be smaller than the thickness (corresponding height) of the conductive copper post 201 and the sacrificial copper post 203. For example, the height of the heat dissipation copper post 202 can be 20-50 μm smaller than the heights of the conductive copper post 201 and the sacrificial copper post 203. Selectively, the conductive copper post 201 and the sacrificial copper post 203 have approximately the same height, thereby exposing the conductive copper post 201 to the first and second surfaces of the frame.

[0033] Here, the conductive copper post 201 is used to provide a conductive connection to the flip-chip element 1001 when packaging the flip-chip element 1001 on the surface of the panel-level fan-out package structure 1000 (see Figure 1(j)). It should be understood that the conductive copper post 201 can be removed from the panel-level fan-out package structure 1000 if the flip-chip element 1001 is not required (as shown in Figure 4).

[0034] Next, as shown in Figure 1(b), a first dielectric material is applied to form a first dielectric layer 301, the first dielectric layer 301 exposing the end faces of the sacrificial copper post 203 and the conductive copper post 201 - step (b). Here, since the height of the heat dissipation copper post 202 is smaller than that of the sacrificial copper post 203 and the conductive copper post 201, the heat dissipation copper post 202 is still covered by the first dielectric layer 301.

[0035] In some embodiments, the method of applying the first dielectric material may be a conventional process such as pressure welding, vacuum high-speed pressure welding, or coating, until the first dielectric material completely covers the conductive copper post 201, the heat dissipation copper post 202, and the sacrificial copper post 203. Next, the first dielectric material is thinned to form the first dielectric layer 301. Here, the thinning process can be a process such as polishing or plasma etching, exposing the end faces of the sacrificial copper post 203 and the conductive copper post 201. The height of the heat dissipation copper post 202 is smaller than the height of the conductive copper post 201 and the sacrificial copper post 203, and the heat dissipation copper post 202 does not need to be thinned by polishing, significantly improving processing efficiency.

[0036] Selectively, the first dielectric material may be a polymer dielectric material containing glass fibers, which contributes to ensuring the strength and rigidity of the substrate. Exemplarily, the polymer dielectric material containing glass fibers is selected from one of the group consisting of liquid crystal polymers, BT (bismaleimide triazine) resins, semi-cured prepregs, ABF (Ajinomoto Build-up) films, epoxy resins (expoxy), and polyimide resins, but the present invention is not limited thereto.

[0037] Next, as shown in Figure 1(c), step (c) is to remove the mounting plate. Here, the removal of the mounting plate includes removing the mounting plate 100 and etching the exposed metal seed layer 101.

[0038] Next, as shown in Figure 1(d), the dielectric material surrounded by the sacrificial copper posts 203 is removed by etching the sacrificial copper posts 203, thereby forming a frame 400 having conductive copper posts 201, heat dissipation copper posts 202, and through-cavity 401 - step (d).

[0039] In some embodiments, the frame 400 includes a first surface 402 and a second surface 403, and the heat dissipation copper post 202 is exposed on the first surface 402 but not on the second surface 403.

[0040] The specific form of etching and removal of the sacrificial copper posts 203 is described in the following exemplary description of this disclosure. First, a first photoresist layer is applied to produce a first characteristic pattern of the sacrificial copper posts 203. Next, etching is performed to etch and remove the sacrificial copper posts 203, and then the film is peeled off to remove the photoresist, thereby obtaining a frame 400 as shown in Figure 1(d).

[0041] Next, as shown in Figure 1(e), the element 500 is mounted in the through cavity, with the terminal surface of the element flush with the second surface 403, and the second dielectric material package element 500 is applied to the first surface 402 to form the second dielectric layer 601 - step (e).

[0042] The element 500 may be an IC chip, a logic circuit component, a power amplifier, a capacitor, an inductor, a resistor, etc., and this disclosure is not limited thereto. The terminal surface of the element 500 includes at least a first terminal 501 and a second terminal 502.

[0043] In some embodiments, an adhesive dielectric layer can be formed on the second surface 403, which is adhesive at room temperature or when heated and can bond devices, and the adhesive dielectric layer can be formed by pressing a dielectric material having a dry film type coating function onto it. Next, the element 500 is placed in the through cavity and bonded to the adhesive dielectric layer, and when bonding, it is possible to select whether or not to heat based on the degree of adhesiveness of the adhesive dielectric layer, for example, the element can be heated when the adhesiveness is low. The adhesive dielectric layer may be removed after the second dielectric layer 601 has been formed.

[0044] Selectively, the second dielectric material may be the same as the first dielectric material or it may be different.

[0045] Next, as shown in Figure 1(f), a first redistribution layer 701 is fabricated on the second surface 403, and a fan-out is performed on the first terminal 501 of the element 500 - step (f).

[0046] In some embodiments, the steps for manufacturing the first redistribution layer 701 may include: first, forming a second metal seed layer on the second surface 403; second, applying a second photoresist layer to the second metal seed layer; patterning the second photoresist layer to form a second feature pattern; subsequently, electroplating the second feature pattern to form a first redistribution layer that fans out the first terminals; and finally, removing the second photoresist layer and etching the exposed second metal seed layer. Here, the material of the second metal seed layer is similar to that of the first metal seed layer, so no further explanation is given. Optionally, the material of the first redistribution layer may be copper.

[0047] Next, as shown in Figure 1(g), a third dielectric material is applied to the first redistribution layer to form a third dielectric layer 801, and a second redistribution layer 702 is fabricated on the third dielectric layer. The second redistribution layer 702 fans out the second terminal 502 of the element and connects it to the first redistribution layer 701 - step (g). The second redistribution layer 702 can also simultaneously perform the role of epitaxially connecting the first redistribution layer.

[0048] In some embodiments, the third dielectric material may be a photosensitive dielectric material with high analytical capability, which is useful for opening subsequent microconducting holes.

[0049] In some embodiments, a third dielectric material is applied to the first redistribution layer by processes such as pressure bonding and coating, and then the third dielectric material is locally removed by exposure and development to expose the second terminal of the element and a portion of the first redistribution layer, and finally the third dielectric layer 801 is cured and formed.

[0050] In some embodiments, the steps for manufacturing the second redistribution layer 702 may include: forming a third metal seed layer on the surface of the third dielectric layer 801; applying a third photoresist layer to the third metal seed layer; patterning the third photoresist layer to form a third characteristic pattern; electroplating the third characteristic pattern to form a second redistribution layer that fans out the second terminals and connects to the first redistribution layer; removing the third photoresist layer; and etching the exposed third metal seed layer.

[0051] As can be seen from the above, the technical solution of the embodiment of this disclosure employs a technique to fan out element terminals in several stages, enabling rational wiring for high-density I / O element fan-out, effectively reducing the horizontal wiring space, and solving the technical problem that conventional FOPLPs have difficulty achieving high-density I / O element fan-out.

[0052] Next, as shown in Figure 1(h), a fourth dielectric material is applied to the second redistribution layer 702 to form a fourth dielectric layer 802, a third redistribution layer 703 is fabricated on the fourth dielectric layer 802, and the third redistribution layer 703 is connected to the second redistribution layer 702 - step (h). Note that the third redistribution layer 703 can epitaxially connect to the second redistribution layer 702.

[0053] The manufacturing processes for the fourth dielectric layer 802 and the third redistribution layer 703 are described below, with reference to the third dielectric layer 801 and the second redistribution layer 702.

[0054] Next, as shown in Figure 1(i), a window is made in the second dielectric layer 601 (i.e., the package layer of the element 500) to expose the conductive copper post 201, the heat dissipation copper post 202, and the back surface of the element 500. A fourth line layer 901 including the functional circuit terminals 9011 and the heat dissipation copper surface 9012 is then fabricated in the second dielectric layer 601 after the window has been made, thereby obtaining the element fan-out package structure 1000 - step (i). The heat dissipation copper surface 9012 is connected to the heat dissipation copper post 202 and the back surface of the element 500, and the functional circuit terminals 9011 are connected to the conductive copper post 201. The heat dissipation copper surface 9012 can almost completely cover the entire first surface of the frame, and if the conductive copper post 201 is present, only the functional circuit terminals 9011 need to be exposed. The large-area heat-dissipating copper posts 202 and heat-dissipating copper surface 9012 help to achieve large-area direct heat dissipation, significantly improving the heat dissipation capacity of the package structure 1000.

[0055] The manufacturing process for the fourth track layer 901 can be described by referring to the third redistribution layer, and will be omitted from the explanation.

[0056] Finally, as shown in Figure 1(j), the functional circuit terminal 9011 can be realized as an upper pad in the package, enabling a conductive connection to another element or the package body 1001, and the third redistribution layer 703 can form a lower pad, enabling a conductive connection to the substrate or PCB board 1002 - step (j). Note that the other element 1001 may be an IC chip.

[0057] An exemplary embodiment of this disclosure provides a method for manufacturing another panel-level fan-out package structure. Figures 3(a) to 3(d) show schematic cross-sectional views of intermediate structures in some steps of the method for manufacturing another panel-level fan-out package structure according to one embodiment of this disclosure. The difference between the package structures manufactured in Figures 3(a) to 3(d) and those manufactured in Figures 1(a) to 1(j) is the absence of the conductive copper post 201. Specifically, the manufacturing method includes the following steps:

[0058] Step (a') is to prepare a frame 400' having heat-dissipating copper posts 202' and through cavities 401', as shown in Figure 3(a). The specific process of step (a') can be found in steps (a) to (d). Since frame 400' does not include conductive copper posts 201, the heat-dissipating copper posts 202' can have a larger surface area, which is advantageous for heat dissipation. Frame 400' is similar to frame 400 and includes a first surface 402' and a second surface 403'. Of these, the heat-dissipating copper posts 202' are exposed on the first surface 402' and enclosed within the second surface 403'.

[0059] Next, as shown in Figure 3(b), step (b') is performed to manufacture the first redistribution layer, the third dielectric layer, the second redistribution layer, the fourth dielectric layer, and the third redistribution layer, referring to the processes of steps (d) to (h). Step (b') enables the element terminals to be fanned out in several stages.

[0060] Next, as shown in Figure 3(c), referring to step (j), a fourth line layer 901' is manufactured to obtain a panel-level fan-out package structure 1000' - step (c'). The fourth line layer 901' includes heat-dissipating copper posts and a heat-dissipating copper surface that covers almost the entire first surface connecting to the back surface of the element, enabling large-area direct heat dissipation. Because there are no conductive copper posts, the area of ​​the heat-dissipating copper posts and heat-dissipating copper surface is larger, which is more helpful for heat dissipation.

[0061] Finally, as shown in Figure 3(d), the third redistribution layer 703 can be used to form pads, allowing the fan-out package structure 1000' to be electrically connected to the substrate or PCB board 1002' - step (d'). However, since there are no conductive copper posts, it is not possible to realize a package with two sides.

[0062] Based on a similar inventive concept, embodiments of the present disclosure further provide a panel-level fan-out package structure. Referring to Figure 2, a schematic cross-sectional view of the panel-level fan-out package structure 1000 provided in embodiments of the present disclosure is shown.

[0063] Specifically, the panel-level fan-out package structure 1000 includes a frame 400, an element 500, a first redistribution layer 701, a third dielectric layer 801, a second redistribution layer 702, a fourth dielectric layer 802, and a third redistribution layer 703. The element 500 is mounted on the frame 400, and the first redistribution layer 701, the third dielectric layer 801, the second redistribution layer 702, the fourth dielectric layer 802, and the third redistribution layer 703 are sequentially mounted on the second surface of the frame 400, with the first redistribution layer 701 and the second redistribution layer 702 connected to the first and second terminals of the element 500, respectively, the first redistribution layer 701 connected to the second redistribution layer 702, and the second redistribution layer 702 connected to the third redistribution layer 703. This structure allows for fan-out of the first and second terminals of element 500 in several stages, enabling rational wiring of high-density I / O element terminal fan-out and reducing the horizontal wiring space.

[0064] In some embodiments, a second dielectric layer 601 and a fourth line layer 901 are installed on the first surface of the frame 400. The fourth line layer 901 includes a functional circuit terminal 9011 and a heat dissipation copper surface 9012. The heat dissipation copper surface 9012 is connected to the back surface of the element 500 and to the heat dissipation copper posts 202. Both ends of the conductive copper posts 201 on the frame 400 are connected to the functional circuit terminal 9011 and the first rewiring layer 701, respectively. As shown in Figure 1(j), the heat dissipation copper surface 9012 can be used to achieve large-area heat dissipation, and the conductive copper posts 201 and functional circuit terminal 9011 can be used to make conductive connections to another element or package body.

[0065] Embodiments of the present disclosure provide yet another panel-level fan-out package structure. Referring to Figure 4, a schematic cross-sectional view of another panel-level fan-out package structure 1000' provided in embodiments of the present disclosure is shown.

[0066] Similar to the panel-level fan-out package structure 1000, the panel-level fan-out package structure 1000' similarly utilizes a first redistribution layer 701', a second redistribution layer 702', and a third redistribution layer 703' to fan out the element terminals in several stages. The difference between the panel-level fan-out package structure 1000' and the panel-level fan-out package structure 1000 is that the frame does not include conductive copper posts 201, so the fourth line layer 901' includes the back surface of the element 500 and the heat-dissipating copper surface connecting the heat-dissipating copper posts 202, but does not include functional circuit terminals.

[0067] The panel-level fan-out package structure of the above embodiment has beneficial effects of the corresponding method embodiment, which will not be described here.

[0068] As those skilled in the art will understand, the consideration of any of the above embodiments is illustrative only and does not imply that the scope of this disclosure (including the claims) is limited to these examples. Combinations of the technical features of the above embodiments or different embodiments are possible in accordance with the spirit of this disclosure, the steps can be performed in any order, and many other variations of the differences of the above embodiments of this disclosure exist, which for the sake of clarity will not be described in detail.

[0069] The embodiments of this disclosure are intended to encompass all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this disclosure should be included within the scope of protection of this disclosure. [Explanation of symbols]

[0070] 100 Mounting plate, panel level mounting plate, 101 First metal seed layer, metal seed layer, 201 Conductive copper post, 202 Heat dissipation copper post, 202' Heat dissipation copper post, 203 Sacrificial copper post, 301 First dielectric layer, 400 Frame, 400' Frame, 401 Through cavity, 401' Through cavity, 402 First surface, 402' First surface, 403 Second surface, 403' Second surface, 500 Second dielectric material package element, element, 501 First terminal, 502 Second terminal, 601 Second dielectric layer, 701 First redistribution layer, 701' First redistribution layer, 702 Second redistribution layer, 702' Second redistribution layer, 703 Third redistribution layer, 703' Third redistribution layer, 801 Third dielectric layer, 802 901 Fourth dielectric layer, 901 Fourth transmission layer, 901' Fourth transmission layer, 1000 Panel-level fan-out package structure, element fan-out package structure, package structure, 1000' Panel-level fan-out package structure, fan-out package structure, 1001 Package body, flip-chip element, element, 1002 PCB board, 1002' PCB board, 9011 Functional circuit terminals, 9012 Heat dissipation copper surface

Claims

1. A panel-level fan-out package structure comprising a frame and an element embedded within the frame, wherein the frame comprises a heat-dissipating copper post and a first dielectric layer separating the heat-dissipating copper post from the element, the frame having a first surface and a second surface facing each other, the second surface having a first redistribution layer, a third dielectric layer and a second redistribution layer in that order, the first redistribution layer and the second redistribution layer being electrically connected to fan out the first and second terminals of the element, and the first redistribution layer being electrically connected to the second redistribution layer.

2. The package structure according to claim 1, further comprising a fourth dielectric layer in the second redistribution layer and a third redistribution layer in the fourth dielectric layer, wherein the third redistribution layer is electrically connected to the second redistribution layer.

3. The package structure according to claim 1, further comprising a second dielectric layer installed on the first surface of the frame and a fourth transmission line layer in the second dielectric layer, wherein the fourth transmission line layer includes a heat-dissipating copper surface, the heat-dissipating copper surface is electrically connected to the heat-dissipating copper post and the back surface of the element, and the heat-dissipating copper surface covers the first surface.

4. The package structure according to claim 1, wherein the frame further includes conductive copper posts separated from the heat-dissipating copper posts by the first dielectric layer, a second dielectric layer installed on the first surface of the frame, and a fourth line layer in the second dielectric layer, the fourth line layer including functional circuit terminals and a heat-dissipating copper surface, the heat-dissipating copper surface being electrically connected to the heat-dissipating copper posts and the back surface of the element, the heat-dissipating copper surface covering the first surface other than the functional circuit terminals, and both ends of the conductive copper posts being electrically connected to the functional circuit terminals and the first rewiring layer, respectively.

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