Etching method and etching apparatus

Abstract

The present invention provides an etching method and an etching apparatus for etching a film to be etched. [Solution] An etching method comprising the steps of: preparing a substrate having a silicon-containing film to be etched and an interface layer formed on the film to be etched and having a pattern of openings; and generating a plasma of the processing gas using a mixed gas of fluorocarbon gas containing fluorine atoms and carbon atoms and O2 gas as the processing gas, and etching the film to be etched through the openings while applying a negative bias voltage with an absolute value of 7000V or more to a substrate support on which the substrate is placed.

Description

Technical Field

[0001] The present disclosure relates to an etching method and an etching apparatus.

Background Art

[0002] Patent Document 1 discloses a technique for etching a lower layer using a hard mask of amorphous carbon.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] On one side, the present disclosure provides an etching method and an etching apparatus for etching an etching target film.

Means for Solving the Problems

[0005] To solve the above problems, according to one aspect, a step of preparing a substrate having an etching target film containing silicon and an interface layer formed on the etching target film and having an opening pattern; generating a plasma of a mixed gas of a fluorocarbon gas containing fluorine atoms and carbon atoms and O2 gas as a processing gas, and etching the etching target film through the opening while applying a negative bias voltage having an absolute value of 7000 V or more to a substrate support portion on which the substrate is placed. An etching method is provided.

Effects of the Invention

[0006] According to one aspect, the present disclosure can provide an etching method and an etching apparatus for etching an etching target film.

Brief Description of the Drawings

[0007] [Figure 1] An example of a flowchart illustrating an etching method. [Figure 2] An example of a schematic cross-sectional view of a substrate after an opening pattern has been formed in the resist film. [Figure 3] An example of a schematic cross-sectional view of a substrate after patterning the interface layer, and an enlarged schematic view showing the surface condition of the interface layer. [Figure 4] An example of a schematic cross-sectional view of the substrate and an enlarged schematic view showing the surface state of the interface layer during the initial stages of etching. [Figure 5] An example of a schematic cross-sectional view of the substrate after the etching process and an enlarged schematic view showing the surface state of the interface layer. [Figure 6] An example of a schematic cross-sectional view of a substrate after etching. [Figure 7] An example of a graph showing the results of EDX analysis. [Figure 8] An example of a cross-sectional view showing the result of the mask shape. [Figure 9] An example graph showing the relationship between bias voltage, etching rate of the film to be etched, and mask aperture width. [Figure 10] An example of a diagram illustrating the configuration of a capacitively coupled plasma processing apparatus. [Modes for carrying out the invention]

[0008] The following describes embodiments for implementing this disclosure with reference to the drawings. In each drawing, the same reference numerals are used for identical components, and redundant explanations may be omitted.

[0009] [Etching method] An etching method for forming a pattern of recesses (or openings) 215, such as holes and trenches, on a film to be etched 210 will be explained using Figures 1 to 6. Figure 1 is an example of a flowchart showing the etching method.

[0010] In step S101, the substrate W is prepared. The substrate W comprises a base material 200 and an etching target film 210 formed on the base material 200.

[0011] The base material 200 may be made of, for example, silicon (Si).

[0012] The etchable film 210 is, for example, a film containing silicon (Si). Alternatively, the etchable film 210 may be, for example, an insulating film (non-dielectric film). Specifically, the etchable film 210 includes a silicon oxide film (SiO) and / or a silicon nitride film (SiN). Furthermore, the etchable film 210 may be either a silicon oxide film (SiO) or a silicon nitride film (SiN), or it may contain both silicon oxide film (SiO) and silicon nitride film (SiN). Also, an etchable film 210 containing both silicon oxide film (SiO) and silicon nitride film (SiN) may, for example, be a mold structure used in DRAM, or a structure in which silicon oxide film (SiO) and silicon nitride film (SiN) are alternately stacked, as used in 3D NAND.

[0013] In step S102, an interface layer 220 is formed. Here, the interface layer 220 is formed on the film 210 to be etched.

[0014] The interface layer 220 is a metal compound that has etching resistance to the etching gas used in step S106 (the process of etching the film 210 to be etched), which will be described later. The interface layer 220 can be a metal oxide or metal nitride containing at least one metal atom such as Be, Mg, Al, Ca, Sc, Ti, V, Co, Ni, Zn, Ga, Sr, Y, Zr, Nb, Ru, Pd, Cd, In, Sn, Ba, La, Ce, Nd, Eu, Gd, Er, Hf, or Ta. Specifically, the interface layer 220 can be IGZO (indium gallium zinc oxide), AlOx (aluminum oxide), HfOx (hafnium oxide), etc. The film thickness of the interface layer 220 is preferably, for example, 1 nm or more and 100 nm or less.

[0015] In step S103, an interface layer mask 230 is formed. Here, the interface layer mask 230 is formed on the interface layer 220.

[0016] The interface layer mask 230 is used as a mask when forming the pattern of the opening 225 in the interface layer 220 in step S105 described later. The interface layer mask 230 can be any one of, for example, a silicon oxide film (SiO), a silicon nitride film (SiN), etc.

[0017] In step S104, the interface layer mask 230 is patterned. Here, a pattern of an opening is formed in the interface layer mask 230.

[0018] For example, an SOC (spin-on carbon) film 241, a SOG (spin-on glass) film 242, and a resist film 243 are sequentially stacked and formed on the interface layer mask 230. Next, a pattern of an opening 245 is formed in the resist film 243 by exposure and development processes.

[0019] FIG. 2 is an example of a cross-sectional schematic view of the substrate W after the pattern of the opening 245 is formed in the resist film 243. As shown in FIG. 2, the substrate W is sequentially stacked with a base material 200, an etching target film 210, an interface layer 220, an interface layer mask 230, an SOC film 241, a SOG film 242, and a resist film 243 having the pattern of the opening 245.

[0020] Then, by etching the SOG film 242 using the resist film 243 having the pattern of the opening 245 as a mask, a pattern of an opening is formed in the SOG film 242. Further, by etching the SOC film 241 using the SOG film 242 having the pattern of the opening as a mask, a pattern of an opening is formed in the SOC film 241. Finally, by etching the interface layer mask 230 using the SOC film 241 having the pattern of the opening as a mask, a pattern of an opening is formed in the interface layer mask 230.

[0021] In step S105, the interface layer 220 is patterned. Here, a pattern of openings 225 is formed on the interface layer 220.

[0022] The interface layer 220 is etched using the interface layer mask 230, which has an opening pattern formed on it, as a mask, thereby forming a pattern of openings 225 on the interface layer 220.

[0023] Furthermore, when etching the interface layer 220 using the interface layer mask 230 as a mask, a plasma of a mixed gas of BCl3, Cl2, and O2 can be used as the etching gas. Also, if the interface layer 220 is a metallic compound containing one of In, Ga, Zn, or Al as the metal, a plasma of a mixed gas of CH4 and H2 may be used. In addition, if the interface layer 220 is a difficult-to-etch material, the interface layer 220 may be etched by Ar sputtering.

[0024] Figure 3 is an example of a schematic cross-sectional view of the substrate W after patterning the interface layer 220, and an enlarged schematic view showing the surface state of the interface layer 220. As shown in Figure 3, the substrate W is constructed by sequentially stacking a base material 200, an etching target film 210, and an interface layer 220 having a pattern of openings 225.

[0025] The above steps S101 to S105 prepare a substrate W on which an interface layer 220 having a pattern of openings 225 is formed on the film to be etched 210. The prepared substrate W is then transported to an etching apparatus for etching the film to be etched 210. In other words, Figure 3 is an example of a schematic cross-sectional view of the substrate W and an enlarged schematic view showing the surface state of the interface layer 220 before the start of the etching process.

[0026] In step S106, the carbon hard mask 251 is self-formed while the film to be etched 210 is etched.

[0027] Here, a mixed gas of a fluorocarbon-based gas containing fluorine (F) and carbon (C) atoms and O2 gas can be used as the processing gas (etching gas). Specifically, the fluorocarbon-based gas can be one or a mixture of C4F8, C4F6, CH2F2, etc. In addition, gases such as N2 and Ar may be added to the processing gas.

[0028] Furthermore, the etching process involves generating a plasma of processing gas and exposing the substrate W to the plasma of the processing gas to etch the target film 210. In addition, a negative bias voltage (a first voltage signal generated by the first voltage generation unit 32a, which will be described later using Figure 10) is supplied to the mounting stage on which the substrate W is placed. This attracts positive ions generated by the plasma into the substrate W. This forms deep groove recesses 215 (see Figure 6, which will be described later) by anisotropic etching.

[0029] Fluorocarbon-based gases are etchants that anisotropically etch the target film 210. Adding O2 gas to the fluorocarbon-based gas improves the etching rate of the target film 210. In addition, reaction byproducts generated when the target film 210 is etched are deposited on the substrate W. These reaction byproducts are removed by oxygen plasma.

[0030] Figure 4 is an example of a schematic cross-sectional view of the substrate W and an enlarged schematic view showing the surface state of the interface layer 220 in the initial stages of the etching process. As shown in Figure 4, CFx derived from a fluorocarbon gas is adsorbed onto the surface of the deposit 250, and a polymer deposit 250 to which -[CFx]- is bound is formed. That is, the deposit 250 is selectively formed on the surface of the interface layer 220 compared to the surface of the film to be etched 210. Then, by applying a high bias voltage to the lower electrode provided on the mounting stage on which the substrate W is placed, CFx ions are attracted toward the substrate W (see the white arrow in Figure 4).

[0031] Figure 5 is an example of a schematic cross-sectional view of the substrate W after the etching process and an enlarged schematic view showing the surface state of the interface layer 220. As shown in Figure 5, when high-energy CFx ions collide with the deposit 250, the carbon atoms of the deposit 250 combine with the CFx ions, causing the deposit 250 to carbonize, and fluorine atoms are removed from the carbon atoms of the deposit 250. As a result, during the etching process, a carbon hard mask 251 with high etching resistance is self-formed on the upper surface of the interface layer 220. On the other hand, on the side surfaces of the interface layer 220 (side walls of the opening 225), the possibility of high-energy CFx ions entering the side walls is low, and the formation of the carbon hard mask 251 is suppressed. In this way, the carbon hard mask 251 is selectively self-formed on the upper surface of the interface layer 220. Furthermore, the increase in film thickness is suppressed because the consumption of the carbon hard mask 251 by plasma etching and ashing with oxygen plasma balances out the self-formation of the carbon hard mask 251.

[0032] Here, it is preferable that the ratio of the number of carbon atoms (C) to the number of fluorine atoms (F) in the fluorocarbon gas is within the range of C / F ≥ 0.5. In other words, it is preferable that the ratio of the number of carbon atoms to the number of fluorine atoms in the fluorocarbon gas is 0.5 or more. This allows for the suitable formation of CFx deposits 250 on the surface of the interface layer 220.

[0033] Furthermore, it is preferable that the ratio of carbon atoms (C) to oxygen atoms (O) in the processing gas be within the range of 0.4 ≤ O / C ≤ 0.6. In other words, it is preferable that the ratio of oxygen atoms to carbon atoms in the processing gas is 0.4 or more and 0.6 or less. Note that if O / C < 0.4, the formation of deposits 250 and / or carbon hard masks 251 becomes too large, inhibiting the etching of the target film 210. Also, if O / C > 0.6, the deposits 250 and / or carbon hard masks 251 on the surface of the interface layer 220 are ashed, inhibiting the formation of carbon hard masks 251.

[0034] Figure 6 shows an example of a schematic cross-sectional view of the substrate W after etching. As shown in Figure 6, the etching gas plasma selectively etches the target film 210 against the carbon hard mask 251. This forms deep groove recesses 215 with a high aspect ratio in the target film 210.

[0035] Furthermore, when forming deep groove recesses 215 with a high aspect ratio in the etchable film 210 using only an amorphous carbon hard mask, the thickness of the carbon hard mask needs to be increased as the thickness of the etchable film 210 increases. However, as the thickness of the carbon hard mask increases, processing to form the opening pattern on the carbon hard mask becomes difficult. In addition, the carbon hard mask has internal stress, and increasing the thickness of the carbon hard mask may cause warping of the substrate W. Moreover, as the thickness of the carbon hard mask increases, the etching rate when etching the etchable film 210 decreases, and the throughput of the etching equipment also decreases. Furthermore, as the thickness of the carbon hard mask increases, twisting or other deformation may occur in the recesses 215 formed in the etchable film 210, potentially degrading their shape.

[0036] In contrast, the process shown in steps S101 to S105 in Figure 1 allows for the formation of an interface layer 220 having an opening 225, and during the etching process (S106), a carbon hard mask 251 can be self-formed on the upper surface of the interface layer 220. Furthermore, warping of the substrate W can be prevented. Compared to the case where only a carbon hard mask is used, the total thickness of the interface layer 220 and the carbon hard mask 251 can be reduced. As a result, the etching speed when etching the film to be etched 210 is improved, and the throughput of the etching apparatus is also improved. In addition, twisting and other deformations of the recesses 215 formed in the film to be etched 210 are suppressed, and a good shape of the recesses 215 can be formed in the film to be etched 210.

[0037] Returning to Figure 1, in step S107, the carbon hard mask 251 is ashing. Here, the carbon hard mask 251 is ashing using O2 plasma. Also, the surface of the interface layer 220 is oxidized to a metal oxide.

[0038] In step S108, the interface layer 220 is removed. For example, if the interface layer 220 is a metal oxide, the interface layer 220 is removed by DHF cleaning using dilute hydrofluoric acid.

[0039] As described above, the substrate processing method shown in Figure 1 allows for the formation of high-aspect-ratio recesses 215 in the etchable film 210. Furthermore, twisting of the recesses 215 formed in the etchable film 210 can be suppressed. This makes it possible to form recesses 215 with a good etching shape.

[0040] Next, the carbon hard mask 251 formed on the upper surface of the interface layer 220 was analyzed by energy-dispersive X-ray fluorescence spectroscopy (EDX analysis). The results of the EDX analysis are explained using Figure 7. Figure 7 is an example of a graph showing the results of the EDX analysis. The vertical axis shows the percentage [%] of all elements to be detected. The horizontal axis shows the height [nm]. Here, IGZO was used as the interface layer 220. After etching, the substrate W (see Figure 5) was coated with an SiO film and then EDX analysis was performed. In Figure 7, the boundary between the interface layer 220 and the carbon hard mask 251 (around 56 nm) and the upper surface of the carbon hard mask 251 (around 75 nm) are shown by dashed lines.

[0041] As shown in Figure 7, the carbon hard mask 251 shows a mixed state of metal atoms and carbon atoms in the interface layer 220 at around 56 nm. Furthermore, a peak of carbon atoms (C) appears at around 75 nm in the carbon hard mask 251. This indicates that the surface of the carbon hard mask 251 is carbonized.

[0042] Next, the relationship between bias voltage and mask shape will be explained using Figure 8. Figure 8 is an example of a cross-sectional view showing the results for different mask shapes. Here, a negative bias voltage is applied to the mounting stage (lower electrode of the substrate support part 11) in order to attract cations. The results for the absolute values ​​of the bias voltage of 4200V and 7000V are shown.

[0043] The polymer deposit 250 to which CFx is bonded is a weakly bonded polymer, and when the absolute value of the bias voltage is 4200V, shoulder drop occurs in the pattern of the interface layer 220, where the shoulder portion (the corner portion between the top surface and the side wall) is worn away by etching.

[0044] In contrast, by setting the absolute value of the bias voltage to 7000V, high-energy CFx ions collide with the deposit 250, forming a carbonized carbon hard mask 251. This suppresses wear in the shoulder portion of the interface layer 220. Thus, it is preferable that the absolute value of the negative bias voltage applied to the mounting base (lower electrode of the substrate support part 11) be 7000V or higher. In other words, it is preferable that the bias voltage be -7000V or lower.

[0045] Figure 9 is an example of a graph showing the relationship between the bias voltage, the etching rate of the film to be etched 210, and the aperture width of the mask. The horizontal axis represents the absolute value of the negative bias voltage applied to the mounting stage (lower electrode of the substrate support part 11). The left vertical axis shows the etching rate of the film to be etched 210, indicated by black circles and solid lines. The right vertical axis shows the aperture width at the top of the mask, indicated by white circles and dashed lines.

[0046] As shown by the black circles and solid lines in Figure 9, the etching rate of the etched film 210 improves as the absolute value of the bias voltage increases. Also, as shown by the white circles and dashed lines in Figure 9, the opening width at the top of the mask narrows as the absolute value of the bias voltage increases. In other words, wear at the shoulder portion of the interface layer 220 can be suppressed, and shoulder drop can be prevented. This improves the shape of the recesses 215 formed in the etched film 210.

[0047] [Plasma Processing System] Next, we will describe an example of the configuration of a plasma processing system. Figure 10 is an example of a diagram illustrating the configuration of a capacitively coupled plasma processing apparatus (etching apparatus) 1.

[0048] The plasma processing system includes a capacitively coupled plasma processing apparatus 1 and a control unit 2. The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply system 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support unit 11 and a gas introduction unit. The gas introduction unit is configured to introduce at least one processing gas into the plasma processing chamber 10. The gas introduction unit includes a shower head 13. The substrate support unit 11 is located inside the plasma processing chamber 10. The shower head 13 is located above the substrate support unit 11. In one embodiment, the shower head 13 constitutes at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the shower head 13, the side walls 10a of the plasma processing chamber 10, and the substrate support unit 11. The plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas to the plasma processing space 10s, and at least one gas outlet for discharging gas from the plasma processing space 10s. The plasma processing chamber 10 is grounded. The shower head 13 and the substrate support portion 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0049] The substrate support portion 11 includes a main body portion 111 and a ring assembly 112. The main body portion 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of the substrate W. The annular region 111b of the main body portion 111 surrounds the central region 111a of the main body portion 111 in a plan view. The substrate W is placed on the central region 111a of the main body portion 111, and the ring assembly 112 is placed on the annular region 111b of the main body portion 111 so as to surround the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also called the substrate support surface for supporting the substrate W, and the annular region 111b is also called the ring support surface for supporting the ring assembly 112.

[0050] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is placed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic chuck electrode 1111b placed within the ceramic member 1111a. The electrostatic chuck electrode 1111b is also called a clamping electrode. In one embodiment, the electrostatic chuck electrode 1111b is electrically connected or coupled to a chuck power supply. The chuck power supply may be a DC power supply or an AC power supply. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Furthermore, other members surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have an annular region 111b. In this case, the ring assembly 112 may be placed on the annular electrostatic chuck or the annular insulating member, or on both the electrostatic chuck 1111 and the annular insulating member. In addition, at least one bias electrode, electrically connected or coupled to the power supply 31 and / or power supply 32 described later, may be placed within the ceramic member 1111a. In this case, at least one bias electrode functions as a lower electrode. Also, the conductive member of the base 1110 and the bias electrode in the ceramic member 1111a may function as multiple lower electrodes. In one embodiment, the first voltage generation unit 32a, which functions as a voltage pulse generation unit described later, is electrically connected or coupled to the bias electrode in the ceramic member 1111a, and the first RF generation unit 31a, described later, is electrically connected or coupled to the conductive member of the base 1110. Furthermore, the electrostatic chuck electrode 1111b may function as a lower electrode. Therefore, the substrate support portion 11 includes at least one lower electrode.

[0051] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one covering ring. The edge rings are formed of a conductive or insulating material, and the covering rings are formed of an insulating material.

[0052] The substrate support section 11 may also include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate W to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid, such as brine or gas, flows through the flow path 1110a. In one embodiment, the flow path 1110a is formed within the base 1110, and one or more heaters are arranged within the ceramic member 1111a of the electrostatic chuck 1111. The substrate support section 11 may also include a heat transfer gas supply section configured to supply heat transfer gas to the gap between the back surface of the substrate W and the central region 111a.

[0053] The showerhead 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas inlet ports 13c. The processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s through the plurality of gas inlet ports 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas introduction unit may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the side wall 10a.

[0054] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one processing gas to the shower head 13 from a corresponding gas source 21 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may include one or more flow modulation devices that modulate or pulse the flow rate of at least one processing gas.

[0055] The power supply system 30 includes a power supply 31 that is electrically connected to or coupled to the plasma processing chamber 10. In one embodiment, the power supply 31 is electrically connected to or coupled to the plasma processing chamber 10 via at least one impedance matcher. The impedance matcher may be a mechanically controlled matcher or an electronically controlled matcher. The power supply 31 is configured to supply at least one RF (Radio Frequency) signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates plasma from at least one processing gas supplied to the plasma processing space 10s. Thus, the power supply 31 can function as at least part of a plasma generation unit configured to generate plasma from one or more processing gases in the plasma processing chamber 10. In addition, by supplying a bias RF signal to at least one lower electrode, a bias potential is generated on the substrate W, and ionic components in the formed plasma can be drawn into the substrate W.

[0056] The power supply 31 includes a first RF generation unit 31a and a second RF generation unit 31b. The first RF generation unit 31a is electrically connected or coupled to at least one lower electrode and / or at least one upper electrode and is configured to generate a source RF signal (source RF power) to generate plasma in the plasma processing space 10s. In one embodiment, the first RF generation unit 31a is electrically connected or coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matcher. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generation unit 31a may be configured to generate a plurality of source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0057] The second RF generation unit 31b is electrically connected to or coupled to at least one lower electrode and is configured to generate a bias RF signal (bias RF power). In one embodiment, the second RF generation unit 31b is electrically connected to or coupled to at least one lower electrode via at least one impedance matcher. If the first RF generation unit 31a is electrically connected to or coupled to a lower electrode, the second RF generation unit 31b may be electrically connected to or coupled to the same lower electrode, or it may be electrically connected to or coupled to a different lower electrode. The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a lower frequency than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generation unit 31b may be configured to generate a plurality of bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0058] The power supply system 30 may also include a power supply 32 that is electrically connected to or coupled to the plasma processing chamber 10. The power supply 32 includes a first voltage generation unit 32a and a second voltage generation unit 32b. In one embodiment, the first voltage generation unit 32a is electrically connected to or coupled to at least one lower electrode and configured to generate a first voltage signal. The generated first voltage signal is applied to at least one lower electrode. In one embodiment, the second voltage generation unit 32b is electrically connected to or coupled to at least one upper electrode and configured to generate a second voltage signal. The generated second voltage signal is applied to at least one upper electrode.

[0059] In various embodiments, the first and / or second voltage signals may be pulsed. In this case, the first voltage generation unit 32a and / or the second voltage generation unit 32b function as voltage pulse generation units configured to generate a sequence of voltage pulses. Thus, the sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. In one embodiment, the sequence of voltage pulses has multiple cycles, each cycle including a burst of voltage pulses in a first period and a constant reference voltage in a second period. That is, in the sequence of voltage pulses, bursts of voltage pulses are repeated. The absolute value of the voltage level of the voltage pulse is greater than the absolute value of the voltage level of the reference voltage. The voltage pulse may have an arbitrary waveform having a rectangular, trapezoidal, triangular, or a combination thereof, and the arbitrary waveform may change over time. The voltage pulse may have positive polarity or negative polarity. The sequence of voltage pulses may also include one or more positive voltage pulses and one or more negative voltage pulses within one cycle. The first and second voltage generation units 32a and 32b may be provided in addition to the power supply 31, and the first voltage generation unit 32a may be provided in place of the second RF generation unit 31b.

[0060] The exhaust system 40 may be connected to, for example, a gas outlet 10e located at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 10s. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0061] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various processes described herein. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, some or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 is implemented, for example, by a computer 2a. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The functions implemented by the processing unit 2a1 described herein may be implemented in a circuit or processing circuitry, including a general-purpose processor, an application-specific processor, integrated circuits, ASICs (Application Specific Integrated Circuits), a CPU (Central Processing Unit), conventional circuitry, and / or a combination thereof, programmed to implement the functions described herein. A processor is considered a circuit or processing circuit, including transistors and other circuitry. A processor may be a programmed processor that executes a program stored in the storage unit 2a2. This program may be stored in the memory unit 2a2 in advance, or it may be retrieved via a medium when needed. The retrieved program is stored in the memory unit 2a2 and read from the memory unit 2a2 and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a, or it may be a communication line connected to the communication interface 2a3. The memory unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing device 1 via a communication line such as a LAN (Local Area Network).In this disclosure, circuits, units, and means are hardware programmed to perform or configured to perform the functions described. Such hardware may be any hardware described in this disclosure, or any hardware known to be programmed to perform or execute the functions described. If such hardware is a processor that is considered to be a type of circuit, such circuit, means, or unit is a combination of hardware and software used to constitute such hardware and / or processor.

[0062] In this description, the plasma processing apparatus (etching apparatus) 1 was explained using an etching apparatus as an example, which has opposing upper and lower electrodes and generates capacitively coupled plasma (CCP) between the electrodes to perform etching on the substrate W. The configuration of the etching apparatus is not limited to this, and other etching apparatuses, such as an etching apparatus that generates inductively coupled plasma (ICP) to perform etching on the substrate W, may also be used.

[0063] Although etching methods and substrate processing measures have been described above, this disclosure is not limited to the embodiments described above, and various modifications and improvements are possible within the scope of the gist of this disclosure as described in the claims. [Explanation of Symbols]

[0064] W board 200 Base material 210 Etching target film 215 recess 220 Interface layer 225 Aperture 230 Interfacial layer mask 241 SOC membrane 242 SOG membrane 243 Resist film 245 Aperture 250 Sediment 251 Carbon Hard Mask

Claims

1. A step of preparing a substrate having a silicon-containing film to be etched and an interface layer formed on the film to be etched and having an opening pattern, Fluorocarbon gas containing fluorine and carbon atoms and O ２ The process includes generating a plasma of a mixed gas with a gas as the processing gas, and etching the film to be etched through the opening while applying a negative bias voltage with an absolute value of 7000V or more to the substrate support on which the substrate is placed. Etching method.

2. The interface layer is a metal compound containing metal atoms, The aforementioned metal atom is It is at least one of the following: Be, Mg, Al, Ca, Sc, Ti, V, Co, Ni, Zn, Ga, Sr, Y, Zr, Nb, Ru, Pd, Cd, In, Sn, Ba, La, Ce, Nd, Eu, Gd, Er, Hf, Ta. The etching method according to claim 1.

3. The aforementioned interface layer is a metal oxide or metal nitride. The etching method according to claim 2.

4. The aforementioned interface layer is It is one of the following: indium gallium zinc oxide, aluminum oxide, or hafnium oxide. The etching method according to claim 3.

5. The aforementioned fluorocarbon gas is The ratio of the number of carbon atoms to the number of fluorine atoms is 0.5 or greater. The etching method according to claim 1.

6. The aforementioned fluorocarbon gas is C ４ F ８ , C ４ F ６ ,CH ２ F ２ It is either one of the following, or a mixture of either of the following gases. The etching method according to claim 5.

7. The aforementioned processing gas is The ratio of oxygen atoms to carbon atoms is 0.4 or greater and 0.6 or less. The etching method according to claim 1.

8. The film to be etched includes a silicon oxide film and / or a silicon nitride film. The etching method according to claim 1.

9. Plasma processing chamber and A substrate support section is provided within the plasma processing chamber to support the substrate, A gas supply unit that supplies processing gas, A plasma generation unit that generates plasma from the aforementioned processing gas, A bias power supply that applies a bias voltage to the substrate support portion, It comprises a control unit and, A step of preparing a substrate having a silicon-containing film to be etched and an interface layer formed on the film to be etched and having an opening pattern, Fluorocarbon gas containing fluorine and carbon atoms and O ２ The system is configured to perform the following steps: generating a plasma of the processing gas using a gas mixture as the processing gas, and etching the film to be etched through the opening while applying a negative bias voltage with an absolute value of 7000V or more to the substrate support portion. Etching equipment.

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