Manufacturing method for high electron mobility transistors

Abstract

This invention provides a method for manufacturing high-electron-mobility transistors. [Solution] A method for manufacturing a high electron mobility transistor includes the steps of: preparing a semiconductor substrate; forming a protective layer at a position corresponding to the gate opening above the semiconductor substrate; forming a coating layer above the semiconductor substrate and around the protective layer, removing the protective layer to form the gate opening; and forming a p-type layer above the gate opening and the coating layer, wherein the material of the coating layer is undoped, unintentionally doped, or n-type doped gallium nitride or aluminum gallium nitride. [Effects] This method simplifies the entire process, lowers technical hurdles, allows for individual control and acquisition of good threshold voltage (Vth) and on-resistance (Rds(ON)), and effectively improves product yield.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing transistors, and more particularly to a method for manufacturing high-electron-mobility transistors, but is not limited thereto. [Background technology]

[0002] In the semiconductor industry, high-voltage switching transistors such as high-electron mobility transistors (HEMTs), junction field-effect transistors (JFETs), and power metal-oxide-semiconductor field-effect transistors (power MOSFETs) are commonly used as semiconductor switching elements in high-voltage, high-power devices. Among these, high-electron mobility transistors, with their advantages such as high power density, high breakdown voltage, high output voltage, and high switching frequency, have become increasingly widely used transistors because they cause very little damage to the device even in high-voltage operating environments.

[0003] Specifically, the superior characteristics of high electron mobility transistors depend primarily on the material properties of GaN, such as a wide bandgap, a high critical electric field, and high carrier mobility. Furthermore, due to the polarization effect unique to GaN, AlGaN / GaN heterostructures can induce the formation of two-dimensional electron gases (2DEGs) in the interface region without doping. As a result, AlGaN / GaN HEMTs achieve high-current output operation while having very low on-resistance.

[0004] In practice, high electron-mobility transistors can be constructed as enhancement-mode semiconductor devices (E-mode), that is, as normally-off structures with a positive threshold voltage. For this purpose, a p-type layer containing a p-type dopant material is generally provided below the gate electrode of a high electron-mobility transistor. This depletes the two-dimensional electron gas when the device is not biased, and further enables the normally-off effect. Current methods for manufacturing the above structure typically involve forming the source and drain metals first, and then forming the p-type layer. Therefore, in order to pattern the p-type layer, it is necessary to remove a portion of the p-type layer using a special etching process. During this process, care must be taken not to over-etch the underlying layers or contaminate the electrode metals to prevent subsequent leakage current or failure of the device. The special etching process is, for example, atomic layer etching (ALE), which is a technique for removing thin layers of material using sequential self-limiting reactions. [Overview of the project]

[0005] The atomic layer etching process described in the prior art is very expensive, technically demanding, and extremely time-consuming. To ensure a sufficient threshold voltage (Vth) for the product, the thickness of the transistor barrier layer must not be excessive. However, the inventors have discovered that when manufacturing transistors using the above method, excessive etching can damage the surface of the barrier layer, potentially negatively impacting yield. Furthermore, the deepening of the defect region in the source, gate, and drain spacing can reduce the charge and increase the on-resistance (Rds(ON)) of the device. Based on this, the inventors propose the following technique: First, a protective layer is formed at the location where the gate of the barrier layer of the semiconductor substrate is to be formed. Next, based on the difference in materials between the protective layer and the coating layer, and the material properties of the protective layer itself, an undoped, unintentionally doped, or n-type doped coating layer is selectively formed around the protective layer. The protective layer is then removed to form the gate opening, and subsequently, a p-type layer is formed above the gate opening and the coating layer. This allows the protective layer to be removed using a relatively simple etching method to form a gate opening, simplifies the entire process by eliminating the need for patterning of the p-type layer, and reduces the adverse effect on on-resistance when the threshold voltage of the p-type layer is increased, as a specific coating layer is provided below the p-type layer. Based on this, the present invention allows for the individual control of the above-mentioned factors related to threshold voltage and on-resistance, and more specifically, the present invention not only avoids the problems of reduced yield and increased on-resistance, but also ensures a sufficient threshold voltage in the final product because the tolerance range for the barrier layer thickness is increased.

[0006] In view of this, one aspect of the present invention provides a method for manufacturing a high electron mobility transistor, comprising the steps of (a) preparing a semiconductor substrate including a channel layer and a barrier layer located above the channel layer; (b) forming a protective layer at a position corresponding to a gate opening above the semiconductor substrate; (c) forming a coating layer above the semiconductor substrate and around the protective layer, and removing the protective layer to form the gate opening; and (d) forming a p-type layer above the gate opening and the coating layer, wherein the material of the coating layer is undoped, unintentionally doped, or n-type doped gallium nitride or aluminum gallium nitride.

[0007] According to one embodiment of the present invention, the manufacturing method further includes: (e) patterning a first dielectric layer above the p-type layer such that the p-type layer is exposed at positions corresponding to the source opening and the drain opening, thereby defining an active region; (f) performing an etching process at positions corresponding to the source opening and the drain opening to form the source opening and the drain opening; (g) patterning an ohmic contact metal layer above the source opening and the drain opening, and alloying the ohmic contact metal layer; (h) patterning a second dielectric layer so as to cover a portion of the first dielectric layer; (i) patterning a first metal layer so as to cover positions corresponding to the source opening, the gate opening and the drain opening, and so as to cover a portion of the first dielectric layer and a portion of the second dielectric layer; and (j) patterning a second metal layer so as to cover positions corresponding to the source opening and the drain opening, and so as to cover a portion of the first metal layer.

[0008] According to one embodiment of the present invention, the length of the gate opening is 1.0 to 3.0 microns.

[0009] According to one embodiment of the present invention, the material of the protective layer is silicon nitride.

[0010] According to an embodiment of the present invention, the thickness of the protective layer is 20 to 50 nanometers.

[0011] According to an embodiment of the present invention, the protective layer is formed by using a low-pressure chemical vapor deposition method (Low Pressure CVD, LPCVD).

[0012] According to an embodiment of the present invention, the thickness of the coating layer is 50 to 150 nanometers.

[0013] According to an embodiment of the present invention, the material of the p-type layer is p-type doped gallium nitride.

[0014] According to an embodiment of the present invention, the thickness of the p-type layer is 70 to 100 nanometers.

[0015] According to an embodiment of the present invention, before forming the protective layer, the method further includes forming an in-situ dielectric layer above the barrier layer.

[0016] According to an embodiment of the present invention, the thickness of the in-situ dielectric layer is 2.0 to 3. nanometers.

[0017] According to an embodiment of the present invention, the material of the first dielectric layer is silicon nitride.

[0018] According to an embodiment of the present invention, the first dielectric layer is formed by using a low-pressure chemical vapor deposition method.

[0019] According to an embodiment of the present invention, the first dielectric layer covers a part of the p-type layer.

[0020] According to an embodiment of the present invention, the source opening and the drain opening are respectively a concave groove exposing the barrier layer or a concave groove exposing the channel layer.

[0021] According to an embodiment of the present invention, the process temperature for alloying the ohmic contact metal layer is 500 to 550 °C.

[0022] According to one embodiment of the present invention, the material of the second dielectric layer is silicon nitride.

[0023] According to one embodiment of the present invention, the second dielectric layer is formed using plasma-enhanced chemical vapor deposition (PECVD).

[0024] According to one embodiment of the present invention, the thickness of the second dielectric layer is 500 nanometers or less.

[0025] In summary, the manufacturing method for high-electron-mobility transistors provided by the present invention appropriately utilizes the differences and numerous advantages in the lattice matching characteristics of the protective layer, barrier layer, and coating layer. As a result, the protective layer can be removed using a relatively simple etching method to form the gate opening, and the entire process is simplified because patterning of the p-type layer is unnecessary. This not only avoids problems such as reduced yield and increased on-resistance, but also increases the tolerance range for the thickness of the barrier layer, thereby ensuring a sufficient threshold voltage in the final product. Furthermore, since a specific coating layer is provided below the p-type layer, the adverse effect on on-resistance when the threshold voltage of the p-type layer is increased can be mitigated. [Brief explanation of the drawing]

[0026] To facilitate understanding of the above and other objectives, features, advantages, and embodiments of the present invention, the accompanying drawings are described below.

[0027] [Figure 1] This is a flowchart of the steps for manufacturing a high-electron-mobility transistor according to one embodiment of the present invention. [Figure 2] This is a flowchart of the steps for manufacturing a high-electron-mobility transistor according to one embodiment of the present invention. [Figure 3] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 4A]These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 4B] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 4C] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 4D] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 5A] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 5B] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 6] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 7A] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 7B] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 8] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 9] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 10] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 11] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 12] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 13] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention. [Figure 14] These are schematic cross-sectional diagrams of high-electron-mobility transistor structures at different manufacturing stages of embodiments of the present invention.

[0028] In typical explanatory methods, various features and elements in the drawings are not depicted to actual scale, but rather are drawn in the most appropriate manner to represent the specific features and elements related to the present invention. Furthermore, identical or similar reference numerals in different drawings refer to similar elements and components. [Modes for carrying out the invention]

[0029] To provide a more detailed and complete description of the present invention, embodiments and specific examples of the present invention are described below, but these are not the only ways of carrying out or operating specific embodiments of the present invention. In this specification and the appended claims, unless otherwise specified in the context, “one” and “the said” may also be interpreted as plural. Also, in this specification and the appended claims, unless otherwise specified, “provided on something” can be considered to be in direct or indirect contact with the surface of said something by attachment or other means, and the definition of said surface should be determined based on the meaning of the content of this specification / paragraph and ordinary knowledge in the art to which the present invention belongs.

[0030] All numerical ranges and parameters used to limit the present invention are approximations; however, in this specification, relevant numerical values ​​in specific examples are shown as accurately as possible. Nevertheless, it is unavoidable that any numerical value inherently contains a standard deviation due to the individual test method. In this specification, “approximately” generally means that the actual numerical value is within ±10%, ±5%, ±1%, or ±0.5% of a particular numerical value or range. Alternatively, the term “approximately” means that the actual numerical value is within the acceptable standard error of the mean value considered by a person of ordinary skill in the art to which the present invention pertains. Therefore, unless otherwise stated, all numerical parameters disclosed in this specification and the appended claims are approximate values ​​that can be changed as desired. At least these numerical parameters should be understood as values ​​obtained using the indicated number of significant figures and common carry methods.

[0031] term As used herein, the term “high electron mobility transistor” may be a naturally normally-on structure with a negative threshold voltage, or it may be converted to a normally-off structure with a positive threshold voltage. On the other hand, the “semiconductor material” of the present invention may include a chemical compound comprising multiple elements, including but not limited to GaN, the elements being one or more elements belonging to different groups of the periodic table. These chemical compounds may include combinations of elements from Group 13 (i.e., the group containing boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl)) and elements from Group 15 (i.e., the group containing nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi)), or combinations of elements from Group 14 (i.e., the group containing elements such as carbon (C), silicon (Si), germanium (Ge), and tin (Sn)), such as silicon carbide (SiC) or silicon germanium alloys. Groups 13 to 15 of the periodic table may also be called Group III, Group IV, and Group V, respectively.

[0032] As used herein, the term “exposure” means a structure in which the surface of an object is not completely covered and in which one or more openings or grooves may be formed on the surface of the object. However, the specific definition should be determined based on the meaning of the context / paragraph of this specification and the ordinary knowledge of the art to which this specification belongs.

[0033] As used herein, the term “appropriate epitaxial growth or deposition process” includes, but is not limited to, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), atomic layer deposition (ALD), molecular layer deposition (MLD), plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), sputtering, etc., or combinations thereof.

[0034] As used herein, the term "photoresist" means a photosensitive material commonly used in the processing of integrated circuits and semiconductor devices, which, upon exposure to light or radiation such as ultraviolet, deep ultraviolet, electron beams, ion beams, or X-rays, exhibits differences in solubility, thereby allowing the surface of an object to be patterned according to the user's purpose. The photoresist can be divided into positive-type photoresist and negative-type photoresist. Positive-type photoresist yields a pattern identical to the reticle after exposure and development, while negative-type photoresist yields a pattern in the opposite phase.

[0035] As used herein, the term “mask / reticle” refers to a light-shielding device commonly used in the fabrication processes of integrated circuits and semiconductor devices, which can be used to define the surface pattern of an object in the process and to perform patterning in combination with a photoresist.

[0036] As used herein, the term “lift-off process” means using a negative photoresist intended to create a metallic region, forming the metal via a photoirradiation process, and then using an etching method to dissolve the sacrificial layer and remove any other metallic deposits that do not need to be created.

[0037] As used herein, the term “appropriate etching process (etching)” includes, but is not limited to, dry etching and wet etching. Here, dry etching includes physical impact methods such as reactive ion etching (RIE) and inductively coupled plasma etching (ICP), while wet etching is a chemical solution etching method well known in the art to which this invention belongs.

[0038] The following description of the present invention contains the necessary technical content to enable a person ordinary in the art to easily understand the invention, and other embodiments of the invention are also included in the claims of the invention if modifications and alterations are made to the invention to adapt it to different uses and circumstances without violating its spirit and scope.

[0039] Examples Figures 1 and 2 are flowcharts of the steps for manufacturing a high-electron-mobility transistor according to one embodiment of the present invention. Figures 3 to 14 are schematic cross-sectional diagrams of the high-electron-mobility transistor structure at different manufacturing stages of the embodiment of the present invention.

[0040] First, please refer to Figure 1. The present invention provides a method for manufacturing a high electron mobility transistor, comprising the steps of: preparing a semiconductor substrate (S100); forming a protective layer at a position corresponding to the gate opening above the semiconductor substrate (S102); forming a coating layer above the semiconductor substrate and around the protective layer (S104), removing the protective layer to form the gate opening; and forming a p-type layer above the gate opening and the coating layer (S106).

[0041] Please refer to Figure 2. The method for manufacturing a high electron mobility transistor of the present invention further includes: step S108, patterning a first dielectric layer above the p-type layer such that the p-type layer is exposed at positions corresponding to the source opening and the drain opening, thereby defining an active region; step S110, performing an etching process at positions corresponding to the source opening and the drain opening to form the source opening and the drain opening; step S112, patterning an ohmic contact metal layer above the source opening and the drain opening, and alloying the ohmic contact metal layer; step S114, patterning a second dielectric layer so as to cover a portion of the first dielectric layer; step S116, patterning a first metal layer so as to cover positions corresponding to the source opening, the gate opening, and the drain opening, and so as to cover a portion of the first dielectric layer and a portion of the second dielectric layer; and step S118, patterning a second metal layer so as to cover positions corresponding to the source opening and the drain opening, and so as to cover a portion of the first metal layer.

[0042] Figure 3 shows the semiconductor substrate 100 prepared in step S100, with reference to Figures 1 and 3 together. According to some embodiments of the present invention, the semiconductor substrate 100 is a structure based on an aluminum gallium nitride (AlGaN) / gallium nitride (GaN) high electron mobility transistor and is an epitaxially grown layer. Specifically, the semiconductor substrate 100 includes a channel layer 108 and a barrier layer 110 provided above the channel layer 108, and there is a dissimilar material interface between the channel layer 108 and the barrier layer 110, thereby enabling the formation of a two-dimensional electron gas region near the interface within the channel layer 108, and the two-dimensional electron gas region can form a conduction channel for free electrons when a bias is applied, thereby achieving, for example, the objective of electrically coupling a source electrode and a drain electrode. Furthermore, the material of the channel layer 108 is undoped or unintentionally doped GaN, and the thickness of the channel layer 108 is 50 to 1000 nm, for example, 50, 100, 150, 200, 250, 300, 350, 400, 450, 500, 550, 600, 650, 700, 750, 800, 850, 900, 950, 1000 nm, or any two of the above values, preferably 150 to 1000 nm. The material of the barrier layer 110 is undoped or unintentionally doped Al x Ga 1-x N is the range of approximately 0.1 to approximately 1, for example, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, or any two of the aforementioned values. The thickness of the barrier layer 110 is 10 to 40 nm, for example, 10, 15, 20, 25, 30, 35, 40 nm, or any two of the aforementioned values, preferably 10 to 20 nm.

[0043] According to a preferred embodiment of the present invention, the layered structure of the semiconductor substrate 100 is, from bottom to top, a base 102, a nucleation layer 104, a buffer layer 106, a channel layer 108, and a barrier layer 110. According to a more preferred embodiment, a surface layer (Cap layer, not shown) may be further included above the barrier layer 110, with a thickness of 1.5 to 2.0 nm, for example, in the range of 1.5, 1.6, 1.7, 1.8, 1.9, 2.0 nm, or any two of the aforementioned values. Here, the base 102 includes a wafer, which may be, for example, a semi-insulating substrate or an un-intentional doped substrate, and is a wafer made from a high-quality single-crystal silicon semiconductor material such as sapphire, GaN, GaAs, silicon crystal, silicon carbide (SiC) polymorph (including wurtzite), AlN, InP, or a base-like material used in semiconductors. The nucleating layer 104 may contain an undoped or unintentionally doped AlN compound. The buffer layer 106 is provided to compensate for mismatches between layers and contains an undoped, unintentionally doped, or carbon-doped GaN.

[0044] Figures 4A to 4D show the structural change in step S102, where a protective layer 200A is formed at a position corresponding to the gate opening above the semiconductor substrate 100, with reference to Figures 1 and 4A to 4D. First, the material for the protective layer 200A is provided above the semiconductor substrate 100 by an appropriate epitaxial growth or deposition process. Here, the protective layer 200A needs to be able to withstand high-temperature epitaxial processes and needs to have different lattice matching characteristics from the barrier layer 110, thereby allowing for selectivity in the manufacturing process. Furthermore, the protective layer 200A needs to avoid the generation of excessive stress and should not react with the barrier layer 110. Preferably, the process for providing the protective layer 200A uses a low-pressure chemical vapor deposition method, and the process temperature is greater than 800°C, for example, in the range of 850, 900, 950, 1000, 1050, 1100°C, or any two of the aforementioned values. The material of the protective layer 200A is silicon oxide (SiO2), silicon oxynitride (SiON) x ), or silicon nitride (SiN x The material is at least one of the following (x is approximately 0.1 to 1.0), preferably silicon nitride. The thickness D1 of the protective layer 200A is 20 to 75 nm, for example, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75 nm, or in the range between any two of the above values, preferably 20 to 50 nm.

[0045] Next, the subsequent gate openings are protected by patterning the protective layer 200A using a mask 300A with an appropriate etching process to specifically provide the gate electrodes on the semiconductor substrate 100 at the locations where they are to be formed. After removing the remaining portions of the protective layer 200A, the mask 300A is then removed. More specifically, after patterning, the distance of the protective layer 200A corresponding to each individual gate opening must be 7 microns or more, for example, 7, 8, 9, or 10 microns, in order to avoid pile-up at the edges when forming material in areas without the protective layer 200A. Preferably, the distance is equivalent to the gate width (Wg) of the subsequently manufactured element.

[0046] Figures 5A and 5B show the structural change in step S104, in which a coating layer 112 is formed around the protective layer 200A above the semiconductor substrate 100 to remove the protective layer 200A, with reference to Figures 1, 5A, and 5B. Here, the material for the coating layer 112 is provided above the semiconductor substrate 100 by an appropriate epitaxial growth or deposition process, preferably using metal-organic chemical vapor deposition (MOCVD). The coating layer 112 can be used to provide a large transconductance upper limit, saturation current, current amplification cutoff frequency, and maximum oscillation frequency, and can reduce drain-source on-resistance (Rds(ON)), and its material is undoped, unintentionally doped, or n-type doped gallium nitride or aluminum gallium nitride, preferably the material for the coating layer 112 is undoped or unintentionally doped aluminum gallium nitride (Al x Ga 1-x N, where x is in the range of approximately 0.1 to approximately 1, and preferably is greater than the Al mole fraction of the barrier layer 110 material.

[0047] Due to the lattice matching characteristics of the material of the coating layer 112, it is selectively deposited on surfaces not covered by the protective layer 200A; in other words, the coating layer 112 is selectively formed around the protective layer 200A. Although not bound by any particular theory, the coating layer 112 can also be an extension of the barrier layer 110, and can further increase the charge density of the channel layer 108. Preferably, this allows for individual control of the amount of charge within the transistor, which is advantageous in obtaining a desired breakdown voltage. This allows the barrier layer 110 to be thinned at the same time, and further, the transistor manufactured later can have a higher threshold voltage (Vth). Specifically, the thickness of the barrier layer may be 12 to 25 nm, for example, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 nm, or any two of the aforementioned values. Next, the protective layer 200A is selectively removed to expose the location on the semiconductor substrate 100 where the gate electrode is to be formed and to form the gate opening 202. More specifically, the protective layer 200A can be selectively removed by using an appropriate etching process based on the structural and compositional differences between the protective layer 200A and the coating layer 112. This allows the gate opening 202 to be formed in a simpler way than in the prior art. According to some embodiments of the present invention, the length of the gate opening 202 is 1.0 to 3.0 microns, for example, 1.0, 1.2, 1.4, 1.6, 1.8, 2.0, 2.2, 2.4, 2.6, 2.8, 3.0 microns, or any two of the above values.

[0048] FIG. 6 shows the situation of the structural change of forming the p-type layer P above the gate opening 202 and the coating layer 112 in step S106. Refer to FIGS. 1 and 6 together. Here, the material of the p-type layer P is provided above the semiconductor substrate 100 by an appropriate epitaxial growth or deposition process. Preferably, the process uses metal organic chemical vapor deposition, and the process temperature is 800 to 1200 ° C., for example, 850, 900, 950, 1000, 1050, 1100, 1150, 1200 ° C., or in the range between any two of the above-mentioned numerical values.

[0049] From the perspective of materials, the p-type layer P may include p-type gallium nitride (p-GaN), p-type aluminum gallium nitride (p-AlGaN), or p-type silicon carbide (p-SiC). Preferably, the p-type layer P includes p-type gallium nitride (p-GaN), preferably includes a p-type doping substance such as Mg, and the doping concentration is 3×10 17 to 3×10 19 cm -3 . Due to its lattice matching characteristics, the p-type layer P is deposited entirely above the gate opening 202 and the coating layer 112 during formation. According to some embodiments of the present invention, the thickness of the p-type layer P is 70 to 100 nm, for example, 70, 75, 80, 85, 90, 95, 100 nm, or in the range between any two of the above-mentioned numerical values, preferably 70 to 85 nm. Without being bound by a specific theory, if the thickness of the p-type layer P is too thin, the forward bias that the device can withstand will be insufficient, so its application may be limited. On the other hand, if the thickness is too thick, the distance between the gate and the channel layer 108 will become too large, so the numerical value of the threshold voltage may change in an overly negative direction. According to some other embodiments of the present invention, the material of the p-type layer P is p-type gallium nitride, and its surface doping concentration is 2×10 12 ~5×10 12 cm -2 , for example, 2.0×10 12 , 2.5×10 12 , 3.0×10 12 , 3.5×10 12, 4.0×10 12 , 4.5×10 12 , 5.0×10 12 cm -2 , or a range between any two of the aforementioned numbers.

[0050] Please refer to Figures 5A to 6. In this invention, the coating layer 112 is provided before the p-type layer P is provided, so structurally, the coating layer 112 is provided between the p-type layer P and the barrier layer 110. This allows the provision of the coating layer 112 to reduce the adverse effect of the p-type layer P on the on-resistance of regions other than the gate in the channel layer 108 below, although this is not constrained by any particular theory. Based on this, according to some embodiments of the present invention, the thickness of the coating layer 112 is 50 to 150 nm, for example, in the range of 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150 nm, or any two of the aforementioned values, and preferably the thickness of the coating layer 112 is 100 to 150 nm, which increases the amount of charge in the channel layer 108 and increases the distance between the p-type layer P and the channel layer 108, further reducing the effect of the p-type layer P.

[0051] According to some embodiments of the present invention, a further material layer (not shown) may be provided below the gate opening 202 of the p-type layer P, which can increase the forward bias that the entire device can withstand and maintain the threshold voltage within an appropriate range. Although not bound by any particular theory, the material layer needs to possess both a high breakdown field and a high dielectric constant. If it has only a high breakdown field but not a high dielectric constant, the material layer can increase the forward bias that the entire device can withstand, but the threshold voltage will shift excessively in the negative direction. If it has only a high dielectric constant but not a high breakdown field, it may not be able to effectively increase the forward bias that the device can withstand. Specifically, the material layer preferably comprises SiO2 or SiN, and more preferably SiO2. The thickness of the material layer is preferably 8 to 20 nm, for example, in the range of 8, 10, 12, 14, 16, 18, 20 nm, or any two of the aforementioned values. More preferably, the material layer comprises SiO2 or SiN formed by low-pressure chemical vapor deposition, and more preferably, SiO2 formed by low-pressure chemical vapor deposition. Although not bound by any particular theory, a material layer formed by low-pressure chemical vapor deposition can have a denser structure, and thus can further increase the critical breakdown field of the material.

[0052] According to some other embodiments of the present invention, the thickness of the protective layer 200A is greater than the thickness of the coating layer 112, and preferably the thickness of the coating layer 112 is half or less of the thickness of the protective layer 200A.

[0053] Please also refer to Figures 4A to 6. According to some preferred embodiments of the present invention, an in situ dielectric layer (not shown) made of the same material may be formed on the semiconductor substrate 100 before forming the protective layer 200A, with a thickness of 2.0 to 3.0 nm, for example, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3.0 nm, or in the range between any two of the aforementioned values. Although not bound by any particular theory, the in situ dielectric layer can not only avoid contamination of the barrier layer 110 without affecting the threshold voltage, but also facilitate the subsequent formation of the p-type layer. Specifically, if an in-situ dielectric layer is not formed above the barrier layer 110 before forming the protective layer 200A, when forming the coating layer 112 above the barrier layer 110 and around the protective layer 200A in the MOCVD process, the MOCVD process temperature is high (usually 1000-1100°C). As a result, a reaction occurs at the interface between the protective layer 200A, formed by LPCVD at a lower process temperature (usually 800-850°C), and the barrier layer 110. This makes it difficult to completely remove the protective layer 200A afterward, and furthermore, makes it difficult to grow the subsequent p-type layer into the gate opening.

[0054] Figures 7A, 7B, and 8 sequentially show the structural changes that define the active region M by patterning the first dielectric layer 200B above the p-type layer P in step S108. Please also refer to Figures 2, 7A, 7B, and 8. First, the material for the first dielectric layer 200B is deposited over the semiconductor substrate 100 using a suitable epitaxial growth or deposition process. Preferably, the process uses low-pressure chemical vapor deposition, and the process temperature is greater than 800°C, for example, 850, 900, 950, 1000, 1050, or 1100°C. The material for the first dielectric layer 200B is preferably silicon nitride (SiO2), silicon oxynitride (SiON) x ), or silicon nitride (SiN x) is at least one of the following (x is approximately 0.1 to 1), and by being used as a field plate in a high electron mobility transistor, the electric field distribution can be adjusted to be more uniform, further improving the breakdown voltage of the device and reducing leakage current. The thickness of the first dielectric layer 200B is 150 to 300 nm, for example, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250, 260, 270, 280, 290, 300 nm, or in the range between any two of the above values.

[0055] Next, the first dielectric layer 200B is patterned using an appropriate etching process so that it covers a portion of the p-type layer P, defining the positions intended to be the source and drain electrodes, and the active region M is further defined using an appropriate etching process so that each element can operate independently without interfering with each other. According to some embodiments of the present invention, the step of defining the active region M may involve changing the resistance of the layers using an appropriate ion implantation process in addition to an appropriate etching process, and further defining the active region M, or preferably, the step of defining the active region M may use a combination of these two processes.

[0056] Figure 9 shows the structural changes that occur in step S110 to form the source opening 204 and the drain opening 206; please refer to Figures 2 and 9 together. In this step, the source opening 204 and the drain opening 206 are formed by further etching the barrier layer 110 or the channel layer 108, respectively, at the locations where the source and drain electrodes are to be formed in the first dielectric layer 200B, using an appropriate etching process (the figure shows the etching process up to the channel layer 108). Specifically, both the source opening 204 and the drain opening 206 are grooves.

[0057] Figures 10 and 11 show the structural change in step S112, where an ohmic contact metal layer 210A is pattern-formed above the source opening 204 and the drain opening 206, and the ohmic contact metal layer 210A is alloyed. Please also refer to Figures 2 and 9-11. Here, the ohmic contact metal layer 210A is formed using an appropriate epitaxial growth or deposition process with an appropriate mask, then the mask is removed, and the objective is achieved to further limit the formation of the ohmic contact metal layer 210A to the source opening 204 and the drain opening 206. Furthermore, the ohmic contact metal layer 210A formed on the source opening 204 and the drain opening 206 is alloyed by an alloying process (shown in Figure 11), and then the source electrode 204E and drain electrode 206E are formed, respectively, to form ohmic contacts in the high electron mobility transistor. According to some preferred embodiments of the present invention, the bottom surfaces of the source opening 204 and the drain opening 206 expose the channel layer 108, so the alloying process can be carried out at a substantially lower process temperature than conventional processes, preferably 500-550°C, for example, 500, 510, 520, 530, 540, 550°C, or in the range between any two of the aforementioned values. According to yet another preferred embodiment of the present invention, the ohmic contact may be formed by forming a highly doped n-type gallium nitride layer (not shown) on the bottom surfaces of the source opening 204 and the drain opening 206, respectively, with a carrier concentration of preferably 10 19 cm -3 More preferably, molecular beam epitaxy (MBE) is used, with a carrier concentration of 10 20 cm -3The ultra-high pressure is set to allow for the replacement or simplification of the alloying process. According to some embodiments of the present invention, the ohmic contact metal layer 210A can be made from any suitable conductive material capable of forming an ohmic contact or other conductive joint, preferably titanium (Ti), aluminum (Al), nickel (Ni), tantalum (Ta), molybdenum (Mo), gold (Au), or a combination thereof.

[0058] Figure 12 shows the structural change that occurs when the second dielectric layer 200C is patterned in step S114; please refer to Figures 2 and 12 together. After the source electrode 204E and the drain electrode 206E are formed, the material for the second dielectric layer 200C is deposited over the semiconductor substrate 100 using an appropriate epitaxial growth or deposition process, and then the second dielectric layer 200C is patterned using an appropriate etching process so as to cover a portion of the first dielectric layer 200B. According to some embodiments of the present invention, the second dielectric layer 200C is formed using plasma-enhanced chemical vapor deposition (PECVD). According to some other embodiments of the present invention, the material for the second dielectric layer 200C may be the same as or different from the material for the first dielectric layer 200B, preferably silicon oxide (SiO2) or silicon oxynitride (SiON). x , or silicon nitride SiN x It is at least one of the (x is approximately 0.1 to 1) and can be used as a field plate in a high electron mobility transistor. According to a more preferred embodiment of the present invention, the first dielectric layer 200B and the second dielectric layer 200C are made of different materials, for example, the material of the first dielectric layer 200B is SiN xThe material of the second dielectric layer 200C is SiO2, which allows for selective etching by utilizing the difference between the two materials when patterning the second dielectric layer 200C. The thickness of the second dielectric layer 200C is less than 500 nm, preferably 200 to 300 nm, for example, in the range of 200, 210, 220, 230, 240, 250, 260, 270, 280, 290, 300 nm or any two of the aforementioned values. Furthermore, the region of the second dielectric layer 200C that covers a portion of the first dielectric layer 200B is substantially located between the planned gate formation location and the drain electrode 206E, however, the specific size of the covered region is not limited in this application.

[0059] Figure 13 shows the structural change in step S116 where the first metal layer 210B is patterned; please refer to Figures 2 and 13 together. In this step, the first metal layer 210B is patterned so as to cover the p-type layer P, a portion of the first dielectric layer 200B, a portion of the second dielectric layer 200C, and the ohmic contact metal layer 210A. Specifically, the objective is to form the first metal layer 210B using an appropriate epitaxial growth or deposition process with an appropriate mask, then remove the mask, and further pattern the first metal layer 210B. More specifically, the first metal layer 210B covers the p-type layer P to form the gate electrode 202E, and simultaneously covers a portion of the first dielectric layer 200B, a portion of the second dielectric layer 200C, and the ohmic contact metal layer 210A, however, the specific size of the covered area is not limited in this application. According to some embodiments of the present invention, the first metal layer 210B can be made from any conductive material that can bias or control the semiconductor device, preferably nickel (Ni), gold (Au), or a combination thereof, or zirconium (Zr), gold (Au), or a combination thereof.

[0060] Figure 14 shows the structural changes that occur when the second metal layer 220 is patterned in step S118; please refer to Figures 2 and 14 together. After step S116 is performed, the second metal layer 220 and a jumper layer (not shown) are further patterned. Both the second metal layer 220 and the jumper layer are formed by a suitable epitaxial growth or deposition process, patterned using a specific mask and / or photoresist, and further provided only in areas other than the gate electrode 202E. The second metal layer 220 is for electrically connecting the same electrodes of different elements and is made from any suitable conductive material. The jumper layer is used as an electrical insulating layer between different electrodes to prevent the different electrodes from conducting in undesirable areas; therefore, any suitable non-conductive material, such as a silicon-containing material, is used.

[0061] According to some embodiments of the present invention, after performing the above steps, a passivation layer (not shown) may be further patterned, preferably. The passivation layer is formed by a suitable epitaxial growth or deposition process and patterned using a specific mask and photoresist, and is made from an organic / inorganic dielectric material, preferably SiO2, SiON x , or SiN x It may be at least one of the following (x is approximately 0.1 to 1).

[0062] In summary, the manufacturing method for high-electron-mobility transistors provided by the present invention appropriately utilizes the differences and numerous advantages in the lattice matching characteristics of the protective layer, barrier layer, and coating layer. As a result, the protective layer can be removed by a relatively simple etching method to form the gate opening, and the overall process is simplified because patterning of the p-type layer is unnecessary. Furthermore, problems of reduced yield and increased on-resistance can be avoided, and the tolerance range for the barrier layer thickness is increased, ensuring a sufficient threshold voltage for the final product. In addition, since the coating layer is provided below the p-type layer, the n-type carriers in the coating layer can compensate for the adverse effect on on-resistance when the threshold voltage of the p-type layer is increased. Therefore, the manufacturing method for high-electron-mobility transistors provided by the present invention can effectively reduce costs and working time compared to conventional techniques, lower the technical hurdles of the process, and improve product yield.

[0063] Although the present invention has been described in detail above, the above is merely a preferred embodiment of the present invention and is not intended to limit the scope of the invention. That is, any equivalent modifications and alterations that can be made by a person with ordinary skill in the art to which the present invention pertains, without departing from the spirit and scope of the invention, are still within the scope of protection of the present invention. [Explanation of Symbols]

[0064] 100 semiconductor substrates 102 Base 104 Nucleation layer 106 Buffer layer 108 channel layer 110 Barrier layer 112 Covering layer 200A protective layer 200B First Dielectric Layer 200C Second Dielectric Layer 202 Gate opening 202E Stamp 204 Source opening 204E Source Electrode 206 Drain opening 206E Drain Electrode 210A Ohmic Contact Metal Layer 210B 1st metal layer 220 2nd metal layer 300A Mask M Active Area P p-type layer S100~S118 Step

Claims

1. (a) A step of preparing a semiconductor substrate including a channel layer and a barrier layer located above the channel layer, (b) The step of forming a protective layer at a position corresponding to the gate opening above the semiconductor substrate, (c) The steps of forming a coating layer on top of the semiconductor substrate and around the protective layer, and removing the protective layer to form the gate opening, (d) The step of forming a p-type layer above the gate opening and the coating layer, A method for manufacturing a high electron mobility transistor, wherein the material of the coating layer is undoped, unintentionally doped, or n-type doped gallium nitride or aluminum gallium nitride.

2. (e) A step of defining the active region by patterning a first dielectric layer above the p-type layer such that the p-type layer is exposed at positions corresponding to the source opening and drain opening, (f) A step of performing an etching process at positions corresponding to the source opening and the drain opening to form the source opening and the drain opening, (g) A step of forming an ohmic contact metal layer in a pattern above the source opening and the drain opening, and alloying the ohmic contact metal layer, (h) The step of forming a pattern of a second dielectric layer so as to cover a part of the first dielectric layer, (i) A step of patterning a first metal layer so as to cover the positions corresponding to the source opening, the gate opening, and the drain opening, and to cover a part of the first dielectric layer and a part of the second dielectric layer, (j) The manufacturing method according to claim 1, further comprising the step of patterning a second metal layer so as to cover the positions corresponding to the source opening and the drain opening and to cover a portion of the first metal layer.

3. The manufacturing method according to claim 1, wherein the length of the gate opening is 1.0 to 3.0 microns.

4. The manufacturing method according to claim 1, wherein the material of the protective layer is silicon nitride.

5. The manufacturing method according to claim 1, wherein the thickness of the protective layer is 20 to 50 nanometers.

6. The manufacturing method according to claim 1, wherein the protective layer is formed using low-pressure chemical vapor deposition (LPCVD).

7. The manufacturing method according to claim 1, wherein the thickness of the coating layer is 50 to 150 nanometers.

8. The manufacturing method according to claim 1, wherein the material of the p-type layer is p-doped gallium nitride.

9. The manufacturing method according to claim 1, wherein the thickness of the p-type layer is 70 to 100 nanometers.

10. The manufacturing method according to claim 1, further comprising the step of forming an in situ dielectric layer above the barrier layer before forming the protective layer.

11. The manufacturing method according to claim 10, wherein the thickness of the in situ dielectric layer is 2.0 to 3.0 nanometers.

12. The manufacturing method according to claim 2, wherein the material of the first dielectric layer is silicon nitride.

13. The manufacturing method according to claim 2, wherein the first dielectric layer is formed using a low-pressure chemical vapor deposition method.

14. The manufacturing method according to claim 2, wherein the first dielectric layer covers a portion of the p-type layer.

15. The manufacturing method according to claim 2, wherein the source opening and the drain opening are, respectively, grooves for exposing the barrier layer or grooves for exposing the channel layer.

16. The manufacturing method according to claim 2, wherein the process temperature for alloying the ohmic contact metal layer is 500 to 550°C.

17. The manufacturing method according to claim 2, wherein the material of the second dielectric layer is silicon nitride.

18. The manufacturing method according to claim 2, wherein the second dielectric layer is formed using plasma-enhanced chemical vapor deposition (PECVD).

19. The manufacturing method according to claim 2, wherein the thickness of the second dielectric layer is 500 nanometers or less.

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