Semiconductor device, system board, and calculation method

Abstract

To provide a semiconductor device that enables good communication between chips. [Solution] The semiconductor device comprises a first chip having a plurality of arithmetic units, and a second chip arranged adjacent to the first chip and having a plurality of arithmetic units, wherein the first chip transfers first data to the second chip, the second chip transfers second data to the first chip, the second chip detects errors in the first data, the first data is used for arithmetic operations on the neural network by the plurality of arithmetic units of the second chip, the second data is used for arithmetic operations on the neural network by the plurality of arithmetic units of the first chip, and the layout design of the first chip is the same as the layout design of the second chip.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a system board, and an arithmetic method.

Background Art

[0002] A multi-chip module type semiconductor device in which a plurality of chips are mounted on a substrate is known. For example, in a multi-chip module in which a plurality of chips are arranged on a substrate such as a silicon interposer, the chips are electrically connected to each other using wirings formed in the wiring layer of the substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] An embodiment of the present invention aims to provide a semiconductor device capable of performing good communication between chips.

Means for Solving the Problems

[0005] To achieve the above object, a semiconductor device according to an embodiment of the present invention includes a first chip having a plurality of arithmetic units, and a second chip disposed adjacent to the first chip and having a plurality of arithmetic units. The first chip transfers first data to the second chip, and the second chip transfers second data to the first chip. The second chip detects an error in the first data. The first data is used for arithmetic operations related to a neural network by the plurality of arithmetic units of the second chip, and the second data is used for arithmetic operations related to the neural network by the plurality of arithmetic units of the first chip. The layout design of the first chip is the same as the layout design of the second chip. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram showing examples of semiconductor devices in a batch of semiconductor devices. [Figure 2] Figure 1 is a block diagram showing an example of a transfer circuit and its surrounding circuitry. [Figure 3] This is a schematic diagram illustrating an example of connecting the bumps on the chip shown in Figure 1 to each other with signal lines (wiring). [Figure 4] As a comparative example, this block diagram shows an example where two chips located diagonally opposite each other are connected by a signal line, without providing the transfer circuit shown in Figure 1 on each chip. [Figure 5] This is a block diagram showing an example of a semiconductor device in another embodiment of the present invention. [Figure 6] This is a block diagram showing an example of a semiconductor device in another embodiment of the present invention. [Figure 7] Figure 5 is a perspective view showing an example of a system board on which the semiconductor device shown in Figure 5 is mounted. [Figure 8] This is a block diagram showing an example of a semiconductor device in another embodiment of the present invention. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described in detail below with reference to the drawings. In the following, symbols indicating signal lines will also be used as signal names (data names). Unless otherwise specified, the following descriptions will be from a plan view (for example, when viewed in the direction in which the substrate BRD shown in Figure 1 and the chips CP (CP1-CP4) arranged and mounted on the substrate BRD overlap).

[0008] Figure 1 is a block diagram showing an example of a semiconductor device in one embodiment of the present invention. The semiconductor device SEM1 shown in Figure 1 has four semiconductor chips CP (the first chip CP1, the second chip CP2, the third chip CP3, and the fourth chip CP4, which are roughly square-shaped (a type of rectangle) with four sides and arranged in a 2x2 grid in a plan view on the substrate BRD. In other words, each of the chips CP1-CP4 is located at a different position on the substrate BRD in a plan view.

[0009] For example, each chip CP1-CP4 is connected to the terminals of the substrate BRD via bumps provided on the back surface, which is the side facing the substrate BRD. Note that other components (electronic components, mechanical components) besides chips CP1-CP4 may be mounted on the substrate BRD. Furthermore, each chip CP1-CP4 may have multiple arithmetic units, each containing an arithmetic unit and memory. The arithmetic units may be multiply-accumulate units or dot-product units, etc.

[0010] Chips CP1 and CP3 are located on the first diagonal D1, which is one diagonal of the rectangular substrate BRD that forms the placement area for chips CP1-CP4, while chips CP2 and CP4 are located on the second diagonal D2, which is the other diagonal of the substrate BRD. Hereinafter, the first diagonal D1 and the second diagonal D2 may be simply referred to as diagonal D1 and D2, respectively. Also, when diagonal D1 and D2 are described without distinction, they may be referred to as diagonal D. In this embodiment, the shape of the outer shape of the substrate BRD in plan view and the shape of the placement area for chips CP1-CP4 are the same. That is, the diagonals of the substrate BRD and the diagonals D1 and D2 of the placement area for chips CP1-CP4 are the same. Furthermore, in this specification, when a chip CP is said to be located on the diagonal D of the substrate BRD, it means that the chip CP, as positioned in a plan view, coincides with the diagonal D of the substrate BRD, and is not limited to the corners of the chip CP being located on the diagonal D of the BRD.

[0011] Chip CP1 has an internal circuit INT1 and a transfer circuit TR1, chip CP2 has an internal circuit INT2 and a transfer circuit TR2, chip CP3 has an internal circuit INT3 and a transfer circuit TR3, and chip CP4 has an internal circuit INT4 and a transfer circuit TR4. Hereafter, each of the internal circuits INT1-INT4 may be referred to as internal circuit INT, and each of the transfer circuits TR1-TR4 may be referred to as transfer circuit TR.

[0012] The internal circuit INT1 of the first chip CP1 and the internal circuit INT2 of the second chip CP2, whose respective sides face each other and are adjacent, are connected via signal lines S12 and S21 provided on the substrate BRD. The first chip CP1 has an input / output circuit IO12 that inputs and outputs signals such as data to and from the signal lines S12 and S21, and the second chip CP2 has an input / output circuit IO21 that inputs and outputs signals such as data to and from the signal lines S12 and S21.

[0013] The internal circuit INT2 of the second chip CP2 and the internal circuit INT3 of the third chip CP3, whose respective sides face each other and are adjacent, are connected via signal lines S23 and S32 provided on the substrate BRD. The second chip CP2 has an input / output circuit IO23 that inputs and outputs signals such as data to and from the signal lines S23 and S32, and the third chip CP3 has an input / output circuit IO32 that inputs and outputs signals such as data to and from the signal lines S23 and S32.

[0014] The internal circuit INT3 of the third chip CP3 and the internal circuit INT4 of the fourth chip CP4, whose respective sides face each other and are adjacent, are connected via signal lines S34 and S43 provided on the substrate BRD. The third chip CP3 has an input / output circuit IO34 that inputs and outputs signals such as data to and from the signal lines S34 and S43, and the fourth chip CP4 has an input / output circuit IO43 that inputs and outputs signals such as data to and from the signal lines S34 and S43.

[0015] The internal circuit INT4 of the fourth chip CP4, which is adjacent to the first chip CP1 with each side facing each other, and the internal circuit INT1 of the first chip CP1 are connected via signal lines S41 and S14 provided on the substrate BRD. The fourth chip CP4 has an input / output circuit IO41 that inputs and outputs signals such as data to signal lines S41 and S14, and the first chip CP1 has an input / output circuit IO14 that inputs and outputs signals such as data to signal lines S41 and S14. Each signal line S12, S21, S23, S32, S34, S43, S41, and S14 is connected, for example, to a bump BP (Figure 3) provided on each chip CP. In the following, when various signal lines are described without distinction, they may be referred to as signal line S.

[0016] On the other hand, the first chip CP1 and the third chip CP3, whose respective corners are positioned opposite each other and which are located on the first diagonal D1 of the substrate BRD, are connected via a signal line S13a provided on the substrate BRD, the first transfer circuit TR2 of the second chip CP2, and a signal line S13b provided on the substrate BRD. Furthermore, the third chip CP3 and the first chip CP1 are connected via a signal line S31a provided on the substrate BRD, the second transfer circuit TR4 of the fourth chip CP4, and a signal line S31b provided on the substrate BRD.

[0017] The second chip CP2 and the fourth chip CP4, whose respective corners are positioned opposite each other and which are located on the second diagonal D2 of the substrate BRD, are connected via a signal line S24a provided on the substrate BRD, the third transfer circuit TR3 of the third chip CP3, and a signal line S24b provided on the substrate BRD. The fourth chip CP4 and the second chip CP2 are connected via a signal line S42a provided on the substrate BRD, the fourth transfer circuit TR1 of the first chip CP1, and a signal line S42b provided on the substrate BRD. Hereafter, the first transfer circuit TR2, the second transfer circuit TR4, the third transfer circuit TR3, and the fourth transfer circuit TR1 may simply be referred to as transfer circuits TR2, TR4, TR3, and TR1, respectively.

[0018] With the above configuration, the semiconductor device SEM1 can mutually communicate signals such as data among the four chips CP1 - CP4. Therefore, for example, when performing calculations using a plurality of arithmetic units mounted on each of the chips CP1 - CP4, the data and calculation results used by the arithmetic units can be input to and output from all the other chips CP. Thus, the semiconductor device SEM1 is suitable for, for example, machine learning that performs data processing using a large number of data and a large number of parameters, particularly deep learning using a neural network.

[0019] The arrows attached to each signal line S indicate the transfer direction of the signal transmitted on the signal line S, and the symbol " / " attached to each signal line S indicates that the signal line S is composed of a plurality of bits. The signal S transmitted on the signal line S includes data, a clock, and the like. The number of bits of the data is not particularly limited, but may be about several tens of bits to 100 bits.

[0020] The transfer circuit TR1 transfers the signal S42a transmitted from the internal circuit INT4 of the chip CP4 to the internal circuit INT2 of the chip CP2 as the signal S42b. The transfer circuit TR2 transfers the signal S13a transmitted from the internal circuit INT1 of the chip CP1 to the internal circuit INT3 of the chip CP3 as the signal S13b. The transfer circuit TR3 transfers the signal S24a transmitted from the internal circuit INT2 of the chip CP2 to the internal circuit INT4 of the chip CP4 as the signal S24b. The transfer circuit TR4 transfers the signal S31a transmitted from the internal circuit INT3 of the chip CP3 to the internal circuit INT1 of the chip CP1 as the signal S31b.

[0021] And in the arrangement regions of the four chips CP1 - CP4, a data transfer method is realized in which data is transferred from one of the two chips CP located on one diagonal D to the other through a transfer circuit TR provided in one of the two chips CP not located on one diagonal D.

[0022] For example, signal line (wiring) S13a can be provided between the opposing sides of chips CP1 and CP2. Similarly, other signal lines S24a, S31a, S42a, S42b, S13b, S24b, and S31b can also be provided between the opposing sides of chip CP. Therefore, compared to connecting the corner between two chips CP located on diagonal line D with diagonal wiring, the number of signal lines S13a, S24a, S31a, S42a, S42b, S13b, S24b, and S31b that can be wired can be increased.

[0023] Furthermore, for example, the multiple signal lines S13a wired between the opposing sides of chips CP1 and CP2 can be made to the same length. By suppressing variations in the length of the signal lines S13a, the skew of the signals transmitted through the signal lines S13a can be reduced, which facilitates timing design and contributes to improving the performance of the semiconductor device SEM1. The same applies to the other signal lines S24a, S31a, S42a, S42b, S13b, S24b, and S31b.

[0024] Furthermore, signal lines S13a, S24a, S31a, S42a, S42b, S13b, S24b, and S31b can be routed using the same rules as those for signal lines S12 and S21 connecting chips CP1 and CP2, for example. Therefore, the layout design of signal lines S13a, S24a, S31a, S42a, S42b, S13b, S24b, and S31b can be made easier.

[0025] As shown in Figure 1, in this embodiment, the signal transmission path between two chip CPs located on diagonal line D is clockwise, and the input and output paths are different from each other. This allows one transfer circuit TR (any of TR1-TR4) to be placed on each chip CP, and the four chip CPs can be designed using common layout data. As a result, chip costs can be reduced, and the cost of the semiconductor device SEM1 can be reduced. Note that the signal transmission path between two chip CPs located on diagonal line D may also be counterclockwise.

[0026] For example, the transfer circuit TR2 outputs the data contained in the signal S13a received from chip CP1 only to the internal circuit INT3 of chip CP3, and not to the internal circuit INT2 of its own chip CP2. In other words, the internal circuit INT2 does not use the data contained in the signal S13a transferred between chips CP1 and CP3 for data processing, and the transfer circuit TR2 functions as a relay circuit for the data contained in the signals S13a and S13b between chips CP1 and CP3. The internal circuit INT2 may also monitor the signal S13a being transferred on the transfer circuit TR2.

[0027] It is preferable that the transfer circuit TR be placed in the central part of the placement area (the central part of the substrate BRD in the embodiments shown in Figures 1 to 3) on each chip CP. This shortens the signal transmission paths between chips CP1 and CP3 and between chips CP2 and CP4, compared to when the transfer circuit TR is placed on the outer edge of the placement area (the outer edge of the substrate BRD), thereby reducing the signal transmission time.

[0028] The substrate BRD may also be a silicon interposer. The semiconductor device SEM1 may be formed by packaging a substrate BRD on which chips CP1-CP4 are mounted. Alternatively, chips CP1-CP4 may each be sealed and packaged with resin or the like. Furthermore, the semiconductor device SEM1 may be connected to a printed circuit board or the like on which other semiconductor components are mounted via bumps provided on the back surface of the substrate BRD on which chips CP1-CP4 are mounted, which is the surface opposite to the front surface.

[0029] Furthermore, if the signal transmission path between two chips CP located on diagonal line D is bidirectional, then, for example, two transfer circuits TR1 and TR3 that transfer signals input and output between chips CP2 and CP4 are provided on only one of chips CP1 and CP3. Similarly, two transfer circuits TR2 and TR4 that transfer signals input and output between chips CP1 and CP3 are provided on only one of chips CP2 and CP4.

[0030] For example, if transfer circuits TR1 and TR3 are provided only on chip CP1, and transfer circuits TR2 and TR4 are provided only on chip CP2, then separate layout designs must be performed for chips CP1 and CP2, and for chips CP3 and CP4. Furthermore, because areas where signal lines S are densely routed and areas where they are sparsely routed will occur on the board BRD, the layout design of the routing becomes difficult.

[0031] Furthermore, the internal circuits INT1 and INT2 of chips CP1 and CP2 occupy a smaller area than the internal circuits INT3 and INT4 of chips CP3 and CP4. Therefore, if chips CP1-CP4 are to be the same size, there may be wasted space in the area of ​​the internal circuits INT3 and INT4 of chips CP3 and CP4 where no circuitry is formed. Moreover, if the chip size of chips CP3 and CP4 is to be smaller than that of chips CP1 and CP2 to eliminate this wasted space, it becomes necessary to design two different types of chips.

[0032] Figure 2 is a block diagram showing an example of the transfer circuit TR2 and its surrounding circuitry from Figure 1. The other transfer circuits TR1, TR3, and TR4 and their surrounding circuits have a similar configuration to that shown in Figure 2.

[0033] The transfer circuit TR2 includes an input buffer 21, an input flip-flop (FF) 22, an error detection / correction circuit 23, a clock swapping circuit 24, staging FFs 25 and 26, an error detection / correction signal generation circuit 27, an output FF 28, and an output buffer 29. The number of staging FFs inserted into the transfer circuit TR2 can be determined depending on the length of the signal transmission path and the clock frequency, and is not limited to the number shown in Figure 2.

[0034] The input buffer 21 receives a multi-bit signal S13a from the chip CP1 via the signal line S13a and outputs the received signal S13a to the input FF22. The input FF22 captures the signal S13a in synchronization with a clock (not shown) and outputs the captured signal S13a to the error detection / correction circuit 23. The clock used by the input FF22 is the clock used by the chip CP1, which is included in the signal S13a output from the chip CP1.

[0035] The error detection / correction circuit 23 uses the error detection / correction signal contained in the multi-bit signal S13a to detect or correct errors in the data contained in signal S13a, and if a correction is made, outputs the corrected data to the clock transposition circuit 24. This allows the corrected data to be transferred to chip CP3 even if an error occurs in the data received from chip CP1 via signal line S13a.

[0036] Furthermore, if the error detection / correction circuit 23 detects an error that cannot be corrected, it may generate error information indicating the detection of an uncorrectable error. In addition, if the error detection / correction circuit 23 corrects a data error, it may generate correction information indicating that the error has been corrected. In this case, the error information or correction information may be output to the internal circuit INT2 of the chip CP2. Furthermore, if the error detection / correction circuit 23 generates the error information or correction information, the internal circuit INT2 of the chip CP2 may retain the error information or correction information, and may use the retained error information or correction information to perform information processing such as calculating the error correction rate.

[0037] Furthermore, the error detection / correction circuit 23 may only perform data error detection. In this case, the error detection / correction signal generation circuit 11 of the internal circuit INT1 may generate a signal that only performs error detection, such as a parity bit. In addition, if the error detection / correction circuit 23 detects a data error, it may generate detection information indicating that an error has been detected and output the generated detection information to the internal circuit INT2. If the error detection / correction circuit 23 generates detection information, the internal circuit INT2 may retain the detection information and use the retained detection information to perform information processing such as calculating the error detection rate.

[0038] Furthermore, the error information, correction information, or detection information generated by the error detection / correction circuit 23 and output to the internal circuit INT2, or information generated based on the error information, correction information, or detection information, may be output to the internal circuit INT3 of chip CP3 via the internal circuit INT2. In this case, for example, the error information, correction information, or detection information, or information generated based on the error information, correction information, or detection information, may be transmitted to the internal circuit INT3 via the input / output circuit IO23 of the internal circuit INT2, signal line S23, and the input / output circuit IO32 of the internal circuit INT3 shown in Figure 1. This prevents signals other than data, error detection / correction signals, and clock signals from being transmitted to signal line S13b, and minimizes the number of signal lines S13b. In other words, signal line S13b can be used only for the purpose of transferring data from chip CP1 to chip CP3.

[0039] The clock swapping circuit 24 converts the data contained in the signal S13a, which is synchronized with the clock of chip CP1, into data synchronized with the clock of chip CP2, and outputs it to the staging FF25. For example, an input asynchronous FIFO (First-In First-Out) may be used as the clock swapping circuit 24. Note that the connection order of the error detection / correction circuit 23 and the clock swapping circuit 24 may be reversed. That is, the data synchronized with the clock of chip CP2 by the clock swapping circuit 24 may be used for error detection by the error detection / correction circuit 23, and errors may be corrected as desired.

[0040] The staging FF25 and FF26 are examples of relay circuits that sequentially relay data. Note that if the signal transfer distance within the transfer circuit TR2 is short, the transfer circuit TR2 does not need to have staging FF25 and FF26. In this case, the data output from the clock swapping circuit 24 may be output directly to the error detection / correction signal generation circuit 27.

[0041] The error detection / correction signal generation circuit 27 generates an error detection / correction signal to correct errors in multi-bit data, and outputs the generated error detection / correction signal along with the data to output FF28. For example, the error detection / correction signal is an ECC (Error Correction Code). Output FF28 outputs the data, error detection / correction signal, and clock to output buffer 29. Output buffer 29 outputs the data, error detection / correction signal, and clock as signal S13b to chip CP3.

[0042] The internal circuit INT1 of the chip CP1, which outputs signal S13a, includes an error detection / correction signal generation circuit 11, an output FF12, and an output buffer 13. The error detection / correction signal generation circuit 11, output FF12, and output buffer 13 have the same functions as the error detection / correction signal generation circuit 27, output FF28, and output buffer 29 of the transfer circuit TR2, respectively.

[0043] The internal circuit INT3 of chip CP3 includes an input buffer 31, an input FF 32, an error detection / correction circuit 33, and a clock swapping circuit 34. The input buffer 31, input FF 32, error detection / correction circuit 33, and clock swapping circuit 34 have the same functions as the input buffer 21, input FF 22, error detection / correction circuit 23, and clock swapping circuit 24 of transfer circuit TR2, respectively.

[0044] The input buffer 31 receives the multi-bit signal S13b transferred from chip CP1 via the transfer circuit TR2 of chip CP2, and outputs the received signal S13b to the input FF32. The input FF32 captures the signal S13b in synchronization with the clock of chip CP2 contained in the signal S13b, and outputs the captured signal S13b to the error detection / correction circuit 33.

[0045] The error detection / correction circuit 33 uses the error detection / correction signal contained in signal S13b to detect or correct errors in the data contained in signal S13b, and if an error is corrected, outputs the corrected data to the clock transposition circuit 34. The clock transposition circuit 34 converts the data contained in signal S13b, which is synchronized with the clock of chip CP2, into data synchronized with the clock of chip CP3. Then, the internal circuit INT3 uses the signal S13b transferred from chip CP1 via the transfer circuit TR2 of chip CP2 to perform data processing, etc. If it is necessary to return the processed data to chip CP1, the internal circuit INT3 transfers the data to chip CP1 via the transfer circuit TR4 of chip CP4 shown in Figure 1. Alternatively, the error detection / correction circuit 33 may only perform error detection, in which case the error detection / correction signal generation circuit 27 of the transfer circuit TR2 may generate a signal that only performs error detection, such as a parity bit.

[0046] Note that the connection order between the error detection / correction circuit 33 and the clock swapping circuit 34 may be reversed. That is, the data synchronized to the clock of chip CP3 by the clock swapping circuit 34 may be used for error detection by the error detection / correction circuit 33, and the errors may be corrected as desired. Also, the transfer circuit TR2 does not need to have the error detection / correction circuit 23 and the error detection / correction signal generation circuit 27, the transfer circuit TR1 does not need to have the error detection / correction signal generation circuit 11, and the transfer circuit TR3 does not need to have the error detection / correction circuit 33.

[0047] Figure 3 is a schematic diagram illustrating an example of connecting bumps BP on chips CP1-CP4 in Figure 1 with signal lines S (wiring). The signal lines S are formed using the wiring layer of a substrate BRD, such as a silicon interposer. The signal lines S connected to the bumps BP shown in Figure 3 are wired according to the same wiring rules, without distinction based on the signal transfer destination. This reduces variations in the lengths of multiple signal lines S, as explained in Figure 1, and reduces signal skew. Note that for clarity, Figure 3 shows bumps BP on each chip CP, and only opposing bumps BP are connected by signal lines S. However, in reality, the bumps BP are located between each chip CP and the substrate BRD. Also, to equalize the lengths of the signal lines S, for example, the bumps BP on the right side of chip CP2 are connected via signal lines S to bumps BP located further back than the bumps BP on the left side of chip CP3.

[0048] Figure 4 is a block diagram showing an example, as a comparative example, in which the transfer circuit TR shown in Figure 1 is not provided on each chip CP, and two chips CP1 and CP3 (or CP2 and CP4) located on a diagonal line D1 (or D2) are connected by signal lines S13 and S31 (or S24 and S42).

[0049] In this case, both input and output signal lines are connected by diagonal wiring using bumps (not shown) provided in the corner regions of chips CP1-CP4 near the intersection of diagonals D1 and D2. Furthermore, signal lines S13 and S31 must cross with signal lines S24 and S42. For this reason, wiring can become difficult if there are many signal lines S13, S31, S24, and S42. In addition, if the number of wiring layers on the substrate BRD, such as a silicon interposer, is increased to enable wiring, the cost will increase and the amount of signal delay may increase. Furthermore, if the lengths of signal lines S13 and S31 (or S24 and S42) vary, there is a risk of signal skew. In contrast, the embodiments shown in Figures 1 to 3 can reduce the above problems.

[0050] In the embodiments shown in Figures 1 to 3, data can be transferred between two chips CP located on diagonal D via a transfer circuit TR provided on two chips CP not located on diagonal D. Since the signal lines S connected to the transfer circuit TR are provided on opposite sides of the two chips CP located on diagonal D, the number of signal lines S that can be wired can be increased compared to when they are connected by diagonal wiring substantially parallel to diagonal D. In addition, two adjacent chips CP connected via opposite sides can input and output data to each other via an input / output circuit IO. As a result, the four chips CP1-CP4 can communicate data of equivalent information to each other, and mutual communication between chips CP1-CP4 can be performed smoothly.

[0051] Since the four chips CP1-CP4 can communicate data of equivalent information to each other, it becomes possible to divide a function that would normally be implemented on a single chip into four chips CP1-CP4 and use them to create the semiconductor device SEM1. In this case, compared to implementing the function on a single chip, it is expected that the yield rate, which is the percentage of good chips CP, will be improved. By improving the yield rate, the chip cost can be reduced, and thus the cost of the semiconductor device SEM1 can be reduced.

[0052] By reducing the variation in the lengths of multiple signal lines S that transmit data between two chips CP located on the diagonal D, the skew of the data transmitted through the signal lines S can be reduced. As a result, timing design can be simplified, and the performance of the semiconductor device SEM1 can be improved.

[0053] By placing the transfer circuit TR towards the center of the substrate BRD on the chip CP (towards the center of the chip CP placement area), the signal transmission path between chip CPs can be shortened compared to placing the transfer circuit TR towards the outer edge of the substrate BRD (towards the outer edge of the chip CP placement area), thereby reducing signal transmission time. By placing one transfer circuit TR on each chip CP, the four chip CPs can be designed using common layout data. As a result, chip costs can be reduced, and the cost of the semiconductor device SEM1 can be reduced.

[0054] Each transfer circuit TR can detect errors in data received from one chip CP via the signal line S, and the error detection / correction circuit 23 can detect or correct the errors, then transfer the correct data to the other chip CP. Furthermore, each transfer circuit TR generates an error detection / correction signal 27 to detect or correct errors in the data being transferred to the other chip CP. This allows the error detection / correction circuit 33 of the receiving chip CP to detect or correct errors even if errors occur in the data output from the transfer circuit TR. Therefore, even when data transmission between two chip CPs located on a diagonal line D is performed via another chip CP, the degradation of data reliability can be reduced.

[0055] Figure 5 is a block diagram showing an example of a semiconductor device in another embodiment of the present invention. Elements similar to those in Figure 1 are denoted by the same reference numerals, and detailed descriptions are omitted. The semiconductor device SEM2 shown in Figure 5 has the same configuration as the semiconductor device SEM1 shown in Figure 1, except that the transfer circuits TR (TR1-TR4) are located on the outer periphery of the placement area of ​​each chip CP (CP1-CP4) (on the outer periphery of the substrate BRD).

[0056] In this embodiment, since the distance over which the signal S is transmitted within each transfer circuit TR is long, each transfer circuit TR has a larger number of staging flip-flops (not shown) than in Figure 2. The configuration of each transfer circuit TR is the same as that of the transfer circuit TR2 shown in Figure 2, except that the number of staging flip-flops is larger. Note that the location of the transfer circuit TR provided on each chip CP is not limited to the location shown in Figure 5, and may include, for example, the central part of each chip CP. Also, the transfer circuit TR may be distributed across multiple regions of each chip CP. The semiconductor device SEM2 shown in Figure 5 can obtain the same effects as the semiconductor device SEM1 shown in Figure 1.

[0057] Figure 6 is a block diagram showing an example of a semiconductor device in another embodiment of the present invention. Elements similar to those in Figure 1 are denoted by the same reference numerals, and detailed descriptions are omitted. The semiconductor device SEM3 shown in Figure 6 has four rectangular chips CP (CP1-CP4) mounted on a substrate BRD, each having long and short sides. Each chip CP has a transfer circuit TR (TR1-TR4) similar to those in Figures 1 and 2, which relays signal transmission between two chips CP located on a diagonal D1 (or D2).

[0058] Furthermore, to ensure that the area surrounding the placement region for chips CP1-CP4 does not have any protrusions, that is, that the outer perimeter of the placement region is approximately rectangular, an empty area is provided in the central part of the substrate BRD (the central part of the chip CP placement region) where chips CP1-CP4 are not placed. In other words, each side of the rectangular placement region where chips CP1-CP4 are placed is formed by one of the long sides and one of the short sides of each chip CP. Also, the other long side of each chip CP faces the other short side of an adjacent chip CP, and the other short side of each chip CP faces the other long side of an adjacent chip CP. The other long sides of two chip CPs located on the diagonal D1 (or D2) face each other via the empty area. The empty area is surrounded by four chips CP1-CP4.

[0059] The other configurations of the semiconductor device SEM3 are the same as those of the semiconductor device SEM1 shown in Figure 1. Note that the location of the transfer circuit TR provided on each chip CP is not limited to the locations shown in Figure 6. Furthermore, the transfer circuit TR may be distributed across multiple regions of each chip CP.

[0060] Figure 7 is a perspective view showing an example of a system board SBRD on which the semiconductor device SEM3 shown in Figure 6 is mounted. In Figure 7, the semiconductor device SEM3 is mounted on the system board SBRD together with other electronic components IC and connector CN. For example, the system board SBRD is a printed circuit board. The system board SBRD may be connected via connector CN to a back panel provided on a rack or the like (not shown). Alternatively, a cluster may be formed by connecting multiple system board SBRDs to a rack or the like.

[0061] Furthermore, the semiconductor device SEM1 in Figure 1, the semiconductor device SEM2 in Figure 5, and the semiconductor device SEM4 in Figure 8 (described later) may also be mounted on the system board SBRD, similar to Figure 7.

[0062] In this embodiment, the same effects as those obtained with the semiconductor device SEM1 shown in Figure 1 can be obtained with the semiconductor device SEM3.

[0063] Figure 8 is a block diagram showing an example of a semiconductor device in another embodiment of the present invention. Elements similar to those in Figures 1 and 6 are denoted by the same reference numerals and their detailed descriptions are omitted. The semiconductor device SEM4 shown in Figure 8 has four rectangular chips CP (CP1-CP4) mounted on a substrate BRD. Each chip CP has a transfer circuit TR (TR1-TR4) similar to those in Figures 1 and 2, and each transfer circuit TR relays the transmission of signals between two chips CP located on a diagonal D1 (or D2).

[0064] In this embodiment, in order to minimize the size of the transfer circuit TR and minimize the delay of the signal S transferred through the transfer circuit TR, the transfer circuit TR is located in the central part of the substrate BRD, which is the placement area for chips CP1-CP4, as in Figure 1. Therefore, each chip CP1-CP4 is mounted on the substrate BRD with one corner close to the intersection of diagonals D1 and D2. As a result, the outer edges of each chip CP1-CP4 are not aligned in a straight line, and the area around the placement area of ​​chips CP1-CP4 has protrusions, allowing the size of the substrate BRD to be determined to match these protrusions. Furthermore, by reducing the empty space within the placement area, the area occupied by chips CP1-CP4 on the substrate BRD can be reduced. Therefore, the area on the substrate BRD that can be used to mount other electronic components can be increased. The other configurations of the semiconductor device SEM4 are the same as those of the semiconductor device SEM1 shown in Figures 1 and 6. The same effects as those of the semiconductor device SEM1 shown in Figure 1 can be obtained in the semiconductor device SEM4 of this embodiment.

[0065] In the embodiments shown in Figures 1, 5, 6, and 8, an example was described in which a transfer circuit TR is provided on each chip CP. However, if data transfer is necessary between chips CP2 and CP4, but not between chips CP1 and CP3, the transfer circuit TR may be provided on chips CP1 and CP3, but not on chips CP2 and CP4. Similarly, if data transfer is necessary between chips CP1 and CP3, but not between chips CP2 and CP4, the transfer circuit TR may be provided on chips CP2 and CP4, but not on chips CP1 and CP3.

[0066] The present invention is not limited to the embodiments specifically disclosed above, and various modifications and changes are possible without departing from the scope of the claims. [Explanation of Symbols]

[0067] 11 Error detection / correction signal generation circuit 12 Output Flip-Flops 13 Output buffer 21 Input Buffer 22 Input Flip-Flops 23 Error detection / correction circuits 24 Clock swapping circuit 25, 26 Staging 27 Error detection / correction signal generation circuit 28 Output Flip-Flops 29 Output buffer 31 Input Buffer 32 Input Flip-Flops 33 Error detection / correction circuits 34 Clock swapping circuit BP Bump BRD substrate CP (CP1, CP2, CP3, CP4) chips D1, D2 diagonal INT(INT1, INT2, INT3, INT4) Internal Circuit S signal line SEM1, SEM2, SEM3, SEM4 Semiconductor Device TR (TR1, TR2, TR3, TR4) transfer circuit IO input / output circuit

Claims

1. A first chip having multiple arithmetic units, The first chip is adjacent to a second chip having a plurality of arithmetic units, The first chip transfers the first data to the second chip. The second chip transfers the second data to the first chip. The second chip detects an error in the first data, The first data is used for arithmetic operations on the neural network by the plurality of arithmetic units of the second chip. The second data is used for arithmetic operations on the neural network by the plurality of arithmetic units of the first chip. The layout design of the first chip is the same as the layout design of the second chip. Semiconductor equipment.

2. The second chip has an input buffer for receiving the first data, The second chip detects errors in the first data received by the input buffer. The semiconductor device according to claim 1.

3. The first chip generates an error detection signal for detecting errors in the first data to be transferred to the second chip and transmits it to the second chip. The second chip uses the received first data and the error detection signal to detect an error in the first data. The semiconductor device according to claim 1 or claim 2.

4. If the second chip detects an error in the first data, it outputs information generated based on the detection information to the internal circuitry of the second chip. The semiconductor device according to any one of claims 1 to 3.

5. The second chip includes an input flip-flop for acquiring the first data, and a clock swapping circuit that converts the first data synchronized with the clock of the first chip to the first data synchronized with the clock of the second chip. The second chip detects errors in the first data acquired by the input flip-flop, or in the first data converted by the clock transposition circuit. The semiconductor device according to any one of claims 1 to 4.

6. The aforementioned clock swapping circuit includes an input asynchronous FIFO, The semiconductor device according to claim 5.

7. The second chip has an error detection / correction circuit that detects or corrects errors in the first data. The semiconductor device according to any one of claims 1 to 6.

8. The second chip, when it detects an uncorrectable error, generates error information indicating that the error is uncorrectable. The semiconductor device according to any one of claims 1 to 7.

9. The second chip generates correction information indicating that an error has been corrected when an error has been corrected. The semiconductor device according to any one of claims 1 to 7.

10. The second chip is, When an uncorrectable error is detected, error information indicating that the error is uncorrectable is generated. At least one of the error information and the correction information, or information generated based on at least one of the error information and the correction information, is output to the internal circuit of the second chip. The semiconductor device according to claim 9.

11. The second chip transmits the first data with the error corrected to another chip. The semiconductor device according to any one of claims 9 to 10.

12. The second chip has an output buffer that outputs an error detection signal to another chip. The semiconductor device according to any one of claims 1 to 11.

13. The second chip calculates the error detection rate of the data transferred from the first chip. The semiconductor device according to any one of claims 1 to 12.

14. The second chip calculates the error correction rate of the data transferred from the first chip. The semiconductor device according to any one of claims 1 to 13.

15. The aforementioned error detection is performed by the Error Correction Code. The semiconductor device according to any one of claims 1 to 14.

16. Each of the first and second chips is rectangular in shape with four sides in a plan view. One side of the first chip is opposite to one side of the second chip. The semiconductor device according to any one of claims 1 to 15.

17. The plurality of arithmetic units of the first chip include at least a multiply-accumulate unit or an inner product unit, The plurality of arithmetic units of the second chip include at least a multiply-accumulate unit or an inner product unit. The semiconductor device according to any one of claims 1 to 16.

18. A first signal line for transferring the first data from the first chip to the second chip, The device comprises a second signal line for transferring the second data from the second chip to the first chip, The lengths of the first signal line and the second signal line are the same. The semiconductor device according to any one of claims 1 to 17.

19. It comprises a third chip adjacent to the second chip and having multiple arithmetic units, and a fourth chip adjacent to the first chip and the third chip and having multiple arithmetic units, The first to fourth chips are rectangles having four sides in a plan view. The adjacent chips are arranged so that their edges face each other. The first chip and the third chip have their respective corners facing each other. The second chip and the fourth chip have their corners facing each other. The layout designs of the first to fourth chips are the same. The semiconductor device according to any one of claims 1 to 18.

20. The first chip transfers the first data to the second chip via a wiring layer formed on a substrate different from the first chip. The semiconductor device according to any one of claims 1 to 19.

21. A system board comprising a semiconductor device according to any one of claims 1 to 20.

22. A method for performing arithmetic operations on a neural network using a semiconductor device according to any one of claims 1 to 20.

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