Calculation unit, processor, and calculation method

Abstract

This allows subsequent floating-point multiply-accumulate instructions to begin without waiting for the preceding floating-point multiply-accumulate instruction to complete. [Solution] The arithmetic unit includes a processor 100 that performs a data-dependent first floating-point multiply-accumulate instruction and a second floating-point multiply-accumulate instruction. The processor bypasses the value C' before rounding and the signal inc indicating whether or not an increment occurred during rounding and uses them as inputs to the processor 100. Before the execution of the first floating-point multiply-accumulate instruction is completed, the second floating-point multiply-accumulate instruction is executed using the inputs to the processor 100.

Description

Technical Field

[0001] The present invention relates to an arithmetic device, a processor, and an arithmetic method.

Background Art

[0002] In recent years, a method for quickly calculating a data-dependent floating-point multiply-accumulate operation (FMA operation), which is also used as an index when measuring the floating-point operation performance of a processor and is also used in the inner product operation frequently occurring in AI processing such as dgemm, has become important.

[0003] The floating-point multiply-accumulate operation is an operation that executes a floating-point multiplication and a floating-point addition at once, represented by the formula A*B+C.

[0004] Here, data dependence refers to an operation in which the operation result of a preceding FMA operation is input to the addend (C) of a subsequent FMA operation.

[0005] Also, as an arithmetic unit that executes the FMA operation, a floating-point multiply-accumulate unit (FMA unit) is generally used.

[0006] When executing a data-dependent FMA operation, the execution of a subsequent FMA operation is waited until the FMA operation of a preceding instruction is completed. Such execution is called sequential execution.

[0007] FIG. 1 is a diagram for explaining a floating-point number.

[0008] The standard format of a floating-point number is defined in IEEE754-2008. A floating-point number has a sign part S (refer to sign A1), an exponent part E (refer to sign A2), and a mantissa part F (refer to sign A3), and is expressed as shown in FIG. 1.

[0009] A normalized number is represented by (-1) *2 E-bias *1.F, and a denormalized number is represented by (-1) S *2 E-bias+1 *0.F. [Prior art documents] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 9-212482 [Overview of the Initiative] [Problems that the invention aims to solve]

[0011] As mentioned above, when executed sequentially, subsequent FMA instructions will wait for the preceding FMA instruction to complete before starting the calculation. If one FMA instruction takes 5 cycles, executing n consecutive data-dependent FMA instructions would require 5n cycles, which may prevent high-speed processing of data-dependent FMA calculations.

[0012] One aspect of this is to allow subsequent floating-point multiply-accumulate instructions to begin without waiting for the preceding floating-point multiply-accumulate instruction to complete. [Means for solving the problem]

[0013] In one aspect, the arithmetic unit includes a processor that performs a data-dependent first floating-point multiply-accumulate instruction and a second floating-point multiply-accumulate instruction, the processor bypasses the value before rounding and a signal indicating whether or not an increment occurred during the rounding process and uses these inputs to execute the second floating-point multiply-accumulate instruction before the completion of the first floating-point multiply-accumulate instruction. [Effects of the Invention]

[0014] One aspect of this is that a subsequent floating-point multiply-accumulate instruction can be initiated without waiting for the preceding floating-point multiply-accumulate instruction to complete. [Brief explanation of the drawing]

[0015] [Figure 1]A diagram for explaining floating point numbers. [Figure 2] A block diagram schematically showing a configuration example of an FMA arithmetic unit in a related example. [Figure 3] A table exemplifying an instruction execution cycle in the FMA arithmetic unit shown in FIG. 2. [Figure 4] A block diagram schematically showing a configuration example of an FMA arithmetic unit in an embodiment. [Figure 5] A table exemplifying an instruction execution cycle in the FMA arithmetic unit shown in FIG. 4. [Figure 6] A diagram for explaining a calculation example in the CSA (Carry Save Adder) TREE and COMPRESSOR shown in FIG. 4. [Figure 7] A diagram for explaining an addition process performed by the CSA TREE and COMPRESSOR shown in FIG. 4. [Figure 8] A diagram for explaining a change in the alignment shift amount. [Figure 9] A flowchart for explaining an FMA arithmetic process in an embodiment. [Figure 10] A block diagram schematically showing a hardware configuration example of an arithmetic device that executes an FMA arithmetic unit in an embodiment. [Figure 11] A table exemplifying an instruction execution cycle when the processing from inputs A and B ends in 4 cycles and the processing from input C ends in 2 cycles. [Figure 12] A table exemplifying an instruction execution cycle when the latency of all inputs is 4 cycles. [Figure 13] A table exemplifying an instruction execution cycle when only the bypass of the FMA operation is performed 1 cycle earlier.

Best Mode for Carrying Out the Invention

[0016] 〔A〕Related Example FIG. 2 is a block diagram schematically showing a configuration example of an FMA arithmetic unit 600 in a related example.

[0017] The FMA arithmetic unit 600 shown in Figure 2 executes FMA instructions in 5 cycles from X1 to X5.

[0018] The FMA arithmetic unit 600 includes FORMAT 61a to 61c to execute processing in cycle X1, and EXP (Exponential) 62a, RSFT (Right Shift) 62b, CSA TREE 62c, and COMPRESSOR 62d to execute processing in cycle X2. Furthermore, the FMA arithmetic unit 600 includes INCREMENTER 63b, ADDER 63c, and LZA (Leading Zero Analyze) 63d to execute processing in cycle X3. In addition, the FMA arithmetic unit 600 includes EXP 64a, INCREMENTER or not 64b, LSFT (Left Shift) 64c, ROUND 64d, and FORMAT 64e to execute processing in cycle X4.

[0019] In cycle X1, the operands, input data A, B, and C, are separated into a sign, exponent, and mantissa, respectively, according to FORMAT 61a to 61c.

[0020] In cycle X2, CSA TREE62c multiplies the mantissas of the multiplication operands A and B and outputs the result as a carry-preserved SUM / CRY. On the other hand, the mantissa of the addend operand C is right-shifted in RSFT62b according to the difference in exponents between A*B. This right shift is generally called alignment.

[0021] The result of CSA TREE62c and the lower part of the aligned C mantissa are converted into a 3-input, 2-input carry-preservation format SUM / CRY in COMPRESSOR62d. Meanwhile, the upper part of the aligned C mantissa is input to INCREMENTER63b.

[0022] EXP62a calculates the shift amount for digit alignment from the exponents of each of the input data A, B, and C. Specifically, it calculates the shift amount by subtracting the exponent of C from the exponent of A*B. Furthermore, the line connecting EXP62a to LSFT64c inputs the shift amount calculated by EXP62a as the normalization shift amount when the exponent of C is larger than the exponent of A*B.

[0023] Furthermore, EXP62a determines the midpoint of the exponent of the calculation result. The determination of the midpoint by EXP62a is similar to the selection by INCREMENTER63b and ADDER63c, where the exponents of A*B and C are compared and the sufficiently larger one is selected as the midpoint.

[0024] In cycle X3, ADDER63c adds the SUM / CRY output of COMPRESSOR62d, which is in carry-preserved format.

[0025] INCREMENTER63b determines whether to add 1 to the upper part of the aligned auger C, depending on whether a carry-out (in other words, a carry-over) occurred in the result of ADDER63c, and outputs the result.

[0026] LZA63d is a circuit that predicts the number of leading zeros in the summation result of ADDER63c.

[0027] The input to LSFT64c is selected from the results of INCREMENTER63b and ADDER63c. This is determined by the difference between the exponent of input C and the exponent of the multiplication result A*B. For example, if the exponent of C is sufficiently larger than the multiplication result A*B, only INCREMENTER63b will be selected; otherwise, the results of ADDER63c will be selected in all cases.

[0028] In cycle X4, LSFT64c left-shifts the selected result according to the exponential difference and the result of LZA63d. This left shift is generally called normalization. This is because the normalized number of floating-point numbers has integer bits set to 1, so a left shift is necessary if the selected result has a leading zero.

[0029] ROUND64d performs rounding on the result of LSFT64c. Rounding is handled by whether or not to increment by +1.

[0030] FORMAT64e outputs the sign, exponent, and mantissa in a standard format.

[0031] EXP64a is a circuit that processes the left shift due to normalization and reflects that in the exponent. For example, if EXP62a selects the exponent A*B as the intermediate value and ADDER63c causes a loss of precision resulting in leading zeros, then the exponent value needs to be reduced by the amount of normalization. EXP64a subtracts the normalization amount from this intermediate value. On the other hand, if INCREMENTER63b is selected, the exponent C is selected as the intermediate value, and EXP64a may perform a left shift by the amount of normalization if a right shift for digit alignment was performed.

[0032] INCREMENTER or not64b is a circuit that corrects the exponent when the mantissa value exceeds 2 due to rounding.

[0033] Figure 3 is a table illustrating the instruction execution cycle in the FMA arithmetic unit 600 shown in Figure 2.

[0034] As shown in Figure 3, in each of the consecutive data-dependent FMA instructions (1) to (3), the processing of cycles X1 to X5 is executed. At times #1 to #5, the processing of cycles X1 to X5 of instruction (1) is executed, at times #6 to #10, the processing of cycles X1 to X5 of instruction (2) is executed, and at times #11 to #15, the processing of cycles X1 to X5 of instruction (3) is executed.

[0035] [B] Embodiment Embodiments will be described below with reference to the drawings. However, the embodiments shown below are merely illustrative, and there is no intention to exclude various modifications or applications of techniques not explicitly shown in the embodiments. In other words, these embodiments can be implemented in various ways without departing from their spirit. Furthermore, each figure is not intended to represent only the components shown in the figure, but may include other components, etc.

[0036] [B-1] Software Configuration Example Figure 4 is a schematic block diagram showing an example configuration of the FMA arithmetic unit 100 in the embodiment.

[0037] The FMA arithmetic unit 100 shown in Figure 4 executes FMA instructions in 5 cycles from X1 to X5.

[0038] The FMA arithmetic unit 100 includes FORMAT 11a to 11c to execute processing in cycle X1, and EXP 12a, RSFT 12b, CSA TREE 12c, and COMPRESSOR 12d to execute processing in cycle X2. Furthermore, the FMA arithmetic unit 100 includes INCREMENTER 13b, ADDER 13c, and LZA 13d to execute processing in cycle X3. In addition, the FMA arithmetic unit 100 includes EXP 14a, INCREMENTER or not 14b, FORMAT 14c, LSFT 14d, ROUND 14e, and FORMAT 14f to execute processing in cycle X4.

[0039] In cycle X1, the operands, input data A, B, and C, are separated into a sign, exponent, and mantissa according to FORMAT 11a to 11c.

[0040] In cycle X2, CSA TREE12c multiplies the mantissas of the multiplication operands A and B and outputs the result as a carry-preserved SUM / CRY. On the other hand, the mantissa of the addend operand C is right-shifted in RSFT12b according to the difference in exponents between A*B. This right shift is generally called alignment.

[0041] The result of CSA TREE12c and the lower part of the aligned C mantissa are converted into two carry-preservation formats, SUM / CRY, from three inputs in COMPRESSOR12d. On the other hand, the upper part of the aligned C mantissa is input to INCREMENTER13b. RSFT12b and COMPRESSOR12d are connected by a signal line for inputting the signal from FORMAT11c, as well as a signal line for inputting the signal inc.

[0042] EXP12a calculates the shift amount for digit alignment from the exponents of each of the input data A, B, and C. Specifically, it calculates the shift amount by subtracting the exponent of C from the exponent of A*B. Furthermore, the line connecting EXP12a to LSFT14d inputs the shift amount calculated by EXP12a as the normalization shift amount when the exponent of C is larger than the exponent of A*B.

[0043] For example, if the exponents of A*B and C are the same, the numbers are aligned until the integer bits of C and A*B are exactly the same. If it is a single-precision floating-point number as defined by IEEE, the mantissa has 23 bits, so if the exponents of C and A*B are the same, the total shift is 24 bits including the integer bits. From here, if C is large, the shift amount is reduced, and if A*B is large, the shift amount is increased.

[0044] However, the shift amount may be set anticipating that the result of multiplying the mantissas of A and B will exceed 2. For example, an extra bit of width may be allocated to ADDER13c, or an additional bit of width may be allocated to INCREMENTER13b to leave a guard bit as rounding information, so it may be designed as a 26-bit shift if the exponents are the same.

[0045] If the exponent of C is slightly larger than the exponent of A*B, the output of ADDER13c and the output of INCREMENTER13b are not mutually exclusive. In such cases, the upper part of the mantissa of C, which has been aligned to the extent that the integer bits are not aligned, remains in INCREMENTER13b, and the output of ADDER13c, which is the sum of the remaining part of the mantissa of C and the mantissa of the result of the multiplication of A*B, is concatenated. At this time, the normalization shift performs a left shift of the same amount as the alignment, and the result of INCREMENTER13b is left-aligned. The value shifted in at that time will be the upper part of the output of ADDER13c.

[0046] Furthermore, EXP12a determines the midpoint of the exponent of the calculation result. The determination of the midpoint by EXP12a is similar to the selection between INCREMENTER13b and ADDER13c, where the exponents of A*B and C are compared and the sufficiently larger one is selected as the midpoint.

[0047] In cycle X3, ADDER13c adds the SUM / CRY output of COMPRESSOR12d, which is in carry-preserved format.

[0048] INCREMENTER13b decides whether to add 1 to the upper part of the aligned mantissa C, depending on whether a carry-out occurred as a result of ADDER13c. If INCREMENTER13b decides to add 1, it outputs the value with 1 added to the upper part of the aligned mantissa C; if it decides not to add 1, it outputs the upper part of the aligned mantissa C as is.

[0049] LZA13d is a circuit that predicts the number of leading zeros in the summation result of ADDER13c.

[0050] The input to LSFT14d is selected from the results of INCREMENTER13b and ADDER13c. This is determined by the difference between the exponent of input C and the exponent of the multiplication result A*B. For example, if the exponent of C is sufficiently large compared to the multiplication result A*B (e.g., above a predetermined threshold), only INCREMENTER13b will be selected; otherwise, the results of ADDER13c will be selected in all cases.

[0051] In cycle X4, LSFT14d left-shifts the selected result according to the exponential difference and the result of LZA13d. This left shift is generally called normalization. This is because the normalized number of floating-point numbers has integer bits set to 1, so a left shift is necessary if the selected result has a leading zero.

[0052] ROUND14e performs rounding on the result of LSFT14d. Rounding is performed according to the decision made by INCREMENTER13b regarding whether to increment by +1.

[0053] FORMAT14f outputs the sign, exponent, and mantissa in a standard format.

[0054] EXP14a is a circuit that processes the left shift due to normalization and reflects that in the exponent. For example, if EXP12a selects the exponent A*B as the intermediate value and ADDER13c causes a loss of precision resulting in leading zeros, then the exponent value needs to be reduced by the amount of normalization. EXP14a subtracts the normalization amount from this intermediate value. On the other hand, if INCREMENTER13b is selected, the exponent C is selected as the intermediate value, and EXP14a may perform a left shift by the amount of normalization if a right shift for digit alignment was performed.

[0055] INCREMENTER or not14b is a circuit that corrects the exponent when the mantissa value exceeds 2 due to rounding.

[0056] In this embodiment, data C', which skips the rounding increment in ROUND14e, is bypassed in order to allow the subsequent FMA instruction to be executed without waiting for the preceding FMA instruction to complete.

[0057] In this case, FORMAT14c generates C' by combining the mantissa data, sign, and exponent, with the rounding increment skipped, into the standard format and bypassing the process.

[0058] Additionally, the signal `inc`, which is used to inform subsequent instructions whether an increment due to rounding occurred (combined with the result C' without rounding), is also bypassed.

[0059] The subsequent instruction treats the exponent and mantissa as usual for input C, but it needs to perform a rounding increment (+1) that was not performed in the preceding instruction. Here, a correction is made based on the signal 'inc' which indicates whether the aforementioned increment occurred. If the correction method is simply to add +1 to the mantissa of input C, the delay will increase and the latency of the FMA calculation will worsen.

[0060] Therefore, to minimize the delay effect, the +1 information is converted into mantissa width data (called a mask) in RSFT12b, and then added using either CSA TREE12c or COMPRESSOR12d (in other words, a carry-preserving adder) which performs A*B+C on the mantissa.

[0061] The number of CSA stages varies depending on the data size being handled, but generally, a 3-input CSA compresses the partial product from 3 rows to 2 rows, and a 5-input CSA compresses it from 4 rows to 2 rows. If there are any remaining partial products, correction can be performed without affecting the delay.

[0062] For example, mask generation is performed in RSFT12b because it can be generated from the signal inc and the digit alignment shift amount, but the circuit for generating the mask may be provided as a separate block.

[0063] Figure 5 is a table illustrating the instruction execution cycle in the FMA arithmetic unit 100 shown in Figure 4.

[0064] As shown in Figure 5, in each of the consecutive data-dependent FMA instructions (1) to (3), the processing of cycles X1 to X5 is executed. At times #1 to #5, the processing of cycles X1 to X5 of instruction (1) is executed, at times #5 to #9, the processing of cycles X1 to X5 of instruction (2) is executed, and at times #9 to #13, the processing of cycles X1 to X5 of instruction (3) is executed.

[0065] Thus, in the example shown in Figure 5, cycle X5 of instruction (1) and cycle X1 of instruction (2) are executed simultaneously at time #5, and cycle X5 of instruction (2) and cycle X1 of instruction (3) are executed simultaneously at time #9. This allows the subsequent FMA instruction to start without waiting for the preceding FMA instruction to complete, resulting in a time reduction of 2 units compared to the related example shown in Figure 3.

[0066] Figure 6 illustrates the calculation examples for CSA TREE12c and COMPRESSOR12d shown in Figure 4.

[0067] The example shown in Figure 6 illustrates a typical CSA calculation when each mantissa is 10 bits and the exponents of C and A*B are the same.

[0068] As shown in symbol B1, when the exponents of C and A*B are the same, the digit alignment result of C and the decimal point position of A*B will be aligned.

[0069] In code B2, the partial products 0-9 and the alignment result portion are calculated for two 5-input CSAs and one 3-input CSA.

[0070] In code B3, for two 3-input CSAs, the sum of partial products 0-3, the cry of partial products 0-3, the sum of partial products 4-7, the cry of partial products 4-7, the + c sum of partial products 8-9, and the + c cry of partial products 8-9 are calculated.

[0071] In code B4, the calculation is performed on one 5-input CSA.

[0072] Then, in code B5, the sum and cry equivalents output by COMPRESSOR12d are output.

[0073] Figure 7 illustrates the addition process performed by the CSA TREE12c and COMPRESSOR12d shown in Figure 4.

[0074] In the example shown in Figure 7, code C1 represents the bypassed value C and the signal inc indicating that it is increased by 1. Code C2 is the sum of inc and a mask that takes the shift amount into account in the bottom row. When a right shift for digit alignment is performed on the input C of code C1, the mask shown in code C2 is generated from the resulting shift amount and the increment signal (inc).

[0075] Figure 8 illustrates the change in the digit alignment shift amount.

[0076] The code D1 represents the bypassed value C and the signal inc, which indicates adding 1 to it. The code D2 is the sum of inc and a mask that takes the shift amount into account in the bottom row. If the exponent of the input C in code D1 is greater than the exponent of the multiplication result A*B, the mask shown in code D2 is generated.

[0077] Code D3 represents the bypassed value C and the signal inc, which indicates adding 1 to it. Code D3 is the sum of inc and a mask that takes the shift amount into account in the bottom row. If the exponent of input C in code D3 is smaller than the exponent of the multiplication result A*B, the mask shown in code D4 is generated.

[0078] Although we have explained the case where the complex multiplication result and the +1 correction position overlap, if the exponent of input C is sufficiently large compared to the exponent of the multiplication result A*B, only the result of INCREMENTER13b will be selected. In that case, the +1 function of INCREMENTER13b may also be used to perform the +1 with the inc signal.

[0079] [B-2] Example of operation The FMA calculation process in this embodiment will be explained according to the flowchart (steps S1 to S10) shown in Figure 9.

[0080] FORMAT11a~11 separates each input data A, B, and C into its sign, exponent, and mantissa (step S1).

[0081] RSFT12b aligns C according to the exponential difference between the exponents of the product of A and B and the exponents of C, and CSA TREE12c multiplies A and B and outputs in carry-over format (SUM / CRY) (step S2).

[0082] COMPRESSOR12d adds SUM,CRY, which is the result of multiplying A and B, with the lower part of C after alignment (step S3).

[0083] INCREMENTER13b determines whether there is a carry-out in the summation result of ADDER13c (step S4).

[0084] If there is a carry-out (see the Yes route in step S4), INCREMENTER13b increments the upper part of the aligned C by +1 (step S5). Then the process proceeds to step S7.

[0085] If there is no carry-out (see No. route in step S4), INCREMENTER13b outputs the upper part of the aligned C as is (step S6).

[0086] LSFT14d selects the upper result of C, the product of A and B, and the sum of the lower parts of C according to the exponential difference (step S7).

[0087] LSFT14d performs a normalized left shift on the selected result (step S8).

[0088] ROUND14e performs rounding on the output of LSFT14d (step S9).

[0089] FORMAT14f outputs a result in which the mantissa, along with the sign and exponent, is combined into a standard format (step S10). Then the FMA calculation process is completed.

[0090] [B-3] Hardware Configuration Example Figure 10 is a schematic block diagram showing an example of the hardware configuration of the arithmetic unit 2 that executes the FMA arithmetic unit 100 in the embodiment.

[0091] As shown in Figure 10, the arithmetic unit 2 comprises a CPU 21, memory 22, display control device 23, storage device 24, input interface (IF) 25, external recording medium processing device 26, and communication IF 27.

[0092] Memory 22 is an example of a storage unit, and exemplifies it as Read Only Memory (ROM) and RAM. The ROM of memory 22 may contain programs such as a Basic Input / Output System (BIOS). The software programs in memory 22 may be read and executed by the CPU 21 as appropriate. The RAM of memory 22 may be used as temporary storage memory or working memory.

[0093] The display control device 23 is connected to the display device 231 and controls the display device 231. The display device 231 is a liquid crystal display, an organic light-emitting diode (OLED) display, a cathode ray tube (CRT), an electronic paper display, etc., and displays various information to the operator of the processing unit 2. The display device 231 may also be combined with an input device, for example, a touch panel.

[0094] The storage device 24 may be, for example, a Solid State Drive (SSD), Storage Class Memory (SCM), or Hard Disk Drive (HDD).

[0095] Input IF25 is connected to an input device such as a mouse 251 or a keyboard 252, and may control such an input device. The mouse 251 and keyboard 252 are examples of input devices, and the operator of the arithmetic unit 2 performs various input operations through these input devices.

[0096] The external recording medium processing device 26 is configured to accommodate a recording medium 260. The external recording medium processing device 26 is configured to read information recorded on the recording medium 260 when the recording medium 260 is mounted. In this example, the recording medium 260 is portable. For example, the recording medium 260 is a non-temporary recording medium such as a flexible disk, optical disk, magnetic disk, magneto-optical disk, or semiconductor memory.

[0097] Communication IF27 is an interface that enables communication with external devices.

[0098] The CPU 21 is an example of a processor, and is a processing unit that performs various control and calculations. The CPU 21 functions as the FMA arithmetic unit 100 shown in Figure 4. The CPU 21 realizes various functions by executing the OS and programs loaded into memory 22. The CPU 21 may be a multiprocessor containing multiple CPUs, a multicore processor having multiple CPU cores, or a configuration having multiple multicore processors.

[0099] The device for controlling the operation of the entire arithmetic unit 2 is not limited to the CPU 21, but may be, for example, one of the following: MPU, DSP, ASIC, PLD, or FPGA. Furthermore, the device for controlling the operation of the entire arithmetic unit 2 may be a combination of two or more types of CPU, MPU, DSP, ASIC, PLD, and FPGA. Note that MPU is an abbreviation for Micro Processing Unit, DSP is an abbreviation for Digital Signal Processor, and ASIC is an abbreviation for Application Specific Integrated Circuit. Also, PLD is an abbreviation for Programmable Logic Device, and FPGA is an abbreviation for Field Programmable Gate Array.

[0100] [B-4] Torture Figure 11 is a table illustrating the instruction execution cycle when processing from inputs A and B takes 4 cycles and processing from input C takes 2 cycles. Figure 12 is a table illustrating the instruction execution cycle when the total latency of all inputs is 4 cycles.

[0101] A method for varying the latency between inputs A, B and input C in an FMA calculator is disclosed in U.S. Patent Publication No. 2011 / 0072066. This method can be applied to the FMA calculator 100 in the embodiment.

[0102] As shown in Figure 11, in each of the consecutive data-dependent FMA instructions (1) to (3), the processing of cycles X1 to X4 is executed. At times #1 to #4, the processing of cycles X1 to X4 of instruction (1) is executed, at times #3 to #6, the processing of cycles X1 to X4 of instruction (2) is executed, and at times #5 to #8, the processing of cycles X1 to X4 of instruction (3) is executed.

[0103] As shown in Figure 12, if the total input latency is 4 cycles, it takes 12 cycles to complete 3 instructions, whereas in the example shown in Figure 11, the calculation is completed in 8 cycles.

[0104] Figure 13 is a table illustrating the instruction execution cycle when only the FMA calculation bypass is performed one cycle earlier.

[0105] A method for bypassing only the FMA calculation one cycle earlier is disclosed in B. Curran, B. McCredie, L. Sigal, E. Schwarz, B. Fleischer, Y.-H. Chan, D. Webber, M. Vaden, and A. Goyal, “4GHz+ low-latency fixed-point and binary floating-point execution units for the power6 processor,” in ISSCC, 2006. This method can also be applied to the FMA arithmetic unit 100 in the embodiment.

[0106] As shown in Figure 13, in each of the consecutive data-dependent FMA instructions (1) to (3), the processing of cycles X1 to X4 is executed. At times #1 to #4, the processing of cycles X1 to X4 of instruction (1) is executed, at times #4 to #7, the processing of cycles X1 to X4 of instruction (2) is executed, and at times #7 to #10, the processing of cycles X1 to X4 of instruction (3) is executed.

[0107] Thus, if the FMA calculation takes 4 cycles, or can be shortened to 3 cycles, the process can be completed in 10 cycles.

[0108] Furthermore, a method for bypassing only the FMA calculation one cycle earlier is also disclosed in HQ Le et al., “IBM power6 microarchitecture,” IBM J. Res. Develop., vol. 51, no. 6, pp. 639-662, 2007.

[0109] [C] Effect According to the arithmetic device, processor, and arithmetic method in the embodiments and modified examples, the following effects can be achieved, for example.

[0110] The FMA arithmetic unit 100 bypasses the value before rounding and the signal indicating whether or not an increment occurred during rounding, and uses them as inputs to the FMA arithmetic unit 100. Before the execution of the first floating-point multiply-accumulate instruction is completed, the FMA arithmetic unit 100 uses the inputs to the FMA arithmetic unit 100 to execute the second floating-point multiply-accumulate instruction.

[0111] This allows subsequent floating-point multiply-accumulate instructions to begin without waiting for the preceding floating-point multiply-accumulate instruction to complete. Furthermore, it enables the high-speed execution of multiple data-dependent FMA operations.

[0112] When the FMA arithmetic unit 100 executes a first floating-point multiply-accumulate instruction represented by A*B+C, it aligns C according to the exponential difference between the exponents of the multiplication result of A and B and the exponent of C, multiplies A and B, and outputs the result in carry-preserved format. The FMA arithmetic unit 100 adds the value represented in carry-preserved format to the lower part of the aligned C. The FMA arithmetic unit 100 normalizes the value obtained by incrementing the upper part of C, which has been aligned according to the exponential difference, or the value obtained by the addition operation, and provides it as input to the FMA arithmetic unit 100 as the value before rounding.

[0113] This allows for faster bypassing to input C while minimizing the impact on calculations from inputs A and B.

[0114] The FMA arithmetic unit 100 increments the upper part of the aligned C if a carry-out occurs in the result of the addition.

[0115] This allows for faster bypassing to input C when carry-out occurs, while minimizing the impact on calculations from inputs A and B.

[0116] When the second floating-point sum-of-accumulate instruction is executed, the FMA arithmetic unit 100 inputs a signal indicating whether or not an increment occurred during rounding as a mask to the carry-save adder.

[0117] This allows us to recognize whether an increment occurred during the skipped rounding process.

[0118] [D] Other The disclosed technology is not limited to the embodiments described above and can be implemented in various modifications without departing from the spirit of this embodiment. Each configuration and process of this embodiment can be selected or combined as needed.

[0119] [E] Note The following additional information is disclosed regarding the embodiments described above.

[0120] (Note 1) A processor that performs a data-dependent first floating-point multiply-accumulate instruction and a second floating-point multiply-accumulate instruction, The aforementioned processor, The value before rounding and a signal indicating whether or not an increment occurred during the rounding process are bypassed and used as input to the processor. Before the execution of the first floating-point multiply-accumulate instruction is completed, the second floating-point multiply-accumulate instruction is executed using the input to the processor. Computing device.

[0121] (Note 2) The aforementioned processor, When executing the first floating-point sum-of-accumulate instruction represented by A*B+C, Depending on the exponential difference between the exponents of the product of A and B and the exponent of C, C is adjusted to the correct number of digits. Multiply A and B and output in carry-over format. The value expressed in the carry-over format and the lower part of the aligned C are added together. The value obtained by incrementing the upper part of the aligned C according to the exponential difference, or the value obtained by performing the addition operation, is normalized and used as the input to the processor as the value before the rounding process. The computing device described in Appendix 1.

[0122] (Note 3) The aforementioned processor, If a carry-out occurs in the result of the above addition, the upper part of the aligned C is incremented. The computing device described in Appendix 2.

[0123] (Note 4) The aforementioned processor, When the second floating-point multiply-accumulate instruction is executed, a signal indicating whether or not an increment occurred in the rounding process is used as a mask and input to the carry-save adder. The arithmetic unit described in Appendix 2 or 3.

[0124] (Note 5) A processor that performs a data-dependent first floating-point multiply-accumulate instruction and a second floating-point multiply-accumulate instruction, The value before rounding and a signal indicating whether or not an increment occurred during the rounding process are bypassed and used as input to the processor. Before the execution of the first floating-point multiply-accumulate instruction is completed, the second floating-point multiply-accumulate instruction is executed using the input to the processor. A processor equipped with a processing unit.

[0125] (Note 6) The aforementioned processing unit, When executing the first floating-point sum-of-accumulate instruction represented by A*B+C, Depending on the exponential difference between the exponents of the product of A and B and the exponent of C, C is adjusted to the correct number of digits. Multiply A and B and output in carry-over format. The value expressed in the carry-over format and the lower part of the aligned C are added together. If a carry-out occurs in the result of the addition, the upper portion of the aligned C is incremented and used as the input to the processor as the value before the rounding process. The processor described in Appendix 5.

[0126] (Note 7) The aforementioned processing unit, If no carry-out occurs in the result of the addition, the upper portion of the aligned C is used as input to the processor, as the value before the rounding process. The processor described in Appendix 6.

[0127] (Note 8) The aforementioned processing unit, When the second floating-point multiply-accumulate instruction is executed, a signal indicating whether or not an increment occurred in the rounding process is used as a mask and input to the carry-save adder. The processor described in Appendix 6 or 7.

[0128] (Note 9) A computer that performs a data-dependent first floating-point sum-of-accumulate instruction and a second floating-point sum-of-accumulate instruction, The value before rounding and a signal indicating whether or not an increment occurred during the rounding process are bypassed and used as input to the computer. Before the execution of the first floating-point sum-of-accumulate instruction is completed, the second floating-point sum-of-accumulate instruction is executed using the input to the computer. A method of calculation used to perform a process.

[0129] (Note 10) The aforementioned computer, When executing the first floating-point sum-of-accumulate instruction represented by A*B+C, Depending on the exponential difference between the exponents of the product of A and B and the exponent of C, C is adjusted to the correct number of digits. Multiply A and B and output in carry-over format. The value expressed in the carry-over format and the lower part of the aligned C are added together. If a carry-out occurs in the result of the addition, the upper portion of the aligned C is incremented and used as the input to the computer as the value before the rounding process. The calculation method described in Appendix 9.

[0130] (Note 11) The aforementioned computer, If no carry-out occurs in the result of the addition, the upper portion of the aligned C is used as input to the computer as the value before the rounding process. The calculation method described in Appendix 10.

[0131] (Note 12) The aforementioned computer, When the second floating-point multiply-accumulate instruction is executed, a signal indicating whether or not an increment occurred in the rounding process is used as a mask and input to the carry-save adder. The calculation method described in Appendix 10 or 11. [Explanation of Symbols]

[0132] 100,600: FMA calculator 11a~11c,14c,14f,61a~61c,64e:FORMAT 12a,14a,62a,64a:EXP 12b,62b:RSFT 12c, 62c: CSA TREE 12d, 62d: COMPRESSOR 13a,14b,63a,64b:INCREMENTER or not 13b,63b: INCREMENTER 13c,63c: ADDER 13d,63d:LZA 14d,64c:LSFT 14e,64d:ROUND 21: CPU 22: Memory 23: Display control device 231:Display device 24:Storage device 26: External recording medium processing device 25: Input IF 251: Mouse 252: Keyboard 260: Recording media 27: Communication Interface 600: FMA calculator

Claims

1. A processor that performs a data-dependent first floating-point multiply-accumulate instruction and a second floating-point multiply-accumulate instruction, The aforementioned processor, The value before rounding and a signal indicating whether or not an increment occurred during the rounding process are bypassed and used as input to the processor. Before the execution of the first floating-point sum-of-accumulate instruction is completed, the second floating-point sum-of-accumulate instruction is executed using the input to the processor. Computing device.

2. The aforementioned processor, When executing the first floating-point sum-of-accumulate instruction represented by A * B + C, Depending on the exponential difference between the exponents of the product of A and B and the exponent of C, C is adjusted to the correct number of digits. Multiply A and B and output in carry-over format. The value expressed in the carry-over format and the lower part of the aligned C are added together. The value obtained by incrementing the upper part of C, which has been aligned according to the exponential difference, or the value obtained by performing the addition operation, is normalized and used as the input to the processor as the value before the rounding process. The computing device according to claim 1.

3. The aforementioned processor, If a carry-out occurs as a result of the above addition, the upper part of the aligned C is incremented. The arithmetic device according to claim 2.

4. The aforementioned processor, When the second floating-point multiply-accumulate instruction is executed, a signal indicating whether or not an increment occurred in the rounding process is used as a mask and input to the carry-save adder. The computing device according to claim 2 or 3.

5. A processor that performs a data-dependent first floating-point sum-of-accumulate instruction and a second floating-point sum-of-accumulate instruction, The value before rounding and a signal indicating whether or not an increment occurred during the rounding process are bypassed and used as input to the processor. Before the execution of the first floating-point sum-of-accumulate instruction is completed, the second floating-point sum-of-accumulate instruction is executed using the input to the processor. A processor equipped with a processing unit.

6. A computer that performs a data-dependent first floating-point sum-of-accumulate instruction and a second floating-point sum-of-accumulate instruction, The value before rounding and a signal indicating whether or not an increment occurred during the rounding process are bypassed and used as input to the computer. Before the execution of the first floating-point sum-of-accumulate instruction is completed, the second floating-point sum-of-accumulate instruction is executed using the input to the computer. A method of calculation used to perform a process.

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