Wiring board and method for manufacturing the same

Abstract

In a wiring board having a glass core layer, the failure of the outer periphery of the core layer is suppressed. [Solution] The wiring board comprises a glass core layer having one side and the other side, a first laminate including a wiring layer and an insulating layer provided on one side of the core layer, and a first resin portion, wherein the first outer periphery of one side of the core layer is exposed from the first laminate, and the first resin portion covers the first outer periphery and the side surface of the first laminate.

Description

Technical Field

[0001] The present invention relates to a wiring board and a method for manufacturing the same.

Background Art

[0002] A wiring board having a core layer and a laminate including wiring layers and insulating layers alternately laminated on the core layer is known (Patent Document 1). In the manufacturing process of such a wiring board, for example, a core layer having a plurality of wiring regions that are separated into individual wiring boards and a cutting region to be cut when separating is prepared, and a laminate is formed on the upper surface of the core layer. Then, the laminate and the core layer located in the cutting region are cut to produce individual wiring boards.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In some cases, a glass core layer is used for a wiring board. In this case, after cutting for separation, there is a risk of breakage such as chipping or cracking occurring in the outer peripheral portion of the glass core layer.

[0005] The present invention has been made in view of the above points, and an object thereof is to suppress breakage of the outer peripheral portion of a core layer in a wiring board having a glass core layer.

Means for Solving the Problems

[0006] This wiring board comprises a glass core layer having one side and the other side, a first laminate including a wiring layer and an insulating layer provided on one side of the core layer, and a first resin portion. The first outer periphery of one side of the core layer is exposed from the first laminate, and the first resin portion covers the first outer periphery and the side surface of the first laminate. [Effects of the Invention]

[0007] According to the disclosed technology, in a wiring substrate having a glass core layer, it is possible to suppress the fracture of the outer periphery of the core layer. [Brief explanation of the drawing]

[0008] [Figure 1] This figure illustrates a wiring board according to the first embodiment. [Figure 2] This is a diagram (part 1) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 3] This is a diagram (part 2) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 4] This is a diagram (part 3) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 5] This is a cross-sectional view illustrating a wiring board according to a modified example of the first embodiment. [Figure 6] This is a cross-sectional view illustrating a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0009] The embodiments for carrying out the invention will be described below with reference to the drawings. In each drawing, the same reference numerals are used for identical components, and redundant explanations may be omitted.

[0010] <First Embodiment> [Structure of the wiring board according to the first embodiment] Figure 1 illustrates a wiring board according to the first embodiment, where Figure 1(a) is a plan view and Figure 1(b) is a cross-sectional view along line AA in Figure 1(a).

[0011] Referring to Figure 1, the wiring board 1 includes a core layer 10 having one surface 10a and the other surface 10b which is the opposite surface of the first surface 10a; a first laminate 51 including wiring layers and insulating layers alternately laminated on one surface 10a of the core layer 10; a second laminate 52 including wiring layers and insulating layers alternately laminated on the other surface 10b of the core layer 10; a first resin part 41; and a second resin part 42. The wiring board 1 may also have an external connection terminal 18.

[0012] The first laminate 51 has a wiring layer 12, an insulating layer 13, a wiring layer 14, an insulating layer 15, a wiring layer 16, and a solder resist layer 17, which are sequentially laminated on one surface 10a of the core layer 10. The second laminate 52 has a wiring layer 22, an insulating layer 23, a wiring layer 24, an insulating layer 25, a wiring layer 26, and a solder resist layer 27, which are sequentially laminated on the other surface 10b of the core layer 10.

[0013] In the first embodiment, for convenience, the solder resist layer 17 side of the wiring board 1 is referred to as the upper side or one side, and the solder resist layer 27 side as the lower side or the other side. Also, the surface on the solder resist layer 17 side of each part is referred to as one surface or the upper surface, and the surface on the solder resist layer 27 side is referred to as the other surface or the lower surface. However, the wiring board 1 can be used upside down or positioned at any angle. Furthermore, a plan view refers to viewing the object from the direction normal to one surface 10a of the core layer 10, and a planar shape refers to the shape of the object viewed from the direction normal to one surface 10a of the core layer 10.

[0014] The core layer 10 is made of glass. The type of glass used to make up the core layer 10 is not limited; for example, alkali-free glass, quartz glass, borosilicate glass, etc., can be used. The thickness of the core layer 10 is, for example, about 100 to 1000 μm. The core layer 10 is provided with through-holes 10x that penetrate through the core layer 10 in the thickness direction. The planar shape of the through-holes 10x is, for example, circular. The diameter of the through-holes 10x can be, for example, 100 μm or more and 500 μm or less.

[0015] One side 10a of the core layer 10, the first outer peripheral portion 10s is exposed from the first laminate 51. The first outer peripheral portion 10s is located in a frame shape outside the first laminate 51 in a plan view. The width of the first outer peripheral portion 10s can be, for example, 50 μm or more and 300 μm or less.

[0016] The side surface 51c of the first laminate 51 is composed of the side surface of the insulating layer 13, the side surface of the insulating layer 15, and the side surface of the solder resist layer 17. The side surface 51c of the first laminate 51 is inclined in a direction away from the side surface 10c of the core layer 10 as it goes toward the solder resist layer 17 side, for example, in a cross-sectional view. The side surface 51c of the first laminate 51 may be perpendicular to one side 10a of the core layer 10.

[0017] The first resin portion 41 covers the first outer peripheral portion 10s and the first outer peripheral portion 10s side of the side surface 51c of the first laminate 51. In the illustrated example, the upper surface of the first resin portion 41 has a region where the height from one side 10a of the core layer 10 decreases as it goes from the side surface 51c side of the first laminate 51 toward the side surface 10c side of the core layer 10. The upper surface of the first resin portion 41 is, for example, the lowest in height from one side 10a of the core layer 10 above the side surface 10c of the core layer 10.

[0018] The thickness of the thinnest portion of the first resin portion 41 in the lamination direction of the first laminate 51 can be, for example, 10 μm or more and 50 μm or less. The thickness of the thickest portion of the first resin portion 41 in the lamination direction of the first laminate 51 can be, for example, 50 μm or more and 250 μm or less. As the material of the first resin portion 41, for example, an insulating resin mainly composed of an epoxy resin or a polyimide resin can be used.

[0019] The second outer peripheral portion 10t of the other side 10b of the core layer 10 is exposed from the second laminate 52. The second outer peripheral portion 10t is located in a frame shape outside the second laminate 52 in a plan view. The width of the second outer peripheral portion 10t can be, for example, 50 μm or more and 300 μm or less.

[0020] The side surface 52c of the second laminate 52 is composed of the side surface of the insulating layer 23, the side surface of the insulating layer 25, and the side surface of the solder resist layer 27. The side surface 52c of the second laminate 52 is inclined in a direction away from the side surface 10c of the core layer 10 as it faces the solder resist layer 27 side, for example, in a cross-sectional view. The side surface 52c of the second laminate 52 may be perpendicular to the other surface 10b of the core layer 10.

[0021] The second resin portion 42 covers the second outer peripheral portion 10t and the side of the side surface 52c of the second laminate 52 on the second outer peripheral portion 10t side. In the illustrated example, the lower surface of the second resin portion 42 has a region where the height from the other surface 10b of the core layer 10 decreases as it goes from the side surface 52c side of the second laminate 52 toward the side surface 10c side of the core layer 10. The lower surface of the second resin portion 42 is, for example, the lowest in height from the other surface 10b of the core layer 10 below the side surface 10c of the core layer 10.

[0022] The thickness of the thinnest portion of the second resin portion 42 in the lamination direction of the second laminate 52 can be, for example, 10 μm or more and 50 μm or less. The thickness of the thickest portion of the second resin portion 42 in the lamination direction of the second laminate 52 can be, for example, 50 μm or more and 250 μm or less. As the material of the second resin portion 42, for example, an insulating resin mainly composed of an epoxy resin or a polyimide resin can be used.

[0023] The wiring layer 12 is disposed on one surface 10a of the core layer 10. Also, the wiring layer 22 is disposed on the other surface 10b of the core layer 10. The wiring layer 12 and the wiring layer 22 are electrically connected by a through wiring 11 formed in the through hole 10x. The wiring layers 12 and 22 are each patterned into a predetermined planar shape. As the material of the wiring layers 12 and 22 and the through wiring 11, for example, copper (Cu) or the like can be used. The thickness of the wiring layers 12 and 22 is, for example, about 10 to 40 μm. Note that the wiring layer 12, the wiring layer 22, and the through wiring 11 may be integrally formed.

[0024] The insulating layer 13 is an interlayer insulating layer that is arranged on one surface 10a of the core layer 10 and covers the wiring layer 12. As the material for the insulating layer 13, for example, an insulating resin mainly composed of epoxy resin or polyimide resin can be used. The thickness of the insulating layer 13 can be, for example, about 30 to 40 μm. The insulating layer 13 may contain fillers such as silica (SiO2).

[0025] The insulating layer 13 has via holes 13x that penetrate the insulating layer 13 and expose the upper surface of the wiring layer 12. The via holes 13x can be in the shape of an inverted truncated cone recess, where the diameter of the opening on the insulating layer 15 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 12.

[0026] The wiring layer 14 is formed on one side of the insulating layer 13. The wiring layer 14 comprises via wiring filled in via holes 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring pattern is electrically connected to the wiring layer 12 via the via wiring. The material of the wiring layer 14 and the thickness of the wiring pattern can be the same as, for example, the wiring layer 12.

[0027] The insulating layer 15 is formed so as to cover the wiring layer 14 on the upper surface of the insulating layer 13. The material and thickness of the insulating layer 15 can be the same as, for example, the insulating layer 13. The insulating layer 15 may contain fillers such as silica (SiO2).

[0028] The insulating layer 15 has via holes 15x that penetrate the insulating layer 15 and expose the upper surface of the wiring layer 14. The via holes 15x can be inverted truncated cone-shaped recesses in which the diameter of the opening that opens to the solder resist layer 17 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 14.

[0029] The wiring layer 16 is formed on one side of the insulating layer 15. The wiring layer 16 consists of via wiring filled in via holes 15x and a pad formed on the upper surface of the insulating layer 15. The pad is electrically connected to the wiring layer 14 via the via wiring. The material of the wiring layer 16 and the thickness of the pad can be the same as, for example, the same as the wiring layer 12. The thickness of the pad may be greater than the thickness of the wiring layer 12. In addition to the pad, the wiring layer 16 may also include a wiring pattern.

[0030] The solder resist layer 17 is a protective insulating layer located on the outermost side of the wiring substrate 1, and is formed to cover the wiring layer 16 on the upper surface of the insulating layer 15. The solder resist layer 17 has an opening 17x, and a portion of the upper surface of the wiring layer 16 is exposed within the opening 17x. The planar shape of the opening 17x can be, for example, circular. The wiring layer 16 exposed within the opening 17x can be used, for example, as a pad for electrically connecting to electronic components such as semiconductor chips. The solder resist layer 17 can be formed from, for example, a photosensitive epoxy insulating resin or an acrylic insulating resin. The thickness of the solder resist layer 17 is, for example, about 15 to 35 μm.

[0031] Furthermore, a metal layer may be formed on the surface of the wiring layer 16 exposed within the opening 17x, or an organic coating may be formed by applying an anti-oxidation treatment such as OSP (Organic Solderability Preservative) treatment. Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer in which Ni and Au layers are stacked in that order), a Ni / Pd / Au layer (a metal layer in which Ni, Pd, and Au layers are stacked in that order), and a Sn layer.

[0032] If necessary, external connection terminals 18 may be provided on the wiring layer 16 exposed within the opening 17x. The external connection terminals 18 are, for example, solder bumps. As the material for the solder bumps, for example, alloys containing Pb, alloys of Sn and Cu, alloys of Sn and Ag, alloys of Sn, Ag and Cu, etc. can be used.

[0033] The insulating layer 23 is an interlayer insulating layer located on the other surface 10b of the core layer 10 and covering the wiring layer 22. The material and thickness of the insulating layer 23 can be the same as, for example, the insulating layer 13. The insulating layer 23 may contain fillers such as silica (SiO2).

[0034] The insulating layer 23 has via holes 23x that penetrate the insulating layer 23 and expose the lower surface of the wiring layer 22. The via holes 23x can be frustoconical recesses in which the diameter of the opening on the insulating layer 25 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the wiring layer 22.

[0035] The wiring layer 24 is formed on the other side of the insulating layer 23. The wiring layer 24 comprises via wiring filled in via holes 23x and a wiring pattern formed on the underside of the insulating layer 23. The wiring pattern is electrically connected to the wiring layer 22 via the via wiring. The material and thickness of the wiring layer 24 can be the same as, for example, the wiring layer 12.

[0036] The insulating layer 25 is formed on the underside of the insulating layer 23 so as to cover the wiring layer 24. The material and thickness of the insulating layer 25 can be the same as, for example, the insulating layer 13. The insulating layer 25 may contain fillers such as silica (SiO2).

[0037] The insulating layer 25 has via holes 25x that penetrate the insulating layer 25 and expose the lower surface of the wiring layer 24. The via holes 25x can be frustoconical recesses in which the diameter of the opening that opens to the solder resist layer 27 side is larger than the diameter of the bottom surface of the opening formed by the lower surface of the wiring layer 24.

[0038] The wiring layer 26 is formed on the other side of the insulating layer 25. The wiring layer 26 comprises via wiring filled in via holes 25x and a wiring pattern formed on the underside of the insulating layer 25. The wiring pattern is electrically connected to the wiring layer 24 via the via wiring. The material and thickness of the wiring layer 26 can be the same as, for example, the wiring layer 12.

[0039] The solder resist layer 27 is a protective insulating layer located on the outermost side of the wiring board 1, and is formed to cover the wiring layer 26 on the underside of the insulating layer 25. The material and thickness of the solder resist layer 27 can be the same as, for example, the solder resist layer 17. The solder resist layer 27 has an opening 27x, and a portion of the underside of the wiring layer 26 is exposed within the opening 27x. The planar shape of the opening 27x can be, for example, circular. The wiring layer 26 exposed within the opening 27x can be used as a pad for electrically connecting to a mounting board such as a motherboard. If necessary, the aforementioned metal layer may be formed on the underside of the wiring layer 26 exposed within the opening 27x, or an anti-oxidation treatment such as OSP treatment may be applied.

[0040] [Manufacturing method for wiring boards] Figures 2 to 4 illustrate the manufacturing process of a wiring board according to the first embodiment. Figure 2 is a plan view, and Figures 3 and 4 are partial cross-sectional views corresponding to the position of line BB in Figure 2.

[0041] First, in the process shown in Figures 2 and 3(a), a glass core layer 10 is prepared. The core layer 10 has multiple wiring regions R that are separated into individual pieces to form a wiring substrate, and cutting regions D that are cut when the core is separated into individual pieces. In Figures 2 and 3(a), the cutting regions D are shown as lines, but they may be regions with a certain width. Next, through holes 10x that penetrate from one surface 10a to the other surface 10b are formed in the core layer 10 located in the wiring regions R.

[0042] The through-hole 10x can be formed, for example, by wet etching. Examples of etching solutions used in this process include hydrofluoric acid and strong alkaline solutions. If the through-hole 10x is formed by drilling, there is a risk of cracks occurring in the glass constituting the core layer 10, but by using wet etching, the through-hole 10x can be formed without cracking the glass.

[0043] Next, in the process shown in Figures 3(b) to 3(d), a first laminate 51 is formed on one surface 10a of the core layer 10, including alternately stacked wiring layers and insulating layers. A second laminate 52 is also formed on the other surface 10b of the core layer 10, including alternately stacked wiring layers and insulating layers. Specifically, as shown in Figure 3(b), first, wiring layers 12 are placed in each wiring region R on one surface 10a of the core layer 10, and wiring layers 22 are placed in each wiring region R on the other surface of the core layer 10, forming through-holes 10x and through-holes 11. For example, a seed layer (copper, etc.) is formed to cover one surface 10a of the core layer 10, the other surface 10b, and the inner wall surface of the through-holes 10x by electroless plating or sputtering, and an electroplated layer (copper, etc.) is formed on the seed layer by electroplating using the seed layer as a power supply layer. As a result, the through-holes 10x are filled with an electroplated layer formed on the seed layer, and a conductive layer is formed on one surface 10a and the other surface 10b of the core layer 10, with the seed layer and the electroplated layer laminated together. Next, the conductive layer is patterned into a predetermined planar shape by subtractive method or the like to form wiring layers 12 and 22.

[0044] Next, as shown in Figure 3(c), insulating layers 13 and 23, and wiring layers 14 and 24 are formed. First, insulating layers 13 are placed in each wiring region R and each cutting region D on one surface 10a of the core layer 10 to cover the upper surface of the wiring layer 12. Specifically, for example, a semi-cured film-like epoxy resin is laminated onto one surface 10a of the core layer 10 to cover the wiring layer 12, and then cured to form the insulating layer 13. Alternatively, instead of laminating with a film-like epoxy resin, a liquid or paste-like epoxy resin may be applied and then cured to form the insulating layer 13. The material and thickness of the insulating layer 13 are as described above. Similarly, insulating layers 23 are placed in each wiring region R and each cutting region D on the other surface 10b of the core layer 10 to cover the lower surface of the wiring layer 22.

[0045] Next, via holes 13x are formed in the insulating layer 13, penetrating the insulating layer 13 and exposing the upper surface of the wiring layer 12. Similarly, via holes 23x are formed in the insulating layer 23, penetrating the insulating layer 23 and exposing the lower surface of the wiring layer 22. The via holes 13x and 23x can be formed, for example, by a laser processing method using a CO2 laser. After forming the via holes 13x and 23x, it is preferable to perform a desmear treatment to remove any resin residue adhering to the surfaces of the wiring layers 12 and 22 exposed at the bottom of the via holes 13x and 23x.

[0046] Next, a wiring layer 14 is formed on one side of the insulating layer 13. The wiring layer 14 consists of via wiring filled in via holes 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring layer 14 is electrically connected to the wiring layer 12 exposed at the bottom of the via holes 13x. Similarly, a wiring layer 24 is formed on the other side of the insulating layer 23. The wiring layer 24 consists of via wiring filled in via holes 23x and a wiring pattern formed on the lower surface of the insulating layer 23. The wiring layer 24 is electrically connected to the wiring layer 22 exposed at the bottom of the via holes 23x. The materials and thickness of the wiring patterns of the wiring layers 14 and 24 can be the same as those of the wiring layer 12, for example. The wiring layers 14 and 24 are formed, for example, by a semi-additive method.

[0047] Next, as shown in Figure 3(d), insulating layers 15 and 25, wiring layers 16 and 26, solder resist layers 17 and 27, and external connection terminals 18 are formed. First, the same process as in Figure 3(c) is repeated to form insulating layers 15 and 25 and wiring layers 16 and 26. Next, a solder resist layer 17 is formed on the upper surface of insulating layer 15 so as to cover the wiring layer 16. Also, a solder resist layer 27 is formed on the lower surface of insulating layer 25 so as to cover the wiring layer 26. The solder resist layer 17 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy insulating resin to the upper surface of insulating layer 15 by screen printing, roll coating, or spin coating so as to cover the wiring layer 16. Alternatively, for example, a film-like photosensitive epoxy insulating resin may be laminated to the upper surface of insulating layer 15 so as to cover the wiring layer 16. The method for forming the solder resist layer 27 is the same as for the solder resist layer 17. Subsequently, the solder resist layers 17 and 27 are exposed and developed to form an opening 17x in the solder resist layer 17 that exposes the wiring layer 16. An opening 27x is also formed in the solder resist layer 27 that exposes a portion of the lower surface of the wiring layer 26. If necessary, an external connection terminal 18 may be provided on the wiring layer 16 exposed within the opening 17x. The external connection terminal 18 is, for example, a solder bump formed by solder reflow.

[0048] Next, in the process shown in Figure 4(a), a first groove 51x is formed that penetrates the first laminate 51 so as to straddle the cutting region D, exposing one surface 10a of the core layer 10. The first groove 51x is formed along the cutting region D and covers the entire cutting region D. In each wiring region R, the one surface 10a of the core layer 10 exposed in the first groove 51x is the portion that will become the first outer periphery 10s after fragmentation. Also, a second groove 52x is formed that penetrates the second laminate 52 so as to straddle the cutting region D, exposing the other surface 10b of the core layer 10. The second groove 52x is formed along the cutting region D and covers the entire cutting region D. In each wiring region R, the other surface 10b of the core layer 10 exposed in the second groove 52x is the portion that will become the second outer periphery 10t after fragmentation. The first groove 51x and the second groove 52x can be formed, for example, by irradiating the first laminate 51 and the second laminate 52 with laser light of a wavelength that is absorbed by them. When laser light is irradiated, the width of the first groove 51x and the second groove 52x increases, for example, as it moves away from the core layer 10. The first groove 51x and the second groove 52x may also be formed using a cutting blade.

[0049] After forming the first groove 51x and the second groove 52x, a laser beam L is irradiated along the cutting region D onto one surface 10a of the core layer 10 exposed within the first groove 51x. By focusing the laser beam into the core layer 10, a modified layer that serves as the starting point for the split is formed inside the core layer 10 located below the cutting region D. In this step, a laser beam with a wavelength that is transparent to the core layer 10 is irradiated.

[0050] Next, in the process shown in Figure 4(b), a first resin portion 41 is formed that covers one surface 10a of the core layer 10 exposed in the first groove 51x, and the side of the inner surface of the core layer 10 facing one surface 10a. A second resin portion 42 is also formed that covers the other surface 10b of the core layer 10 exposed in the second groove 52x, and the side of the inner surface of the core layer 10 facing the other surface 10b. For example, the first resin portion 41 can be formed by applying uncured resin into the first groove 51x by potting and curing it. The second resin portion 42 can be formed in the same manner. The first resin portion 41 and the second resin portion 42 are, for example, thinnest at the position overlapping with the cutting region D in a plan view, and become thicker as they move away from the cutting region D in a plan view.

[0051] As the material for the first resin part 41 and the second resin part 42, for example, an insulating resin mainly composed of epoxy resin or polyimide resin can be used. Preferably, the first resin part 41 and the second resin part 42 do not contain fillers. Alternatively, it is preferable that they contain less filler than the resin of the insulating layer. This makes it easier to cut the first resin part 41 and the second resin part 42 when cutting the first resin part 41, the core layer 10, and the second resin part 42 in the cutting region D in the process shown in Figure 4(c).

[0052] Furthermore, the thickness of the thinnest part of the first resin portion 41 in the lamination direction of the first laminate 51 can be, for example, 10 μm or more and 50 μm or less. The thickness of the thinnest part of the second resin portion 42 in the lamination direction of the second laminate 52 can be, for example, 10 μm or more and 50 μm or less. By making the thickness of the thinnest parts of the first resin portion 41 and the second resin portion 42 10 μm or more, the first outer peripheral portion 10s exposed from the first laminate 51 can be sufficiently protected by the first resin portion 41, and the second outer peripheral portion 10t exposed from the second laminate 52 can be sufficiently protected by the second resin portion 42. In addition, by making the thickness of the thinnest parts of the first resin portion 41 and the second resin portion 42 50 μm or less, the cutting of the first resin portion 41 and the second resin portion 42 becomes easier when cutting the first resin portion 41, the core layer 10, and the second resin portion 42 in the cutting region D in the process shown in Figure 4(c).

[0053] Next, in the process shown in Figure 4(c), the first resin portion 41, the core layer 10, and the second resin portion 42 are cut in the cutting region D shown in Figure 4(b) to produce a plurality of individual wiring boards 1. By cutting in the cutting region D, the first groove portion 51x is divided, and in each wiring board 1, the first resin portion 41 covers the first outer periphery portion 10s and the first outer periphery portion 10s side of the side surface 51c of the first laminate 51. Also, the second groove portion 52x is divided, and in each wiring board 1, the second resin portion 42 covers the second outer periphery portion 10t and the second outer periphery portion 10t side of the side surface 52c of the second laminate 52.

[0054] Cutting can be performed, for example, by attaching the structure shown in Figure 4(b) to an expandable tape and expanding the expandable tape in the direction of the outer circumference of the structure. By expanding the expandable tape, a force in the direction of the expansion of the expandable tape can be applied to the modified portion of the core layer 10, the first resin portion 41, and the second resin portion 42. As a result, the core layer 10 is divided along the modified layer that serves as the starting point for the division, and the first resin portion 41 and the second resin portion 42 are also divided near the cutting region D.

[0055] Alternatively, instead of expanding the expandable tape, force may be applied near the cutting area D using, for example, a roller or a rod-shaped pressing member to separate the first resin portion 41, the core layer 10, and the second resin portion 42.

[0056] In this method for manufacturing the wiring board 1, a first groove 51x is formed so as to straddle the cutting region D, a laser beam is irradiated onto one surface 10a of the core layer 10 exposed within the first groove 51x to form a modified layer inside the core layer 10, and a first resin portion 41 is formed within the first groove 51x. A second groove 52x is also formed so as to straddle the cutting region D, and a second resin portion 42 is formed within the second groove 52x. Subsequently, the first resin portion 41, the core layer 10, and the second resin portion 42 are cut along the cutting region D to produce multiple individual wiring boards 1.

[0057] As a result, in the individualized wiring board 1, the first outer peripheral portion 10s of one surface 10a of the core layer 10 is covered by the first resin portion 41, thereby suppressing damage such as chipping or cracking of the first outer peripheral portion 10s. Furthermore, in the individualized wiring board 1, the second outer peripheral portion 10t of the other surface 10b of the core layer 10 is covered by the second resin portion 42, thereby suppressing damage such as chipping or cracking of the second outer peripheral portion 10t.

[0058] <Variations of the first embodiment> In the modified version of the first embodiment, an example is shown in which the upper surface of the resin part is flat. Note that in the modified version of the first embodiment, the description of components that are the same as those described in the previously described embodiment may be omitted.

[0059] Figure 5 is a cross-sectional view illustrating a modified wiring board according to the first embodiment. Referring to Figure 5, wiring board 1A differs from wiring board 1 (see Figure 1(b), etc.) in that the first resin part 41 and the second resin part 42 are replaced by the first resin part 45 and the second resin part 46.

[0060] The first resin portion 45, like the first resin portion 41, covers the first outer peripheral portion 10s and the side surface 51c of the first laminate 51 on the side of the first outer peripheral portion 10s. The upper surface of the first resin portion 45 is flat and, for example, parallel to one surface 10a of the core layer 10. The thickness of the first resin portion 45 in the lamination direction of the first laminate 51 is constant and can be, for example, 10 μm or more and 100 μm or less.

[0061] The second resin portion 46, like the second resin portion 42, covers the second outer periphery 10t and the side surface 52c of the second laminate 52 on the side of the second outer periphery 10t. The lower surface of the second resin portion 46 is flat and, for example, parallel to the other surface 10b of the core layer 10. The thickness of the second resin portion 46 in the lamination direction of the second laminate 52 is constant and can be, for example, 10 μm or more and 100 μm or less.

[0062] For the materials of the first resin part 45 and the second resin part 46, for example, an insulating resin mainly composed of epoxy resin or polyimide resin can be used. In this application, "parallel" means that an error of ±10 degrees from strictly parallel is permitted. Also, "constant thickness" means that the thickness of the thickest part is +10% or less of the thickness of the thinnest part.

[0063] To form the first resin portion 45 and the second resin portion 46, for example, in the process shown in Figure 4(b) of the first embodiment, a semi-cured film-like insulating resin cut to an appropriate size is placed in the first groove portion 51x and the second groove portion 52x and cured. After that, the same process as shown in Figure 4(c) of the first embodiment can be carried out.

[0064] Thus, the upper surface of the first resin part 45 and the lower surface of the second resin part 46 may be flat. In this case as well, since the first outer peripheral part 10s of one surface 10a of the core layer 10 is covered by the first resin part 45, it is possible to suppress damage such as chipping or cracking of the first outer peripheral part 10s. Furthermore, since the second outer peripheral part 10t of the other surface 10b of the core layer 10 is covered by the second resin part 46, it is possible to suppress damage such as chipping or cracking of the second outer peripheral part 10t.

[0065] <Second Embodiment> The second embodiment shows an example of a semiconductor device in which a semiconductor chip is mounted on a wiring board according to the first embodiment. In the second embodiment, descriptions of components that are the same as those described in the previously described embodiments may be omitted.

[0066] Figure 6 is a cross-sectional view illustrating a semiconductor device according to the second embodiment. Referring to Figure 6, the semiconductor device 2 includes the wiring board 1 shown in Figure 1, a semiconductor chip 70, bumps 80, and underfill resin 90.

[0067] The semiconductor chip 70 has a chip body 71 and electrodes 72. The chip body 71 is formed by creating a semiconductor integrated circuit (not shown) on a thin semiconductor substrate (not shown) made of, for example, silicon. Electrodes 72 are formed on the semiconductor substrate (not shown) and are electrically connected to the semiconductor integrated circuit.

[0068] The bump 80 is formed on the electrode 72 of the semiconductor chip 70 and electrically connects the electrode 72 to the external connection terminal 18 of the wiring board 1. The electrode 72 can be formed from, for example, copper. The bump 80 is, for example, a solder bump. As the material for the solder bump, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag and Cu, etc. can be used. The underfill resin 90 is filled between the semiconductor chip 70 and the upper surface of the solder resist layer 17 of the wiring board 1.

[0069] In this way, a semiconductor device can be realized by mounting a semiconductor chip on the wiring board according to the first embodiment. Wiring board 1A may be used instead of wiring board 1.

[0070] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims.

[0071] For example, the above embodiment described a wiring board having a first laminate on one side of a glass core layer and a second laminate on the other side. However, the present invention can also be applied to a wiring board having a first laminate on one side of a glass core layer but not a second laminate on the other side, and will produce similar effects. In the case of a wiring board that does not have a second laminate, through-holes do not need to be provided in the core layer. [Explanation of symbols]

[0072] 1.1A Wiring Board 2 Semiconductor devices 10-core layer 10a One side 10b The other side 10c side 10s 1st outer circumference 10t 2nd outer circumference 10x Through Hole 11. Through-wiring 12,14,16,22,24,26 wiring layer 13, 15, 23, 25 Insulating layer 13x, 15x, 23x, 25x Beer Hall 17,27 Solder Resist Layer 17x,27x opening 18 External connection terminals 41,45 First resin part 42,46 Second resin part 51. First layer 51c,52c side 51x 1st groove 52. Second layer 52x Second groove 71 Chip body 72 electrode 80 Bump 90 Underfill resin

Claims

1. A glass core layer having one side and the other side, A first laminate including a wiring layer and an insulating layer provided on one side of the core layer, It has a first resin part, The first outer periphery of one surface of the core layer is exposed from the first laminate, The first resin portion is a wiring board that covers the first outer periphery and the side surface of the first laminate.

2. The wiring board according to claim 1, wherein the upper surface of the first resin portion decreases in height from one side of the core layer as it moves from the side of the first laminate toward the side of the core layer.

3. The wiring board according to claim 1 or 2, wherein the first resin portion does not contain a filler.

4. The wiring board according to claim 1 or 2, wherein the upper surface of the first resin portion is parallel to one surface of the core layer.

5. A second laminate including a wiring layer and an insulating layer provided on the other side of the core layer, It has a second resin part, The second outer periphery of the other surface of the core layer is exposed from the second laminate, The wiring board according to claim 1, wherein the second resin portion covers the second outer periphery and the side surface of the second laminate.

6. The wiring board according to claim 5, wherein the height of the lower surface of the second resin portion decreases from the other surface of the core layer as you move from the side surface of the second laminate toward the side surface of the core layer.

7. The wiring board according to claim 5 or 6, wherein the second resin portion does not contain a filler.

8. The wiring board according to claim 5 or 6, wherein the lower surface of the second resin portion is parallel to the other surface of the core layer.

9. A process of preparing a glass core layer having multiple wiring regions that will be separated into individual pieces to form a wiring board, and cutting regions that will be cut during the separation process, A step of forming a first laminate including a wiring layer and an insulating layer on one side of the core layer, A step of forming a first groove that penetrates the first laminate and exposes one side of the core layer, so as to straddle the aforementioned cutting region, A step of irradiating one surface of the core layer exposed in the first groove along the cutting region with laser light to form a modified layer inside the core layer, A step of forming a first resin portion that covers one surface of the core layer exposed in the first groove and the inner surface of the first groove, A method for manufacturing a wiring board, comprising the steps of cutting the first resin portion and the core layer at the cutting region to produce a plurality of individual wiring boards.

10. A step of forming a second laminate including wiring layers and insulating layers alternately stacked on the other side of the core layer, A step of forming a second groove that penetrates the second laminate and exposes the other surface of the core layer, so as to straddle the aforementioned cutting region, The process includes the step of forming a second resin portion that covers the other surface of the core layer exposed within the second groove, and the other surface side of the core layer on the inner surface of the second groove, The method for manufacturing a wiring board according to claim 9, wherein in the cutting step, the first resin portion, the core layer, and the second resin portion are cut in the cutting region to produce a plurality of individual wiring boards.

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