Microelectronic assembly with multiple liners in glass-penetrating vias

Abstract

To relieve stress within glass through vias, a microelectronic assembly is provided that includes multiple liner materials as a base for the conductor. [Solution] The microelectronic assembly includes a glass core 103 having vias 192 containing a first conductive material, a first liner 422 containing a dielectric material having a width between 0.1 and 100 nanometers and located on the side walls 190-4 of the vias, and a second liner 424 between the first liner and the first conductive material containing a second conductive material having a width between 5 and 20 nanometers. In some embodiments, the first conductive material is copper, and the second conductive material is ruthenium or copper. In some embodiments, the microelectronic assembly further includes a third liner between the second liner and the first conductive material, the third liner containing a third conductive material having a width between 100 and 250 nanometers.

Description

[Background technology]

[0001]

[0001] For the past several decades, scaling of feature elements in integrated circuits (ICs) has been a driving force behind the ever-growing semiconductor industry and emerging applications in fields such as big data, artificial intelligence, mobile communications, and autonomous driving. Scaling toward smaller feature elements allows for an increase in the density of functional units within a limited area of ​​a semiconductor chip. For example, reducing transistor size allows for an increase in the number of memory or logic devices incorporated on the chip, resulting in the manufacture of products with increased capacity. However, the ever-increasing demand for capacity is not without its challenges. The need to optimize the manufacturing and performance of each component (e.g., each transistor) is becoming increasingly important.

[0002]

[0002] In parallel with optimization at the transistor level, the field of advanced IC packaging is rapidly developing to adapt to the expected performance and requirements of reducing transistor size. Multiple IC dies are now commonly coupled together in a multi-die IC package to integrate features or functionality and facilitate connectivity to other components such as the package substrate. For example, an IC package may include an embedded multi-die interconnect bridge (EMIB) for coupling two or more IC dies.

[0003]

[0003] Integrating multiple dies within a single IC package offers significant advantages, but it also introduces additional complexity due to the placement of materials with different material properties in close proximity to each other. When an IC package undergoes multiple processes involving varying temperature and pressure loads, the individual materials within the package may behave differently from each other, potentially resulting in out-of-plane deformation of various layers known as "package warpage." One way to address package warpage is to use a rigider core to which the different IC dies are mounted. Recently, glass cores have been studied as an alternative to organic resin cores (e.g., cores based on the use of ABF (Ajinomoto Build-up Film)). Glass is considered to be more rigid than organic resin materials and offers several advantages such as superior thermal properties, a low coefficient of thermal expansion (CTE), high electrical insulation, chemical resistance, light transmittance, and compatibility with advanced semiconductor properties. However, a major challenge to the widespread adoption of glass cores is that glass is highly susceptible to damage caused by mechanical and / or thermal stresses, such as damage caused by stresses in metal-filled through-glass vias (TGVs). [Brief explanation of the drawing]

[0004]

[0004] Embodiments will be readily understood by the following detailed description relating to the accompanying drawings. To facilitate this description, similar reference numerals indicate similar structural elements. Embodiments are shown in the drawings of the accompanying drawings as examples, not as limitations. [Figure 1]

[0005] Figure 1 is a schematic side cross-sectional view of an exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 2]

[0006] Figure 2 is a schematic side cross-sectional view of another exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 3]

[0007] Figure 3 shows the surface of a glass core that may be the source of TGV stress according to some embodiments of this disclosure. [Figure 4A]

[0008] Figure 4A is a simplified schematic side cross-sectional view of an exemplary portion of a microelectronic assembly according to some embodiments of the present disclosure. [Figure 4B]

[0008] Figure 4B is a simplified schematic side cross-sectional view of an exemplary portion of a microelectronic assembly according to some embodiments of the present disclosure. [Figure 4C]

[0008] Figure 4C is a simplified schematic side cross-sectional view of an exemplary portion of a microelectronic assembly according to some embodiments of the present disclosure. [Figure 5A]

[0009] Figure 5A is a simplified side cross-sectional view illustrating various manufacturing steps of an exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 5B]

[0009] Figure 5B is a simplified side cross-sectional view showing various manufacturing steps of an exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 5C]

[0009] Figure 5C is a simplified side cross-sectional view showing various manufacturing steps of an exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 5D]

[0009] Figure 5D is a simplified side cross-sectional view showing various manufacturing steps of an exemplary microelectronic assembly according to some embodiments of the present disclosure. [Figure 6]

[0010] Figure 6 is a flowchart illustrating an exemplary manufacturing method for providing a glass core having multiple liners in one or more TGVs, according to some embodiments of the present disclosure. [Figure 7]

[0011] Figure 7 is a cross-sectional view of a device package that may include one or more microelectronic assemblies according to any embodiment disclosed herein. [Figure 8]

[0012] Figure 8 is a side cross-sectional view of a device assembly that may include one or more microelectronic assemblies according to any embodiment disclosed herein. [Figure 9]

[0013] Figure 9 is a block diagram of an exemplary computing device which may include one or more microelectronic assemblies according to any embodiment disclosed herein. [Modes for carrying out the invention]

[0005]

[0014] The structures and assemblies disclosed herein may include a glass core, also referred to herein as a “glass layer,” through which TGVs extend for front-to-back connectivity between two different substrates. The substrates may include a dielectric material having conductive paths internally formed on the surface of the glass core. Conductive paths through the dielectric material can provide routing for design flexibility, and the uniform diameter of the TGVs can provide dimensional stability and improved connectivity. Compared to conventional epoxy cores, glass cores offer several advantages, including, among others, higher TGV density, lower signal loss, and lower total thickness variation (TTV). Another advantage is that glass cores enable TGVs with higher aspect ratios. Higher aspect ratio TGVs are required to achieve the desired finer pitch. In some implementations, TGVs can extend between the top and bottom surfaces of the glass core to provide electrical connectivity between electronic elements, such as dies and / or package substrates, bonded to the top and bottom surfaces of the glass core, for example. In other implementations, the TGV may be blind vias that extend from the upper / lower surface of the glass core toward the opposite surface but do not reach it, for example, providing an electrical connection from the surface of the glass core to a conductive trace or IC element embedded in the glass core. The TGV can also support efficient thermal management by providing a path for heat dissipation from the active element to the external environment of the package.

[0006]

[0015] As mentioned above, glass possesses properties that promise integration in advanced IC packaging. By incorporating TGVs within a glass core, more compact and efficient designs for microelectronic assemblies become possible. However, the integration of TGVs into a glass core is no trivial matter. Traditionally, the fabrication of TGVs involves forming an opening for the future TGV, lining the opening with a seed material, and then depositing a conductive bulk filler material within the lined opening. The seed material typically includes a low-resistivity metal such as copper, which can be deposited as a thin film on a substantially non-conductive surface (e.g., the sidewall) of the opening in the glass core. The seed material is intended to provide a conductive surface for uniform and controlled deposition of the conductive bulk filler material in subsequent deposition steps, such as when the conductive bulk filler material is deposited within the lined opening using a process such as electroplating. One challenge related to the integration of materials into the TGV's glass core arises from the difference in CTE (Cell Temperature Expansion) between the materials that can be used for the glass core and the metals used for the seed material and conductive bulk filler material deposited within the TGV (this phenomenon is sometimes called "CTE mismatch"). CTE is a measure of how much a material expands or contracts with respect to temperature changes. CTE is typically defined as the rate of increase in length per unit temperature rise, measured, for example, in parts per million (ppm) or ppm / K per Kelvin (K) degree. Glass materials and metals that can be used in the glass core have significantly different CTEs. Metals have relatively high CTEs, meaning they can expand and contract significantly with temperature changes. Glass materials, on the other hand, have much lower CTEs and are less responsive to temperature changes. For example, the CTE of a glass material may be on the order of about 3.5 ppm / K, while the CTE of a metal like copper may be on the order of about 15 to 17 ppm / K.When a metal is in close contact with glass (for example, conductive bulk filler or seed material in a TGV within a glass structure), and the assembly is exposed to temperature changes such as heating or cooling, the metal will heat or cool much faster and to a greater extent than the glass. This leads to the generation of significant stress at the interface between the two materials. For example, an expanding metal may cause compressive stress, while a contracting metal may cause tensile stress. Stresses high enough can exceed the strength of the glass, leading to crack formation, which can then propagate and compromise the structural integrity of the glass. Even if cracks do not form immediately, repeated thermal cycles can gradually weaken the glass, potentially leading to surface scratches or microcracks. Prolonged exposure to stress induced by a CTE mismatch causes the glass to gradually degrade and become more brittle over time.

[0007]

[0016] Embodiments of the present disclosure relate to techniques, as well as related devices and methods, for mitigating (e.g., mitigating or reducing) CTE mismatch-induced stress caused by the proximity of the conductive material of a TGV to the glass material of a glass structure, such as a glass core. Embodiments of the present disclosure are based on the understanding that including multiple liners (e.g., two or more liners) on the sidewalls of a TGV, which function as a buffer layer between the conductive material and the glass core within the TGV, may help reduce TGV stress because the liners separate the glass from the conductive bulk filler material deposited within the TGV.

[0008]

[0017] In particular, in some embodiments, the liners may include a first liner of dielectric material deposited on the sidewall of the TGV, followed by a second liner of conductive material deposited on top of the first liner on the sidewall of the TGV. Implementing a first liner containing dielectric material in direct contact with the glass may help reduce tensile stress caused, for example, by the shrinkage of the metal later filled into the TGV. In some embodiments, the first liner may have a lower CTE than the second liner, which may be particularly advantageous in reducing stress induced by the mismatch in CTEs, as well as in reducing compressive stress caused, for example, by the expansion of the metal later filled into the TGV. Furthermore, a first liner positioned directly along the sidewall of the TGV may help smooth the glass surface at the sidewall. The second liner may be deposited on the first liner within the TGV, and the conductive material of the second liner has improved adhesion to the dielectric material of the first liner, which reduces mechanical stress and enables conformal coating and high step coverage without additional adhesive layers, even within a TGV with a high aspect ratio.

[0009]

[0018] Accordingly, the disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, the microelectronic assembly may include a core having through vias (the through vias comprising a first conductive material having a first average particle size); a first liner material (including a dielectric material) in the sidewalls of the through vias; and a second liner material between the first liner material and the first conductive material of the through vias (comprising a second conductive material having a second average particle size, where the first average particle size is greater than the second average particle size). In some such embodiments, the first and second conductive materials may include copper. In another embodiment, the microelectronic assembly may include a glass layer having a first surface and a second surface on the opposite side; vias (containing a first conductive material) extending through the glass layer between the first and second surfaces; a first liner material (containing a dielectric material having a width between 0.1 nanometers and 100 nanometers) on the sidewalls of the vias; and a second liner material (containing a second conductive material having a width between 5 nanometers and 20 nanometers, unlike the first conductive material) between the first liner material and the first conductive material of the vias. In some such embodiments, the first conductive material may contain copper, and the second conductive material may contain ruthenium. In some such embodiments, the microelectronic assembly may further include a third liner material between the second liner material and the first conductive material of the vias, the third liner material containing a third conductive material having a width between 100 nanometers and 250 nanometers. In yet another embodiment, the microelectronic assembly may include a glass core having a first surface and a second surface on the opposite side; conductive vias penetrating the glass core; a first liner (containing dielectric material) within the conductive vias; and a second liner (containing alternating layers of the first and second conductive materials, with the total width of the second liner being between 5 nanometers and 30 nanometers) between the first liner and the material of the conductive vias.In some such embodiments, the first conductive material may include ruthenium and the second conductive material may include copper.

[0010]

[0019] Each of the structures, assemblies, packages, methods, devices, and systems of the present disclosure may have several novel aspects, and only one of those aspects alone may not carry all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0011]

[0020] In the following detailed description, various aspects of the exemplary implementations will be described using terms commonly used by those skilled in the art to convey the substance of their work to other skilled artisans.

[0012]

[0021] The terms "circuit" and "circuitry" mean one or more passive and / or active electrical and / or electronic components configured to cooperate with each other to provide a desired function. These terms also refer to analog circuits, digital circuits, wired circuits, programmable circuits, microcontroller circuits, and / or any other type of physical hardware electrical and / or electronic components.

[0013]

[0022] The term "integrated circuit" means a circuit integrated into a monolithic semiconductor or similar material.

[0014]

[0023] In some embodiments, the IC dies disclosed herein may include a substantially single-crystal semiconductor such as silicon or germanium as a base material when the integrated circuit is manufactured using conventional semiconductor processing methods. The semiconductor substrate may include, for example, N-type or P-type materials. The die may include, for example, bulk silicon (or other bulk semiconductor material) or a crystal-based material formed using a semiconductor-on-insulator (SOI) structure. In some other embodiments, one or more base materials of the IC die may include alternative materials that may or may not be combined with silicon, and these alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of Group III-N, Group III-V, Group II-VI, or Group IV materials. In yet another embodiment, the base material may include a compound semiconductor having, for example, a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In yet another embodiment, the base material may include an intrinsic IV or III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in an alternative embodiment, nominal impurity dopant levels may be present. In yet another embodiment, the die may include an amorphous material such as a polymer; for example, the base material may include a silica-filled epoxy. In yet another embodiment, the base material may include a high-mobility oxide semiconductor material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide.Generally, the base material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, plattnerite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, and each of these may optionally be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although several examples of the die material are described herein, any material or structure that can function as a basis (e.g., the base material) on which an IC circuit and structure as described herein can be constructed may fall within the spirit and scope of this disclosure.

[0015]

[0024] Unless otherwise stated, the IC die described herein includes one or more IC structures (or, simply put, "ICs") configured to perform (i.e., execute) a predetermined function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement a memory circuit (e.g., one or more of an IC that implements a memory device, a memory array, a control logic configured to control the memory device and array, etc.). In another such example, the term "arithmetic die" may be used to describe a die that includes one or more ICs that implement a logic / arithmetic circuit (e.g., an IC that implements one or more of input / output (I / O) functions, arithmetic operations, pipelining of data, etc.).

[0016]

[0025] In another example, the terms "package" and "IC package" are synonymous, similar to the terms "die" and "IC die." Note that the terms "chip," "chipset," "die," and "IC die" are interchangeable in this context.

[0017]

[0026] The term “optical structure” includes, as referred to herein, arrangements of forms created within an IC for receiving, converting, and / or transmitting optical signals. This may include photoconductors such as waveguides, electromagnetic radiation sources such as lasers and light-emitting diodes (LEDs), and electro-optical devices such as photodetectors.

[0018]

[0027] In various embodiments, any photonic IC (PIC) described herein may include semiconductor materials, such as N-type or P-type materials. The PIC may include, for example, bulk silicon (or other bulk semiconductor materials) or crystalline-based materials formed using an SOI structure (or, generally, a semiconductor-on-insulator structure). In some embodiments, the PIC may be formed using alternative materials, which may or may not be combined with silicon, including, but are not limited to, lithium niobate, indium phosphide, silicon dioxide, germanium, silicon-germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum arsenide-gallium, aluminum arsenide, indium arsenide-aluminum, aluminum arsenide-indium, indium arsenide-gallium, gallium nitride, indium nitride-indium, or gallium antimonide, or other combinations of Group III-N or Group IV materials. In some embodiments, the PIC may include an amorphous material such as a polymer. In some embodiments, the PIC may be formed on a printed circuit board (PCB). In some embodiments, the PIC may be heterogeneous, including a carrier material (such as glass or silicon carbide) as a base material having a thin semiconductor layer on which an active surface containing transistors and similar components is located. While several examples of materials for a PIC are described herein, any material or structure that may serve as a basis on which a PIC may be built falls within the spirit and scope of this disclosure.

[0019]

[0028] Unless otherwise specified, the term "insulating" means "electrically insulating," and the term "conductive" means "electrically conductive." With respect to optical signals and / or devices, components, and elements that operate with or in relation to optical signals, the term "conductive" may also mean "optically conductive."

[0020]

[0029] Terms such as "oxide," "carbide," and "nitride" refer to compounds that contain oxygen, carbon, nitrogen, etc., respectively.

[0021]

[0030] The term "high-k dielectric" refers to materials with a dielectric constant higher than that of silicon oxide, while the term "low-k dielectric" refers to materials with a dielectric constant lower than that of silicon oxide.

[0022]

[0031] The term “insulating material” refers to a substantially nonconductive solid material (and / or a liquid material that solidifies after processing as described herein). These may include, for example, but not limited to, organic polymers and plastics, as well as inorganic materials, such as ionic crystals, porcelain, glass, silicon and alumina, or combinations thereof. They may include dielectric materials, highly polarizable materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of this disclosure. Further examples of insulating materials are underfill and molded or molded materials used in packaging applications, including, for example, organic interposers, package supports, and other such components.

[0023]

[0032] In various embodiments, elements associated with the IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, and the like. In various embodiments, elements associated with the IC may include those integrated into the IC, mounted on the IC, or connected to the IC. The ICs described herein may be either analog or digital and, depending on the components associated with the IC, may be used in a number of applications such as microprocessors, optoelectronics, logic blocks, and audio amplifiers. The ICs described herein may be employed on a single IC die or as part of a chipset to perform one or more related functions in a computer.

[0024]

[0033] In various embodiments of this disclosure, the transistor described herein may be a field-effect transistor (FET), such as a metal-oxide-semiconductor (MOS) FET (MOSFET). Generally, an FET is a three-terminal device having a source terminal, a drain terminal, and a gate terminal, which uses an electric field to control the current flowing through the device. An FET typically includes a channel material, a source region and a drain region provided in and / or on the channel material, and a gate electrode material (also called a "work function" material) provided on a portion of the channel material between the source region and the drain region ("channel portion"), and optionally also including a gate dielectric material between the gate electrode material and the channel material.

[0025]

[0034] In a general sense, “interconnection” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnection provides electrical connectivity between two electrical components, facilitating the communication of electrical signals between them; an optical interconnection provides optical connectivity between two optical components, facilitating the communication of optical signals between them. As used in this context, both electrical and optical interconnections are included in the term “interconnection.” The nature of the interconnection described should be understood in this context in relation to the signaling medium to which they are associated. Thus, when used in reference to electronic devices such as ICs that operate using electrical signals, the term “interconnection” refers to any element formed from a conductive material to provide electrical connectivity to or between one or more elements related to the IC. In such cases, the term “interconnection” can refer to both conductive traces (sometimes called “lines,” “wires,” “metal lines,” or “trenches”) and conductive vias (sometimes called “vias” or “metal vias”). Sometimes conductive traces and vias are referred to as “conductive traces” and “conductive vias,” respectively, to emphasize that these elements contain a conductive material such as metal. Similarly, when used in reference to devices that also operate on optical signals, such as PICs, “interconnection” can also refer to any element formed from an optoconductive material to provide optical connectivity to one or more elements associated with the PIC. In such cases, the term “interconnection” may refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0026]

[0035] The term "waveguide" typically refers to any structure that acts to guide the propagation of light from one place to another through a substrate material such as silicon or glass. In various examples, waveguides can be formed from silicon, doped silicon, silicon nitride, glass such as silica (e.g., silicon dioxide or SiO2), borosilicate (e.g., 70-80 wt% SiO2, 7-13 wt% B2O3, 4-8 wt% Na2O or K2O, and 2-8 wt% Al2O3), and similar materials. Waveguides may be formed using a variety of techniques, including but not limited to in situ formation of waveguides. For example, in some embodiments, waveguides may be formed in situ within glass using low-temperature interglass coupling or by laser direct drawing. Waveguides formed in situ may have lower loss characteristics.

[0027]

[0036] The term "conductive trace" may be used to describe a conductive element insulated by an insulating material. Within an IC die, such an insulating material includes an interlayer low-k dielectric provided within the IC die. Within a package substrate and printed circuit board (PCB), such an insulating material includes organic materials such as Ajinomoto Buildup Film (ABF), polyimide, or epoxy resin. Such conductive lines are typically located at several levels or layers of the metallization stack.

[0028]

[0037] The term "conductive via" may be used to describe a conductive element that interconnects two or more conductive lines at different levels of a metallization stack. To this end, vias may be provided substantially perpendicular to the plane of the IC die / chip, or to the support structure on which the IC structure is mounted, and can interconnect two conductive lines at adjacent levels or two conductive lines at non-adjacent levels.

[0029]

[0038] The term “package substrate” can be used to describe any substrate material that facilitates the packaging of any assembly of semiconductor dies and / or other electrical elements, such as passive electrical elements. As used herein, a package substrate may be formed from any material, including but not limited to insulating materials such as resin-impregnated glass fiber (e.g., PCB or printed wiring board (PWB)), glass, ceramic, silicon, and silicon carbide. Furthermore, as used herein, a package substrate may refer to a substrate that includes a build-up layer (e.g., an ABF layer).

[0030]

[0039] The term "metallization stack" may be used to refer to a stack of one or more interconnects for providing connections between different circuit elements on an IC die / chip and / or package substrate.

[0031]

[0040] In this context, the term "pitch" of interconnections refers to the center-to-center distance between adjacent interconnections.

[0032]

[0041] In the context of a stack of coupled dies, or in the context of dies coupled to a package substrate, the term “interconnection” may also refer to die-to-die (DTD) interconnects and die-to-package substrate (DTPS) interconnects, respectively. DTD interconnects may be referred to as first-level interconnects (FLI). DTPS interconnects may be referred to as second-level interconnects (SLI). For the sake of simplicity in the drawings, not specifically shown in all of these examples, but where DTD or DTPS interconnects are described, the surface of a first die may contain a first set of conductive contacts, or the surface of a second die or package substrate may contain a second set of conductive contacts. One or more conductive contacts of the first set may be electrically and mechanically coupled to some of the conductive contacts of the second set by the DTD or DTPS interconnect. In some embodiments, the pitch of the DTD interconnects may differ from the pitch of the DTPS interconnects, while in other embodiments, these pitches may be substantially the same.

[0033]

[0042] It will be recognized that the IC packages described herein may have one or more levels of underfill (e.g., organic polymer materials such as benzotriazole, imidazole, polyimide, or epoxy) which may not be labeled to avoid cluttering the drawings. In various embodiments, the underfill levels may contain the same or different insulating materials. In some embodiments, the underfill levels may contain thermosetting epoxy with silicon oxide particles; in some embodiments, the underfill levels may contain any suitable material capable of performing an underfill function such as supporting the die and reducing thermal stress at the interconnects. In some embodiments, the selection of the underfill material may be based on design considerations such as shape factors, size, stress, and operating conditions; in other embodiments, the selection of the underfill material may be based on material properties and processing conditions such as curing temperature, glass transition temperature, viscosity, and chemical resistance, among other factors; in some embodiments, the selection of the underfill material may be based on both design considerations and processing considerations.

[0034]

[0043] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photosensitive dielectric, dry film photosensitive dielectric, acrylic, solvent) may be provided within the IC package described herein and may not be labeled or shown to avoid cluttering the drawings. The solder resist may be a liquid or dry film material containing a photosensitive dielectric. In some embodiments, the solder resist may be non-photosensitive.

[0035]

[0044] The terms “substantially,” “near,” “approximately,” “near,” and “about” generally refer to being within + / - 20% of a target value (for example, within + / - 5% or 10% of a target value) based on the context of a particular value, as used herein or as known in the art.

[0036]

[0045] Terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, generally refer to being within + / - 5% to 20% of a target value, based on the context of a particular value, as described herein or as known in the art.

[0037]

[0046] The term "connected" refers to a direct connection between multiple objects without any intermediate devices (which may be one or more of mechanical, electrical, and / or thermal connections), while the term "joined" refers to either a direct connection between multiple connected objects or an indirect connection through one or more passive or active intermediate devices.

[0038]

[0047] This description uses the phrases "in one embodiment" or "in multiple embodiments," which may each refer to one or more of the same or different embodiments.

[0039]

[0048] Furthermore, terms such as “comprising,” “including,” and “having” used in relation to embodiments of this disclosure are synonyms.

[0040]

[0049] This disclosure may use descriptions based on perspective views such as “top,” “bottom,” “upper,” “bottom,” and “side”; such descriptions are used for the sake of clarity and are not intended to limit the applicability of the disclosed embodiments.

[0041]

[0050] The terms "over," "under," "between," and "on" used in this context refer to the relative position of one material layer or component to another. For example, a layer being positioned above or below another layer may mean it is in direct contact with the other layer, or it may have one or more intervening layers. Furthermore, a layer being positioned between two layers may mean it is in direct contact with one or both of the two layers, or it may have one or more intervening layers. In contrast, when a first layer is described as being "on" a second layer, it refers to a layer that is in direct contact with that second layer. Similarly, unless otherwise specified, a feature positioned between two features may be in direct contact with an adjacent feature, or it may have one or more intervening layers.

[0042]

[0051] The term "arrange" as used in this context refers to location, place, arrangement, and / or configuration, rather than any specific configuration method.

[0043]

[0052] When used in relation to measurement ranges, the term "between" includes both ends of the measurement range.

[0044]

[0053] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). Where used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0045]

[0054] In this case, a specific element may be mentioned individually, but such an element may include multiple sub-elements. For example, "conductive material" may include one or more conductive materials. In another example, "dielectric material" may include one or more dielectric materials.

[0046]

[0055] Unless otherwise specified, the use of ordinal adjectives such as “first,” “second,” and “third” to describe a common object merely indicates that different instances of a similar object are being referred to, and is not intended to suggest that the objects described in this way must be in a given order, temporally, spatially, in a ranked manner, or in any other way.

[0047]

[0056] The following detailed description refers to accompanying drawings, which form part of this document, illustrating possible embodiments. It should be understood that other embodiments may be used, and that structural or logical modifications may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be construed as restrictive.

[0048]

[0057] The attached drawings are not necessarily drawn to scale.

[0049]

[0058] If included in the attached drawing, the coordinates specify thickness or height by the z dimension, width by the y dimension, and length by the x dimension. The diameter or cross-section may be specified by the xy dimensions.

[0050]

[0059] In drawings, the same reference numeral refers to the same or similar element / material shown; therefore, unless otherwise stated, the description of an element / material with a given reference numeral provided in one context of the drawings is applicable to other drawings in which elements / materials with the same reference numeral may be shown.

[0051]

[0060] Furthermore, while the drawings may show some schematic diagrams of exemplary structures of the various devices and assemblies described herein with precise right angles and straight lines, it should be understood that such schematic diagrams may not reflect actual process limitations that could cause features to appear as “ideally” when any structure described herein is examined using images from appropriate feature description tools, such as scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, or non-contact surface profile measuring devices. In such images, the average grain size of the material may be determined. Also, in images of such actual structures, possible processing and / or surface defects may be visible, such as surface roughness, curvature or profile deviations, pits or scratches, edges that are not perfectly straight in the material, tapered vias or other openings, unintentional rounding or variation in the thickness of different material layers, accidental twists, edges, or combination dislocations within crystalline regions, and / or accidental dislocation defects of single atoms or clusters of atoms. Other defects not listed in this case may exist that are common in the field of device manufacturing and / or packaging.

[0052]

[0061] In the drawings, various components (e.g., interconnections) are shown aligned (e.g., at each interface) simply for the sake of illustration; it should be noted that in reality, some or all of them may not be aligned. Furthermore, other components such as bond pads, landing pads, and metallizations may exist within the assembly that are not shown in the drawings to prevent clutter. Moreover, the drawings are intended to show the relative arrangement of components within those assemblies, and generally, such assemblies may include other components not shown (e.g., various interface layers, or various other components related to optical function, electrical connectivity, or thermal relaxation). For example, in some further embodiments, an assembly as shown in the drawings may include more dies along with other electrical components. Furthermore, while some components of an assembly are shown in the drawings as planar rectangles or formed from rectangular solids, this is merely for the sake of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped, as is sometimes inevitable and determined by the manufacturing process used to produce the various components.

[0053]

[0062] In the drawings, a specific number and arrangement of structures and components are presented for illustrative purposes, and in various embodiments, any desired number or arrangement of such structures and components may exist.

[0054]

[0063] Furthermore, unless otherwise specified, the structures shown in the figures may take on any appropriate form or shape depending on the material properties, manufacturing process, and operating conditions.

[0055]

[0064] For convenience, if there is a set of drawings designated with different letters (e.g., Figures 5A-5D), such a set may be referred to in this case without the letters (e.g., as "Figure 5"). Similarly, if there is a set of reference numbers designated with different numbers and / or letters (e.g., 148-1, 148-2), such a set may be referred to in this case without the numbers (e.g., as "148").

[0056]

[0065] Various operations may be described sequentially as multiple separate operations or processes in the manner that best helps to understand the matters relating to the claims. However, the order of description should not be interpreted as meaning that these operations are necessarily order-dependent. In particular, these operations may not be performed in the order presented. The operations described may be performed in a different order than in the embodiments described. Various additional operations may be performed, and / or the operations described may be omitted in additional embodiments.

[0057]

[0066] Figure 1 is a schematic cross-sectional view of an exemplary microelectronic assembly 100 in which a glass core having a TGV with multiple liners described herein may be mounted, according to some embodiments of the present disclosure. The microelectronic assembly 100 may include a glass core 190 having a first surface 190-1, a second surface 190-2 opposite the first surface 190-1, and a TGV 110 extending between the first surface 190-1 and the second surface 190-2.

[0058]

[0067] Any TGV 110 may be a conductive via having multiple liners as described herein. The TGV 110 may have any suitable size and shape. The thickness (e.g., z dimension) of an individual TGV 110 may be between 50 microns and 2 millimeters (i.e., 200 microns and 1 millimeter). The diameter (e.g., xy dimension) of an individual TGV 110 may be between 5 microns and 100 microns (e.g., 20 microns and 50 microns). In some embodiments, the TGV 110 has an aspect ratio between 5:1 and 30:1. The aspect ratio of the TGV 110 is the ratio of the overall thickness (e.g., z dimension or z height) of the TGV to the diameter (e.g., xy dimension) of the TGV, for example, a TGV with a thickness of 200 microns and a diameter of 20 microns has an aspect ratio equal to 10:1. In Figure 1, the TGV 110 is shown as having straight sides; however, in various embodiments, the TGV 110 may have sides that taper towards the center (for example, having an hourglass shape as shown in Figure 2), sides that are tapered toward the first surface 190-1 or the second surface 190-2 (for example, having a V-shape), and / or other irregularities depending on the processing conditions for producing the TGV 110. The TGV 110 may be formed using any preferred process, for example, in which via openings can be formed by laser activation and wet etching, laser ablation, or laser drilling, and conductive material can be deposited within the via openings. The TGV 110 can be formed from any suitable conductive material such as copper, silver, nickel, gold, aluminum, or other metals or alloys. In some embodiments, the pitch of the TGV 110 may be between 25 microns and 200 microns (for example, between 75 microns and 150 microns).

[0059]

[0068] The glass core 103 may have an overall thickness 191 (e.g., z dimension or z height) between 50 microns and 2 millimeters (e.g., 200 microns and 1 millimeter). The material of the glass core 103 may include glass, such as bulk clear glass, and is also referred to herein as the “glass layer.” As used herein, the term “core” refers to the structure (e.g., part of the glass layer) of any glass material, such as quartz, silica, fused silica, silicate glass (e.g., borosilicate, aluminosilicate, aluminoborosilicate), soda-lime glass, soda-lime silica, borofloat glass, lead borate glass, photosensitive glass, non-photosensitive glass, or ceramic glass. In particular, the glass core 103 may be a bulk glass or solid volume / layer of glass, as opposed to materials that may contain glass particles, such as glass fiber reinforced polymers. Such glass materials are typically amorphous and often transparent amorphous solids. In some embodiments, the glass core 103 may be an amorphous solid glass layer. In some embodiments, the glass core 103 may contain silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass core 103 may contain a material in which the weight percentage of silicon is at least about 0.5%, for example, between about 0.5% and 50%, between about 1% and 48%, or at least about 23%, such as any of the above materials. For example, if the glass core 103 is fused silica, the weight percentage of silicon may be about 47%. In some embodiments, the glass core 103 may contain at least 23% by weight of silicon and / or at least 26% by weight of oxygen, but in some further embodiments, the glass core 103 may further contain at least 5% by weight of aluminum.In some embodiments, the glass core 103 may contain any of the above-mentioned materials and may further contain one or more additives such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. In some embodiments, the glass core 103 may be a layer of glass that does not contain an organic adhesive or organic material. The glass core 103 may be distinguished from a “prepreg” or “RF4” core of a PCB substrate, which typically contains glass fibers embedded in a resin organic material such as epoxy. In some embodiments, the cross-section of the glass core 103 in the xz, yz, and / or xy planes of the exemplary coordinate system shown in Figure 1 may be substantially rectangular.

[0060]

[0069] The microelectronic assembly 100 may further include a first substrate 148-1 on a first surface 190 of the glass core 103 and a second substrate 148-2 on a second surface 190 of the glass core 103. The first and second substrates 148-1, 148-2 may include conductive paths 196 (e.g., including conductive traces and / or conductive vias, as shown) penetrating the dielectric material. Substrate 148 may include a set of first conductive contacts 172 on the bottom surface of substrate 148 and a set of second conductive contacts 174 on the top surface of substrate 148, with the conductive paths 196 electrically coupling the first conductive contacts 172 and the second conductive contacts 174, respectively. In some embodiments, the conductive contacts 174, 172 on the first surface 190-1 and the second surface 190-2 of the core 103 may be omitted.

[0061]

[0070] The first and second substrates 148-1 and 148-2 may be manufactured using any suitable technique such as a semi-additive process, a subtractive etching technique, or other conventional substrate packaging techniques. In some embodiments, the dielectric material of substrate 148 may include bismaleimide triazine (BT) resin, polyimide material, epoxy material (e.g., glass-reinforced epoxy matrix material, epoxy build-up film, etc.), molding material, oxide material (e.g., silicon dioxide or spin-on oxide), or low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics). The TGV 110 within the glass core 103 can electrically couple the first substrate 148-1 and the second substrate 148-2. In this application, the glass core 103, accompanied by the second substrate 148-2 and / or the first substrate 148-1, may be referred to as the package substrate. The TGV 110 within the glass core 103 enables power supply, grounding, and signal connections to components located on both sides of the glass core 103, for example, between the dies 114-1, 114-2 and the circuit board 131.

[0062]

[0071] The microelectronic assembly 100 may further include dies 114-1 and 114-2 electrically coupled to the upper surface of the second substrate 148-2 by an interconnect 150 (e.g., a DTPS interconnect). In particular, conductive contacts 122 on the bottom surface of dies 114-1 and 114-2 may be electrically and mechanically coupled to conductive contacts 174 on the upper surface of the second substrate 148-2 by the interconnect 150.

[0063]

[0072] The interconnect 150 can enable electrical coupling between die 114-1 and die 114-2 via a conductive path 196 in the substrate 148-2. The interconnect 150 disclosed herein can take any suitable form. In some embodiments, the set of interconnects 150 may include solder (e.g., solder bumps or balls that undergo thermal reflow to form the interconnect 150). The interconnect 150 including solder may include any suitable solder material such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, the set of interconnects 150 may include an anisotropic conductive material such as an anisotropic conductive film or anisotropic conductive paste. The anisotropic conductive material may include a conductive material dispersed in a non-conductive material. In some embodiments, the anisotropic conductive material may include fine conductive particles embedded in a binder or thermosetting adhesive film (e.g., a thermosetting biphenyl-type epoxy resin or acrylic material). In some embodiments, the conductive particles may include a polymer and / or one or more metals (e.g., nickel or gold). For example, the conductive particles may include nickel-clad gold or silver-clad copper, which are coated with a polymer. In another example, the conductive particles may include nickel. When the anisotropic conductive material is not compressed, there are no conductive paths from one side of the material to the other. However, when the anisotropic conductive material is properly compressed (e.g., by conductive contacts on either side of the anisotropic conductive material), conductive material near the compression region may come into contact with each other to form conductive paths from one side of the film to the other in the compression region. In some embodiments, the interconnect 150 disclosed herein may have a pitch between approximately 18 and 150 microns. Figure 1 shows dies 114-1 and 114-2 electrically coupled to substrate 148-2 by interconnect 150, but dies 114-1 and 114-2 may be electrically coupled by any suitable interconnect.

[0064]

[0073] The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and a plurality of conductive paths formed through the insulating material. In some embodiments, the insulating material of the die 114 may include dielectric materials such as silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photoimaging dielectrics, and / or benzocyclobutene polymers). In some embodiments, the insulating material of the die 114 may include semiconductor materials such as silicon, germanium, or III-V material (e.g., gallium nitride), and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths within the die 114 may include conductive traces and / or conductive vias, and may connect any conductive contacts within the die 114 in any suitable manner (e.g., connecting multiple conductive contacts on the same or different surfaces of the die 114). The conductive paths within the die 114 may be bordered as appropriate by liner materials such as adhesion liners and / or barrier liners. In some embodiments, the die 114 is a wafer. In some embodiments, the die 114 is monolithic silicon, a fan-out or fan-in package die, or a die stack (e.g., a wafer stack, a die stack, or a multilayer die stack).In various embodiments, die 114 may include, or be part of, one or more of the following: a central processing unit (CPU), a memory device (e.g., a high-bandwidth memory device), logic circuits, input / output circuits, transceivers such as field-programmable gate array transceivers, gate array logic such as field-programmable gate array logic, power supply circuits, III-V or III-N devices such as III-N or III-N amplifiers (e.g., GaN amplifiers), peripheral component interconnect express (PCIe) circuits, double data rate (DDR) transfer circuits, or other electronic elements known in the art. In some embodiments, dies 114-1 and dies 114-2 may have different functions. As used herein, the term “functionality” in relation to a die refers to one or more functions (e.g., capabilities, tasks, operations, actions, instruction execution, etc.) that the die in question is capable of performing. For example, die 114-1 may be a CPU, and die 114-2 may be a graphics processing unit (GPU) or memory. In other embodiments, dies 114-1 and 114-2 may include the same or similar functions. For example, dies 114-1 and 114-2 may each include memory.

[0065]

[0074] The microelectronic assembly 100 in Figure 1 may also include a bridge die 202. The bridge die 202 may be at least partially located within the dielectric material of the second substrate 148 (e.g., at least partially embedded within a cavity). The bridge die 202 may be electrically coupled to the dies 114 (e.g., dies 114-1 and 114-2) by an interconnect 140 (e.g., a DTD interconnect). In particular, conductive contacts 122 on the bottom surface of die 114 may be electrically and mechanically coupled to conductive contacts 124 on the top surface of the bridge die 202 by the interconnect 140. In some embodiments, the interconnect 140 disclosed herein may have a pitch of about 18 to 75 microns. The bridge die 202 may be electrically coupled to a conductive path 196 of the second substrate 148-2 by an interconnect 120. In some embodiments, the interconnect 120 disclosed herein may have a pitch of approximately 18 to 75 microns. In some embodiments, as shown, the interconnects 140 and 120 may include solder and may include any form described above with reference to the interconnect 150. The bridge die 202 includes appropriate circuitry on / inside the semiconductor substrate and can connect at speeds comparable to silicon interconnects with a small footprint. In some embodiments, the bridge die 202 may include active elements such as transistors and diodes in addition to a bridge circuit including metallization traces, vias, and passive elements to enable electrical coupling between two ICs; in other embodiments, the bridge die 202 may include a bridge circuit including metallization traces, vias, and passive elements to enable electrical coupling between die 114-1 and die 114-2, and may not include active elements. In some embodiments, the bridge die 202 may be omitted.

[0066]

[0075] The microelectronic assembly 100 in Figure 1 may also include an insulating material 135 that seals the die 114 (for example, on and around the die 114 and interconnect 150). The insulating material 135 may extend from the upper surface of the second substrate 148-2 to the upper surface of the die 114. In some embodiments, the insulating material 135 may be a dielectric material. In some embodiments, the insulating material 135 may be a molding material such as an organic polymer, resin material, or epoxy material having inorganic silicon oxide or aluminum oxide particles. In some embodiments (not shown), other components such as a heat sink may be coupled to the microelectronic assembly 100 based on specific needs.

[0067]

[0076] The microelectronic assembly 100 in Figure 1 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend around the interconnect 150 associated between the dies 114-1,114-2 and the second substrate 148. In some embodiments, the underfill material 127 may be located between the bottom surface of the bridge die 202 and the second substrate 148-2 (not shown). The underfill material 127 may be an insulating material such as a suitable epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that assists in soldering the dies 114-1,114-2 to the second substrate 148-2 when forming the interconnect 150, and then polymerizes and encapsulates the interconnect 150. The underfill process may include distributing underfill material in liquid form, allowing the material to flow and fill gaps around the interconnects 150, and subjecting the assembly to a curing process such as baking to solidify the material. In some embodiments, the underfill material 127 may be omitted. Figure 1 shows two separate underfill 127 portions beneath dies 114-1, 114-2, but the underfill 127 may be a single underfill 127 beneath dies 114-1, 114-2. The underfill material 127 can be selected to have a coefficient of thermal expansion (CTE) that can reduce or minimize stress between the die 114 and the second substrate 148-2 resulting from uneven thermal expansion within the microelectronic assembly 100. In some embodiments, the CTE of the underfill material 127 may be an intermediate value between the CTE of the second substrate 148-2 (e.g., the CTE of the dielectric material of substrate 148) and the CTE of the insulating material of die 114.

[0068]

[0077] The microelectronic assembly 100 in Figure 1 may also include a circuit board 131. In particular, conductive contacts 172 on the bottom surface of the first substrate 148-1 can be electrically coupled to conductive contacts 146 on the top surface of the circuit board 131 by an interconnect 180. The interconnect 180 disclosed herein may take any suitable form, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or lands in a land grid array arrangement, or any form described above with reference to the interconnect 150. As shown in Figure 1, in some embodiments, the set of interconnects 180 may include solder (e.g., solder bumps or balls that are subjected to thermal reflow to form the interconnect 180). In some embodiments, the interconnects 180 disclosed herein may have a pitch between approximately 50 and 300 microns. In some embodiments, underfill material 127 may extend between the first substrate 148-1 and the circuit board 131 around the interconnect 180 in question. The circuit board 131 may be, for example, a motherboard, and may have other components mounted on it. The circuit board may include conductive paths and other conductive contacts for routing power, ground, and signals through the circuit board, as is known in the art. In some embodiments, the interconnect 180 may not be coupled to the circuit board 131, but instead to another IC package, interposer, or any other suitable component.

[0069]

[0078] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable dielectrics, dry film photoimageable dielectrics, acrylic, solvent) may be provided within the IC package described herein and may not be labeled or illustrated to avoid cluttering the drawings. The solder resist may be a liquid or dry film material containing a photoimageable dielectric. In some embodiments, the solder resist may be non-photosensitive.

[0070]

[0079] Many of the elements of the microelectronic assembly 100 shown in Figure 1 are included in other accompanying drawings; the description of these elements is not repeated in describing those drawings, and any of these elements can take any form disclosed herein. Furthermore, although Figure 1 shows various elements included in the microelectronic assembly 100, some of these elements may not be included in various embodiments. For example, in various embodiments, the first substrate 148-1 and / or the second substrate 148-2, the underfill material 127, and the circuit board 131 may not be present in the microelectronic assembly 100. In some embodiments, individual components of the microelectronic assembly 100 disclosed herein may function as a system-in-package (SiP) containing multiple dies 114 having different functionalities. In such embodiments, the microelectronic assembly 100 may be referred to as a SiP.

[0071]

[0080] Figure 2 is a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to certain embodiments of the present disclosure. The configuration of the illustrated embodiment is similar to that of Figure 1, except for differences which will be further described. The microelectronic assembly 100 of Figure 2 includes a glass core 190 having a first surface 103-1 and a second surface 190-2 on the opposite side, and one or more dies 114 electrically coupled to a TGV 110 within the glass core 103. The glass core 103 can provide mechanical stability to the microelectronic assembly 100 of Figure 2, can reduce warping, and can provide a more robust surface for mounting to a package substrate 102 or other substrate (e.g., an interposer or circuit board).

[0072]

[0081] The glass core 103 may include a cavity 129 having an opening facing a second surface 190-2, and the die 114-1 may be fully or at least partially fitted (or nested) within the cavity 129. As shown in Figure 2, if the die 114-1 is fully fitted within the cavity 129, the top surface of the die 114-1 may be coplanar with or below the second surface 103-2 of the glass core 190. If the die 114-1 is partially fitted within the cavity 129, the top surface of the die 114-1 may extend above the second surface 103-2 of the glass core 190. The cavity 129 may be at least partially filled with insulating material 133. The die 114-1 may be attached to the bottom surface of the cavity 129 by a die-attach film (DAF) 132. DAF 132 may be any suitable material, including a non-conductive adhesive, a die-attach film, a B-stage underfill, or an adhesive polymer film. DAF 132 may have any suitable dimensions; for example, in some embodiments, DAF 132 may have a thickness (e.g., height or z-height) between 5 microns and 10 microns.

[0073]

[0082] Die 114-1 can be coupled to dies 114-2 and 114-3, which are located above die 114-1, via an interconnect 140. The interconnect 140 can be positioned between some of the conductive contacts 122 at the bottom of dies 114-2 and 114-3 and some of the conductive contacts 124 at the top of die 114-1. Some other conductive contacts 122 at the bottom of dies 114-2 and / or 114-3 can be further coupled to one or more of dies 114-2 and 114-3 to the glass core 103 by a glass core-to-die (GCTD) interconnect 142. The GCTD interconnect 142 can be positioned between some of the conductive contacts 122 at the bottom of dies 114-2 and 114-3 and some of the conductive contacts 128 at the top of the glass core 103. The GCTD interconnect 142 may be similar to the interconnect 150 described above. In some embodiments, the underfill material 127 can extend between different dies 114 around the associated interconnect 140 and / or GCTD interconnect 142. In some embodiments, dies 114-2 and / or dies 114-3 may be embedded in the insulating material 133. In some embodiments, the overall thickness (e.g., z-height) of the insulating material 133 may be between 200 and 800 microns (e.g., substantially equal to the thickness of dies 114-2 or 114-3 and the underfill material 127). In some embodiments, the insulating material 133 may form multiple layers (e.g., dielectric material formed in multiple layers as known in the art), and one or more dies 114 may be embedded in the layers. In some embodiments, the insulating material 133 may be an organic dielectric material, a flame retardant grade 4 material (FR-4), BT resin, a polyimide material, a glass-reinforced epoxy matrix material, or a dielectric material such as a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In some embodiments, the insulating material 133 may be a molding material such as an organic polymer having inorganic silica particles.

[0074]

[0083] As shown in Figure 2, the glass core 103 may further include a conductive contact 126 at its bottom, and the TGV 110 may extend between the conductive contact 126 at the bottom of the glass core 103 and the conductive contact 128 at the top of the glass core 103, thereby electrically coupling them. The conductive contacts 126, 128 may be similar to other conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 144, and / or 146), and may include, for example, bond pads, solder bumps, conductive posts, or any other suitable conductive contacts. As shown in Figure 2, in some embodiments, at least some of the TGV 110 may have an hourglass shape. For example, at least some of the TGV 110s may have a first width at the first surface 190-1 of the glass core 103 (e.g., at the bottom surface of the glass core 103), a second width at the second surface 190-2 of the glass core 103 (e.g., at the top surface of the glass core 103), and a third width between the first surface 190-1 and the second surface 190-2 of the glass core 103, wherein the third width is smaller than the first and second widths.

[0075]

[0084] Dies 114-2 and 114-3 may be electrically coupled to the package substrate 102 via a TGV 110 and a glass core-to-package substrate (GCTPS) interconnect 152, which may be a power supply interconnect or a high-speed signal interconnect. The GCTPS interconnect 152 may be similar to the interconnect 180 described above. The top surface of the package substrate 102 may include a set of conductive contacts 246, the glass core 103 may include a set of conductive contacts 126 on the first surface 190-1, and the GCTPS interconnect 152 is located between the conductive contacts 246 and can be coupled to the corresponding conductive contacts 126. In some embodiments, an underfill material 127 may extend between the glass core 103 and the package substrate 102 around the relevant GCTPS interconnect 152.

[0076]

[0085] The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive paths (e.g., including conductive traces and / or conductive vias, as shown) for routing power, ground, and signals through the dielectric material. In some embodiments, the insulating material of the package substrate 102 may be a dielectric material such as an organic dielectric material, a flame-retardant grade 4 material (FR-4), a bismaleimide-triazine (BT) resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric with an inorganic filler, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In particular, if the package substrate 102 is formed using a standard PCB process, the package substrate 102 may include FR-4, and the conductive paths within the package substrate 102 may be formed by patterned sheets of copper separated by a build-up layer of FR-4. The conductive paths within the package substrate 102 may, as appropriate, be bordered by a liner material such as an adhesive liner and / or a barrier liner. In some embodiments, the package substrate 102 may be formed using a via packaging process defined by lithography. In some embodiments, the package substrate 102 may be manufactured using a standard organic package manufacturing process, and thus the package substrate 102 may take the form of an organic package. In some embodiments, the package substrate 102 may be a set of redistribution layers formed on a panel carrier by lamination or spin-on in a dielectric material and the creation of conductive vias and lines by laser drilling and plating. In some embodiments, the package substrate 102 may be formed on a removable carrier using any suitable technique such as redistribution layer technique. Any method known in the art for manufacturing the package substrate 102 may be used, and for the sake of brevity, such methods will not be described in further detail herein.

[0077]

[0086] A glass core 103, included in a microelectronic assembly 100 as described with reference to Figure 1 or Figure 2, or included in any other microelectronic assembly or device, may be subjected to TGV stress before being incorporated into the microelectronic assembly 100. For example, Figure 3 shows a surface of the glass core 103 that may be subject to TGV stress according to some embodiments of the present disclosure. As shown in Figure 3, the glass core 103 may have a first surface 190-1 and an opposite second surface 190-2, for example, a bottom and top surface when the glass core 103 is incorporated into the microelectronic assembly 100 (wherein the first and second surfaces 190-1, 190-2 may be collectively referred to as “surface 190”). The glass core 103 may also include a side 190-3, which is a surface of the glass core 103 that may be referred to as an edge or sidewall of the glass core 103, i.e., a surface extending between the first surface 103-1 and the second surface 190-2. As further shown in Figure 3, a TGV opening 192 may be formed in the glass core 103 and extend between the first surface 190-1 and the second surface 190-2. Thus, sidewall 190-4 may refer to one or more sidewalls of the TGV opening 192. When conductive material is deposited within the TGV opening 192, TGV stress may arise from the sidewall 190-4 due to a mismatch in CTE between the glass material of the glass core 103 and the conductive material within the TGV opening 192.

[0078]

[0087] FIG. 4A shows a simplified schematic side cross-sectional view of an exemplary portion of a microelectronic assembly according to some embodiments of the present disclosure. FIG. 4A shows a glass core 103 having a TGV opening 192, the TGV opening 192 having a first liner 422 and a second liner 424 that line the TGV opening and the first surface 190-1 and the second surface 190-2 of the glass core 103. The first liner 422 can include any suitable material capable of separating the glass material of the glass core 103 at the sidewalls of the TGV opening 192 from the conductive bulk fill material that will later be deposited in the TGV opening 192, and aids in smoothing the glass surface at the sidewalls of the TGV opening 192, e.g., to withstand tensile stresses caused by shrinkage of a metal that will later fill the TGV opening 192. In some embodiments, the first liner 422 is a dielectric material, an inorganic material containing silicon and oxygen (e.g., SiO2, SiO x ), those containing silicon and nitrogen (e.g., SiN, SiN x ), those containing silicon and carbon (e.g., silicon carbide), those containing silicon, oxygen, and carbon (e.g., Si x O y C z H w ), or those containing silicon, nitrogen, and carbon (e.g., SiN x C y H z ) such as a dielectric material like a dielectric encapsulation layer. The first liner 422 can have some suitable dimensions so as to function as a buffer between the glass core 103 and the conductive bulk fill material of the TGV 110. In some embodiments, the first liner 422 can have a width (e.g., y dimension) that is between about 0.1 nanometers to 100 nanometers, e.g., between about 2 nanometers to about 50 nanometers, or between about 25 nanometers to about 75 nanometers.

[0079]

[0088] The second liner 424 may contain any suitable conductive material and may have any suitable dimensions to separate the first liner 422 from the conductive bulk filler material that is later deposited in the TGV opening 192 (e.g., for forming the TGV 110 shown in Figures 1 and / or 2), for example, to help reduce tensile stress caused by shrinkage of the metal that is later filled in the TGV opening 192. In some embodiments, the conductive bulk filler material of the TGV 110 may contain copper, ruthenium, nickel, gold, palladium, platinum, or silver. The dimensions of the second liner 424 may depend on the process used to deposit the second liner 424 (e.g., atomic layer deposition (ALD)). In some embodiments, the material of the second liner 424 may contain ruthenium having a width (e.g., y dimension) between 5 nanometers and 20 nanometers. In some embodiments, the material of the second liner 424 may include copper having a width (e.g., y dimension) between 5 nanometers and 30 nanometers and an average grain size between 8 nanometers and 20 nanometers. In such embodiments, the conductive bulk filler material of TGV 110 may include copper having an average grain size larger than that of the copper in the second liner 424. For example, the conductive bulk filler material of TGV 110 may have an average grain size between 100 nanometers and 2 microns.

[0080]

[0089] Figure 4B shows a simplified schematic side section view of another exemplary portion of a microelectronic assembly according to certain embodiments of the present disclosure. The configuration of the embodiment shown in the figure is similar to that of Figure 4A, except for differences which will be further described. In particular, Figure 4B shows an embodiment in which the assembly further includes a liner 426 of the die 3 on top of a second liner 424 that lines the TGV opening 192 and the first surface 190-1 and second surface 103-2 of the glass core 190. The third liner 426 may contain any suitable conductive material and may have any suitable dimensions, and may separate the second liner 424 from the conductive bulk filler material which will later be deposited in the TGV opening 192 (e.g., for forming the TGV 110 as shown in Figures 1 and / or 2) to help reduce tensile stress caused by shrinkage of the metal which will later be filled in the TGV opening 192, for example. The dimensions of the third liner 426 may depend on the process used to deposit the third liner 426 (e.g., physical vapor deposition (PVD)). In some embodiments, the third liner 426 has a width (e.g., y dimension) between 100 nanometers and 250 nanometers. In some embodiments, the material of the third liner 426 may include metals having a potential difference of -1 to +1 relative to copper, such as ruthenium, zinc, iron, nickel, tin, lead, and silver. In some embodiments, the material of the third liner 426 may include copper having an average particle size between 10 nanometers and 100 nanometers. In such embodiments, the conductive material of TGV 110 (e.g., conductive bulk filler material) may further include copper having an average particle size of 100 nanometers to 2 microns.

[0081]

[0090] Figure 4C shows a simplified schematic side section view of another exemplary portion of a microelectronic assembly according to some embodiments of the present disclosure. The configuration of the embodiment shown in the figure is similar to that of Figure 4A, except for differences which will be described further. In particular, Figure 4C shows an embodiment in which the second liner 424 includes alternating layers of a first conductive material 423 (e.g., 423-1 to 423-n) and a second conductive material 425 (e.g., 425-1 to 425-n) that line the TGV opening 192 and the first and second surfaces 190-1 and 2 190-2 of the glass core 103. The alternating layers of the first conductive material 423 and the second conductive material 425 can be deposited at the angstrom level using an ALD process. In some embodiments, the first conductive material 423 contains ruthenium and the second conductive material 425 contains copper. For example, a single layer of the first conductive material 423 containing ruthenium may have a width of about 1.2 angstroms (e.g., y dimension), and a single layer of the second conductive material 425 containing copper may have a width of about 0.7 angstroms (e.g., y dimension), and the two combined single layers form a single alternating layer having a width of about 0.2 nanometers (e.g., y dimension). The second liner 424 may have a total width (e.g., y dimension) between 5 nanometers and 30 nanometers and may contain alternating layers (e.g., n layers) between 50 and 300. In other words, the second liner 424 may be composed of 25 layers of the second conductive material 425 alternating with 25 layers of the first conductive material 423, or 150 layers of the second conductive material 425 alternating with 150 layers of the first conductive material 423.

[0082]

[0091] Techniques relating to the use of multiple liners to reduce TGV stress, as described herein, may be applied to reduce TGV stress before incorporating the glass core 103 into the microelectronic assembly 100. Any suitable technique may be used to manufacture the microelectronic assembly 100 disclosed herein. For example, Figures 5A to 5D are side cross-sectional views of various stages in an exemplary process for manufacturing an exemplary glass core 103 having multiple liners (e.g., liners 422, 424, 426, as shown in Figures 4A to 4C) within the microelectronic assembly 100, according to various embodiments. The processes described below with reference to Figures 5A to 5D (and other accompanying drawings representing the manufacturing process) are shown in a specific order, but these processes may be performed in any suitable order. Furthermore, additional processes not shown may be performed without departing from the scope of this disclosure. Also, various of the processes described herein with reference to Figures 5A to 5D may be modified in accordance with this disclosure to manufacture other microelectronic assemblies 100 disclosed herein.

[0083]

[0092] Figure 5A shows an assembly 502 including a glass core 190 having a first surface 190-1 and a second surface 103-2, and a TGV opening 192. The glass core 103 may have any suitable dimensions; for example, the glass core 103 may include a full-panel glass core with a surface area of ​​approximately 500 mm × 500 mm (e.g., xy dimensions), or a quarter-panel glass core with a surface area of ​​approximately 250 mm × 250 mm. In some embodiments, the glass core 103 may have a surface area of ​​approximately 10 mm × 10 mm to approximately 240 mm × 240 mm. Figures 5A and 5B to 5D show TGV openings 192 extending between a first surface 190-1 and a second surface 190-2 of the glass core 103, but the description herein is also applicable to blind openings, for example, openings that start from one of surfaces 190-1, 190-2 and extend toward but not reach the other surface 190-1, 190-2. Furthermore, although two TGV openings 192 are shown in Figures 5A and 5B to 5D, in other embodiments the microelectronic assembly described herein may include any number of TGV openings 192. In various embodiments, the TGV openings 192 may be formed in the glass core 103 using any suitable subtractive technique such as direct laser drilling or laser-induced etching processes, and optionally in combination with any suitable patterning technique such as photolithography or electron beam (e-beam) patterning. In other embodiments, the TGV opening 192 may be formed during the manufacturing of the glass core 103 itself, for example, when molten glass is filled into a mold having space for the future TGV opening 192.

[0084]

[0093] Figure 5B shows assembly 504 after the first liner 422 has been deposited on the sidewall of the TGV opening 192 within the glass core 103. In the case of the TGV opening 192 which may be implemented as a blind opening, the first liner 422 may be deposited at the bottom of the TGV opening 192. In various embodiments, the first liner 422 may be deposited using any suitable deposition technique such as chemical vapor deposition (CVD), ALD, PVD, slit / spray coating, or vacuum lamination. In some embodiments, in addition to being deposited as a liner within the TGV opening 192, the first liner 422 may also be deposited on (over) a first surface 190-1, a second surface 190-2, or both surfaces, depending on the deposition technique used to provide the first liner 422. In such embodiments, the first liner 422 deposited on the first surface 190-1 and / or the second surface 190-2 can be substantially continuous with the first liner 422 on the sidewall of the TGV opening 192. In some embodiments, the portion of the first liner 422 located on the side wall of the TGV opening 192 can be in contact with the side wall of the TGV opening 192 (for example, in contact with the glass core 103 on the side wall of the TGV opening 192). In some embodiments, the first liner 422 may be deposited as a conformal layer, i.e., it may conform to the shape of the substrate surface on which the first liner 422 is deposited. In some embodiments, the first liner 422 may be deposited in multiple layers to achieve a desired width (e.g., y dimension). The first liner 422 may contain any suitable material and have any suitable dimensions, as described above with reference to Figure 4A.

[0085]

[0094] Figure 5C shows assembly 506 after the second liner 424 has been deposited on the first liner 422 located on the sidewall of the TGV opening 192 within the glass core 103. In various embodiments, the second liner 424 may be deposited using any suitable deposition technique, such as ALD, including thermal ALD or plasma-enhanced ALD. In some embodiments, in addition to being deposited as a liner within the TGV opening 192, the second liner 424 may be deposited on the first liner 422, on a first surface 190-1, a second surface 190-2, or both surfaces. In such embodiments, the second liner 424 deposited on the first surface 190-1 and / or the second surface 190-2 can be substantially continuous with the second liner 424 located on the sidewall of the TGV opening 192. In some embodiments, the second liner 424 may be deposited as a conformal layer, i.e., it may conform to the shape of the substrate surface on which the second liner 424 is deposited. In some embodiments, the second liner 424 may be deposited in multiple layers to achieve a desired width (e.g., y dimension). The second liner 424 may contain any suitable material and have any suitable dimensions, as described above with reference to Figures 4A and 4C. In embodiments including alternating layers of a first conductive material 423 and a second conductive material 425, as shown in Figure 4C, the alternating layers may be deposited using any suitable technique such as angstrom-level ALD and may be repeated until a desired width (e.g., y dimension) is achieved. In embodiments including a third liner 426 (e.g., as shown in Figure 4B), the third liner 426 may be deposited using any suitable deposition technique such as PVD. In some embodiments, in addition to being deposited as a liner within the TGV opening 192, the third liner 426 may be deposited on the first surface 190-1, the second surface 190-2, or both surfaces of the second liner 424. In such embodiments, the third liner 426 deposited on the first surface 190-1 and / or the second surface 190-2 can be substantially continuous with the third liner 426 on the sidewall of the TGV opening 192. In some embodiments, the third liner 426 may be deposited as a conformal layer, i.e., it may conform to the shape of the substrate surface on which the third liner 426 is deposited. In some embodiments, the third liner 426 may be deposited in multiple layers to achieve a desired width (e.g., y dimension). The third liner 426 may contain any suitable material and have any suitable dimensions, as described above with reference to Figure 4B.

[0086]

[0095] Figure 5D shows assembly 508 after forming a TGV 110 by depositing conductive bulk filler material within the TGV opening 192 lined with the first liner 422 and the second liner 424. The TGV opening 192 filled with conductive material is one example of any of the TGV 110s described herein. The conductive bulk filler material of the TGV 110 may include any suitable conductive material, e.g., any of the materials described above with reference to Figure 4A. The conductive bulk filler material may be deposited using any suitable deposition technique such as electroplating, ALD, CVD, or PVD.

[0087]

[0096] Figure 6 is a flow diagram of an exemplary process for manufacturing exemplary microelectronic assemblies according to various embodiments. In 602, a glass core 103 having one or more TGV openings 192 may be formed. In 604, the TGV openings 192 may be lined with a first liner 422 deposited using CVD, ALD, PVD, slit / spray coating, or vacuum lamination. The first liner 422 may contain a dielectric material. In 606, the TGV openings 192 may be lined with a second liner 424. The second liner 424 may contain a first conductive material deposited using ALD, or it may contain repeating alternating layers of the first conductive material and the second conductive material deposited using ALD. In 608, the TGV openings 192 may optionally be lined with a third liner 426. The third liner 426 may contain a third conductive material deposited using PVD. In 610, a conductive bulk filler material may be deposited within the TGV opening (e.g., TGV metallization) to form a TGV 110 including a first liner 422 and a second liner 424.

[0088]

[0097] The various embodiments of the TGV having multiple liners described above can, advantageously, be readily manufactured in parallel with conventional manufacturing techniques for glass core substrates. The various arrangements of the microelectronic assembly 100 and glass core 103 shown in Figures 1 to 5 do not represent an exhaustive range of combinations of microelectronic assemblies and glass cores on which one or more TGVs having multiple liners described herein may be mounted, but merely provide some illustrative examples. In particular, the number and location of the various elements shown in Figures 1 to 5 are purely illustrative, and in various other embodiments, other numbers of these elements, located in other positions, may be used in accordance with the general architectural considerations described herein. For example, although not specifically shown in the drawings herein, in some embodiments the microelectronic assembly 100 may include a redistribution layer (RDL) between any pair of layers shown in Figures 1 and 2, the RDL including multiple interconnection structures (e.g., conductive lines and conductive vias) to assist in routing signals and / or power between components. In yet another example, any one feature from Figures 1 to 5 may be combined with any other feature from Figures 1 to 5. For example, in some embodiments, a portion of the glass core 103 may include one or more TGV 110 having multiple liners, while other portions of the glass core 103 may include TGV 110 without multiple liners.

[0089]

[0098] Any of the packages disclosed herein, for example, the microelectronic assembly 100, or any further embodiments described herein, may be included in any suitable electronic device. Figures 7 to 9 show various examples of packages, assemblies, and devices that may be used with, or include, any IC package disclosed herein.

[0090]

[0099] Figure 7 is a side cross-sectional view of an exemplary IC package 2200, which may include a microelectronic assembly according to any embodiment disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).

[0091]

[0100] As shown in Figure 7, the package support 2252 can be formed from an insulator (e.g., ceramic, build-up film, epoxy film with internal filler particles, etc.) and may have conductive paths extending through the insulator between the first surface 2272 and the second surface 2274, or between various positions on the first surface 2272, and / or between various positions on the second surface 2274. These conductive paths can take the form of interconnection structures including lines and / or vias, as described above with reference to Figure 1, for example.

[0092]

[0101] The package support 2252 may include conductive contacts 2263 coupled to a conductive path 2262 via the package support 2252, allowing circuits in the die 2256 and / or interposer 2257 to be electrically coupled to various of the conductive contacts 2264 (or to other devices (not shown) included in the package support 2252).

[0093]

[0102] The IC package 2200 may include the interposer 2257 coupled to the package support 2252 via conductive contacts 2261 of the interposer 2257, a first level interconnect (FLI) 2265, and conductive contacts 2263 of the package support 2252. The FLI 2265 shown in Figure 7 is a solder bump, but any suitable FLI 2265 such as a solder bump, solder post, or bond wire may be used.

[0094]

[0103] The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254, FLI 2258, and conductive contacts 2260 of the interposer 2257. In various embodiments, the interposer 2257 may include a glass core 103 containing glass, as described herein. The conductive contacts 2260 may be coupled to a conductive path (not shown) via the interposer 2257, allowing circuits within the die 2256 to be electrically coupled to various conductive contacts 2261 (or to other devices (not shown) included in the interposer 2257). The FLI 2258 shown in Figure 7 is a solder bump, but any suitable FLI 2258 such as a solder bump, solder post, or bond wire may be used. As used in this context, “conductive contact” may refer to a portion of a conductive material (e.g., metal) that functions as an interface between different components; the conductive contact may be pressed into the surface of a component, coplanar with it, or extending away from it, and may take any preferred form (e.g., a conductive pad or socket).

[0095]

[0104] In some embodiments, the underfill material 2266 may be positioned around the FLI 2265 between the package support 2252 and the interposer 2257, and the mold 2268 may be positioned around the die 2256 and the interposer 2257 in contact with the package support 2252. In some embodiments, the underfill material 2266 may be the same as the mold 2268. An exemplary material that may be used for the underfill material 2266 and the mold 2268 is a suitable epoxy. A second level interconnect (SLI) 2270 can be coupled to a conductive contact 2264. The SLI 2270 shown in Figure 7 is a solder ball (for example, for a ball grid array (BGA) arrangement), but any suitable SLI 2270 may be used (for example, a pin in a pin grid array arrangement, or a land in a land grid array arrangement). As is known in the art, and as will be described below with reference to Figure 9, the SLI 2270 can be used to couple the IC package 2200 to a circuit board (e.g., a motherboard), an interposer, or another component such as another IC package.

[0096]

[0105] In embodiments where the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may contain circuitry that performs any desired function. For example, in addition to one or more of the dies 2256 that include components of die 114 as described herein, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), or one or more of the dies 2256 may be memory dies (e.g., high-bandwidth memory), etc. In some embodiments, at least some of the dies 2256 may not include components of die 114 as described herein.

[0097]

[0106] The IC package 2200 shown in Figure 7 is a flip-chip package, but other package architectures may be used. For example, the IC package 2200 may be a BGA package such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200, the IC package 2200 may contain any desired number of dies 2256. The IC package 2200 may include additional passive elements such as surface-mount resistors, capacitors, and inductors, which are located on the first face 2272 or the second face 2274 of the package support 2252, or on either face of the interposer 2257. More generally, the IC package 2200 may include any other active or passive elements known in the art.

[0098]

[0107] Figure 8 is a side cross-sectional view of an IC device assembly 2300 which may include components having one or more microelectronic assemblies 100 according to any embodiment disclosed herein. The IC device assembly 2300 includes a number of components arranged on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components arranged on a first surface 2340 of the circuit board 2302 and a second surface 2342 opposite to the circuit board 2302; generally, components can be arranged on one or both surfaces 2340 and 2342. In particular, any suitable component of the IC device assembly 2300 may include one or more microelectronic assemblies 100 according to any embodiment disclosed herein; for example, any IC package discussed below with reference to the IC device assembly 2300 may take any form of an embodiment of the IC package 2200 described above with reference to Figure 7.

[0099]

[0108] In some embodiments, the circuit board 2302 may be a PCB comprising a plurality of metal layers separated from each other by insulating layers and interconnected by conductive vias. Any one or more of the metal layers may be formed with a desired circuit pattern to route electrical signals (optionally together with other metal layers) between components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB package support.

[0100]

[0109] Figure 8 shows that in some embodiments, the IC device assembly 2300 may include a package-on-interposer structure 2336 coupled to a first surface 2340 of a circuit board 2302 by a coupling element 2316. Not shown for the sake of simplicity in the drawings, the package-on-interposer structure 2336 may include a glass core 103, such as a glass layer, in some embodiments. In other embodiments, the package-on-interposer structure 2336 may not include a core. The coupling element 2316 can electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and may include solder balls (as shown), male and female sockets, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0101]

[0110] The package-on-interposer structure 2336 may include an IC package 2320 coupled to the interposer 2304 by a coupling element 2318. In some embodiments, the IC package 2320 may include a microelectronic assembly 100 and other components, such as those described herein, which are not shown to avoid cluttering the drawings. The coupling element 2318 can take any suitable form depending on the desired function, such as the embodiments described above with reference to the coupling element 2316. In some embodiments, the IC package 2320 may be, or include, an IC package 2200, as described above with reference to Figure 7, for example.

[0102]

[0111] Although Figure 8 shows a single IC package 2320, multiple IC packages may be coupled to the interposer 2304; in fact, additional interposers may be coupled to the interposer 2304. The interposer 2304 can provide an intervening package support used to bridge the circuit board 2302 and the IC package 2320. Generally, the interposer 2304 can redistribute connections to a wider pitch or reroute connections to different connections. For example, the interposer 2304 may couple the IC package 2320 to the BGA of the coupling element 2316 for coupling to the circuit board 2302.

[0103]

[0112] In the embodiment shown in Figure 8, the IC package 2320 and the circuit board 2302 are mounted on opposite sides of the interposer 2304. In other embodiments, the IC package 2320 and the circuit board 2302 may be mounted on the same side of the interposer 2304. In some embodiments, three or more components may be interconnected by the interposer 2304.

[0104]

[0113] The interposer 2304 may be formed from an epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymer material such as polyimide. In some implementations, the interposer 2304 may be formed from alternative rigid or flexible materials, which may include the same materials as above for use in semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 2304 may include a metal interconnect 2308 and vias 2310 including a TSV 2306. The interposer 2304 may further include embedded devices 2314, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 2304. The package-on-interposer structure 2336 can take any form of package-on-interposer structure known in the art.

[0105]

[0114] In some embodiments, the IC device assembly 2300 may include an IC package 2324 coupled to a first surface 2340 of a circuit board 2302 by a coupling element 2322. The coupling element 2322 can take the form of any embodiment described above with reference to the coupling element 2316, and the IC package 2324 can take the form of any embodiment described above with reference to the IC package 2320.

[0106]

[0115] In some embodiments, the IC device assembly 2300 may include a package-on-package structure 2334 coupled to a second surface 2342 of a circuit board 2302 by a coupling element 2328. The package-on-package structure 2334 may include IC packages 2326 and 2332 coupled together by a coupling element 2330, so that IC package 2326 is placed between the circuit board 2302 and IC package 2332. The coupling elements 2328 and 2330 can take the form of any embodiment of the coupling element 2316 described above, and IC packages 2326 and / or 2332 can take the form of any embodiment of the IC package 2320 described above. The package-on-package structure 2334 can be configured according to any package-on-package structure known in the art.

[0107]

[0116] Figure 9 is a block diagram of an exemplary computing device 2400, which may include one or more components having one or more IC packages according to any embodiment disclosed herein. For example, any suitable component of the computing device 2400 may include a microelectronic assembly 100 including glass according to any embodiment disclosed herein. In another example, any one or more components of the computing device 2400 may include any embodiment of the IC package 2200 (as shown, for example, in Figure 7). In yet another example, any one or more components of the computing device 2400 may include an IC device assembly 2300 (as shown, for example, in Figure 8).

[0108]

[0117] In Figure 9, numerous components are shown as being included in the computing device 2400, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the computing device 2400 may be mounted on one or more motherboards. In some embodiments, some or all of these components are manufactured on a single SOC die.

[0109]

[0118] Furthermore, in various embodiments, the computing device 2400 may not include one or more of the components shown in Figure 9, but it may include interface circuits for coupling with one or more components. For example, the computing device 2400 may not include the display device 2406, but it may include a display device interface circuit (e.g., connector and driver circuit) to which the display device 2406 may be coupled. In another example, the computing device 2400 may not include the audio input device 2418 or the audio output device 2408, but it may include an audio input or output device interface circuit (e.g., connector and support circuit) to which the audio input device 2418 or the audio output device 2408 may be coupled.

[0110]

[0119] The arithmetic device 2400 may include processing devices 2402 (e.g., one or more processing devices). As used herein, the terms “processing device” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. Processing devices 2402 may include one or more digital signal processors (DSPs), ASICs, CPUs, GPUs, cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The arithmetic device 2400 may include memory 2404, which itself may include one or more memory devices such as volatile memory (e.g., dynamic random-access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard drives. In some embodiments, memory 2404 may include memory that shares a die with processing device 2402. This memory may be used as cache memory and may include embedded dynamic random-access memory (eDRAM) or spin-transfer torque magnetic random-access memory (STT-MRAM).

[0111]

[0120] In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips; note that the terms “chip,” “die,” and “IC die” are used interchangeably herein). For example, the communication chip 2412 may be configured to manage wireless communication for transferring data to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that are capable of communicating data by using modulated electromagnetic radiation over a non-solid medium. This term does not mean that the devices in question are wire-free, although in some embodiments they may be wire-free.

[0112]

[0121] The 2412 communication chip can implement any of the numerous wireless standards or protocols, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), and Long-Term Evolution (LTE) projects with any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra-Mobile Broadband (UMB) project (also known as "3GPP2")). IEEE 802.16-compatible broadband radio access (BWA) networks are commonly referred to as WiMAX networks, an acronym for Worldwide Interoperability for Microwave Access, and a certification mark for products that have passed IEEE 802.16 conformance and interoperability tests. The communication chip 2412 can operate according to the Global System for Mobile Communications (GSM), General-Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 can operate according to GSM Evolution Extension Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Extended Cordless Telecommunications (DECT), Evolution Data Optimization (EV-DO), and their derivatives, as well as any other radio protocol designated as 3G, 4G, 5G, and beyond. In other embodiments, the communication chip 2412 may operate according to other radio protocols. The computing device 2400 may include an antenna 2422 for facilitating and / or receiving other wireless communications (such as AM or FM radio transmissions).

[0113]

[0122] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 may include multiple communication chips. For example, the first communication chip 2412 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth®, and the second communication chip 2412 may be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 2412 may be dedicated to wireless communications, and the second communication chip 2412 may be dedicated to wired communications.

[0114]

[0123] The computing device 2400 may include a battery / power circuit 2414. The battery / power circuit 2414 may include a circuit for coupling one or more energy storage devices (e.g., batteries or capacitors) and / or components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).

[0115]

[0124] The computing device 2400 may include a display device 2406 (or a corresponding interface circuit as described above). The display device 2406 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat-panel display.

[0116]

[0125] The computing device 2400 may include an audio output device 2408 (or a corresponding interface circuit as described above). The audio output device 2408 may include any device that generates an audible indicator, such as a speaker, headset, or earphones.

[0117]

[0126] The computing device 2400 may include an audio input device 2418 (or a corresponding interface circuit as described above). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a digital instrument interface (MIDI) output).

[0118]

[0127] The computing device 2400 may include a GPS device 2416 (or a corresponding interface circuit as described above). The GPS device 2416 may communicate with a satellite-based system and receive the position of the computing device 2400, as is known in the art.

[0119]

[0128] The computing device 2400 may include other output devices 2410 (or corresponding interface circuits as described above). Examples of other output devices 2410 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0120]

[0129] The computing device 2400 may include other input devices 2420 (or corresponding interface circuits as described above). Examples of other input devices 2420 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices such as mice, styluses, touchpads, barcode readers, quick response (QR) code readers, some kind of sensor, or radio frequency identification (RFID) readers.

[0121]

[0130] The computing device 2400 may have any desired shape factor, such as a handheld or mobile computing device (e.g., cell phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing element, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0122]

[0131] The above description of the described implementations of this disclosure, including the matters described in the abstract, is not intended to be exhaustive or to limit this disclosure to the exact form disclosed. While the specific implementations and examples of this disclosure are described for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be apparent to those skilled in the art.

[0123]

[0132] The following paragraphs provide various examples of the embodiments disclosed herein.

[0124]

[0133] Example 1 provides a microelectronic assembly comprising a core including through vias (the through vias comprising a first conductive material having a first average particle size); a first liner material (containing a dielectric material) on the sidewalls of the through vias; and a second liner material (containing a second conductive material having a second average particle size, wherein the first average particle size is greater than the second average particle size) between the first liner material and the first conductive material of the through vias.

[0125]

[0134] Example 2 provides a microelectronic assembly of Example 1 in which the first conductive material contains copper and the second liner material also contains copper.

[0126]

[0135] Example 3 provides a microelectronic assembly of Example 2 in which the first average particle size is between 100 nanometers and 2 microns, and the second average particle size is between 8 nanometers and 20 nanometers.

[0127]

[0136] Example 4 provides a microelectronic assembly from any one of Examples 1 to 3, wherein the second liner material has a width between 5 nanometers and 30 nanometers.

[0128]

[0137] Example 5 provides a microelectronic assembly from any one of Examples 1 to 4 in which the dielectric material of the first liner material comprises silicon and oxygen; silicon and nitrogen; silicon and carbon; silicon, oxygen, and carbon; or silicon, nitrogen, and carbon.

[0129]

[0138] Example 6 provides a microelectronic assembly from any one of Examples 1 to 5, wherein the first liner material has a width between 0.1 nanometers and 100 nanometers.

[0130]

[0139] Example 7 provides a microelectronic assembly from any one of Examples 1 to 6, wherein the core material includes bulk glass.

[0131]

[0140] Example 8 provides a microelectronic assembly from any one of Examples 1 to 7, wherein the core thickness is between 50 microns and 2 millimeters.

[0132]

[0141] Example 9 provides a microelectronic assembly of any one of Examples 1 to 8, wherein the through-via is one of a plurality of through-vias, and the microelectronic assembly further comprises a substrate on a first face of the core (including a first conductive path through a first dielectric material, electrically coupled to at least one of the plurality of through-vias); and a second substrate on a second face of the core (the second face of the core is on the opposite side of the first face, and the second substrate includes a second conductive path through a second dielectric material, electrically coupled to at least one of the plurality of through-vias).

[0133]

[0142] Example 10 provides a microelectronic assembly of Example 9 that further includes a die located on a second substrate and electrically coupled to one or more of the second conductive paths within the second substrate.

[0134]

[0143] Example 11 provides a microelectronic assembly of Example 10, further comprising an interconnect die that is at least partially located within the second dielectric material of the second substrate and electrically coupled to the die.

[0135]

[0144] Example 12 provides a microelectronic assembly of Example 10 or 11, further comprising an insulating material surrounding the die.

[0136]

[0145] Example 13 provides a microelectronic assembly from any one of Examples 9 to 12, further comprising a circuit board located on the first substrate and electrically coupled to one or more of the first conductive paths.

[0137]

[0146] Example 14 provides a microelectronic assembly comprising: a glass layer having a first surface and a second surface opposite to it; vias (containing a first conductive material) extending through the glass layer between the first and second surfaces; a first liner material in the sidewall of the via (the first liner material comprising a dielectric material having a width between 0.1 nanometers and 100 nanometers); and a second liner material between the first liner material and the first conductive material of the via (containing a second conductive material different from the first conductive material, having a width between 5 nanometers and 20 nanometers).

[0138]

[0147] Example 15 provides a microelectronic assembly of Example 14 in which the first conductive material comprises copper and the second liner material comprises ruthenium.

[0139]

[0148] Example 16 provides a microelectronic assembly of Example 14 or 15 in which the dielectric material of the first liner material comprises silicon and oxygen; silicon and nitrogen; silicon and carbon; silicon, oxygen, and carbon; or silicon, nitrogen, and carbon.

[0140]

[0149] Example 17 provides a microelectronic assembly from any one of Examples 14 to 16 in which the glass core thickness is between 50 microns and 2 millimeters.

[0141]

[0150] Example 18 provides a microelectronic assembly from any one of Examples 14 to 17 in which the vias have an aspect ratio between 5:1 and 30:1.

[0142]

[0151] Example 19 further provides a microelectronic assembly according to any one of claims 14 to 18, comprising a third liner material between a second liner material and a first conductive material of a via, wherein the third liner material comprises a third conductive material having a width between 100 nanometers and 250 nanometers.

[0143]

[0152] Example 20 provides a microelectronic assembly of Example 19 in which the third conductive material comprises copper having an average particle size between 10 nanometers and 100 nanometers.

[0144]

[0153] Example 21 provides a microelectronic assembly of Example 19 or 20 in which the third conductive material comprises ruthenium, zinc, iron, nickel, tin, lead, or silver.

[0145]

[0154] Example 22 provides a microelectronic assembly of any one of Examples 14 to 22, wherein the via is one of a plurality of through vias, and the microelectronic assembly further comprises a first substrate on a first surface of a glass layer (including a first conductive path penetrating a first dielectric material, electrically coupled to at least one of the plurality of through vias); and a second substrate on a second surface of a glass layer (including a second conductive path penetrating a second dielectric material, electrically coupled to at least one of the plurality of vias).

[0146]

[0155] Example 23 provides a microelectronic assembly of Example 22 that further includes a die located on a second substrate and electrically coupled to one or more of the second conductive paths within the second substrate.

[0147]

[0156] Example 24 provides a microelectronic assembly of Example 23, further comprising an interconnect die that is at least partially located within the second dielectric material of the second substrate and electrically coupled to the die.

[0148]

[0157] Example 25 provides a microelectronic assembly from any one of Examples 22 to 24, further comprising a circuit board located on the first substrate and electrically coupled to one or more of the first conductive paths.

[0149]

[0158] Example 26 provides a microelectronic assembly comprising: a glass core having a first surface and a second surface opposite to it; conductive vias penetrating the glass core; a first liner (containing dielectric material) within the conductive vias; and a second liner (containing alternating layers of the first conductive material and the second conductive material, with the overall width of the second liner being between 5 nanometers and 30 nanometers) between the first liner and the material of the conductive vias.

[0150]

[0159] Example 27 provides a microelectronic assembly of Example 26 in which the first conductive material comprises ruthenium and the second liner material comprises copper.

[0151]

[0160] Example 28 provides a microelectronic assembly of Example 26 or 27 that includes 50 to 300 alternating layers.

[0152]

[0161] Example 29 provides a microelectronic assembly from any one of Examples 26 to 29 in which the width of a single alternating layer is approximately 0.2 nanometers.

[0153]

[0162] Example 30 provides a microelectronic assembly from any one of Examples 26 to 29 in which the dielectric material of the first liner material comprises silicon and oxygen; silicon and nitrogen; silicon and carbon; silicon, oxygen, and carbon; or silicon, nitrogen, and carbon.

[0154]

[0163] Example 31 provides a microelectronic assembly from any one of Examples 26 to 30, wherein the first liner has a width between 0.1 nanometers and 100 nanometers.

[0155]

[0164] Example 32 provides a microelectronic assembly from any one of Examples 26 to 31 in which the glass core thickness is between 50 microns and 2 millimeters.

[0156]

[0165] Example 33 provides a microelectronic assembly from any one of Examples 26 to 32, further comprising a first dielectric (including a first conductive path electrically coupled to a conductive via) on the surface of a glass core die 1; and a second dielectric (including a second dielectric material electrically coupled to a conductive via) on the second surface of the glass core.

[0157]

[0166] Example 34 further provides the microelectronic assembly of Example 33, further comprising a die located in a second dielectric and electrically coupled to a second conductive path within the second dielectric.

[0158]

[0167] Example 35 provides a microelectronic assembly of Example 34, further comprising an interconnect die that is at least partially located within a second dielectric and electrically coupled to the die.

[0159]

[0168] Example 36 provides a microelectronic assembly of Example 34 or 35, further comprising an insulating material surrounding the die.

[0160]

[0169] Example 37 provides a microelectronic assembly from any one of Examples 33 to 36, further comprising a circuit board located in the first dielectric and electrically coupled to the first conductive path.

[0161]

[0170] Example 38 provides a microelectronic assembly from any one of Examples 26 to 37, further comprising a cavity in a second surface of a glass core and a die at least partially located within the cavity.

[0162]

[0171] Example 39 provides the microelectronic assembly of Example 38, wherein the die is a first die, and the microelectronic assembly further includes a second die located on a second surface of a glass core, the second die being electrically coupled to the first die via a conductive via.

[0163]

[0172] Example 40 provides a microelectronic assembly of any one of the above-described embodiments in which the through-via, via, or conductive via has an hourglass shape.

[0164]

[0173] Example 41 provides a microelectronic assembly of any one of the above-described embodiments in which the through via, via, or conductive via has a V-shape.

[0165]

[0174] Example 42 provides a microelectronic assembly of any one of the above-described embodiments in which the through via, via, or conductive via has a cylindrical shape.

Claims

1. It is a microelectronic assembly: A core comprising through vias, wherein the through vias comprise a first conductive material having a first average particle size; A first liner material located on the side wall of the through via, comprising a dielectric material; and A second liner material located between the first liner material and the first conductive material of the through via, wherein the second liner material comprises a second conductive material having a second average particle size, and the first average particle size is greater than the second average particle size; A microelectronic assembly equipped with [a specific feature].

2. A microelectronic assembly according to claim 1, wherein the first conductive material comprises copper and the second liner material comprises copper.

3. A microelectronic assembly according to claim 2, wherein the first average particle size is between 100 nanometers and 2 microns, and the second average particle size is between 8 nanometers and 20 nanometers.

4. A microelectronic assembly according to claim 1, wherein the second liner material has a width between 5 nanometers and 30 nanometers.

5. A microelectronic assembly according to claim 1, wherein the dielectric material of the first liner material comprises silicon and oxygen; silicon and nitrogen; silicon and carbon; silicon, oxygen, and carbon; or silicon, nitrogen, and carbon.

6. A microelectronic assembly according to claim 1, wherein the first liner material has a width between 0.1 nanometers and 100 nanometers.

7. A microelectronic assembly according to claim 1, wherein the core material comprises bulk glass.

8. A microelectronic assembly according to any one of claims 1 to 7, wherein the thickness of the core is between 50 microns and 2 millimeters.

9. It is a microelectronic assembly: A glass layer having a first surface and a second surface opposite to it; A via extending through the glass layer between the first surface and the second surface, comprising a first conductive material; A first liner material located on the side wall of the via, the first liner material comprising a dielectric material having a width between 0.1 nanometers and 100 nanometers; and A second liner material located between the first liner material and the first conductive material of the via, wherein the second liner material comprises a second conductive material different from the first conductive material and has a width between 5 nanometers and 20 nanometers; A microelectronic assembly equipped with [a specific feature].

10. A microelectronic assembly according to claim 9, wherein the first conductive material comprises copper and the second conductive material comprises ruthenium.

11. A microelectronic assembly according to claim 9, wherein the dielectric material of the first liner material comprises silicon and oxygen; silicon and nitrogen; silicon and carbon; silicon, oxygen, and carbon; or silicon, nitrogen, and carbon.

12. A microelectronic assembly according to claim 9, wherein the vias have an aspect ratio between 5:1 and 30:

1.

13. A microelectronic assembly according to any one of claims 9 to 12, further comprising: A microelectronic assembly comprising a third liner material between the second liner material and the first conductive material of the via, wherein the third liner material comprises a third conductive material having a width between 100 nanometers and 250 nanometers.

14. A microelectronic assembly according to claim 13, wherein the third conductive material comprises copper having an average particle size between 10 nanometers and 100 nanometers.

15. A microelectronic assembly according to claim 13, wherein the third conductive material comprises ruthenium, zinc, iron, nickel, tin, lead, or silver.

16. It is a microelectronic assembly: A glass core having a first surface and a second surface opposite to it; A conductive via penetrating the glass core; A first liner in the conductive via, comprising a dielectric material; A second liner in the conductive via, located between the first liner and the conductive via material, wherein the second liner comprises alternating layers of the first conductive material and the second conductive material, and the overall width of the second liner is between 5 nanometers and 30 nanometers; A microelectronic assembly including [a specific component].

17. A microelectronic assembly according to claim 16, wherein the first conductive material comprises ruthenium and the second conductive material comprises copper.

18. A microelectronic assembly according to claim 16, wherein the second liner comprises 50 to 300 alternating layers.

19. A microelectronic assembly according to claim 16, wherein the dielectric material of the first liner comprises silicon and oxygen; silicon and nitrogen; silicon and carbon; silicon, oxygen, and carbon; or silicon, nitrogen, and carbon.

20. A microelectronic assembly according to claim 16, wherein the first liner has a width between 0.1 nanometers and 100 nanometers.

21. A microelectronic assembly according to claim 16, wherein the thickness of the glass core is between 50 microns and 2 millimeters.

22. A microelectronic assembly according to any one of claims 16 to 21, further comprising: A first dielectric on the first surface of the glass core, comprising a first conductive path electrically coupled to the conductive via; and A second dielectric located on the second surface of the glass core, comprising a second conductive path electrically coupled to the conductive via; A microelectronic assembly including [a specific component].

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