Voltage detection circuit, semiconductor device, and display driver

Abstract

This invention provides a voltage detection circuit capable of accurately detecting electromagnetic noise superimposed on the power supply voltage. [Solution] The device includes a first capacitance element C11 with one end connected to a first power supply terminal nvhp and the other end connected to a first node n11, a second capacitance element C12 with one end connected to a first node and the other end connected to a second power supply terminal nvss, a first transistor 11 with its gate connected to a first node and its source and drain connected to a third power supply terminal nvdd and a second node n12, respectively, a first switch SW11 which is ON during the backup period to supply a third power supply voltage to the first node and OFF during the detection period following the backup period, a second switch SW12 which is ON during the backup period to supply a second power supply voltage to the second node and OFF during the detection period, and a detection signal generation circuit which outputs a detection signal indicating an abnormality in the first power supply voltage when the voltage of the second node changes significantly above a predetermined value.

Description

Technical Field

[0001] The present disclosure relates to a voltage detection circuit, a semiconductor device, and a display driver.

Background Art

[0002] In recent years, as an electronic device, in order to prevent malfunction due to electromagnetic noise (power supply electromagnetic noise) that has entered the interior from its own power supply terminal, a semiconductor integrated circuit device equipped with such a power supply electromagnetic noise detection circuit has been proposed (see, for example, Patent Document 1). In the power supply electromagnetic noise detection circuit described in Patent Document 1, the voltage of the power supply terminal is stepped down, and when the stepped-down voltage is higher than a predetermined voltage, it is determined that positive-polarity electromagnetic noise is generated, and when the voltage of the power supply terminal is lower than the predetermined voltage, it is determined that negative-polarity electromagnetic noise is generated. Thus, the power supply electromagnetic noise detection circuit detects both positive-polarity electromagnetic noise and negative-polarity electromagnetic noise superimposed on the power supply terminal.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] By the way, in the voltage detection circuit of Patent Document 1, the high-potential-side power supply voltage received at the power supply terminal is directly supplied to a logic circuit (for example, a NAND gate), and the detection of negative-polarity electromagnetic noise is performed based on the output result of this logic circuit. Therefore, the detection of whether negative-polarity electromagnetic noise is generated depends on the threshold value of the logic circuit, that is, actually on the threshold voltage of the transistor.

[0005] Therefore, in the voltage detection circuit of Patent Document 1, even if negative electromagnetic noise is generated and the power supply voltage drops as a result, it cannot be detected as negative electromagnetic noise unless the dropped voltage exceeds the transistor's threshold voltage. In other words, according to the voltage detection circuit of Patent Document 1, if the power supply voltage on the high-potential side to be detected is higher than the power supply voltage for the logic circuit, there are cases where even if a relatively large amplitude change occurs, it cannot be detected as electromagnetic noise.

[0006] The voltage detection circuit according to this disclosure includes a first power terminal that receives a first power supply voltage, a second power supply terminal that receives a second power supply voltage, a third power supply terminal that receives a third power supply voltage, a first capacitive element with one end connected to the first power supply terminal and the other end connected to a first node, a second capacitive element with one end connected to the first node and the other end connected to the second power supply terminal, a first transistor with its gate connected to the first node and its source and drain connected to the third power supply terminal and the second node, respectively, and The system includes: a first switch which is ON during the preparation period and OFF during the detection period, and which is OFF during the preparation period and which is OFF during the detection period, at predetermined intervals including the preparation period and the detection period following the preparation period; a second switch which is ON during the preparation period and which is OFF during the detection period and which is OFF during the detection period; and a detection signal generation circuit which outputs a detection signal indicating that an abnormality has occurred in the first power supply voltage when the voltage of the second node changes by a predetermined value from the state of the second power supply voltage toward the third power supply voltage. [Brief explanation of the drawing]

[0007] [Figure 1] This is a circuit diagram showing the configuration of the voltage detection circuit 100_1. [Figure 2] This is a time chart showing the operation of the voltage detection circuit 100_1. [Figure 3A] This is a circuit diagram showing the configuration of the voltage detection circuit 100_2A. [Figure 3B] This is a circuit diagram showing the configuration of the voltage detection circuit 100_2B. [Figure 3C] This is a circuit diagram showing the configuration of the voltage detection circuit 100_2C. [Figure 4] This is a circuit diagram showing the configuration of the voltage detection circuit 100_3. [Figure 5] This is a time chart showing the operation of the voltage detection circuit 100_3. [Figure 6] This is a circuit diagram showing the configuration of the voltage detection circuit 100_4. [Figure 7A] This is a circuit diagram showing the configuration of the voltage detection circuit 200_1. [Figure 7B] This is a time chart showing the operation of the voltage detection circuit 200_1. [Figure 8] This is a block diagram showing the configuration of the display device 2000. [Figure 9A] This is a time chart showing an example of the control of the voltage detection circuit 100_3 when it is installed in the display driver. [Figure 9B] This is a time chart showing an example of the control of the voltage detection circuit 100_4 when it is installed in the display driver. [Modes for carrying out the invention] [Examples]

[0008] Figure 1 is a circuit diagram showing the configuration of a voltage detection circuit 100_1 as a first embodiment of the present disclosure.

[0009] The voltage detection circuit 100_1 is formed on the semiconductor device 1000, as shown in Figure 1. The semiconductor device includes a semiconductor circuit formed on a semiconductor substrate such as silicon and a thin-film semiconductor circuit formed on an insulating substrate. Along with the voltage detection circuit 100_1, the semiconductor device 1000 also has a main circuit 110 that performs the main functions of the semiconductor device 1000, a control unit 109, and an ESD (Electro-Static Discharge) protection circuit 120. Furthermore, the semiconductor device 1000 has a plurality of electrode pads (not shown) including a power pad (terminal) PAD for receiving the high-potential power supply voltage VHP used by the main circuit 110 from an external source, and a power line LB for transmitting the power supply voltage VHP received by the power pad PAD to the main circuit 110. In addition to the power supply voltage VHP, the power supply voltage supplied to the semiconductor device 1000 via the power pad PAD may also be provided with a voltage detection circuit 100_1, similar to the power supply voltage VHP in Figure 1. For the sake of explanation, the following will be explained using the power supply voltage VHP as an example.

[0010] The ESD protection circuit 120 is located near the electrode pads. The ESD protection circuit 120 protects the main circuit 110 from large currents by forcibly diverting the current to the ground wire when a large current due to electrostatic discharge (ESD) enters through the electrode pads.

[0011] The control unit 109 controls the operation of the main circuit 110 and supplies control signals (S11, S12) to the voltage detection circuit 100_1 to control the operation of the voltage detection circuit 100_1, and receives the output signal of the detection result from the voltage detection circuit 100_1.

[0012] The voltage detection circuit 100_1 operates based on control signals S11 and S12 supplied from the control unit 109, and detects instantaneous voltage fluctuations caused by electromagnetic noise that has entered the semiconductor device 1000 via the power supply pad PAD, for example, due to electromagnetic interference (EMI). In particular, the voltage detection circuit 100_1 can detect voltage fluctuations caused by negative polarity electromagnetic noise that, when superimposed on the power supply voltage VHP, instantaneously lowers the voltage value of the power supply voltage VHP (voltage fluctuations that reduce the power supply voltage difference of the main circuit 110). When the voltage detection circuit 100_1 detects such an instantaneous voltage fluctuation of the power supply voltage, it generates a detection signal VO indicating that an abnormal voltage fluctuation has occurred for a predetermined period of time, and supplies this to the control unit 109. On the other hand, the main circuit 110 is supplied with the power supply voltage VHP and a voltage different from the power supply voltage VHP (power supply voltage VSS in Figure 1), and operates within the voltage difference between the two power supply voltages (VHP-VSS). If the power supply voltage VHP experiences instantaneous and large voltage fluctuations due to negative electromagnetic noise, the power supply voltage difference in the main circuit 110 may decrease significantly instantaneously, potentially causing some kind of circuit operation abnormality in the main circuit 110. Therefore, when the control unit 109 receives the detection signal VO indicating an abnormality, it performs various processes (not described) on the main circuit 110 to resolve the abnormality (malfunction) that may be caused by the electromagnetic noise.

[0013] The voltage detection circuit 100_1 that still detects instantaneous power supply voltage fluctuations due to electromagnetic noise is required to reliably detect voltage fluctuations that particularly reduce the power supply voltage difference. For example, the ESD protection circuit 120 functions for voltage fluctuations that increase the power supply voltage difference. Also, circuit operation does not become abnormal due to a slight increase in the power supply voltage difference. On the other hand, there is nothing that detects voltage fluctuations in which the power supply voltage difference instantaneously decreases significantly and then returns. Many general voltage detection circuits detect abnormalities when voltage fluctuations continue for a certain period of time or longer. When a large voltage fluctuation occurs that instantaneously falls below the operable voltage range of the main circuit 110 due to electromagnetic noise, even if it quickly returns to the original voltage, it cannot be denied that there is a possibility of causing some abnormality in the main circuit 110. In contrast, the voltage detection circuit 100_1 of the present invention is provided as a voltage detection circuit that can detect instantaneous power supply voltage fluctuations that reduce the power supply voltage difference due to electromagnetic noise.

[0014] As shown in FIG. 1, the voltage detection circuit 100_1 includes capacitive elements C11, C12, a transistor 11 of the first conductivity type (for example, P-channel type), switches SW11, SW12, and a detection signal generation circuit 91. Note that the voltage detection circuit 100_1 receives supply of control signals S11, S12 from the control unit 109, and the output signal of the detection result of the voltage detection circuit 100_1 is output to the control unit 109.

[0015] One end of the capacitive element C11 is connected to a power supply terminal nvhp that receives the high-potential-side power supply voltage VHP, and the other end is connected to one end of the capacitive element C12 via a node n11. The other end of the capacitive element C12 is connected to a power supply terminal nvss that receives the low-potential-side power supply voltage VSS. Thus, the capacitive elements C11 and C12 are connected in series between the power supply terminal nvhp and the power supply terminal nvss via the node n11.

[0016] The source of the transistor 11 is connected to a power supply terminal nvdd that receives, for example, the power supply voltage VDD for a logic circuit, the drain of the transistor 11 is connected to a node n12, and the gate of the transistor 11 is connected to the node n11.

[0017] Furthermore, the power supply voltages VHP, VDD, and VSS described above have the following magnitude relationship.

[0018] VHP ≧ VDD > VSS Switch SW11 is composed of a P-channel transistor same as transistor 11. Its source is connected to the power supply terminal nvdd described above, its drain is connected to node n11, and it receives a switch control signal S11 at its gate. That is, when switch SW11 is turned on according to the switch control signal S11, it applies the power supply voltage VDD to node n11, thereby setting transistor 11 to the off state.

[0019] Switch SW12 is composed of a transistor of the second conductivity type (for example, N-channel type). Its source is connected to the power supply terminal nvss described above, its drain is connected to node n12, and it receives a switch signal S12 at its gate. That is, when switch SW12 is turned on according to the switch control signal S12, it applies the power supply voltage VSS to node n12.

[0020] The switch control signals S11 and S12 are logic signals of the power supply voltages VDD / VSS, and are a binary signal S11 that alternately and periodically repeats the state of logic level 0 (VSS) and the state of logic level 1 (VDD), and a signal S12 obtained by inverting the logic level of signal S11. Both are generated by the control unit 109 and supplied to the voltage detection circuit 100_1.

[0021] The detection signal generation circuit 91 is composed of a logic circuit that operates by receiving the power supply voltages VDD and VSS, and receives the voltage of node n12 as voltage V12.

[0022] The detection signal generation circuit 91 generates a detection signal VO, for example, a logic level 1 signal indicating an abnormality, when, for example, electromagnetic noise causes a large voltage fluctuation in the power supply voltage VHP and the change in the voltage value of voltage V12 exceeds a predetermined threshold voltage. On the other hand, if the voltage fluctuation of the power supply voltage VHP is small and the change in the voltage value of voltage V12 remains below the predetermined threshold voltage, the detection signal generation circuit 91 generates a detection signal VO, for example, a logic level 0 signal indicating that no abnormality has occurred.

[0023] The operation of the voltage detection circuit 100_1 shown in Figure 1 will be explained below with reference to the time chart shown in Figure 2.

[0024] The voltage detection circuit 100_1 repeatedly performs the operation of a detection operation period Tw1, which consists of a preliminary period T1 and a detection period T2 that follows the preliminary period T1, as shown in Figure 2.

[0025] In other words, during the backup period T1, a switch control signal S11 with logic level 0 is supplied to switch SW11, and a switch control signal S12 with logic level 1 is supplied to switch SW12.

[0026] Therefore, during the backup period T1, switch SW11 is turned ON, the power supply voltage VDD is applied to node n11 as voltage V11, and transistor 11 is turned OFF. Furthermore, during the backup period T1, switch SW12 is turned ON, and the power supply voltage VSS is applied to node n12. As a result, the power supply voltage VSS (e.g., 0V) is supplied to the detection signal generation circuit 91 as voltage V12.

[0027] During the detection period T2, a switch control signal S11 with logic level 1 is supplied to switch SW11, and a switch control signal S12 with logic level 0 is supplied to switch SW12.

[0028] Therefore, during the detection period T2, both switches SW11 and SW12 are in the OFF state.

[0029] During the detection period T2, when negative-polarity electromagnetic noise NZ, which causes the voltage value of the power supply voltage VHP to fluctuate in a downward direction as shown in Figure 2, is superimposed on the power supply voltage VHP, the capacitive elements C11 and C12 generate a voltage V11 with the amplitude of the electromagnetic noise NZ attenuated. As a result, V11 = Vnz·Ca / (Ca + Cb) Vnz: Amplitude of electromagnetic noise NZ Capacitance of Ca:C11 Cb:C12 capacitance The voltage V11 represented by is applied to the gate of transistor 11 via node n11.

[0030] In this case, if the voltage V11 corresponding to the electromagnetic noise NZ drops significantly below the threshold voltage (absolute value) Vt of transistor 11 from the power supply voltage VDD at time t1 shown in Figure 2, transistor 11 turns on and raises the voltage V12 at node n12. Then, if the voltage V12 changes significantly above a predetermined value at time t2 shown in Figure 2, the detection signal generation circuit 91 outputs a logic level 1 detection signal VO indicating the occurrence of an anomaly for a predetermined period (from time t2 to the start time t3 of the next buffer period T1 in Figure 2).

[0031] As described above, the voltage detection circuit 100_1 first extracts the voltage fluctuation (amplitude) occurring in the power supply voltage VHP using capacitive elements C11 and C12, and generates a voltage V11 by attenuating that amplitude by the capacitance ratio of the two. Then, the voltage detection circuit 100_1 detects whether or not a large voltage fluctuation due to negative electromagnetic noise is occurring in the power supply voltage VHP by checking whether or not the voltage V11 exceeds the threshold voltage Vt of transistor 11.

[0032] In this case, the voltage detection circuit 100_1 detects whether or not negative electromagnetic noise is present by utilizing the threshold voltage Vt of transistor 11. The detection sensitivity of electromagnetic noise can be optimally adjusted by changing the capacitance ratio of capacitive elements C11 and C12.

[0033] Therefore, the voltage detection circuit 100_1 makes it possible to reliably detect negative electromagnetic noise superimposed on the power supply voltage VHP, that is, voltage fluctuations in the direction of reducing the voltage difference between the power supply voltage VSP and the power supply voltage VSS, regardless of the magnitude of the power supply voltage VHP.

[0034] Furthermore, in the voltage detection circuit 100_1, the electromagnetic noise component superimposed on the power supply voltage VHP is divided and extracted by the capacitive elements C11 and C12, and the extracted divided noise (voltage fluctuation amount) is detected by the simple on / off operation of transistor 11, making it possible to detect electromagnetic noise with a nanosecond width at high speed. By setting the cycle period Tw1, which consists of a preparatory period T1 and a detection period T2, to a relatively short length, it is possible to ignore the off-leak effect of the off switches SW1 and SW2, and relatively small capacitance elements C11 and C12 can be used, making it possible to reduce the area of ​​the device.

[0035] Furthermore, the voltage detection circuit 100_1 has a back gate with a PN junction in the case of a semiconductor circuit formed on a semiconductor substrate, but there is no back gate with a PN junction in a thin-film semiconductor circuit formed on an insulating substrate. The characteristic configuration of a semiconductor circuit including a back gate will be explained using the circuit diagrams that include the back gate in the following embodiments.

[0036] As detailed above, the voltage detection circuit of this disclosure includes the following configuration, enabling accurate detection of instantaneous and large power supply voltage fluctuations of negative polarity caused by electromagnetic noise entering from the outside.

[0037] In other words, the voltage sensing circuit of this disclosure includes first to third power supply terminals (nvhp, nvss, nvdd) that receive first to third power supply voltages (VHP, VSS, VDD), and the following first and second capacitive elements, a first transistor, first and second switches, and a sensing signal generation circuit.

[0038] The first capacitive element (C11) has one end connected to the first power supply terminal (nvhp) and its other end connected to the first node (n11). The second capacitive element (C12) has one end connected to this first node and its other end connected to the second power supply terminal (nvss). The first transistor (11) of the first conductivity type (P-channel type) has its gate connected to the first node, and its source and drain are connected to the third power supply terminal (nvdd) and the second node (n12), respectively. The first switch (SW11) is turned ON during the preparation period and supplies the third power supply voltage (VDD) to the first node (n11) at predetermined cycles (Tw1) including a preparation period (T1) and a detection period (T2) following the preparation period, and is turned OFF during the detection period (T2). The second switch (SW12) is ON during the backup period, supplying the second power supply voltage (VSS) to the second node (n12), and is OFF during the detection period. The detection signal generation circuit (91) outputs a detection signal (VO) indicating that an abnormality has occurred in the first power supply voltage (VHP) when the voltage at the second node changes significantly from the state of the second power supply voltage (VSS) toward the third power supply voltage (VDD) by more than a predetermined value. [Examples]

[0039] Figure 3A is a circuit diagram showing the configuration of a voltage detection circuit 100_2A formed on a semiconductor substrate such as silicon as a second embodiment of the present disclosure. Note that in Figure 3A, the ESD protection circuit 120, main circuit 110, and semiconductor IC chip 1000 shown in Figure 1 are omitted (the same applies to each of the following embodiments) to show the configuration of the voltage detection circuit 100_2A. A control unit 109 that supplies switch control signals S11 and S12 to the voltage detection circuit 100_2A is also shown.

[0040] Voltage detection circuit 100_2A is an example of a circuit used when the power supply voltage VDD / VSS shown in Figure 1 is, for example, a logic power supply voltage (3.3V / 0V), and the power supply voltage VHP is at a higher potential than VDD (for example, 7V to 24V). In voltage detection circuit 100_2A, the configuration is the same as voltage detection circuit 100_1 shown in Figure 1, except that the back gates of the P-channel transistor switch SW11 and the back gate of transistor 11 are connected to the power supply terminal nvhp. In Figure 3A, the back gates of transistor 11 and switch SW11, which are characterized by their back gate connections, are shown, but the back gates of other transistors, including SW12, are connected to a common source, and the back gates are not shown.

[0041] In the configuration of the voltage detection circuit 100_2A, each element (C11, C12, 11, SW11) included in the area enclosed by the dashed line is a high-voltage element with a voltage rating higher than the voltage (VHP-VSS), while each of the other elements is a low-voltage element with a voltage rating higher than the voltage (VDD-VSS) and lower than the voltage (VHP-VSS).

[0042] In other words, from the perspective of saving space, it is desirable to use low-voltage components for elements that operate in response to the power supply voltage VDD / VSS. However, the transistor 11 and switch SW11 connected to node n11 are at risk of exceeding the voltage rating of the low-voltage components due to fluctuations in the voltage V11.

[0043] Therefore, in the voltage detection circuit 100_2A, the transistor 11 and switch SW11 are made of high-voltage components along with the capacitive elements C11 and C12, while the switch SW12 is made of a low-voltage component.

[0044] Furthermore, in the configuration shown in Figure 3A, the back gates of transistor 11 and switch SW11 are connected to the power terminal nvhp, and the switch control signal S11 that controls the on / off state of switch SW11 is a high-voltage signal having a voltage (VHP-VSS).

[0045] The effect of back-gate connection of transistor 11 and switch SW11 is to detect only negative electromagnetic noise fluctuations that reduce the voltage amplitude caused by power supply voltage VHP and VSS, as a result of electromagnetic noise superposition. In other words, when the fluctuation of power supply voltage VHP due to electromagnetic noise superposition increases the voltage amplitude caused by power supply voltage VHP and VSS, i.e., when positive electromagnetic noise is generated, both transistor 11 and switch SW11 are in the off state, and the detection signal VO does not change.

[0046] Figure 3B is a circuit diagram showing the configuration of a voltage detection circuit 100_2B as a modified example of the voltage detection circuit 100_2A shown in Figure 3A.

[0047] Furthermore, the voltage detection circuit 100_2B is a voltage detection circuit that is effective when the voltage difference between the power supply voltage VHP and VDD is sufficiently large. In other words, when the voltage difference between the power supply voltage VHP and VDD is sufficiently large, the back gate effect in transistor 11 and switch SW11 increases, making it difficult to control each of them to the ON state.

[0048] Therefore, in the voltage detection circuit 100_2B, as shown in Figure 3B, the back gates of the transistor 11 and the switch SW11 are connected to the power terminal nvmp, which receives the power supply voltage VMP having a voltage value between the power supply voltage VHP and the power supply voltage VDD. The other configurations are the same as those of the voltage detection circuit 100_2A shown in Figure 3A. Furthermore, the switch signal S11 that controls the on / off state of the switch SW11 is a high-voltage signal having a voltage value between the voltage between the power supply voltages VHP and VMP and the power supply voltage VSS. This improves the reliability of on / off control of the transistor 11 and the switch SW11 compared to the configuration shown in Figure 3A.

[0049] Figure 3C is a circuit diagram showing the configuration of the voltage detection circuit 100_2C, which is an improvement over the configurations shown in Figures 3A and 3B, in that each element except for the capacitive elements C11 and C12 can be made of low-voltage elements.

[0050] In the voltage detection circuit 100_2C shown in Figure 3C, a clamp element 81 is newly provided in order to realize the transistor 11 and switch SW11 connected to node n11 as low-voltage elements. Furthermore, in the voltage detection circuit 100_2C, the back gates of switch SW11 and transistor 11 are connected to the power supply terminal nvdd, and the back gate of switch SW12 is connected to the power supply terminal nvss which receives the low-potential power supply voltage VSS.

[0051] The clamp element 81 can be configured, for example, as an N-channel transistor whose drain is connected to node n11 and whose gate, source, and back gate are connected to power supply terminal nvss.

[0052] The clamp element 81 receives negative electromagnetic noise during the detection period T2, and if the voltage V11 at node n11 fluctuates to a level significantly lower than the power supply voltage VSS, it flows current from the power supply terminal nvss to node n11 via the forward bias of its PN junction between its back gate and drain. This clamps the fluctuation in voltage V11 to a level lower than the power supply voltage VSS by the threshold voltage of the PN junction. The switch SW11 is in the off state during the detection period T2, and the power supply voltage VDD is applied to its gate by the switch control signal S11. However, if the voltage V11 fluctuates to a level significantly higher than the power supply voltage VDD, i.e., if it receives positive electromagnetic noise, it flows current from node n11 to the power supply terminal nvdd via the forward bias of its PN junction between its drain and back gate. This keeps the fluctuation in voltage V11 at a level higher than the power supply voltage VDD by the threshold voltage of the PN junction, making it possible to use low-voltage elements for the transistor 11 and switch SW11.

[0053] Note that while the clamp element 81 in Figure 3C is an example composed of an N-channel transistor, it is also possible to use a P-channel transistor instead, where its source is connected to the power supply terminal nvdd and its gate and drain are connected to node n11. However, in that case, the threshold voltage (absolute value) of the P-channel transistor constituting the clamp element should be designed to be greater than the threshold voltage (absolute value) of transistor 11.

[0054] Furthermore, although Figure 3C shows an example of a semiconductor circuit with a back gate, a similar configuration is possible even with a thin-film semiconductor circuit without a back gate. In that case, when the voltage V11 at node n11 is subjected to a fluctuation that drops significantly below the power supply voltage VSS, the clamp element 81 of the N-channel transistor maintains its gate connection, with the source connected to the power supply terminal nvss becoming the drain and the drain connected to node n11 becoming the source, forming a diode connection. This causes current to flow from the power supply terminal nvss to node n11, clamping the voltage fluctuation V11 to a voltage slightly lower than the threshold voltage of the clamp element 81 than the power supply voltage VSS. On the other hand, if the voltage V11 at node n11 is subjected to a fluctuation that rises significantly higher than the power supply voltage VDD, the P-channel transistor switch SW11 maintains its gate voltage VDD, and the source connected to the power supply terminal nvdd becomes the drain, while the drain connected to node n11 becomes the source, forming a diode connection. This allows current to flow from node n11 to the power supply terminal nvdd, clamping the voltage fluctuation V11 to a voltage slightly higher than the power supply voltage VDD and the threshold voltage (absolute value) of switch SW11. Other than the above, its operation is the same as that of a semiconductor circuit with a back gate. [Examples]

[0055] Figure 4 is a circuit diagram showing the configuration of a voltage detection circuit 100_3 as a third embodiment of the present disclosure. The voltage detection circuit 100_3 is identical to the voltage detection circuit 100_1 shown in Figure 1, except that a logic value conversion circuit 92 is newly added and a detection signal generation circuit 91_1 is used instead of the detection signal generation circuit 91. Furthermore, a control unit 109_1 is used instead of the control unit 109 to supply control signals S11, S12 and SC to the voltage detection circuit 100_3.

[0056] The logic value conversion circuit 92 includes, for example, a switch SW13 made of a P-channel transistor, an N-channel transistor 12, and a current source Is13.

[0057] Switch SW13 has its source connected to the power terminal nvdd as described above, its drain connected to node n13, and receives the switch control signal S13 at its gate. In other words, when switch SW13 turns ON in response to the switch control signal S13, it applies the power supply voltage VDD to node n13.

[0058] Transistor 12 has its source connected to the power supply terminal nvss described above, its drain connected to node n13, and its gate receives the voltage V12 of node n12 described above. In other words, when transistor 12 turns on in response to the voltage V12, it pulls node n13 down towards the power supply voltage VSS.

[0059] The current source Is13 generates a small constant current that is sufficient to maintain the voltage value V13 at node n13 at logic level 1, corresponding to the power supply voltage VDD, even after the switch SW13 has transitioned from the ON state to the OFF state, and sends this current to node n13.

[0060] The detection signal generation circuit 91_1 includes an inverter IV and an RS flip-flop FF.

[0061] Inverter IV supplies voltage V14, which is the inverted logic level of voltage V13 at node n13, to the R terminal of the RS flip-flop FF. Therefore, if the voltage V12 at node n12, which is the input to the logic value conversion circuit 92, is lower than the threshold voltage of transistor 12, voltage V13 will be logic level 1 and voltage V14 will be logic level 0. If voltage V12 is equal to or greater than the threshold voltage of transistor 12, voltage V13 will be logic level 0 and voltage V14 will be logic level 1 supplied to the R terminal of the RS flip-flop FF. The RS flip-flop FF receives a binary control signal SC, which represents logic level 0 or 1, at its S terminal.

[0062] The RS flip-flop FF receives a control signal SC at input terminal S and a voltage V14 at input terminal R, which has a logical value indicating the presence or absence of a large voltage fluctuation (abnormality) on the negative side of the power supply voltage VHP. When voltage V14 receives a logical level 1 indicating an abnormality in the power supply voltage VHP, the flip-flop outputs a logical level 1 indicating an abnormality from the inverting output terminal XQ for a period corresponding to the logical level of the control signal SC. Specifically, when the logical level of the control signal SC is 1, the voltage V14 input to input terminal R is set to logical level 0, and the detection signal VO output from the inverting output terminal XQ is set to logical level 0 indicating normality. Subsequently, when the control signal SC becomes logical level 0, the detection signal VO output from the inverting output terminal XQ maintains the same logical level as the voltage V14 received at input terminal R. During this time, if the voltage V14 input to input terminal R changes to a logical level 1 indicating an abnormality, the detection signal VO output from the inverting output terminal XQ also changes to a logical level 1 indicating an abnormality. The detection signal VO at logical level 1 indicating an abnormality is then maintained until the control signal SC changes to logical level 1 again. Therefore, when the detection signal VO changes to logic level 1, which indicates an abnormality, the retention period for the subsequent logic level of the detection signal VO is set by the timing of the change in the logic level of the control signal SC, regardless of the change in the logic level of the output signal of the preceding circuit of the detection signal generation circuit 91_1.

[0063] With the above configuration, in the voltage detection circuit 100_3, when the voltage V11 at node n11 drops due to instantaneous fluctuations in the power supply voltage VHP caused by superimposed electromagnetic noise, and exceeds the threshold voltage Vt of transistor 11, transistor 11 instantaneously turns on, raising the voltage V12 at node n12. At this time, the voltage V12 fluctuates depending on the speed and magnitude of the fluctuation of voltage V11, but does not necessarily rise to the power supply voltage VDD. In particular, near the boundary between the allowable range (normal) and unacceptable range (abnormal) of the amount of fluctuation of the power supply voltage VHP, the voltage V12 remains at an intermediate voltage. For example, if the voltage V12 only rises to an intermediate voltage between the power supply voltage VDD and VSS, and the detection signal generation circuit 91_1 directly receives that voltage V12, the logic level of the output voltage V14 of inverter IV will not be determined to be 0 or 1, resulting in an intermediate voltage that may prevent the RS flip-flop FF from operating normally. Furthermore, a through-current may flow within inverter IV and RS flip-flop FF, potentially generating unnecessary current consumption.

[0064] Therefore, the voltage detection circuit 100_3 is provided with a logic value conversion circuit 92. The logic value conversion circuit 92 converts the voltage V13 at node n13 to a voltage value corresponding to logic level 0 if the voltage V12 exceeds the threshold voltage of transistor 12. On the other hand, if the voltage V12 is less than or equal to the threshold voltage of transistor 12, the logic value conversion circuit 92 converts the voltage V13 at node n13 to a voltage value corresponding to logic level 1. In other words, the logic value conversion circuit 92 reliably assigns the voltage V13 to either logic level 0 or 1 even when the fluctuation amount of the power supply voltage VHP is near the boundary between the allowable range (normal) or the unallowable range (abnormal) (when the voltage V12 remains near the threshold voltage of transistor 12).

[0065] Switch SW13, like switches SW11 and SW12, is controlled to be on during the preliminary period T1 shown in Figure 2 and off during the detection period T2, in response to the switch signal S13. At this time, the current source Is13 supplies a sufficiently small constant current to node n13, thereby stably maintaining the logic level 1 state when the voltage V13 at node n13 is in the logic level 1 state during the detection period T2. In the example shown in Figure 4, a switch SW13 and a current source Is13 are provided, but other configurations are also acceptable as long as the voltage V13 can be reliably distributed to logic level 0 or 1 in response to fluctuations in voltage V12.

[0066] Figure 5 is a time chart showing the operation of the voltage detection circuit 100_3 shown in Figure 4.

[0067] As shown in Figure 5, the voltage detection circuit 100_3, similar to the voltage detection circuit 100_1, repeatedly performs operations during a detection operation period Tw1 consisting of a preliminary period T1 and a subsequent detection period T2 to detect whether or not a large voltage fluctuation (abnormality) due to electromagnetic noise is occurring in the power supply voltage VHP to be detected.

[0068] In other words, during the backup period T1, logic level 0 switch control signals S11 and S13 are supplied to switches SW11 and SW13, respectively, and logic level 1 switch control signal S12 is supplied to switch SW12. As a result, during the backup period T1, switches SW11, SW12, and SW13 are all controlled to be in the ON state, and voltages V11 and V13 become the power supply voltage VDD, and voltage V12 becomes the power supply voltage VSS.

[0069] On the other hand, during the detection period T2, logic level 1 switch control signals S11 and S13 are supplied to switches SW11 and SW13, respectively, and logic level 0 switch control signal S12 is supplied to switch SW12. As a result, switches SW11, SW12, and SW13 all turn off. Therefore, if the power supply voltage VHP fluctuates significantly to the low potential side due to electromagnetic noise, voltage V11 also fluctuates in conjunction, and consequently transistor 11 temporarily turns on, raising voltage V12 towards the power supply voltage VDD. However, there are cases where voltage V12 does not reach the power supply voltage VDD and remains at an intermediate voltage. Therefore, the voltage detection circuit 100_3 uses a logic value conversion circuit 92 to supply voltage V13, which is assigned to logic level 0 or 1 according to the voltage value of voltage V12, to the detection signal generation circuit 91_1 even when voltage V12 remains at an intermediate voltage.

[0070] The detection signal generation circuit 91_1 maintains and outputs the logic level of the detection signal VO according to the timing of the logic level switching of the control signal SC. The control signal SC is a signal having a predetermined period TW that includes multiple detection operation periods Tw1 consisting of a preliminary period T1 and a subsequent detection period T2. Only the initial setting period T0 immediately after the start of each period TW is set to logic level 1, and the remaining period within the period TW is set to logic level 0. In addition, the voltages V11, V12, V13, and V14 of nodes n11, n12, n13, and n14, respectively, of the initial setting period T0 are set to the same logic level as the preliminary period T1. For example, the preliminary period T1 of the first detection operation period Tw1 among the multiple detection operation periods Tw1 included in the period TW may be made to match the initial setting period T0 of the period TW.

[0071] Then, within the detection period T2 of an arbitrary detection operation period Tw1 included in the period TW, negative electromagnetic noise NZ is generated in the power supply voltage VHP, and when the voltage V11 at node n11 drops below the threshold voltage (absolute value) of transistor 11, the voltage V12 at node n12 rises from the power supply voltage VSS. When the voltage V12 rises above the threshold voltage of transistor 12, the voltage V13 at node n13 drops and the voltage V13 returns to the state of the power supply voltage VSS corresponding to logic level 0. Upon receiving the voltage V13 corresponding to logic level 0, the detection signal generation circuit 91_1 outputs a logic level 1 detection signal VO indicating a significant drop (abnormality) in the power supply voltage VHP. Subsequently, in the next detection operation period Tw1, if all switches SW11~SW13 are turned on in the reserve period T1 according to the switch signals S11~S13, the voltages V11 and V13 at nodes n11 and n13 return to the power supply voltage VDD, and the voltage V12 at node n12 returns to the power supply voltage VSS. However, the detection signal generation circuit 91_1 continues to output a detection signal VO at logic level 1, indicating the generation of electromagnetic noise. Subsequently, upon receiving a control signal SC at logic level 1, i.e., at the start of the next cycle TW, the detection signal generation circuit 91_1 returns the detection signal VO to logic level 0.

[0072] In other words, the voltage detection circuit 100_3 repeatedly performs the operation of the detection operation period Tw1 (T1, T2) within each period TW of the control signal SC shown in Figure 5. When it detects a significant drop (abnormality) in the power supply voltage VHP due to electromagnetic noise, the voltage detection circuit 100_3 outputs a detection signal VO that maintains a logic level 1 state indicating the occurrence of electromagnetic noise from the time of electromagnetic noise detection until the end of period TW.

[0073] Furthermore, if the detection operation period Tw1 is cycled multiple times during one cycle of the control signal SC, as shown in Figure 5, the duration of each detection period T2 is shortened. As a result, the influence of the off-leak current of the off-state switches SW11, SW12, and SW13 can be ignored, allowing the capacitance values ​​of the capacitive elements C11 and C12 and the parasitic capacitances of nodes n12 and n13 to be set small, and enabling the voltage detection circuit 100_3 to be realized in a smaller area. [Examples]

[0074] Figure 6 is a circuit diagram showing the configuration of a voltage detection circuit 100_4 as a fourth embodiment of the present disclosure.

[0075] The voltage detection circuit 100_4 shown in Figure 6 includes voltage detection units BL1 and BL2, each consisting of, for example, the voltage detection circuit 100_3 shown in Figure 4, and an OR gate.

[0076] The control unit 109_2 generates the control signal SC shown in Figure 5, similar to the control unit 109_1, and supplies it to the voltage detection units BL1 and BL2.

[0077] Furthermore, the control unit 109_2 generates the switch control signals S11 to S13 shown in Figure 5, similar to the control unit 109_1, and supplies them to the voltage detection unit BL1 as switch signals S11_1 to S13_1, respectively.

[0078] Furthermore, the control unit 109_2 generates switch signals S11_2 to S13_2, each of the above-mentioned switch signals S11_1 to S13_1 with a predetermined phase shift, and supplies each of them to the voltage detection unit BL2. It is desirable that the reserve period T1 for switch signals S11_1 to S13_1 and the reserve period T1 for switch signals S11_2 to S13_2 are set so as not to overlap.

[0079] As described above, the voltage detection units BL1 and BL2 consist of a voltage detection circuit 100_3, and one end of the capacitive element C11 contained in each is connected to the power supply terminal nvhp.

[0080] Furthermore, in the voltage detection unit BL1, the above-mentioned switch signals S11_1 to S13_1 are received as switch signals S11 to S13, respectively, at the gates of switches SW11 to SW13. In addition, the voltage detection unit BL1 receives the above-mentioned control signal SC at the S terminal of its own RS flip-flop FF. On the other hand, in the voltage detection unit BL2, the above-mentioned switch signals S11_2 to S13_2 are received as switch signals S11 to S13, respectively, at the gates of switches SW11 to SW13. In addition, the voltage detection unit BL2 receives the above-mentioned control signal SC at the S terminal of its own RS flip-flop FF.

[0081] Voltage detection unit BL1 supplies the detection signal VO output from its RS flip-flop FF to the OR gate as detection signal VO1. Voltage detection unit BL2 supplies the detection signal VO output from its RS flip-flop to the OR gate as detection signal VO2.

[0082] The OR gate outputs a logic level 1 detection signal VO when the detection signal VO1 or VO2 is logic level 1, indicating a large fluctuation (abnormality) in the power supply voltage VHP.

[0083] Thus, the voltage detection circuit 100_4 uses two voltage detection circuits 100_3 with their respective electromagnetic noise detection timings (T1 and T2) shifted relative to each other.

[0084] In other words, a single voltage detection circuit 100_3 alone cannot correctly detect instantaneous fluctuations in the power supply voltage VHP caused by electromagnetic noise that occurs during the backup period T1.

[0085] However, in the voltage detection circuit 100_4, the backup periods T1 of the two voltage detection circuits are set so that they do not overlap. That is, while one of the two voltage detection circuits is operating during the backup period T1, the other voltage detection circuit is operated during the detection period T2. As a result, the voltage detection circuit 100_4 can continuously detect the presence or absence of abnormalities in response to instantaneous fluctuations in the power supply voltage VHP due to electromagnetic noise, regardless of the backup period T1.

[0086] In addition, although the voltage detection circuit 100_4 shown in Figure 6 employs the voltage detection circuit 100_3 as the internal configuration of the voltage detection units BL1 and BL2 respectively, the aforementioned voltage detection circuits 100_1, 100_2A, 100_2B, or 100_2C may be used instead. [Examples]

[0087] Figure 7A is a circuit diagram showing the configuration of a voltage detection circuit 200_1 as a fifth embodiment of the present disclosure.

[0088] The voltage detection circuit 200_1 detects instantaneous voltage fluctuations caused by electromagnetic noise that has entered the semiconductor device via a power supply pad PAD that receives a low-potential power supply voltage VLN lower than the power supply voltage VSS. In particular, the voltage detection circuit 200_1 can detect voltage fluctuations (voltage fluctuations that reduce the power supply voltage difference) caused by positive polarity electromagnetic noise that, when superimposed on the power supply voltage VLN, instantaneously increases the voltage value of the power supply voltage VLN. Note that this semiconductor device, as in Figure 1, includes a main circuit that receives the externally supplied power supply voltage VLN via the power supply pad and performs its main function, a control unit (109A), and an ESD protection circuit (120A), but the notation of the semiconductor device and main circuit is omitted in Figure 7A.

[0089] As shown in Figure 7A, the voltage detection circuit 200_1 includes capacitive elements C21 and C22, a first-conductivity type (e.g., N-channel type) transistor 21, switches SW21 and SW22, and a detection signal generation circuit 91A. The voltage detection circuit 200_1 receives control signals S21 and S22 from the control unit 109A, and the output signal of the detection result of the voltage detection circuit 200_1 is output to the control unit 109A. In other words, the voltage detection circuit 200_1 is configured differently from the voltage detection circuit 100_1 in Figure 1 in that the detection target is changed from the high-potential side power supply voltage to the low-potential side power supply voltage, the polarity of the power supply voltage is reversed, and the conductivity types of the transistor and switches are reversed.

[0090] Capacitor element C21 has one end connected to power terminal nvln, which receives the low-potential power supply voltage VLN, and the other end connected to one end of capacitor element C22 via node n21. The other end of capacitor element C22 is connected to power terminal nvdd, which receives the power supply voltage VDD. In other words, capacitor elements C21 and C22 are connected in series between power supply terminal nvln and power supply terminal nvdd via node n21.

[0091] Transistor 21 has its source connected to power supply terminal nvss, which receives the power supply voltage VSS, its drain connected to node n22, and its gate connected to node n21.

[0092] Switch SW21 is an N-channel transistor, the same type as transistor 22. Its source is connected to the power supply terminal nvss mentioned above, its drain is connected to node n21, and it receives the switch control signal S21 at its gate. In other words, when switch SW21 turns ON in response to the switch control signal S21, it applies the power supply voltage VSS to node n21, thereby turning off transistor 21.

[0093] Switch SW22 consists of a second-conductivity type (e.g., P-channel type) transistor, with its source connected to the power supply terminal nvdd as described above, its drain connected to node n22, and its gate receiving the switch control signal S22. That is, when switch SW22 turns ON in response to the switch control signal S22, it applies the power supply voltage VDD to node n22.

[0094] The switch control signals S21 and S22 are binary logic signals. S21 is a binary signal that periodically alternates between logic level 0 and logic level 1, and S22 is a signal obtained by inverting the logic level of signal S21. Both are generated by the control unit 109A and supplied to the voltage detection circuit 200_1. When transistor 22 and switch SW21 are configured with high-voltage elements corresponding to the power supply voltage difference (VDD-VLN), control signal S21 becomes a high-voltage signal with voltage (VDD-VLN). When transistor 22 and switches SW21 and SW22 are configured with low-voltage elements corresponding to the power supply voltage difference (VDD-VSS), control signal S21, along with control signal S22, becomes a low-voltage signal with voltage (VDD-VSS). Furthermore, a clamp element may be provided to suppress large fluctuations in the voltage V21 of node n21 that exceed the power supply voltage VDD.

[0095] The detection signal generation circuit 91A consists of logic circuits that operate in response to the power supply voltage VDD and VSS, and receives the voltage at node n12 as voltage V12.

[0096] The detection signal generation circuit 91A generates a signal, for example, logic level 1, as the detection signal VO when, for example, electromagnetic noise causes a large voltage fluctuation in the power supply voltage VLN and the change in the voltage value of voltage V22 exceeds a predetermined threshold voltage. On the other hand, if the voltage fluctuation of the power supply voltage VLN is small and the change in the voltage value of voltage V22 remains below the predetermined threshold voltage, the detection signal generation circuit 91A generates a signal, for example, logic level 0, as the detection signal VO, indicating that no abnormality has occurred.

[0097] The operation of the voltage detection circuit 200_1 shown in Figure 7A will be explained below with reference to the time chart shown in Figure 7B.

[0098] The voltage detection circuit 200_1 repeatedly performs the operation of a detection operation period Tw1, which consists of a preliminary period T1 and a detection period T2 that follows the preliminary period T1, as shown in Figure 7B.

[0099] In other words, during the backup period T1, a logic level 1 switch control signal S21 is supplied to switch SW21, and a logic level 0 switch control signal S22 is supplied to switch SW22.

[0100] Therefore, during the backup period T1, both switches SW21 and SW22 are in the ON state. As a result, the power supply voltage VSS is applied to node n21 as voltage V21, and transistor 21 is turned OFF. Furthermore, the power supply voltage VDD is applied to node n22. Therefore, during the backup period T1, the power supply voltage VDD is supplied to the detection signal generation circuit 91A as voltage V22.

[0101] During the detection period T2 shown in Figure 7B, a switch control signal S21 with logic level 0 is supplied to switch SW21, and a switch control signal S22 with logic level 1 is supplied to switch SW22.

[0102] Therefore, during the detection period T2, both switches SW21 and SW22 are in the OFF state. During this detection period T2, when positive electromagnetic noise NZ that causes the power supply voltage VLN to fluctuate in a direction that increases the voltage value of VLN is superimposed on the power supply voltage VLN, as shown in Figure 7B, the capacitive elements C21 and C22 generate a voltage V21 with the amplitude of the electromagnetic noise NZ attenuated. If this voltage V21 exceeds the threshold voltage Vt of transistor 21 at time t1 shown in Figure 7B, for example, transistor 21 turns on and lowers the voltage V22 at node n22. Then, if this voltage V22 changes significantly above a predetermined value at time t2 shown in Figure 7B, the detection signal generation circuit 91A outputs a logic level 1 detection signal VO indicating the occurrence of an anomaly for a predetermined period (from time t2 to the start time t3 of the next preliminary period T1 in Figure 7A).

[0103] The voltage detection circuit in Figure 7A includes the following configuration to accurately detect instantaneous and large positive power supply voltage fluctuations caused by electromagnetic noise entering from the outside, i.e., large power supply voltage fluctuations in the direction of reducing the power supply voltage difference. The voltage detection circuit in Figure 7A includes first to third power supply terminals (nvln, nvdd, nvss) that receive first to third power supply voltages (VLN, VDD, VSS), and the following first and second capacitive elements, first transistor, first and second switches, and detection signal generation circuit.

[0104] The first capacitive element (C21) has one end connected to the first power supply terminal (nvln) and its other end connected to the first node (n21). The second capacitive element (C22) has one end connected to this first node and its other end connected to the second power supply terminal (nvdd). The first transistor (21) of the first conductivity type (N-channel type) has its gate connected to the first node, and its source and drain are connected to the third power supply terminal (nvss) and the second node (n22), respectively. The first switch (SW21) is turned ON during the preparation period and supplies the third power supply voltage (VSS) to the first node (n21) at predetermined cycles (Tw1) including a preparation period (T1) and a detection period (T2) following the preparation period, and is turned OFF during the detection period (T2). The second switch (SW22) is ON during the backup period, supplying the second power supply voltage (VDD) to the second node (n22), and is OFF during the detection period. The detection signal generation circuit (91A) outputs a detection signal (VO) indicating that an abnormality has occurred in the first power supply voltage (VLN) when the voltage at the second node changes significantly from the state of the second power supply voltage (VDD) toward the third power supply voltage (VSS) by more than a predetermined value. [Examples]

[0105] Figure 8 is a block diagram showing the configuration of the display device 2000 including the voltage detection circuit of the present disclosure.

[0106] The display device 2000 includes a display panel 700 on which a display unit 400 and a display driver 500 are mounted.

[0107] The display unit 400 includes a plurality of scan lines extending horizontally across the two-dimensional screen, data lines extending vertically across the two-dimensional screen, and a plurality of display cells formed at the intersections of each scan line and each data line, which are made of, for example, an organic EL (Electro-Luminescence) element or a liquid crystal element.

[0108] The display driver 500 is an application example of the semiconductor device 1000 shown in Figure 1 and includes a control unit, a drive unit, a charge pump control unit, and a DC-DC control unit, multiple electrode pads (PADs), an ESD protection circuit (not shown), and voltage detection circuits J1 to J4.

[0109] The control unit receives video signals and various control signals supplied from an externally connected host device via electrode pads (PADs). Based on these video signals and control signals, it generates a video data signal containing a sequence of pixel data fragments indicating the brightness of each display cell and supplies it to the drive unit. The control unit also supplies multiple control signals to the charge pump unit, DC-DC control unit, and voltage detection circuits J1 to J4, respectively, to control the operation of those circuits.

[0110] The drive unit operates by receiving power voltages PV1 and PV2 supplied from an external power supply via electrode pads, power voltages PV3 and PV4 generated by controlling the external circuit of the display driver 500 via the electrode pads by the charge pump (CP) control unit and DCDC control unit within the display driver 500 and supplied into the display driver 500 via the electrode pads, and a power voltage (not shown) that is internally generated based on the supplied power voltages.

[0111] These power supply voltages include, for example, power supply voltages for logic circuits, positive and negative power supply voltages for analog circuits, and positive and negative power supply voltages for gate circuits. The charge pump (CP) control unit and DC-DC control unit are connected to components such as capacitive elements and coils included in the external circuitry via multiple electrode pads.

[0112] The drive unit supplies scanning pulses to multiple scan lines of the display unit 400 in response to control signals supplied from the host device, and also supplies multiple drive voltages corresponding to the pixel data included in the video data signal to multiple data lines of the display unit 400.

[0113] Voltage detection circuits J1 to J4 each consist of the aforementioned voltage detection circuits 100_1 to 100_4 or 200_1, operate by receiving multiple control signals Sxx from the control unit, and supply detection signals VO that they individually generate to the control unit. For example, voltage detection circuits J1 and J2 are connected to electrode pads to which power supply voltages PV1 and PV2 are supplied from an external power supply unit. They detect whether large voltage fluctuations (abnormalities) affecting the operation of the drive unit and pixel data are occurring due to electromagnetic noise entering through the electrode pads into the power supply voltages PV1 and PV2 (e.g., high-potential voltage and low-potential voltage) supplied from the power supply unit, and supply detection signals VO_1 and VO_2 indicating the detection result to the control unit. Voltage detection circuits J3 and J4 are connected to two electrode pads that receive the power supply voltages PV3 and PV4 generated by the external circuit to the display driver 500. They individually detect whether or not a large voltage fluctuation (abnormality) due to the electromagnetic noise described above is occurring in the power supply voltages PV3 and PV4, and supply detection signals VO_3 and VO_4 indicating the respective detection results to the control unit.

[0114] If the control unit receives a detection signal VO indicating a large voltage fluctuation (abnormality) from, for example, one of the voltage detection circuits J1 to J4, it controls the drive unit to stop writing pixel data fragments to the display unit 400, that is, to stop supplying scan pulses to the multiple scan lines of the display unit 400. The control unit then controls the drive unit to resume writing pixel data fragments to the display unit 400 from the next frame after electromagnetic noise detection, returning to normal operation.

[0115] As a result, if electromagnetic noise is superimposed on the power supply voltage supplied from outside the display driver 500 via the electrode pads, and the voltage value fluctuates so much that it affects the operation of the drive unit or pixel data, the writing of pixel data fragments to the display unit 400 is immediately stopped, minimizing the extent of display defects. Furthermore, the drive unit is controlled to retain the display from the previous frame in the display area where writing has been stopped.

[0116] Furthermore, if the control unit receives a detection signal VO indicating the occurrence of an abnormality, it may feed that information back to the host device, and then control the drive unit to resume writing pixel data to the display unit 400 in response to a command from the host device to resume normal operation. [Examples]

[0117] Figure 9A is a time chart showing an example of the control of the voltage detection circuit 100_3 when it is mounted on the display driver 500 shown in Figure 8.

[0118] Furthermore, in order to perform operations according to the time chart shown in Figure 9A, the voltage detection circuit 100_3 shown in Figure 4 will be used as the voltage detection circuit. In this case, the control unit 109_1, which is responsible for controlling the voltage detection circuit 100_3, will use the vertical synchronization signal Vsync, which is included in the control signal supplied from the host device to the display driver 500, as the control signal SC. In addition, the control unit 109_1 will use the strobe signal STB, which is included in the video data signal and indicates the writing timing of each pixel data piece, as the switch control signal S12, and the inverted logic level of STB will be used as the switch control signals S11 and S13. In other words, the aforementioned detection operation period Tw1 will be one data period for writing one pixel data piece.

[0119] Here, when the display unit 400 is performing a normal display based on the video data signal, as shown in Figure 9A, if electromagnetic noise NZ occurs in the power supply voltage VHP and the voltage level drops sharply for a moment, the detection signal VO of the voltage detection circuit transitions from logic level 0 (normal) to 1 (abnormal). Upon receiving this logic level 1 (abnormal) detection signal VO, the control unit controls the drive unit to stop the writing operation of pixel data fragments to the display unit. As shown in Figure 9A, once the detection signal VO transitions to logic level 1, it is reset to logic level 0 in accordance with the vertical synchronization signal Vsync(SC) of the next frame. In other words, the logic level 1 detection signal VO indicating an abnormality continues until the start of the next frame, and the control unit controls the drive unit to resume writing pixel data fragments to the display unit from that next frame. As a result, the display unit 400 returns to a normal display state based on the video data signal.

[0120] Figure 9B is a time chart showing another example of the control of the voltage detection circuit when the voltage detection circuit of this disclosure is mounted on the display driver 500.

[0121] Furthermore, in order to perform operations according to the time chart shown in Figure 9B, the voltage detection circuit 100_4 shown in Figure 6 shall be used as the voltage detection circuit. In this case, the control unit 109_2, which is responsible for controlling the voltage detection circuit 100_4, uses the vertical synchronization signal Vsync included in the control signal supplied from the host device to the display driver 500 as the control signal SC.

[0122] Furthermore, the control unit 109_2 extracts a sequence of odd-numbered pulses from the pulse train of the strobe signal STB included in the video data signal, and supplies the signal consisting of this extracted pulse train as a switch control signal S12_1 to the voltage detection unit BL1 shown in Figure 6. In addition, the control unit 109_2 supplies signals obtained by inverting the logic level of this switch control signal S12_1 as switch control signals S11_1 and S13_1 to the voltage detection unit BL1.

[0123] Furthermore, the control unit 109_2 extracts a sequence of even-numbered pulses from the pulse train of the strobe signal STB described above, and supplies the signal consisting of this extracted pulse train as a switch control signal S12_2 to the voltage detection unit BL2 shown in Figure 6. In addition, the control unit 109_2 supplies signals obtained by inverting the logic level of this switch control signal S12_2 as switch control signals S11_2 and S13_2 to the voltage detection unit BL2.

[0124] With this operation, even if a large voltage fluctuation (abnormality) occurs in the power supply voltage VHP due to electromagnetic noise NZ during the backup period T1 of the voltage detection unit BL1, as shown in Figure 9B, the voltage detection unit BL2 can detect that voltage fluctuation (abnormality).

[0125] Therefore, the voltage detection circuit 100_4 makes it possible to continuously detect abnormal voltage fluctuations in the power supply voltage VHP within one frame period, regardless of the backup period T1.

[0126] Furthermore, this disclosure is not limited to the embodiments described above, and various improvements and design changes are possible without departing from the gist of this disclosure. In addition, while the voltage detection circuits of the present invention have been described in each embodiment as detecting instantaneous and large power supply voltage fluctuations (abnormalities) of the power supply voltage to be detected due to electromagnetic noise, it is of course possible to detect gradual and large power supply voltage fluctuations (abnormalities) due to failure modes unrelated to electromagnetic noise. [Note] This specification discloses the following configuration:

[0127] (Composition 1) A first power terminal that receives a first power supply voltage, and a second power supply terminal that receives a second power supply voltage, The device includes: a third power terminal that receives a third power supply voltage; a first capacitive element with one end connected to the first power supply terminal and the other end connected to a first node; a second capacitive element with one end connected to the first node and the other end connected to the second power supply terminal; a first transistor of a first conductivity type with its gate connected to the first node and its source and drain connected to the third power supply terminal and the second node, respectively; a first switch that, at predetermined intervals including a backup period and a detection period following the backup period, is ON during the backup period to supply the third power supply voltage to the first node and OFF during the detection period; a second switch that is ON during the backup period to supply the second power supply voltage to the second node and OFF during the detection period; and a detection signal generation circuit that outputs a detection signal indicating that an abnormality has occurred in the first power supply voltage when the voltage at the second node changes by a predetermined value from the state of the second power supply voltage toward the third power supply voltage.

[0128] (Configuration 2) The voltage detection circuit according to configuration 1, wherein the first power supply voltage and the third power supply voltage have the same voltage polarity with respect to the second power supply voltage, and the voltage difference between the first power supply voltage and the second power supply voltage is greater than or equal to the voltage difference between the first power supply voltage and the third power supply voltage.

[0129] (Composition 3) The voltage detection circuit according to configuration 1 or 2 above, wherein the detection signal generation circuit detects instantaneous fluctuations in the first power supply voltage due to electromagnetic noise and detects fluctuations in a direction that reduces the voltage difference between the first power supply voltage and the second power supply voltage.

[0130] (Composition 4) A voltage detection circuit according to any one of the above configurations 1 to 3, wherein the first capacitive element, the second capacitive element, the first transistor, and the first switch are composed of high-voltage elements capable of handling the voltage difference between the first power supply voltage and the second power supply voltage, and when the voltage difference between the first power supply voltage and the second power supply voltage is greater than the voltage difference between the third power supply voltage and the second power supply voltage, the second switch is composed of a low-voltage element capable of handling the voltage difference between the third power supply voltage and the second power supply voltage.

[0131] (Composition 5) The voltage detection circuit according to configuration 4, comprising a fourth power terminal that receives a fourth power voltage having a voltage value between the first power voltage and the third power voltage, wherein the first switch is composed of a transistor of the same conductivity type as the first transistor, and the back gates of the first transistor and the first switch, respectively, are connected to the first power terminal or the fourth power terminal.

[0132] (Composition 6) A voltage detection circuit according to any one of configurations 1 to 5, comprising a clamp element that limits the voltage fluctuation of the first node to a predetermined voltage range from the third power supply voltage when the voltage of the first node fluctuates toward the second power supply voltage, wherein the first switch is composed of a transistor of the same conductivity type as the first transistor, the first capacitive element and the second capacitive element are composed of high-voltage elements capable of corresponding to the voltage difference between the first power supply voltage and the second power supply voltage, and the first transistor, the first switch and the second switch are composed of low-voltage elements capable of corresponding to the voltage difference between the third power supply voltage and the second power supply voltage.

[0133] (Composition 7) The voltage detection circuit according to configuration 6, wherein the back gates of the first transistor and the first switch are each connected to the third power supply terminal, and the clamp element is a second-conductivity transistor whose drain is connected to the first node and whose source, gate and back gate are commonly connected to the second power supply terminal.

[0134] (Composition 8) A voltage detection circuit according to any one of configurations 1 to 7, comprising: a second transistor of a second conductivity type whose drain and source are connected to a third node and the second power terminal, and whose gate is connected to the second node; and a current source or third switch connected between the third power terminal and the third node, wherein the detection signal generation circuit receives the voltage of the third node and generates the detection signal based on the voltage of the third node.

[0135] (Composition 9) A voltage detection circuit comprising: first and second voltage detection units, each including the voltage detection circuit described in any one of the above configurations 1 to 8; an OR gate that receives the detection signals generated in each of the first and second voltage detection units and outputs the logical OR result of the two; and a control signal supplied to each of the first and second voltage detection units to control the timing of the preparatory period and the detection period in the first voltage detection unit and the timing of the preparatory period and the detection period in the second voltage detection unit, and to control so that the preparatory periods of each unit do not overlap.

[0136] (Composition 10) A semiconductor device comprising the voltage detection circuit described in any one of the above configurations 1 to 8, and an electrode pad to which the first power supply terminal included in the voltage detection circuit is connected.

[0137] (Composition 11) A display driver for driving a display unit in which display cells are arranged at each intersection of a plurality of data lines and a plurality of scan lines, comprising: a drive unit that generates a plurality of drive voltages based on a video signal and supplies them to the plurality of data lines and sequentially applies scan pulses to the plurality of scan lines; a plurality of power supply voltages supplied from an external source via a pad to operate the drive unit; a voltage detection circuit as described in configuration 1 or 9 that receives a power supply voltage from any one of the plurality of power supply voltages and detects voltage fluctuations of an abnormal level of the one power supply voltage; and a control unit that controls the operation of the drive unit and the voltage detection circuit, wherein the voltage detection circuit receives a switch control signal supplied from the control unit and controls the on / off status of the first switch and the second switch during the preparatory period and the detection period for each of the plurality of data periods in each frame of the video signal, and the control unit controls the drive unit to stop the data writing operation of the display unit from the time of output of the detection signal indicating an abnormality from the voltage detection circuit in one frame of the video signal until the start of the next frame of the first frame, and to start the data writing operation of the display unit from the next frame. [Explanation of Symbols]

[0138] 11, 21 transistors SW1-SW13, SW21, SW22 switches 91, 91_1, 91A Detection signal generation circuit Voltage detection circuit 100_1~100_4, 200_1 109, 109_1, 109_2, 109A Control Unit C11, C12, C21, C22 Capacitive elements

Claims

1. A first power supply terminal that receives a first power supply voltage, A second power supply terminal that receives a second power supply voltage, A third power terminal that receives a third power supply voltage, A first capacitive element having one end connected to the first power terminal and the other end connected to the first node, A second capacitive element, one end of which is connected to the first node and the other end of which is connected to the second power terminal, A first transistor of a first conductivity type, having its gate connected to the first node and its source and drain connected to the third power terminal and the second node, respectively, At predetermined intervals including a preparatory period and a detection period following the preparatory period, a first switch is configured to be ON during the preparatory period, supplying the third power supply voltage to the first node, and to be OFF during the detection period. A second switch that is ON during the aforementioned preparatory period and supplies the second power supply voltage to the second node, and is OFF during the aforementioned detection period, A voltage detection circuit including a detection signal generation circuit that outputs a detection signal indicating that an abnormality has occurred in the first power supply voltage when the voltage of the second node changes by a predetermined value from the state of the second power supply voltage toward the third power supply voltage. (Comment: The limitation on electromagnetic noise detection is referred to claim 3 of the dependent claim.)

2. The voltage detection circuit according to claim 1, wherein the first power supply voltage and the third power supply voltage have the same voltage polarity with respect to the second power supply voltage, and the voltage difference between the first power supply voltage and the second power supply voltage is greater than or equal to the voltage difference between the first power supply voltage and the third power supply voltage. (Comment: The wording has been changed to also cover Figure 7A.)

3. The voltage detection circuit according to claim 2, wherein the detection signal generation circuit detects instantaneous fluctuations in the first power supply voltage due to electromagnetic noise and detects fluctuations in a direction that reduces the voltage difference between the first power supply voltage and the second power supply voltage.

4. The first capacitive element, the second capacitive element, the first transistor, and the first switch are composed of high-voltage elements capable of handling the voltage difference between the first power supply voltage and the second power supply voltage. The voltage detection circuit according to claim 2, wherein when the voltage difference between the first power supply voltage and the second power supply voltage is greater than the voltage difference between the third power supply voltage and the second power supply voltage, the second switch is configured with a low-voltage element capable of handling the voltage difference between the third power supply voltage and the second power supply voltage.

5. It includes a fourth power terminal that receives a fourth power voltage having a voltage value between the first power voltage and the third power voltage, The first switch is composed of a transistor of the same conductivity type as the first transistor. The voltage detection circuit according to claim 4, wherein the back gates of the first transistor and the first switch are connected to the first power supply terminal or the fourth power supply terminal.

6. When the voltage of the first node fluctuates toward the second power supply voltage, the system includes a clamping element that limits the voltage fluctuation of the first node to a predetermined voltage range from the third power supply voltage. The first switch is composed of a transistor of the same conductivity type as the first transistor. The first capacitive element and the second capacitive element are composed of high-voltage elements capable of handling the voltage difference between the first power supply voltage and the second power supply voltage. The voltage detection circuit according to claim 2, wherein the first transistor, the first switch, and the second switch are composed of low-voltage elements capable of responding to the voltage difference between the third power supply voltage and the second power supply voltage. (Comment: This also includes cases of thin-film semiconductor circuits that do not have a back gate.)

7. The back gates of the first transistor and the first switch are each connected to the third power supply terminal. The voltage detection circuit according to claim 6, wherein the clamping element is a second-conductivity transistor whose drain is connected to the first node and whose source, gate, and back gate are commonly connected to the second power supply terminal.

8. A second transistor of second conductivity type, whose drain and source are connected to the third node and the second power terminal, respectively, and whose gate is connected to the second node, The system includes a current source or a third switch connected between the third power terminal and the third node, The voltage detection circuit according to claim 1, wherein the detection signal generation circuit receives the voltage of the third node and generates the detection signal based on the voltage of the third node.

9. Each of the first and second voltage detection units includes the voltage detection circuit described in claim 1, An OR gate that receives the detection signals generated by each of the first and second voltage detection units and outputs the logical OR result of the two, A voltage detection circuit having control signals supplied to the first and second voltage detection units respectively, which control the timing of the preparatory period and the detection period in the first voltage detection unit and the timing of the preparatory period and the detection period in the second voltage detection unit, and which control such that the preparatory periods of each unit do not overlap.

10. The voltage detection circuit according to claim 1, A semiconductor device including an electrode pad to which the first power supply terminal included in the voltage detection circuit is connected.

11. A display driver for driving a display unit in which display cells are arranged at each intersection of multiple data lines and multiple scan lines, A drive unit that generates multiple drive voltages based on a video signal and supplies them to the multiple data lines, and sequentially applies scan pulses to the multiple scan lines, A plurality of power supply voltages supplied from an external source via a pad to operate the drive unit, and a voltage detection circuit according to claim 1 or 9 that receives a power supply voltage from any one of the plurality of power supply voltages and detects a voltage fluctuation of an abnormal level of the one power supply voltage, It includes a control unit that controls the operation of the drive unit and the voltage detection circuit, The voltage detection circuit receives a switch control signal supplied from the control unit and, for each of the multiple data periods within each frame of the video signal, performs on / off control of the first switch and the second switch during the preparatory period and the detection period. The control unit controls the drive unit to stop the data writing operation of the display unit from the time the voltage detection circuit outputs the detection signal indicating an abnormality within one frame of the video signal until the start of the next frame, and to start the data writing operation of the display unit from the next frame.

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