Pixel circuit and display device including pixel circuit

Abstract

To provide a display device capable of suppressing the loss of holding potential. [Solution] The pixel circuit includes a first transistor electrically connected between an image data signal line to which a data potential is supplied and a second node, the switching of which is controlled using a first control signal; a second transistor electrically connected between a third node and a fourth node, having a gate electrode electrically connected to the second node; a sixth transistor electrically connected between a reference potential line to which a reference potential is supplied and a first node, the switching of which is controlled using a second control signal; a first capacitive element electrically connected between the first node and the third node; a second capacitive element electrically connected between the first node and the second node; and a light-emitting element.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a pixel circuit and a display device including the pixel circuit. [Background technology]

[0002] In recent years, display devices containing light-emitting elements have been implemented in televisions, smartphones, and other devices, and are becoming widespread. For example, a display device includes multiple pixels and a control circuit for driving the multiple pixels. Each of the multiple pixels includes multiple transistors, capacitive elements, and light-emitting elements. The light-emitting elements are elements that emit light in a self-emissive manner (self-emissive light-emitting elements), such as light-emitting diodes (LEDs), tiny light-emitting diodes (micro-LEDs), or organic electroluminescence (EL) elements. The control circuit in the display device can supply a potential to each of the multiple pixels and allow a current corresponding to the supplied potential to flow through the light-emitting elements contained in each of the multiple pixels. Each light-emitting element emits light with a brightness corresponding to the current flowing through it, and the pixels containing the light-emitting elements can display an image with gradations corresponding to that brightness.

[0003] For example, Patent Document 1 discloses a display device including a light-emitting element. The pixels in the display device described in Patent Document 1 include nine transistors (T1 to T9), two series-connected capacitive elements (Chold, Cst), and one light-emitting element (LED). Furthermore, the driving method for the display device described in Patent Document 1 includes electrically connecting the gate electrode (Gate) of transistor T1 and one electrode-side node (D-node) of the capacitive element Chold with transistor T3 during the initialization period and the light-emitting period. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent No. 11972726 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] For example, during the light-emitting period, when transistor T3 electrically connects the gate electrode Gate of transistor T1 to one electrode-side node (D-node) of the capacitive element Chold, the charge held in the capacitive elements Chold and Cst is redistributed to the gate electrode Gate of transistor T1, the capacitive elements Chold and Cst. For example, when this charge is redistributed, the potential difference between the potential applied to the gate electrode Gate of transistor T1 and the potential applied to the source electrode Source of transistor T1 decreases (i.e., the holding voltage decreases, or the holding voltage is lost), and the light-emitting element LED may not emit light at the predetermined brightness. Furthermore, in recent years, in order to accommodate the increasing resolution and larger screen size of display devices including light-emitting elements, there has been a demand for higher resolution pixels with a reduced number of elements within each pixel.

[0006] In view of these challenges, one embodiment of the present invention aims to provide a pixel circuit capable of suppressing the loss of holding voltage. Another embodiment of the present invention aims to provide a display device including a pixel circuit capable of suppressing the loss of holding voltage. Another embodiment of the present invention aims to provide a pixel circuit capable of high resolution. Another embodiment of the present invention aims to provide a display device including a pixel circuit capable of high resolution. [Means for solving the problem]

[0007] A pixel circuit according to one embodiment of the present invention includes a first transistor electrically connected between an image data signal line to which a data potential is supplied and a second node, the switching of which is controlled using a first control signal; a second transistor electrically connected between a third node and a fourth node, having a gate electrode electrically connected to the second node; a sixth transistor electrically connected between a reference potential line to which a reference potential is supplied and a first node, the switching of which is controlled using a second control signal; a first capacitive element electrically connected between the first node and the third node; a second capacitive element electrically connected between the first node and the second node; and a light-emitting element.

[0008] A display device according to one embodiment of the present invention includes a plurality of pixels, each including a pixel circuit, and the plurality of pixels are arranged in a matrix in a first direction and a second direction intersecting the first direction. The pixel circuit includes a first transistor electrically connected between a second node and an image data signal line to which a data potential is supplied and whose switching is controlled using a first control signal; a second transistor electrically connected between a third node and a fourth node, having a gate electrode electrically connected to the second node; a sixth transistor electrically connected between a first node and a reference potential line to which a reference potential is supplied and whose switching is controlled using a second control signal; a first capacitive element electrically connected between the first node and the third node; a second capacitive element electrically connected between the first node and the second node; and a light-emitting element. The light-emitting element is electrically connected between a third node and a reference potential line to which a reference potential is supplied. The pixel circuit further includes a fifth transistor electrically connected between a drive potential line, to which a drive potential higher than the reference potential is supplied and whose switching is controlled using a third control signal, and the fourth node; a third transistor electrically connected between a reset potential line, to which a reset potential is supplied and whose switching is controlled using a fourth control signal, and the second node; and a fourth transistor electrically connected between an initialization potential line, to which an initialization potential is supplied and whose switching is controlled using a fifth control signal, and the third node.

[0009] A pixel circuit according to one embodiment of the present invention includes a first transistor electrically connected between an image data signal line to which a data potential is supplied and a second node, the switching of which is controlled using a first control signal; a second transistor electrically connected between a third node and a fourth node, having a gate electrode electrically connected to the second node; a sixth transistor electrically connected between a reference potential line to which a reference potential is supplied and a first node, the switching of which is controlled using a second control signal; a first capacitive element electrically connected between the first node and the third node; a second capacitive element electrically connected between the first node and the second node; and a light-emitting element. The pixel circuit further includes a fifth transistor electrically connected between a fourth node and a fifth node, the switching of which is controlled using a third control signal; and the light-emitting element is electrically connected between a reference potential line to which a reference potential is supplied and the fifth node.

[0010] A display device according to one embodiment of the present invention includes a plurality of pixels, each including a pixel circuit, wherein the plurality of pixels are arranged in a matrix in a first direction and a second direction intersecting the first direction. The pixel circuit includes a first transistor electrically connected between a second node and an image data signal line to which a data potential is supplied, and whose switching is controlled using a first control signal; a second transistor electrically connected between a third node and a fourth node, having a gate electrode electrically connected to the second node; a sixth transistor electrically connected between a first node and a reference potential line to which a reference potential is supplied, and whose switching is controlled using a second control signal; a first capacitive element electrically connected between the first node and the third node; a second capacitive element electrically connected between the first node and the second node; and a light-emitting element. The pixel circuit further includes a fifth transistor electrically connected between a fourth node and a fifth node, whose switching is controlled using a third control signal, and whose switching is controlled using a fourth control signal; and the light-emitting element is electrically connected between a fifth node and a reference potential line to which a reference potential is supplied. The pixel circuit further includes a third transistor electrically connected between a reset potential line to which a reset potential is supplied and the second node, the switching of which is controlled using a fourth control signal; a fourth transistor electrically connected between a constant potential line to which a constant potential is supplied and the fifth node, the switching of which is controlled using a second control signal; and a seventh transistor electrically connected between a drive potential line to which a drive potential higher than the reference potential is supplied and the third node, the switching of which is controlled using a fifth control signal. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic diagram showing the configuration of a display device according to the first embodiment of the present invention. [Figure 2] This is a schematic diagram showing the input signals to the pixel circuit according to the first embodiment of the present invention. [Figure 3] This is a circuit diagram showing the configuration of a pixel circuit according to one embodiment of the present invention. [Figure 4]This is a timing chart of a display device according to the first embodiment of the present invention. [Figure 5] This is a timing chart of a display device according to the first embodiment of the present invention. [Figure 6] This is a timing chart of a display device according to the first embodiment of the present invention. [Figure 7] There is a timing chart of a display device according to the first embodiment of the present invention. [Figure 8] This is a timing chart of a display device according to the first embodiment of the present invention. [Figure 9] This is a layout diagram of pixels according to the first embodiment of the present invention. [Figure 10] This is a layout diagram of pixels according to the first embodiment of the present invention. [Figure 11] This is an end view showing an end face cut along A1 - A2 in the layout shown in FIG. 9. [Figure 12] This is an end view showing an end face cut along B1 - B2 in the layout shown in FIG. 9. [Figure 13] This is an end view showing a modified example of an end face cut along A1 - A2 in the layout shown in FIG. 9. [Figure 14] This is a sequence diagram showing a manufacturing method of a display device according to the first embodiment of the present invention. [Figure 15] This is a layout diagram of pixels according to the first embodiment of the present invention. [Figure 16] This is a layout diagram of pixels according to the first embodiment of the present invention. [Figure 17] This is a layout diagram of pixels according to the first embodiment of the present invention. [Figure 18] This is a schematic diagram showing the configuration of a display device according to the second embodiment of the present invention. [Figure 19] This is a schematic diagram showing an input signal to a pixel circuit according to the second embodiment of the present invention. [Figure 20] This is a circuit diagram showing the configuration of a pixel circuit according to the second embodiment of the present invention. [Figure 21]This is a timing chart of a display device according to the second embodiment of the present invention. [Figure 22] This is a timing chart of a display device according to the second embodiment of the present invention. [Figure 23] This is a timing chart of a control circuit according to the second embodiment of the present invention. [Figure 24] This is a timing chart of a pixel circuit according to a second embodiment of the present invention. [Modes for carrying out the invention]

[0012] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different forms, and is not limited to the embodiments described below. In addition, the drawings may schematically represent the width, thickness, shape, and configuration of each part compared to the actual embodiments in order to make the explanation clearer, but these are merely examples and do not limit the interpretation of the present invention. The letters "1st" and "2nd" attached to each element are convenient indicators used to distinguish each element and have no further meaning unless otherwise specified.

[0013] Furthermore, in this specification, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A, B, and C, unless otherwise explicitly stated. Moreover, these expressions do not exclude cases where α includes other elements.

[0014] In one embodiment of the present invention, the first direction D1 intersects the second direction D2, and the third direction D3 intersects the first direction D1 and the second direction D2 (the D1D2 plane).

[0015] In the specification of this application, when the terms "identical" and "identical" are used, the terms "identical" and "identical" may include errors within the scope of the design. Furthermore, in one embodiment of the present invention, if errors within the scope of the design are included, the expressions "approximately identical" and "approximately identical" may be used.

[0016] A display device according to one embodiment of the present invention can use LEDs, micro-LEDs, EL elements, etc., as self-emissive light-emitting elements. However, the self-emissive light-emitting elements are not limited to LEDs, micro-LEDs, or EL elements. For example, a display device according to one embodiment of the present invention is a display device that uses an EL element as a self-emissive light-emitting element. For example, a display device that uses an EL element may be referred to as a self-emissive display device, an EL display device, etc.

[0017] [1. First Embodiment] [1-1. Overview of the display device 10] Referring to Figure 1, an overview of the display device 10 according to the first embodiment will be described. Figure 1 is a schematic diagram showing the configuration of the display device 10. The configuration of the display device 10 shown in Figure 1 is an example, and the configuration of the display device 10 is not limited to the configuration shown in Figure 1.

[0018] The display device 10 includes an array substrate 100, a flexible printed circuit board 200 (FPC200), and an IC chip 110. The display device 10 also includes a display area 22 superimposed on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0019] In the display area 22, multiple pixels 180 are arranged in a matrix along a first direction D1 (column direction) and a second direction D2 (row direction) intersecting the first direction D1. A pixel 180 is the smallest unit that constitutes a part of the image displayed in the display area 22. Each of the multiple pixels 180 may correspond to, for example, a sub-pixel R, sub-pixel G, and sub-pixel B. Three sub-pixels may form one pixel. There are no restrictions on the arrangement of the multiple pixels 180, and the arrangement of the multiple pixels 180 may be a delta arrangement, a pentile arrangement, etc. For example, the arrangement of the multiple pixels 180 in the display device 10 is a stripe arrangement.

[0020] Sub-pixels R, G, and B are configured to display images of different colors from each other. For example, each of sub-pixels R, G, and B includes a light-emitting element containing a light-emitting layer that emits red, green, and blue light, respectively. By supplying an arbitrary potential or current to each of the three sub-pixels, the display device 10 can display an image.

[0021] The peripheral area 24 is provided with an IC chip 110 and two control circuits 120. The two control circuits 120 are located on the left and right sides of the display area 22. The IC chip 110 is connected to the terminal section 150 using connection wires 341. Each of the two control circuits 120 is connected to the IC chip 110 using connection wires 342. The peripheral area 24 is sometimes referred to as the frame area. The connection wires 341 may be referred to as connection wires 341 on their own, or as a bundle of multiple connection wires 341. Similarly to connection wires 341, connection wires 342 may be referred to as connection wires 342 on their own, or as a bundle of multiple connection wires 342.

[0022] The terminal area 26 is provided with a terminal section 150 and an FPC 200 electrically connected to the terminal section 150. The terminal area 26 is the area opposite to the area where the display area 22 is provided, along the first direction D1, relative to the peripheral area 24.

[0023] The FPC200 is connected to an external device (not shown) outside the display device 10. The display device 10 is connected to the external device via the FPC200 and the terminal section 150. Control signals and potentials are transmitted from the external device to the display device 10 via the FPC200 and the terminal section 150. The display device 10 uses the received control signals and potentials from the external device to drive each pixel 180 provided on the display device 10. As a result, the display device 10 can display an image in the display area 22.

[0024] The IC chip 110 supplies signals, potentials, etc., to drive each pixel 180 to the two control circuits 120 and each pixel 180 (pixel circuit 181) via the FPC 200, terminal section 150, and connecting wiring 341.

[0025] Each of the IC chip 110 and the two control circuits 120 may be referred to as a control circuit individually, or a group of circuits including part or all of each of the IC chip 110 and the two control circuits 120 may be referred to as a control circuit.

[0026] [1-2. Configuration of IC chip 110] Referring to Figure 1, the outline of the IC chip 110 will be described. The IC chip 110 is located adjacent to the display area 22 along a first direction D1. Image data signal lines 321, 322, and 323 extend from the IC chip 110 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0027] For example, the IC chip 110 includes a plurality of selection circuits (not shown). For example, each of the plurality of selection circuits is a switch controlled based on an ON signal and an OFF signal supplied to the selection signal. The selection circuit is selected by the ON signal supplied to the selection signal and supplies an image data signal SL(m), including the data signal VDATA, to the image data signal line 321 and the pixels 180 electrically connected to the image data signal line 321. For example, the selection signal and the image data signal SL(m) are transmitted as digital signals from an external device to the IC chip 110 via the FPC 200 and the terminal section 150. Also, for example, the data signal VDATA (image data signal SL(m)) is DA-converted by the IC chip 110 into an analog signal including a data potential between potential VSIGL (see Figure 5) and potential VSIGH (see Figure 5). Potential VSIGH is a higher potential than potential VSIGL.

[0028] For example, the ON signal is a signal that includes a potential that conducts the selection circuit (switch), and the OFF signal is a signal that includes a potential that blocks the selection circuit (switch). In the present invention, the ON signal may be a high-level potential (High, HI) and the OFF signal may be a low-level potential (Low, LO), or the ON signal may be a low-level potential (Low, LO) and the OFF signal may be a high-level potential (High, HI). A high-level potential is higher than a low-level potential. In one example of a display device according to one embodiment of this specification, the ON signal is a high-level potential and the OFF signal is a low-level potential.

[0029] [1-3. Configuration of Control Circuit 120] Referring to Figure 1, the control circuit 120 is outlined. Two control circuits 120 are located adjacent to each other on both sides of the display area 22 along a second direction D2. Scan signal lines 330, 331, 332, 333, and 334 extend from the control circuits 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. For example, each scan signal line of the display device 10 shown in Figure 1 is connected to both of the two control circuits 120. Each scan signal line may be connected to one of the two control circuits 120. For example, the nth scan signal line may be electrically connected to the control circuit 120 on the right side of the display area 22 along the second direction D2, and the (n+1)th scan signal line may be electrically connected to the control circuit 120 on the left side of the display area 22 along the second direction D2, where n is a positive integer.

[0030] The control circuit 120 includes a shift register circuit 130 and a scan driver circuit 160. For example, the control circuit 120 is a gate driver and receives control signals including a clock signal, a start pulse, and multiple enable signals, as well as potentials such as the drive potential VDDEL (see Figure 2) and the reference potential VSSEL (see Figure 2). The control circuit 120 can sequentially select scan lines based on the input of control signals and power supply.

[0031] The shift register circuit 130 is electrically connected to the scan driver circuit 160. The shift register circuit 130 includes multiple shift registers (not shown). The shift register circuit 130 is supplied with the above-mentioned multiple control signals via multiple connection wires 342, the drive potential VDDEL is supplied via the drive potential line PVDD (see Figure 2), and the reference potential VSSEL is supplied via the reference potential line PVSS (see Figure 2). Based on the above-mentioned multiple control signals, the shift register circuit 130 generates multiple output signals (not shown) that are shifted at different timings and outputs them sequentially to the scan driver circuit 160.

[0032] The scan driver circuit 160 includes multiple scan drivers (not shown). For example, multiple output signals are supplied to the multiple scan drivers from the shift register circuit 130, and the above-mentioned multiple enable signals are supplied from the IC chip 110 via multiple connection lines 342, the drive potential VDDEL is supplied via the drive potential line PVDD, and the reference potential VSSEL is supplied via the reference potential line PVSS. Based on the multiple output signals and multiple enable signals (not shown), the multiple scan drivers sequentially supply scan signals with different timings (for example, a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), and a fifth scan signal SC5(n)) to each scan signal line, and also drive the pixels 180 (pixel circuit 181) electrically connected to each scan signal line. For example, the third scan signal SC3(n) and the scan signal line 332 to which the third scan signal SC3(n) is supplied are so-called scan signal and scan signal line.

[0033] [1-4. 180-pixel configuration] The overview of the pixel 180 and pixel circuit 181 will be explained with reference to Figures 1 to 3. Figure 2 is a schematic diagram showing the input signals to the pixel circuit 181 included in the pixel 180. Figure 3 is a circuit diagram showing the configuration of the pixel circuit 181. Figures 2 and 3 show the configuration of the pixel circuit 181 of the pixel 180 shown in Figure 1 as an example. The configuration of the pixel 180 and pixel circuit 181 is not limited to the configurations shown in Figures 1 to 3. Configurations identical or similar to those in Figure 1 will be explained as necessary, and explanations of configurations identical or similar to those in Figure 1 may be omitted.

[0034] Pixel circuit 181 is a circuit for driving pixel 180. The pixel circuits of sub-pixels R, G, and B included in pixel 180 are the same as those of pixel circuit 181, but the color of light emitted by the light-emitting OLED differs. In the following explanation, a light-emitting OLED that emits red light will be described as an example.

[0035] As shown in Figure 2, the pixel circuit 181 is supplied with image data signal SL(m), first scan signal SC1(n), second scan signal SC2(n), third scan signal SC3(n), fourth scan signal SC4(n), fifth scan signal SC5(n), reset potential VRES, reference potential VREF, and initialization potential VINI. In addition, the pixel circuit 181 is supplied with drive potential VDDEL and reference potential VSSEL as power supplies to drive the pixel 180. For example, the reset potential VRES, reference potential VREF, initialization potential VINI, drive potential VDDEL, and reference potential VSSEL may be constant potentials, or they may be variable potentials that fluctuate according to the timing of each signal.

[0036] The first scan signal SC1(n) is supplied to scan signal line 330, the second scan signal SC2(n) is supplied to scan signal line 331, the third scan signal SC3(n) is supplied to scan signal line 332, the fourth scan signal SC4(n) is supplied to scan signal line 333, and the fifth scan signal SC5(n) is supplied to scan signal line 334. The first scan signal SC1(n) may be referred to as the second control signal, the second scan signal SC2(n) may be referred to as the fourth control signal, the third scan signal SC3(n) may be referred to as the first control signal, the fourth scan signal SC4(n) may be referred to as the fifth control signal, and the fifth scan signal SC5(n) may be referred to as the third control signal.

[0037] Furthermore, the reset potential VRES is supplied to the reset potential line SVRE, the reference potential VREF is supplied to the reference potential line SVR, the initialization potential VINI is supplied to the initialization potential line SVI, the drive potential VDDEL is supplied to the drive potential line PVDD, and the reference potential VSSEL is supplied to the reference potential line PVSS. For example, each of the reset potential line SVRE, the reference potential line SVR, the initialization potential line SVI, the drive potential line PVDD, and the reference potential line PVSS is electrically connected to a different connection wiring 342. Alternatively, each of the reset potential line SVRE, the reference potential line SVR, the initialization potential line SVI, the drive potential line PVDD, and the reference potential line PVSS may be connected to a different connection wiring 342.

[0038] For example, the reset potential VRES, reference potential VREF, initialization potential VINI, drive potential VDDEL, and reference potential VSSEL may be supplied to the IC chip 110 from an external device via the FPC 200, terminal section 150, and connection wiring 341. Alternatively, for example, the reset potential VRES, reference potential VREF, initialization potential VINI, drive potential VDDEL, and reference potential VSSEL may be generated by the IC chip 110 and supplied from the IC chip 110 to a plurality of pixels 180 (pixel circuits 181) via connection wiring 342, reset potential line SVRE, reference potential line SVR, initialization potential line SVI, drive potential line PVDD, and reference potential line PVSS. Although not shown in the diagram, the reset potential VRES, reference potential VREF, initialization potential VINI, drive potential VDDEL, and reference potential VSSEL may be connected from an external device via the FPC 200, terminal section 150, and connection wiring 341, without going through the IC chip 110 and connection wiring 342, to the reset potential line SVRE, reference potential line SVR, initialization potential line SVI, drive potential line PVDD, and reference potential line PVSS, and may be supplied to multiple pixels 180 (pixel circuit 181). For example, the reset potential VRES, reference potential VREF, initialization potential VINI, and reference potential VSSEL are lower than the drive potential VDDEL.

[0039] As shown in Figure 3, the pixel 180 (pixel circuit 181) includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a capacitive element CV, a capacitive element CD, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (source electrode and drain electrode) consisting of a first electrode and a second electrode. Each of the capacitive element CV, the capacitive element CD, and the light-emitting element OLED has a pair of electrodes consisting of a first electrode and a second electrode. Note that the capacitive element CV may be referred to as the first capacitive element, and the capacitive element CD may be referred to as the second capacitive element.

[0040] For example, the first transistor T1 is a selection transistor. The first transistor T1 has the function of supplying image data signal SL(m) to the second node N2.

[0041] For example, the second transistor T2 is a driving transistor. As will be described in detail later, a threshold voltage (a threshold potential difference Vgs) VTH is acquired between the first node N1 and the first electrode (source) 624 based on the reset potential VRES, and the acquired threshold voltage VTH is applied to the capacitive element CV, thereby performing the acquisition and retention (storage) of the threshold voltage VTH. Furthermore, the second transistor T2 controls the amount of current flowing from the driving potential line PVDD to the light-emitting element OLED based on the gate potential (potential between gate electrode 622 and the first electrode 624) corrected for variations in the threshold voltage VTH and the input image data signal SL(m). In other words, the second transistor T2 has the function of supplying current to the light-emitting element OLED from the driving potential VDDEL according to the display gradation (brightness), thereby causing the light-emitting element OLED to emit light.

[0042] For example, the third transistor T3 has the function of connecting the second node N2 and the reset potential line SVRE, supplying the reset potential VRES to the second node N2, and fixing the potential supplied to the second node N2 to the reset potential VRES. As will be described in detail later, when the potential supplied to the second node N2 is fixed to the reset potential VRES, current flows from the drive potential line PVDD to the fourth node N4 and the third node N3 via the fifth transistor T5, and the capacitive element CV (the first electrode 42 of the capacitive element CV) begins to charge. The charging stops when the potential difference Vgs (the potential difference (Vgs) between the potential supplied to the gate electrode 622 (second node N2) and the potential supplied to the first electrode 624 (third node N3)) reaches the threshold voltage VTH.

[0043] The fourth transistor T4 has the function of supplying the initialization potential VINI to the third node N3 by conducting the initialization potential line SVI to the third node N3, thereby initializing the third node N3.

[0044] The fifth transistor T5 has the function of conducting the drive potential line PVDD and the fourth node N4.

[0045] The sixth transistor T6 conducts the first node N1 and the reference potential line SVR, supplying the reference potential VREF to the first node N1, and has the function of fixing the potential supplied to the first node N1 to the reference potential VREF during the initialization of the third node N3, when the threshold voltage VTH is acquired and held, and when the image data signal SL(m) is written.

[0046] The capacitive element CV has the function of holding (storing) a charge corresponding to the threshold voltage VTH of the second transistor T2. That is, the capacitive element CV has the function of holding (storing) the potential difference between the potential supplied to the first node N1 and the potential supplied to the third node N3, which includes information about the threshold voltage VTH of the second transistor T2. The driving method of the display device 10 includes obtaining the threshold voltage VTH by applying a driving potential VDDEL from the second electrode 626 (drain electrode) side of the second transistor T2 via the driving potential line PVDD.

[0047] The capacitive element CD has the function of holding (storing) the charge corresponding to the data potential (potential above VSIGL (see Figure 5) and below VSIGH (see Figure 5)) contained in the image data signal SL(m) supplied to the second node N2. In other words, the capacitive element CD has the function of holding (storing) the potential difference between the potential supplied to the second node N2 and the potential supplied to the first node N1, which includes the data potential information of the image data signal SL(m).

[0048] The light-emitting OLED has diode characteristics and functions to emit light based on the current flowing through it. The current flowing through the light-emitting OLED is the drain current (current Ion) of the second transistor T2.

[0049] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scan signal line 332. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, the second electrode 636 of the third transistor T3, and the second electrode 54 of the capacitive element CD. The switching of the first transistor T1 is controlled using the third scan signal SC3(n). In other words, the conduction state (on state) and non-conduction state (off state) of the first transistor T1 are controlled by the third scan signal SC3(n). When the signal supplied to the third scan signal SC3(n) is LO, the first transistor T1 is in a non-conduction state. When the signal supplied to the third scan signal SC3(n) is HI, the first transistor T1 becomes conductive.

[0050] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The first electrode 624 is electrically connected to the third node N3, the first electrode 42 of the capacitive element CV, and the second electrode 34 of the light-emitting element OLED. The second electrode 626 is electrically connected to the fourth node N4 and the first electrode 654 of the fifth transistor T5. The threshold voltage of the second transistor T2 is the threshold voltage VTH. The second transistor T2 controls the amount of current flowing to the light-emitting element OLED according to the potential difference Vgs and the potential difference Vds between the potential supplied to the second electrode 626 (fourth node N4) and the potential supplied to the first electrode 624 (third node N3). For example, if the potential difference Vgs is less than the threshold voltage VTH, the second transistor T2 is in a non-conducting state. In this case, no current flows to the light-emitting element OLED, and the pixel 180 displays black. For example, when the potential difference Vgs is greater than or equal to the threshold voltage VTH and the potential difference Vds is greater than 0V, the second transistor T2 becomes conductive, and the current flowing through the light-emitting element OLED is controlled according to the magnitude of the display grayscale of the potential difference Vgs, causing the light-emitting element OLED to emit light at a brightness based on the display grayscale.

[0051] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the scan signal line 331. The first electrode 634 is electrically connected to the reset potential line SVRE. The switching of the third transistor T3 is controlled using the second scan signal SC2(n). In other words, the conduction state (on state) and non-conduction state (off state) of the third transistor T3 are controlled by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the third transistor T3 is in a non-conducting state, and when the signal supplied to the second scan signal SC2(n) is HI, the third transistor T3 is in a conduction state.

[0052] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the scan signal line 333. The first electrode 644 is electrically connected to the initialization potential line SVI. The switching of the fourth transistor T4 is controlled using the fourth scan signal SC4(n). In other words, the conduction state (on state) and non-conduction state (off state) of the fourth transistor T4 are controlled by the fourth scan signal SC4(n). When the signal supplied to the fourth scan signal SC4(n) is LO, the fourth transistor T4 is in a non-conducting state, and when the signal supplied to the fourth scan signal SC4(n) is HI, the fourth transistor T4 is in a conduction state.

[0053] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the scan signal line 334. The second electrode 656 is electrically connected to the drive potential line PVDD. The switching of the fifth transistor T5 is controlled using the fifth scan signal SC5(n). In other words, the conduction state (on state) and non-conduction state (off state) of the fifth transistor T5 are controlled by the fifth scan signal SC5(n). When the signal supplied to the fifth scan signal SC5(n) is LO, the fifth transistor T5 is in a non-conducting state, and when the signal supplied to the fifth scan signal SC5(n) is HI, the fifth transistor T5 is in a conduction state.

[0054] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the scan signal line 330. The first electrode 664 is electrically connected to the reference potential line SVR. The second electrode 666 is electrically connected to the first node N1, the second electrode 44 of the capacitance element CV, and the first electrode 52 of the capacitance element CD. The switching of the sixth transistor T6 is controlled using the first scan signal SC1(n). In other words, the conduction state (on state) and non-conduction state (off state) of the sixth transistor T6 are controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the sixth transistor T6 is in a non-conducting state, and when the signal supplied to the first scan signal SC1(n) is HI, the sixth transistor T6 is in a conduction state.

[0055] The capacitive element CV includes a first electrode 42 and a second electrode 44.

[0056] The capacitive element CD includes a first electrode 52 and a second electrode 54.

[0057] The first electrode 32 of the light-emitting OLED is the cathode, and the second electrode 34 of the light-emitting OLED is the anode. The first electrode 32 is electrically connected to the reference potential line PVSS.

[0058] For example, the conduction state of a transistor in the display device 10 is defined as the source electrode and drain electrode of the transistor conducting, indicating that the transistor is ON, while the non-conducting state of a transistor in the display device 10 is defined as the source electrode and drain electrode of the transistor not conducting, indicating that the transistor is OFF. In each transistor, the source electrode and drain electrode may be swapped depending on the potential supplied to each electrode or the potential. Furthermore, it is easily understood by those skilled in the art that even when a transistor is OFF, a small current may flow, such as leakage current.

[0059] Each transistor shown in Figure 3 is an n-channel field-effect transistor. Each transistor includes a channel region. For example, the channel region is the region through which the current flows between the first electrode (for example, sometimes referred to as the drain or drain electrode) and the second electrode (for example, sometimes referred to as the source or source electrode) of each transistor. As will be described in detail later, for example, the channel region includes a group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor properties. Also, for example, each transistor in the display device 10 is formed using a thin-film transistor (TFT). Depending on the application and specifications, the transistor configuration, retention capacitance connection, power supply potential, etc., of the display device 10 may be appropriately adapted.

[0060] [1-5. Method for driving the display device 10] The driving method of the display device 10 will be explained with reference to Figures 4 to 8. Figures 4 to 8 are schematic diagrams showing the timing chart of the display device 10. Configurations identical or similar to those in Figures 1 to 3 will be explained as necessary, and explanations of identical or similar configurations may be omitted.

[0061] In each embodiment, the horizontal axis of the timing chart represents time. In addition, in the image data signal SL(m) including the data signal VDATA in each embodiment, as an example, the data signal VDATA supplied to the selected pixel (pixel circuit) is shown with a diagonal line as a data potential between VSIGL and VSIGH, while the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit) is omitted and shown with a solid line. In reality, in each embodiment, the image data signal SL(m) including the data signal VDATA also continuously or intermittently supplies the potential of the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit).

[0062] For example, the frequency used to drive the display device 10 is 60Hz, and one frame (1FRAME) is driven at 60Hz. For example, Figure 4 shows the current frame (KthFRAME), a portion of the frame immediately preceding it (K-1stFRAME), and a portion of the frame immediately following it (K+1stFRAME). Figures 5 to 8 show the emission period PEM of the frame immediately preceding it (K-1stFRAME), the period PIN, period PVH, period PWR, and period PEM of the current frame (KthFRAME), and the period PIN, period PVH, period PWR, and period PEM of the frame immediately following it. Figures 5 to 8 also show one horizontal period (horizontal period HRP) for a single pixel 180 (pixel circuit 181).

[0063] First, with reference to Figure 4, an overview of the driving method of the display device 10 will be explained. As shown in Figure 4, the driving method of the display device 10 includes at least an initialization period PIN (period PIN), a threshold voltage acquisition and holding period PVH (period PVH), and a write period PWR (period PWR) within one frame. In the pixel 180 (pixel circuit 181) included in the display device 10, period PWR is executed after period PVH. Furthermore, after the light emission period PEM of the frame immediately preceding the current frame, the period PIN, period PVH, and period PWR of the current frame are executed, and after the light emission period PEM of the current frame, the period PIN, period PVH, and period PWR of the frame immediately following the current frame are executed.

[0064] For example, period PIN is the period for initializing the first node N1, the second node N2, and the third node N3. Period PVH is the period during which the threshold voltage of the second transistor T2 is obtained by performing an operation to make the potential difference Vgs of the second transistor T2 equal to the threshold voltage, and the capacitive element CV holds a charge equivalent to the threshold voltage. Period PWR is the period during which the data signal VDATA is written to the pixel 180 (pixel circuit 181). That is, period PWR is the period during which the data potential is supplied to the second node N2, and the capacitive element CD holds a charge equivalent to the data potential. Furthermore, the light emission period PEM is the period during which the pixel 180 emits light based on the written data potential and the obtained threshold voltage of the second transistor T2 (threshold voltage correction).

[0065] Next, with reference to Figures 4 to 8, a specific method for driving the pixels 180 (pixel circuit 181) of the display device 10 will be explained.

[0066] Pixel 180 (pixel circuit 181) receives the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), the image data signal SL(m) including the data signal VDATA, the reset potential VRES, the initialization potential VINI, and the reference potential VREF. For example, pixel 180 (pixel circuit 181) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n). The image data signal SL(m), the reset potential VRES, the initialization potential VINI, and the reference potential VREF are input to the selected pixel 180 (pixel circuit 181) according to the timing of each signal. The same operation is performed for all pixels 180 (pixel circuits 181), and based on the image data signal SL(m) input to all pixels 180 (pixel circuits 181), the image of the current frame corresponding to 1 FRAME is displayed in the display area 22 of the display device 10.

[0067] For example, the potential supplied to each signal and each node during each period of each frame in the timing charts shown in Figures 4 to 8 is shown in Table 1.

[0068] [Table 1]

[0069] For example, as shown in Table 1, the threshold voltage VTH of the second transistor T2 is 1V, the reference potential VSSEL is 0V, the drive potential VDDEL is 8V, the potential VH(HI) is 10V, and the potential VL(LO) is -2V. The reset potential VRES is 1.4V, the reference potential VREF is 2.6V, and the initialization potential VINI is -0.6V. The potential VSIGL is 0.4V, and pixel 180 supplied with the potential VSIGL will not emit light and will appear black. Also, for example, the potential VSIGH is 4.4V, and pixel 180 supplied with the potential VSIGH will emit light and produce a white color. The reference potential VREF differs from the reset potential VRES, and both the reference potential VREF and the reset potential VRES are higher than the reference potential VSSEL and lower than the drive potential VDDEL. The initialization potential VINI is lower than the reference potential VSSEL. Note that the potentials shown in Table 1 are examples, and the potentials related to the display device 10 are not limited to those shown in Table 1. Each potential related to the display device 10 can be appropriately selected according to the application and specifications of the display device 10.

[0070] [1-5-1. First example of a method for driving the display device 10] Referring to Figure 5 and Table 1, a first example of a driving method for the display device 10 will be described. The driving method shown in the first example includes the following: a pixel 180 (pixel circuit 181) displays a white image based on the potential VSIGH of the data signal VDATA in the frame immediately preceding the current frame (KthFRAME), and then the pixel 180 (pixel circuit 181) displays a black image based on the potential VSIGL of the data signal VDATA in the KthFRAME. In other words, the driving method shown in the first example includes displaying images of different colors in consecutive frames.

[0071] For each period, an image data signal SL(m) containing the data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is analog data (analog potential) containing potentials between VSIGL and VSIGH. For example, in the period PWR, a selection signal (not shown in the figure) is used to select a potential between VSIGL and VSIGH, and this is supplied to the image data signal SL(m). For example, in periods other than the PWR period, the data signal VDATA is supplied to a potential other than the selected pixel 180 (pixel circuit 181).

[0072] The light emission period PEM of the K-1stFRAME is the period during which pixel 180 (pixel circuit 181) emits light in accordance with the potential difference Vgs of the second transistor T2. For example, pixel 180 (pixel circuit 181) emits red light, and three pixels using a red-emitting pixel 180, a blue-emitting pixel 180, and a green-emitting pixel 180 emit white light.

[0073] For example, during the emission period PEM of the K-1stFRAME, the potential of the data signal VDATA is supplied to all pixels except the selected pixel 180 (pixel circuit 181). The first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are supplied with LO, and the fifth scan signal SC5(n) is supplied with HI. The first transistor T1, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are in the off state, and the fifth transistor T5 is in the on state. Also, for example, at this time, the potential held at the first node N1 is potential Vb, the potential held at the second node N2 is potential Vc, and the potential held at the third node N3 is potential Va. Potential Vb is smaller than potential Vc. Potential Vc is lower than the drive potential VDDEL. The potential difference Vgs (potential Vc - potential Va) is greater than the threshold voltage VTH, and the second transistor T2 is in the ON state. Therefore, the second transistor T2 can supply a current Ion based on the potential difference Vgs and potential difference Vds corresponding to the potential VSIGH input during the horizontal period HRP of the K-1st FRAME from the drive potential line PVDD to the light-emitting element OLED and the reference potential line PVSS. As a result, the light-emitting element OLED emits light. For example, pixel 180 (pixel circuit 181) emits red light, and three pixels using a red-emitting pixel 180, a blue-emitting pixel 180, and a green-emitting pixel 180 emit white light. The potential held at the first node N1 is potential Vb due to capacitive coupling by the capacitive elements CV and CD.

[0074] During the period between the emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, following the emission period PEM of the K-1stFRAME, the potential of the data signal VDATA supplied to all pixels except the selected pixel 180 (pixel circuit 181) is supplied. Initially, the fifth scan signal SC5(n) changes from a state where HI is supplied to a state where LO is supplied. When the fifth scan signal SC5(n) is supplied with LO, the first scan signal SC1(n) changes from a state where LO is supplied to a state where HI is supplied. The second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are all supplied with LO.

[0075] Furthermore, during the KthFRAME period PIN, the potential of the data signal VDATA is supplied to all pixels except the selected pixel 180 (pixel circuit 181) for the image data signal SL(m) (data signal VDATA). When the first scan signal SC1(n) is supplied with HI, the fourth scan signal SC4(n) changes from a state where LO is supplied to a state where HI is supplied. The fourth scan signal SC4(n) maintains a state where HI is supplied, and then changes from a state where HI is supplied to a state where LO is supplied. Also, when the fourth scan signal SC4(n) is supplied with LO, the second scan signal SC2(n) changes from a state where LO is supplied to a state where HI is supplied. The third scan signal SC3(n) and the fifth scan signal SC5(n) maintain a state where LO is supplied, and the first scan signal SC1(n) maintains a state where HI is supplied.

[0076] As a result, during the period between the light emission period PEM of K-1stFRAME and the period PIN of KthFRAME, the fifth transistor switches from the ON state to the OFF state during the period PIN of KthFRAME, and the current Ion stops flowing from the drive potential line PVDD to the light-emitting element OLED and the reference potential line PVSS.

[0077] Furthermore, when the sixth transistor T6 switches from the off state to the on state, the first node N1 becomes conductive with the reference potential line SVR, and the potential supplied to the first node N1 decreases from potential Vb towards the reference potential VREF (potential Vd), becoming potential VREF (potential Vd). At this time, the first transistor T1 and the third transistor T3 are in the off state, and the second node N2 is in a floating state. Therefore, as the potential supplied to the first node N1 decreases from potential Vb to potential Vd, the potential supplied to the second node N2 decreases from potential Vc towards potential Ve, becoming potential Ve. Note that the potential difference between potential Vb and potential Vd is approximately the same as the potential difference between potential Vc and potential Ve.

[0078] Furthermore, the fourth transistor T4 switches from the off state to the on state, and the third node N3 conducts to the initialization potential line SVI, supplying the third node N3 with the initialization potential VINI (potential Vf, -0.6V). For example, the threshold voltage VTHEL of the light-emitting element OLED is 0.7V, and the potential Vf supplied to the third node N3 is smaller than the threshold voltage VTHEL, so the light emission of the light-emitting element OLED stops. Even though the potential supplied to the third node N3 becomes potential Vf, the sixth transistor T6 remains on, so the potential supplied to the first node N1 remains at potential Vd. Also, since the first transistor T1 and the third transistor T3 remain off, the potential supplied to the second node N2 remains at potential Ve. At this time, the potential difference Vgs is the potential difference between potential Ve and potential Vf, but since the potential difference between potential Ve and potential Vf is greater than the threshold voltage VTH, the second transistor T2 remains on. However, since the fifth scan signal SC5(n) remains supplied with LO and the fifth transistor T5 is in the off state, no drain current (current Ion) flows from the drive potential VDDEL to the second transistor T2.

[0079] Furthermore, when LO is supplied to the fourth scan signal SC4(n), the fourth transistor T4 turns from the ON state to the OFF state, and the initialization potential line VINI and the third node N3 are disconnected. Also, when LO is supplied to the fourth scan signal SC4(n) and HI is supplied to the second scan signal SC2(n), the third transistor T3 turns from the OFF state to the ON state, the second node N2 conducts to the reset potential line SVRE, and the potential supplied to the second node N2 drops from potential Ve towards the reset potential VRES (potential Vg, for example, 1.4V) to become potential Vg. At this time, the potential difference Vgs is the potential difference between potential Vg and potential Vf, but since the potential difference between potential Vg (reset potential VRES, 1.4V) and potential Vf (-0.6V) (2V) is greater than the threshold voltage VTH (1V), the second transistor T2 is in the ON state.

[0080] As described above, during the period PIN, the first node N1 is initialized by the reference potential VREF, the second node N2 is initialized by the reset potential VRES, and the third node N3 is initialized by the initialization potential VINI.

[0081] During period PVH, following period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the same potential as the data signal VDATA supplied to all pixels except the selected pixel 180 (pixel circuit 181). The fifth scan signal SC5(n) changes from a LO state to a HI state, and the fifth transistor T5 changes from an off state to an on state. Other scan signals and other transistors remain in the same state as during period PIN.

[0082] As a result, during period PVH, the first node N1 maintains a potential Vd, and the second node N2 maintains a potential Vg. Also, for example, at the beginning of period PVH, the potential difference Vgs is 2V, and the second transistor T2 is ON. Because the fifth transistor T5 and the second transistor T2 are ON, the fourth node N4 and the third node N3 conduct, and current Ion flows from the drive potential line PVDD to the fourth node N4 and the third node N3. Because the fourth transistor is OFF, the potential supplied to the third node N3 is already released and gradually rises from the potential Vf. That is, the third node N3 is charged. When the potential difference Vgs (the potential difference between the potential supplied to the second node N2 and the potential supplied to the third node N3) reaches the threshold voltage VTH, the second transistor T2 turns OFF. At this time, the first node N1 maintains a potential Vd, and the second node N2 maintains a potential Vg (reset potential VRES, 1.4V). Therefore, for example, if the threshold voltage VTH is 1V (design value), the potential supplied to the third node N3 will be 0.4V (1.4V - 1V). At this time, the potential difference between the potential Vg supplied to the second node N2 (the second electrode 54 of the capacitive element CD) and the 0.4V supplied to the third node N3 (the first electrode 42 of the capacitive element CV) is the threshold voltage VTH, with the potential Vg (reset potential VRES, 1.4V) supplied to the second node N2 as the reference (potential of the third node N3 = VRES - VTH). In reality, the threshold voltage VTH varies during manufacturing, but the driving method of the display device 10 includes ensuring that the potential supplied to each node becomes a potential corresponding to the threshold voltage VTH which varies during manufacturing, through operation during period PVH. Therefore, the driving method for the display device 10 includes acquiring a threshold voltage VTH that varies during manufacturing and applying a correction using the acquired threshold voltage VTH. As a result, the driving method for the display device 10 can achieve correction of the threshold voltage VTH by operating during the period PVH.

[0083] As described above, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0084] During the period between period PVH and period PWR, following period PVH, the potential of the data signal VDATA is supplied to all but the selected pixel 180 (pixel circuit 181). Initially, the fifth scan signal SC5(n) changes from a HI state to a LO state. When the fifth scan signal SC5(n) is supplied with LO, the second scan signal SC2(n) changes from a HI state to a LO state. The first scan signal SC1(n) is supplied with HI, and the third scan signal SC3(n) and the fourth scan signal SC4(n) are supplied with LO. The fifth transistor T5 and the third transistor T3 change from an ON state to an OFF state. The other transistors are in the same state as during period PVH. The potential supplied to the first node N1 remains at potential Vd, the potential supplied to the second node N2 remains at potential Vg, and the potential supplied to the third node N3 remains at potential Vh, with the potential difference Vgs being potential Vg - potential vh (0.4V). The second transistor T2 remains in the off state.

[0085] During the period PWR, which follows the period between period PVH and period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a potential VSIGL (0.4V). The third scan signal SC3(n) changes from a state where LO is supplied to a state where HI is supplied, and the first transistor T1 changes from the off state to the on state. Other control signals and transistors remain in the same state as during period PVH. The potential supplied to the first node N1 remains at potential Vd, and the potential supplied to the third node N3 remains at potential Vh. As the first transistor T1 changes from the off state to the on state, the second node N2 conducts to the image data signal line 321, and the potential supplied to the second node N2 gradually decreases from potential Vg to potential Vh (potential VSIGL, 0.4V) until it reaches potential Vh. At this time, the capacitive element CD maintains the potential difference (-2.2V relative to the potential supplied to the first node N1) by holding a charge equivalent to the potential difference between Vd (reference potential VREF, 2.6V) supplied to the first node N1 and the potential Vh (0.4V) supplied to the second node N2. Similarly, the capacitive element CV maintains the potential difference (2.2V relative to the potential supplied to the third node N3) by holding a charge equivalent to the potential difference between Vd (reference potential VREF, 2.6V) supplied to the first node N1 and the potential Vh (0.4V) supplied to the third node N3. The sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (-2.2V + 2.2V) is 0V, that is, the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state.

[0086] As described above, during the PWR period, the data signal VDATA is written to pixel 180 (pixel circuit 181). In addition, the capacitive element CD maintains (holds) the data potential of the data signal VDATA.

[0087] During the period following the PWR, the third scan signal SC3(n) changes from a HI state to a LO state. When the third scan signal SC3(n) is supplied with LO, the first scan signal SC1(n) changes from a HI state to a LO state. The first transistor T1 and the sixth transistor T6 change from the ON state to the OFF state. The other scan signals and other transistors remain in the same state as during the PWR. The potential supplied to the first node N1, which is capacitively coupled by capacitive elements CV and CD, maintains potential Vd, while the potential supplied to the second node N2 and the potential supplied to the third node N3 maintains potential Vh. That is, the potential difference Vgs is maintained at 0V, and the second transistor T2 is in the OFF state.

[0088] During the KthFRAME emission period PEM, which follows the KthFRAME period PWR, the image data signal SL(m) (data signal VDATA) is supplied with the same potential as the data signal VDATA supplied to all pixels except the selected pixel 180 (pixel circuit 181). Also, the fifth scan signal SC5(n) changes from a state where LO is supplied to a state where HI is supplied. Therefore, the fifth transistor T5 changes from an off state to an on state. Other scan signals and other transistors remain in the same state as during the KthFRAME period PWR.

[0089] As a result, when the fifth transistor T5 is turned on, the drive potential line PVDD conducts to the fourth node N4. Since the second transistor T2 is off, no current Ion flows, and the potential supplied to the third node N3 remains at potential Vh. In addition, the potential supplied to the first node N1 remains at potential Vd due to the capacitive coupling of the capacitive element CV, and the potential supplied to the second node N2 remains at potential Vh due to the capacitive coupling of the capacitive elements CD and CV. The potential difference Vgs is the sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (potential of data signal VDATA (potential VSIGL, 0.4V) - reference potential VREF (2.6V) + reference potential VREF (2.6V) - (reset potential VRES (1.4V) - threshold voltage VTH (1V) = 0V). Pixel 180 (pixel circuit 181) containing the potential VSIGL of the data signal VDATA has a potential difference Vgs of 0V, and the second transistor T2 is in the off state, so electrode Ion does not flow. Therefore, the light-emitting element OLED does not emit light. As a result, the red-emitting pixel 180 (pixel circuit 181) becomes black. Similarly, the blue-emitting pixel 180 and the green-emitting pixel 180 also do not emit light, so the three pixels using the red-emitting pixel 180, the blue-emitting pixel 180, and the green-emitting pixel 180 become black.

[0090] As described above, the display device 10 does not include a transistor connected between the gate electrode 622 of the second transistor T2 and the second electrode 54 of the capacitive element CD, and has a configuration in which the gate electrode 622 of the second transistor T2 is connected to the second electrode 54 of the capacitive element CD. The display device 10 also has a configuration in which the light-emitting element OLED is placed between the third node N3 (the first electrode 624 of the second transistor T2) and the reference potential line PVSS. The display device 10 also includes a capacitive element CV and a capacitive element CD connected in series, with the first electrode 52 of the capacitive element CD and the second electrode 44 of the capacitive element CV connected to the first node N1, and a configuration in which a reference potential VREF is supplied to the first node N1, a potential difference corresponding to the charge corresponding to the data potential is acquired and maintained on the capacitive element CD with respect to the reference potential VREF, and a potential difference corresponding to the charge corresponding to the threshold voltage VTH of the second transistor T2 is acquired and maintained on the capacitive element CV with respect to the reference potential VREF. Furthermore, each node of the display device 10 can be controlled independently. Furthermore, the method for driving the display device 10 includes executing the PWR period after the PVH period.

[0091] For example, a display device 10 and a driving method for the display device 10, including the above configuration, can apply threshold voltage VTH information (data) to the low-potential side of the potential difference Vgs of the second transistor T2 (the first electrode 42, the first electrode 624, and the third node N3 of the capacitive element CV) with respect to a reference potential VREF, and can apply the potential (data) of the data signal VDATA to the high-potential side of the potential difference Vgs of the second transistor T2 (the second electrode 54, the gate electrode 622, and the second node N2 of the capacitive element CD), thereby minimizing fluctuations in the potential supplied to the first node N1, the second node N2, and the third node N3 from the PWR period to the PEM period.

[0092] Furthermore, for example, the display device 10 including the above configuration includes a pixel circuit 181 containing six transistors, and includes a configuration that can suppress the number of elements in the pixel. As a result, the display device 10 has a configuration that can suppress the number of elements to be formed, is expected to improve yield, and enables high resolution and large screen size.

[0093] [1-5-2. Second example of a method for driving the display device 10] Referring to Figure 6, a second example of the driving method for the pixel circuit 181 will be described. The driving method shown in the second example includes the pixel 180 (pixel circuit 181) displaying a white image based on the potential VSIGH contained in the data signal VDATA in the frame immediately preceding the current frame (KthFRAME) (K-1stFRAME), and then the pixel 180 (pixel circuit 181) displaying a white image based on the potential VSIGH contained in the data signal VDATA in the KthFRAME as well. In other words, the driving method shown in the second example includes displaying images of the same color (white) in consecutive frames. Configurations identical or similar to those in Figures 1 to 5 will be described as necessary.

[0094] The light emission period PEM of the K-1thFRAME to the period PVH of the KthFRAME, and the potentials of each node during the period between the KthFRAME period PVH and the KthFRAME period PWR, are the same as those described in "1-5-1. First Example of Driving Method of Display Device 10". Furthermore, the configuration of each scan signal and the operation of each transistor during each period are the same as those described in "1-5-1. First Example of Driving Method of Display Device 10". Therefore, configurations similar to those described in "1-5-1. First Example of Driving Method of Display Device 10" will be explained as needed and may be omitted. Note that during the KthFRAME period PWR, the image data signal SL(m) is supplied with a data signal VDATA including VSIGH (4V) corresponding to white, and during periods other than the KthFRAME period PWR, the same data signal VDATA as described in "1-5-1. First Example of Driving Method of Display Device 10" is supplied.

[0095] In the K-1stFRAME's light emission period PEM, similar to the configuration described in "1-5-1. First Example of Driving Method for Display Device 10," the pixel 180 emits white light using three pixels: a red-emitting pixel 180, a blue-emitting pixel 180, and a green-emitting pixel 180.

[0096] During the period between the light emission period PEM of K-1stFRAME and the period PIN of KthFRAME, and during the period PIN of KthFRAME, the first node N1 is initialized with the reference potential VREF, the second node N2 is initialized with the reset potential VRES, and the third node N3 is initialized with the initialization potential VINI, similar to the configuration described in "1-5-1. First Example of Driving Method of Display Device 10".

[0097] In the period PVH following period PIN, the threshold voltage VTH of the second transistor T2 is obtained by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, similar to the configuration described in "1-5-1. First Example of Driving Method for Display Device 10," and a charge equivalent to the threshold voltage VTH is held in the capacitive element CV. In reality, the threshold voltage VTH varies during manufacturing, but the second example of driving method for display device 10, similar to the configuration described in "1-5-1. First Example of Driving Method for Display Device 10," includes the operation in period PVH to ensure that the potential supplied to each node corresponds to the threshold voltage VTH that varies during manufacturing, and to obtain the threshold voltage VTH that varies during manufacturing and apply a correction using the obtained threshold voltage VTH. As a result, the second example of driving method for display device 10, similar to the configuration described in "1-5-1. First Example of Driving Method for Display Device 10," can achieve threshold voltage VTH correction by an operation in period PVH.

[0098] During the period between period PVH and period PWR, following period PVH, the potential supplied to the first node N1 maintains potential Vd, the potential supplied to the second node N2 maintains potential Vg, the potential supplied to the third node N3 maintains potential Vh, and the potential difference Vgs is potential Vg - potential Vh.

[0099] During the period PVH followed by the period PWR following the period between period PVH and period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a potential VSIGH (potential Ve, e.g., 4.4V). The potential supplied to the first node N1 maintains potential Vd, and the potential supplied to the third node N3 maintains potential Vh (0.4V). The potential supplied to the second node N2 gradually increases from potential Vg (reset potential VRES, 1.4V) towards potential Ve, becoming potential Ve. At this time, the capacitive element CD maintains the potential difference (1.8V relative to the potential supplied to the second node N2) by holding a charge equivalent to the potential difference (1.8V relative to the potential supplied to the second node N2) between the potential Vd (reference potential VREF, 2.6V) supplied to the first node N1 and the potential Ve (potential VSIGH, 4.4V) supplied to the second node N2. Furthermore, the capacitive element CV maintains the potential difference (potential Vd - potential Vh (2.2V) relative to the potential supplied to the third node N3) by holding a charge equivalent to the potential difference between the potential Vd supplied to the first node N1 and the potential Vh supplied to the third node N3. The sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (1.8V + 2.2V) is 4V, and the potential difference Vgs is 4V.

[0100] As described above, during the PWR period, the data signal VDATA is written to pixel 180 (pixel circuit 181). In addition, the capacitive element CD maintains (holds) the data potential of the data signal VDATA.

[0101] In the period following the PWR period, the potential supplied to the first node N1, which is capacitively coupled by capacitive elements CV and CD, remains at potential Vd; the potential supplied to the second node N2 remains at potential Ve; and the potential supplied to the third node N3 remains at potential Vh. That is, the potential difference Vgs is maintained at 4V, and the second transistor T2 is in the ON state.

[0102] During the PEM period of the KthFRAME following the PWR period, the potential difference Vgs is maintained at 4V, and since the second transistor T2 is ON, a current Ion flows, causing the potential supplied to the third node N3 to rise from potential Vh to potential Vd. The sixth transistor T6 is OFF, and the first node N1 is floating. Also, the first transistor T1 and the third transistor T3 are OFF, and the second node N2 is floating. Therefore, since the potential supplied to the third node N3 has risen from potential Vh to potential Vd, the potential supplied to the first node N1 rises from potential Vd to potential Vb due to capacitive coupling between the third node N3 and the first node N1 by the capacitive element CV, and the potential supplied to the second node N2 rises from potential Ve to potential Vc due to capacitive coupling between the first node N1 and the second node N2 by the capacitive element CD. As a result, the potential difference Vgs is the sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (potential of data signal VDATA (potential VSIGH, 4.4V) - reference potential VREF (2.6V) + reference potential VREF (2.6V) - (reset potential VRES (1.4V) - threshold voltage VTH (1V) = 4V)). When the data signal VDATA includes potential VSIGH, the potential difference Vgs is 4V and the second transistor T2 is ON, so the drive potential line PVDD A current Ion flows from the light-emitting element OLED to the reference potential line PVSS, causing the light-emitting element OLED to emit light. For example, a red-emitting pixel 180, a blue-emitting pixel 180, and a green-emitting pixel 180 each emit light, and the three pixels using the red-emitting pixel 180, the blue-emitting pixel 180, and the green-emitting pixel 180 become white. In other words, based on the data signal VDATA and the corrected threshold voltage, the pixel 180 (pixel circuit 181) can display an image.

[0103] The second example of the driving method for the display device 10 produces the same effects as those described in "1-5-1. First Example of Driving Method for the Display Device 10".

[0104] [1-5-3. Third example of a method for driving the display device 10] Referring to Figure 7, a third example of the driving method for the display device 10 will be described. The driving method shown in the third example includes the following: after the pixel 180 (pixel circuit 181) displays a black image based on the potential VSIGL included in the data signal VDATA in the frame immediately preceding the current frame (KthFRAME) (K-1stFRAME), the pixel 180 (pixel circuit 181) also displays a black image based on the potential VSIGL included in the data signal VDATA in the KthFRAME. In other words, the driving method shown in the third example includes displaying images of the same color (black) in consecutive frames. Configurations identical or similar to those in Figures 1 to 6 will be described as necessary. Configurations identical or similar to those in Figures 1 to 6 will be described as necessary.

[0105] The potentials of each node during the PVH period of KthFRAME and the PEM period of KthFRAM are the same as those described in "1-5-1. First Example of Driving Method for Display Device 10". Furthermore, the configuration of each scan signal and the operation of each transistor during each period are the same as those described in "1-5-1. First Example of Driving Method for Display Device 10". Therefore, configurations similar to those described in "1-5-1. First Example of Driving Method for Display Device 10" will be explained as needed.

[0106] In the K-1stFRAME's luminescence period PEM, for example, the potential held at the first node N1 is potential Vd (reference potential VREF, 2.6V). Also, the potential supplied to the second node N2 and the potential held at the third node N3 are potential Vh (0.4V), and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, no ions flow through the drain electrode Ion, and the light-emitting element OLED does not emit light.

[0107] As a result, the red-emitting pixel 180 (pixel circuit 181), the blue-emitting pixel 180, and the green-emitting pixel 180 do not emit light, and the three pixels using the red-emitting pixel 180, the blue-emitting pixel 180, and the green-emitting pixel 180 appear black.

[0108] Following the light emission period PEM of the K-1stFRAME, during the period between the light emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, and then during the period PIN of the KthFRAME, similar to the configuration described in "1-5-1. First Example of Driving Method of Display Device 10," the potential supplied to the first node N1 maintains potential Vd, and the potential supplied to the third node N3 changes from potential Vh to the initialization potential VINI (potential Vf, -0.6V). While the third transistor T3 remains in the off state, the potential supplied to the second node N2 maintains potential Vh. When the fourth scan signal SC4(n) changes from a HI state to a LO state, and the second scan signal SC2(n) changes from a LO state to a HI state, the third transistor T3 turns from the off state to the on state, the second node N2 conducts with the reset potential line SVRE, and the potential supplied to the second node N2 gradually rises from potential Vh to potential Vg (reset potential VRES) until it reaches potential Vg. Therefore, the potential difference Vgs is potential Vg - potential Vf (1.4V - (-0.6V) = 2V), and the second transistor T2 is in the on state.

[0109] As described above, in the same configuration as described in "1-5-1. First Example of Driving Method for Display Device 10", during the period PIN, the first node N1 is initialized with the reference potential VREF, the second node N2 is initialized with the reset potential VRES, and the third node N3 (fifth node N5) is initialized with the initialization potential VINI.

[0110] In the period PVH following period PIN, the threshold voltage VTH of the second transistor T2 is obtained by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, similar to the configuration described in "1-5-1. First Example of Driving Method for Display Device 10," and a charge equivalent to the threshold voltage VTH is held in the capacitive element CV. In reality, the threshold voltage VTH varies during manufacturing, but the third example of driving method for display device 10, similar to the configuration described in "1-5-1. First Example of Driving Method for Display Device 10," includes the operation in period PVH to ensure that the potential supplied to each node corresponds to the threshold voltage VTH that varies during manufacturing, and to obtain the threshold voltage VTH that varies during manufacturing and apply a correction using the obtained threshold voltage VTH. As a result, the third example of driving method for display device 10, similar to the configuration described in "1-5-1. First Example of Driving Method for Display Device 10," can achieve correction of the threshold voltage VTH by an operation in period PVH.

[0111] In the PWR period following the PVH period, the data signal VDATA is written to the pixel 180 (pixel circuit 181), similar to the configuration described in "1-5-1. First Example of Driving Method of Display Device 10". In addition, the capacitive element CD maintains (holds) the data potential of the data signal VDATA.

[0112] During the period following the PWR period, and during the PEM period of the KthFRAME that follows the PWR period, the pixel circuit 181 operates in the same manner as described in "1-5-1. First Example of Driving Method of Display Device 10," where the potential difference Vgs is 0V and the second transistor T2 is in the off state, so no ion flows through the drain electrode Ion, and the light-emitting element OLED does not emit light. As a result, the pixel 180 becomes black, consisting of three pixels: a red-emitting pixel 180, a blue-emitting pixel 180, and a green-emitting pixel 180.

[0113] The third example of the driving method for the display device 10 produces the same effects as those described in "1-5-1. First Example of Driving Method for the Display Device 10".

[0114] [1-5-4. Fourth example of a method for driving the display device 10] Referring to Figure 8, a fourth example of the driving method for the display device 10 will be described. The driving method shown in the fourth example includes the following: after a pixel 180 (pixel circuit 181) displays a black image based on the potential VSIGL of the data signal VDATA in the frame immediately preceding the current frame (KthFRAME) (K-1stFRAME), the pixel 180 (pixel circuit 181) displays a white image based on the potential VSIGH of the data signal VDATA in the KthFRAME. In other words, the driving method shown in the fourth example includes displaying images of different colors in consecutive frames. Configurations identical or similar to those in Figures 1 to 7 will be described as necessary.

[0115] The potentials of each node, the configuration of each scan signal, and the operation of each transistor during the light emission period PEM of the K-1stFRAME to the light emission period PVH of the KthFRAME are the same as those described in "1-5-3. Third Example of Driving Method of Display Device 10". Furthermore, the potentials of each node, the configuration of each scan signal, and the operation of each transistor during the period after the light emission period PVH of the KthFRAME to the light emission period PEM are the same as those described in "1-5-2. Second Example of Driving Method of Display Device 10". Therefore, further explanation is omitted here.

[0116] The fourth example of the driving method for the display device 10 produces the same effects as those described in "1-5-1. First Example of Driving Method for the Display Device 10".

[0117] [1-6. Edge structure of 180 pixels] The end face structure of the pixel 180 will be described with reference to Figures 9 to 17. Figures 9 and 10 are layout diagrams of the pixel 180 as seen from the surface (first surface 101A) side of the display device 10. Figure 11 is an end face diagram showing the end face cut along A1-A2 in the layout shown in Figure 9. Figure 12 is an end face diagram showing the end face cut along B1-B2 in the layout shown in Figure 9. Figure 13 is an end face diagram showing a modified example of the end face cut along A1-A2 in the layout shown in Figure 9. The layout of the pixel 180 shown in Figures 9 and 10, and the end faces of the pixel 180 shown in Figures 11 to 13 are examples, and the layout and end faces of the pixel 180 are not limited to the examples shown in Figures 9 to 13. Configurations identical or similar to those in Figures 1 to 8 will be described as necessary.

[0118] In the layout of pixel 180 shown in Figure 9, for the sake of clarity, all components except the semiconductor layer 122, conductive layer 127, conductive layer 132, first contact hole opening 135, second contact hole opening 138, and third contact hole opening 129 are omitted. Also, in the layout of pixel 180 shown in Figure 10, for the sake of clarity, each element shown in Figure 9, a part of the conductive layer 140, and the anode 143 are shown with dashed lines, a part of the conductive layer 140, conductive layer 142, and the contact hole opening 147 for the anode are shown with solid lines, and all other elements and their reference numerals are omitted. Furthermore, in the end faces of pixel 180 shown in Figures 11 and 13, the structure of the layers above the insulating layer 141 is omitted along the third direction D3.

[0119] Furthermore, the end face of the pixel 180 shown in Figure 11 is an example of an end face of the pixel 180, and is the end face along the second electrode 142A, the first electrode 140B, the gate wiring 127H, the first wiring 132J, the first contact hole openings 135P and 135I, the semiconductor layer 122E, the gate wiring 127E, the first wiring 132K, the first contact hole opening 135J, and the third contact hole opening 129. The end face of the pixel 180 shown in Figure 12 is an example of an end face of the pixel 180, and is the end face along the anode 143, the functional layer 148, the cathode 149, the first wiring 132B, the first electrode 140C, the contact hole opening for the anode 147A, the gate wiring 127D, the first wiring 132C, the semiconductor layer 122B, the first contact hole opening 135C, and the gate wiring 127A. The end face of the pixel 180 shown in Figure 13 is an example of the end face of the pixel 180, and is the end face along the second electrode 142A, the first electrode 140B, the gate wiring 127H, the first wiring 132J, the first contact hole openings 135P and 135I, the semiconductor layer 122E, the gate wiring 127E, the first wiring 132K, the first contact hole opening 135J, and the third contact hole opening 129.

[0120] The substrate 101 includes a first surface 101A and a second surface 101B opposite to the first surface 101A. A semiconductor layer 122 is provided on the first surface 101A of the substrate 101 via a base layer 121. The semiconductor layer 122 includes semiconductor layer 122E and semiconductor layer 122B. Semiconductor layer 122B includes a channel region 123 and an impurity region 124A. For example, the impurity region may be denoted as the source region or drain region. Also, for example, the second transistor T2 and the fifth transistor T5 include semiconductor layer 122B, and the first electrode 624 (see Figure 15) and the second electrode 626 (see Figure 15), as well as the first electrode 654 (see Figure 15) and the second electrode 656 (see Figure 15), include impurity region 124A. In other words, semiconductor layer 122B serves as both the channel region and the impurity region of the second transistor T2 and the fifth transistor T5. The sixth transistor T6 includes a semiconductor layer 122E, and the first electrode 664 (see Figure 15) and the second electrode 666 (see Figure 15) include an impurity region 124A. In other words, the semiconductor layer 122E includes the channel region of the sixth transistor T6.

[0121] Similar to semiconductor layer 122B, the first transistor T1 includes semiconductor layer 122A (see Figure 15), the third transistor T3 includes semiconductor layer 122C (see Figure 15), and the fourth transistor T4 includes semiconductor layer 122D. Furthermore, the first and second electrodes of each transistor include impurity regions. Specifically, the first electrode 614 (see Figure 15) and second electrode 616 (see Figure 15) of the first transistor T1, the first electrode 634 (see Figure 15) and second electrode 636 (see Figure 15) of the third transistor T3, and the first electrode 644 (see Figure 15) and second electrode 646 (see Figure 15) of the fourth transistor T4 include impurity regions. In other words, semiconductor layer 122A includes the channel region of the first transistor T1, semiconductor layer 122C includes the channel region of the third transistor T3, and semiconductor layer 122D includes the channel region of the fourth transistor T4.

[0122] On the semiconductor layer 122, a gate insulating layer 125, a conductive layer 127, an insulating layer 128, and a conductive layer 132 are provided in this order. The conductive layer 127 includes gate wiring 127H, gate wiring 127E (gate electrode 662), gate wiring 127D (scan signal line 334), and gate wiring 127A (scan signal line 332). The conductive layer 132 includes the first wiring 132J, the first wiring 132K, the first wiring 132B, and the first wiring 132C. The region where the conductive layer 127 and the semiconductor layer 122 overlap is the channel region. In other words, the region where the gate electrode of each transistor and the semiconductor layer overlap is the channel region.

[0123] Each transistor in the pixel 180 is formed using a semiconductor layer 122 (e.g., semiconductor layer 122B, channel region 123, and impurity region 124A), a gate insulating layer 125, and a conductive layer 127 (e.g., gate wiring 127A).

[0124] First contact hole openings 135I and 135J that reach the semiconductor layer 122 penetrate the gate insulating layer 125 and the insulating layer 128 and are provided in the gate insulating layer 125 and the insulating layer 128. And 135A penetrate the gate insulating layer 125 and the insulating layer 128 and are provided in the gate insulating layer 125 and the insulating layer 128. For example, the first contact hole openings 135I and 135J expose the semiconductor layer 122E (for example, the second electrode 666 and the first electrode 664), the first wiring 132J is electrically connected to the semiconductor layer 122D by the first contact hole opening 135I, and the first wiring 132K is electrically connected to the semiconductor layer 122D by the first contact hole opening 135J. Furthermore, the first contact hole opening 135C exposes the semiconductor layer 122B (for example, the first electrode 624), and the first wiring 132C is electrically connected to the semiconductor layer 122B by the first contact hole opening 135C. Also, the first wiring 132J is electrically connected to the gate wiring 127H by the first contact hole opening 135P. That is, the first contact hole opening may penetrate and open through the gate insulating layer 125 and the insulating layer 128 to expose the semiconductor layer 122, or the first contact hole opening may penetrate and open through the insulating layer 128 to expose the conductive layer 127.

[0125] The insulating layer 136 is provided so as to cover the conductive layer 132 and the insulating layer 128 in which the conductive layer 132 is not exposed. The insulating layer 136 is provided so as to cover the insulating layer 131.

[0126] A second contact hole opening is provided in the insulating layer 138. For example, the second contact hole opening includes a second contact hole opening 138A. A conductive layer 140 is provided on the insulating layer 136 and in the second contact hole opening 138A. The conductive layer 140 includes a first electrode 140C (second electrode 34) and a first electrode 140B (second electrode 54). The second contact hole opening 138A penetrates the insulating layer 136 and exposes the first wiring 132C. The first electrode 140C is electrically connected to the first wiring 132C via the second contact hole opening 138A. For example, the first electrode 140C also serves as a pixel electrode. Although not shown in the illustration, for example, the second contact hole opening 138 exposes some of the multiple terminals (not shown) included in the terminal portion 150. Some of the exposed terminals are electrically connected to the FPC200 using a conductive film such as an anisotropic conductive film (not shown in the illustration). Furthermore, pixel electrodes are provided independently for each pixel.

[0127] The insulating layer 131 is provided on an insulating layer 136 that does not have a conductive layer 140, and is provided so as to cover the conductive layer 140. A third contact hole opening 129 is provided on the insulating layers 131 and 136. The conductive layer 142 is provided on the insulating layer 131 and in the third contact hole opening 129. The conductive layer 142 includes a second electrode 142A (first electrode 52, second electrode 44). The third contact hole opening 129 penetrates the insulating layers 131 and 136 and exposes the first wiring 132K. The second electrode 142A is electrically connected to the first wiring 132K via the third contact hole opening 129. For example, the capacitive element CV is formed using an insulating layer 131 as a dielectric and a first electrode 140B (first electrode 42) and a second electrode 142A (second electrode 44), while the capacitive element CD is formed using an insulating layer 131 as a dielectric and a first electrode 140B (second electrode 54) and a second electrode 142A (first electrode 52).

[0128] The insulating layer 141 is provided on top of the insulating layer 131, which does not have a conductive layer 142, and is provided so as to cover the conductive layer 142.

[0129] For example, the base layer 121, semiconductor layer 122, gate insulating layer 125, conductive layer 127, insulating layer 128, conductive layer 132, insulating layer 136, conductive layer 140, insulating layer 131, conductive layer 142, and insulating layer 141 are collectively referred to as the array section 170.

[0130] Next, a plurality of layers laminated on the insulating layer 141 will be described. A contact hole opening 147 for the anode is provided in the insulating layer 141. The contact hole opening 147 for the anode includes a contact hole opening 147A for the anode. The contact hole opening 147A for the anode penetrates the insulating layers 141 and 131 and is provided in the insulating layers 141 and 131, exposing the conductive layer 140 (for example, the first electrode 140C).

[0131] The anode 143 is provided so as to cover the exposed first electrode 140C, the contact hole opening 147A for the anode, and the insulating layers 141 and 131. The functional layer 148 is provided on top of the anode 143. The cathode 149 (the first electrode 32 of the light-emitting element OLED) is provided on top of the functional layer 148 so as to cover the functional layer 148. The cathode 149 is electrically connected to the reference potential line PVSS. Here, the light-emitting element OLED is composed of the anode 143, the functional layer 148, and the cathode 149.

[0132] The configuration of the functional layer 148 can be selected as appropriate. For example, the functional layer 148 can be composed of a combination of a carrier injection layer, a carrier transport layer, an emissive layer, a carrier blocking layer, an exciton blocking layer, and so on. For example, the functional layer 148 shown in Figure 12 includes a first layer 144, a second layer 145, and a third layer 146. For example, the first layer 144 is a carrier (hole) injection and transport layer, the second layer 145 is an emissive layer, and the third layer 146 is a carrier (electron) injection and transport layer. For example, the functional layer 148 can be provided independently for each pixel, similar to the pixel electrodes.

[0133] A sealing film 165 is provided on the cathode 149. For example, the sealing film 165 includes a first inorganic insulating layer 152, an organic insulating layer 154, and a second inorganic insulating layer 156. The first inorganic insulating layer 152 and the second inorganic insulating layer 156 are formed to cover at least the display area 22. A cover film 158 is placed on the second inorganic insulating layer 156.

[0134] For example, the first layer 144, the second layer 145 (light-emitting layer), and the third layer 146 included in the functional layer 148, as well as the anode 143, are not placed on top of the IC chip 110 and the control circuit 120. The sealing film 165 and the cover film 158 are placed on top of the IC chip 110 and the control circuit 120. The sealing film 165 and the cover film 158 prevent impurities (water, oxygen, etc.) from entering the light-emitting element OLED and each transistor from outside the display device 10.

[0135] For example, as shown in Figure 13, the first electrode 140B may include a plurality of protrusions 140BC projecting from the insulating layer 136 toward the insulating layer 131 along the third direction D3, and the second electrode 142A may include a plurality of protrusions 142AC projecting from the insulating layer 131 toward the insulating layer 141 along the plurality of protrusions 140BC.

[0136] Because the capacitive element CD includes multiple protrusions 140BC and multiple protrusions 142AC, the surface area of ​​the first electrode 140B and the second electrode 142A increases, thereby increasing the capacitance value formed across the insulating layer 131. Similarly, the capacitance value formed across the insulating layer 131 can also be increased for the capacitive element CV, just like for the capacitive element CD. By using a high-dielectric material (high-k material) with a high dielectric constant for the insulating layer 131, the capacitance values ​​of the capacitive elements CV and CD can be further increased. As a result, a decrease in the holding voltage or loss of the holding voltage can be suppressed.

[0137] [1-7. Method for manufacturing the display device 10] The manufacturing method of the display device 10 (pixel 180) will be described with reference to Figures 9, 10, and 14-17. Figure 14 is a sequence diagram showing the manufacturing method of the display device 10. Figures 15-17 are layout diagrams of the pixels 180 as viewed from the surface (first surface 101A) side of the display device 10. Configurations identical or similar to those in Figures 1-13 will be described as necessary, and descriptions of identical or similar configurations may be omitted. The manufacturing method of the display device 10 includes, as an example, an oxide semiconductor layer formed using an oxide semiconductor.

[0138] When the manufacturing of the display device 10 (180 pixels) begins, the underlayer 121 (see Figures 11-13) is formed on the first surface 101A (see Figures 11-13) of the substrate 101 (see Figures 11-13) (step 10 (S10) in Figure 14). For example, the substrate 101 is a glass substrate.

[0139] As shown in Figure 15, semiconductor layer 122 includes semiconductor layers 122A, 122B, 122C, 122D, and 122E. Semiconductor layer 122A is the semiconductor layer for the first transistor T1. Semiconductor layer 122B serves as both the semiconductor layer for the second transistor T2 and the semiconductor layer for the fifth transistor T5. Semiconductor layer 122C is the semiconductor layer for the third transistor T3. Semiconductor layer 122D is the semiconductor layer for the fourth transistor T4. Semiconductor layer 122E is the semiconductor layer for the sixth transistor T6. In other words, semiconductor layer 122A includes the channel region of the first transistor T1, semiconductor layer 122B includes the channel region of the second transistor T2 and the channel region of the fifth transistor T5, semiconductor layer 122C includes the channel region of the third transistor T3, semiconductor layer 122D includes the channel region of the fourth transistor T4, and semiconductor layer 122E includes the channel region of the sixth transistor T6.

[0140] A gate insulating layer 125 (see Figures 11 to 13) is formed on top of the semiconductor layer 122 and on top of the underlayer 121 on which the semiconductor layer 122 is not formed (step 12 (S12) in Figure 14).

[0141] A conductive layer 127 (see Figures 11-13) is formed on top of the gate insulating layer 125 (see Figures 11-13) (step 13(S13) in Figure 14). As shown in Figures 9, 15-17, the conductive layer 127 includes gate wiring 127A (scan signal line 332), gate wiring 127B (scan signal line 331), gate wiring 127C (scan signal line 333), gate wiring 127D (scan signal line 334), gate wiring 127E (scan signal line 330), gate wiring 127F, gate wiring 127G, gate wiring 127H, and gate wiring 127I (gate electrode 622). Gate wiring 127A includes gate electrode 612, gate wiring 127B includes gate electrode 632, gate wiring 127C includes gate electrode 642, gate wiring 127D includes gate electrode 652, and gate wiring 127E includes gate electrode 662.

[0142] The region where the gate electrode 622 and semiconductor layer 122B of the second transistor T2 overlap is the channel region 123, and the channel region 123 corresponds to the channel length of the second transistor T2. Similarly to the second transistor T2, the region where the gate electrode 612 and semiconductor layer 122A of the first transistor T1 overlap is the channel region of the first transistor T1 and corresponds to its channel length. For transistors other than the second transistor T2 and the first transistor T1, similarly to the second transistor T2 and the first transistor T1, the region where the gate electrode and semiconductor layer overlap is the channel region of the transistor and corresponds to its channel length.

[0143] As shown in Figure 15, in plan view, the channel region 123 of the second transistor T2 is larger (longer) than the channel regions of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. That is, the channel length of the second transistor T2 is longer than the channel length of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. Since the second transistor T2 operates in the saturation region, it is necessary to suppress the kink effect. Furthermore, it is preferable that the resistance of the second transistor T2 to hot carriers is higher than that of the other transistors in the pixel 180. To suppress the kink effect and ensure reliability (hot carrier resistance), the channel length of the second transistor T2 is longer than that of the other transistors in the pixel 180.

[0144] An insulating layer 128 (see Figures 11 to 13) is formed on top of the conductive layer 126 and on top of the gate insulating layer 125 on which the conductive layer 126 is not formed (step 14 (S14) in Figure 14).

[0145] As shown in Figures 9 and 15-17, the first contact hole openings 135A-135Q are opened (step 15 (S15) in Figure 14). Each opening may open the gate insulating layer 125 and the insulating layer 128 to expose the semiconductor layer, and each opening may open the insulating layer 128 to expose the gate wiring. For example, the first contact hole opening 135A exposes the semiconductor layer 122A, and the first contact hole opening 135Q exposes the gate wiring 127I. The other openings also expose the corresponding semiconductor layer or gate wiring.

[0146] A conductive layer 132 (see Figures 11 to 13) is formed on the insulating layer 128 or in the first contact hole opening 135 (step 16 (S16) in Figure 14). As shown in Figures 9, 16 and 17, the conductive layer 132 includes a first wiring 132A (image data signal line 321), a first wiring 132B, a first wiring 132C, a first wiring 132D (reset potential line SVRE), a first wiring 132E, a first wiring 132F (initialization potential line SVI), a first wiring 132G, a first wiring 132H (drive potential line PVDD), a first wiring 132I (reference potential line SVR), a first wiring 132J, and a first wiring 132K.

[0147] As shown in Figure 16, in a plan view, for example, the first wiring 132A is electrically connected to the first transistor T1 via the first contact hole opening 135A. The first wiring 132B is electrically connected to the first transistor T1 via the first contact hole opening 135B and electrically connected to the gate wiring 127I (gate electrode 622) via the first contact hole opening 135Q. The first wiring 132C is electrically connected to the fourth transistor T4 via the first contact hole opening 135G and electrically connected to the second transistor T2 via the first contact hole opening 135C. The other first wirings are also electrically connected to gate wiring or transistors (semiconductor layer 122) via their respective openings.

[0148] An insulating layer 136 (see Figures 11 to 13) is formed on top of the conductive layer 132 and on top of the insulating layer 128 on which the conductive layer 132 is not formed (step 17 (S17) in Figure 14).

[0149] As shown in Figures 9, 16, and 17, the second contact hole opening 138 is opened (step 18 (S18) in Figure 14). The second contact hole opening 138 includes second contact hole openings 138A to 138C. For example, the second contact hole opening 138A exposes the first wiring 132C. Each opening opens the insulating layer 136 and exposes the first wiring corresponding to each opening.

[0150] A conductive layer 140 (see Figures 11-13) is formed on the insulating layer 136 (see Figures 11-13) and in the second contact hole opening 138 (step 19 (S19) in Figure 14). As shown in Figures 10 and 17, the conductive layer 140 includes the first electrode 140A (first electrode 42), 140B (second electrode 54), and 140C (second electrode 34).

[0151] As shown in Figure 10 or Figure 17, in a plan view, for example, the first electrode 140A is electrically connected to the first wiring 132C via the second contact hole opening 138C and is electrically connected to the fourth transistor T4 via the first contact hole opening 135G. Also, for example, the first electrode 140C is electrically connected to the first wiring 132C via the second contact hole opening 138A and is electrically connected to the second transistor T2 via the second contact hole opening 138C, is electrically connected to the fourth transistor T4 via the first contact hole opening 135G, and is electrically connected to the first electrode 140A via the second contact hole opening 138C. The first electrode 140B is electrically connected to the corresponding first wiring, as well as to the corresponding gate wiring and transistor, similar to the first electrodes 140A and 140C.

[0152] An insulating layer 131 (see Figures 11 to 13) is formed on top of the conductive layer 140 and on top of the insulating layer 136 where the conductive layer 140 is not provided (step 20 (S20) in Figure 14).

[0153] As shown in Figures 9-11, 13, and 17, the third contact hole opening 129 is opened (step 21 (S21) in Figure 14). The third contact hole opening 129 opens the insulating layers 131 and 136 and exposes the conductive layer 132. For example, the third contact hole opening 129 exposes the first wiring. Other third contact hole openings also expose their respective insulating layers, wiring, or electrodes.

[0154] A conductive layer 142 (see Figures 11-13) is formed on the insulating layer 131 (see Figures 11-13) and in the third contact hole opening 129 (step 22 (S22) in Figure 14). For example, as shown in Figure 10, the conductive layer 140 includes a second electrode 142A (second electrode 44, first electrode 52). The second electrode 142A is electrically connected to the first wiring 132K via the third contact hole opening 129 and to the sixth transistor T6 via the first contact hole opening 135J. Other conductive layers 140 are electrically connected to the corresponding first wiring and to the corresponding gate wiring or transistor, similar to the second electrode 142A.

[0155] An insulating layer 141 (organic insulating layer) (see Figures 11 to 13) is formed on top of the conductive layer 142 and on top of the insulating layer 131 on which the conductive layer 142 is not formed (step 23 (S23) in Figure 14).

[0156] Furthermore, an insulating layer 141 (organic insulating layer) (see Figure 12) is opened (step 24 (S24) in Figure 14). In the opening of S24, a contact hole opening portion 147A for the anode is opened. The contact hole opening portion 147A for the anode removes the insulating layers 141 and 131 on the first electrode 140C, exposing the first electrode 140C. The contact hole opening portion 147A for the anode may sometimes be referred to as the organic insulating layer opening portion.

[0157] An anode 143 (see Figures 10 and 12) is provided on the exposed first electrode 140C, on the anode contact hole opening 147A, and on the insulating layers 141 and 131 (step 25 (S25) in Figure 14). A functional layer 148 (see Figure 12) is provided on the anode 143. A cathode 149 (see Figure 12) is provided on the functional layer 148. For example, an anode 143 may be provided for each pixel, a functional layer 148 may be provided for each pixel, and the cathode 149 may be provided so as to overlap the display area 22.

[0158] After S25, the sealing film 165 is placed on the cathode 149, and the cover film 158 is placed on the sealing film 165 (see Figure 12). That is, the sealing film 165 and the cover film 158 are placed on the cathode 149 in this order (see Figure 12).

[0159] With the above steps completed, the manufacturing of the display device 10 (180 pixels) is finished.

[0160] The manufacturing method for the display device 10 (pixel 180) includes forming a conductive layer 127 along a first direction D1 and forming a conductive layer 132 along a second direction D2. The manufacturing method for the display device 10 (pixel 180) also includes forming a conductive layer 140 and a conductive layer 142. The wiring routed within the display device 10 is mainly formed from the conductive layer 127 and the conductive layer 132, and the capacitive elements CV and CD, as well as the anode 143, are formed using the conductive layer 140 or the conductive layer 142. In other words, the manufacturing method for the display device 10 (pixel 180) allows the formation of the routed wiring and the formation of the capacitive elements to be done using different wiring or electrodes. Therefore, the manufacturing method for the display device 10 (pixel 180) allows the capacitive elements CV and CD contained in a pixel to be placed in very close proximity to the capacitive elements CV and CD contained in adjacent pixels. As a result, the manufacturing method of the display device 10 (pixel 180) allows for larger capacitance values ​​of the capacitive elements CV and CD compared to the case where the routing wiring and capacitive elements are not formed using different wiring or electrodes. Furthermore, because the capacitance values ​​of the capacitive elements CV and CD can be increased, a decrease in the holding voltage or loss of the holding voltage can be suppressed.

[0161] Furthermore, as shown in Figure 10, in a plan view, the area of ​​the second electrode 142A is larger than the area of ​​the first electrode 140A and the area of ​​the first electrode 140B. Therefore, for example, as shown in the side wall portion 190 of Figure 11, in an end view, the capacitance value of the capacitive element can be increased by the side wall of the first electrode 140B and the side wall of the second electrode 142A. As a result, a decrease in the holding potential or loss of the holding potential can be suppressed.

[0162] Furthermore, as shown in Figure 10, in a plan view, the capacitive elements CV and CD are arranged separately from the image data signal line 321 without overlapping. As a result, fluctuations in the potential held by the capacitive elements CV and CD due to potential fluctuations in the image data signal line 321 are suppressed.

[0163] [1-8. Materials of each component of the display device 10] As the substrate 101, a rigid substrate that is translucent and inflexible can be used, such as a glass substrate, a quartz substrate, or a sapphire substrate. If the substrate 101 needs to be flexible, a flexible substrate containing resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, can be used. Impurities may be introduced into the resin to improve the heat resistance of the substrate SUB.

[0164] For example, the semiconductor layer 122 includes a channel region and contains Group 14 elements such as silicon (Si) and germanium (Ge), or an oxide exhibiting semiconductor properties. As the oxide exhibiting semiconductor properties, a metal oxide having semiconductor properties can be used. For example, as described in "1-7. Method for Manufacturing the Display Device 10", the semiconductor layer 122 includes an oxide semiconductor as the metal oxide exhibiting semiconductor properties. For example, the oxide semiconductor contains two or more metals, including indium (In). In addition to indium, the metal oxide having semiconductor properties may include gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanides. Furthermore, the metal oxide having semiconductor properties may be amorphous, crystalline, or a mixed phase of amorphous and crystalline materials.

[0165] Furthermore, for example, the semiconductor layer 122 containing group 14 elements may contain crystalline silicon. The crystalline silicon may be low-temperature polysilicon (LTPS) or single-crystal silicon. Also, the crystalline silicon is implanted with impurities. If the transistor is an n-channel field-effect transistor, the crystalline silicon is implanted with impurities (e.g., phosphorus (P)) to become n-type, and if the transistor is a p-channel field-effect transistor, the crystalline silicon is implanted with impurities (e.g., boron (B)) to become p-type. In addition, the channel region of each transistor included in the display device 10 may be formed using single-crystal silicon such as a silicon wafer or SOI substrate.

[0166] Furthermore, if the display device 10 includes both a transistor containing a group 14 element and a transistor containing an oxide exhibiting semiconductor properties as a semiconductor layer 122 (channel region), the manufacturing method of the display device 10 includes forming a semiconductor layer containing a group 14 element and forming a semiconductor layer containing an oxide exhibiting semiconductor properties (for example, an oxide semiconductor layer).

[0167] For example, the leakage current of a transistor made of a metal oxide with semiconductor properties is extremely small. Therefore, when using a transistor made of a metal oxide with semiconductor properties, the charge corresponding to the potential written to the capacitive element is difficult to escape from the capacitive element. As a result, by using a transistor made of a metal oxide with semiconductor properties, it is possible to retain the charge written to the capacitive element for a long time. Also, under the same conditions for the gate-source potential difference (potential difference between the gate electrode and the source electrode) and the source-drain potential difference, the drain current of a transistor made of a metal oxide with semiconductor properties may be greater than the drain current of a transistor made of crystalline silicon (for example, low-temperature polysilicon (LTPS)). As a result, under the same conditions for the drain current, the gate-source potential difference and source-drain potential difference of a transistor made of a metal oxide with semiconductor properties can be made smaller than those of a transistor made of crystalline silicon. Therefore, by using a transistor made of a metal oxide with semiconductor properties, the power consumption of the display device 10 can be suppressed.

[0168] Common metallic materials are used as conductive layers 127, 132, 140, and 142. For example, common metallic materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof. Depending on the application and specifications of the display device 10, each conductive layer may consist of a single layer of the above metallic material or a laminated layer of the above metallic material.

[0169] The materials forming the base layer 121, gate insulating layer 125, insulating layer 131, first inorganic insulating layer 152, and second inorganic insulating layer 156 can be general insulating materials. For example, silicon oxide (SiO₂) can be used as these insulating layers. x ), silicon oxide nitride (SiO x N y ), silicon nitride (SiN x) Silicon nitride oxide (SiN x O y ) and other inorganic insulating layers are used. SiO x N y is a silicon compound and an aluminum compound containing nitrogen (N) in a ratio (x > y) less than that of oxygen (O). SiN x O y is a silicon compound and an aluminum compound containing oxygen in a ratio (x > y) less than that of nitrogen. Further, the insulating layer 131 may be formed using a high dielectric constant material (high-k material).

[0170] For example, materials for forming the insulating layer 128, the insulating layer 136, the insulating layer 141, and the organic insulating layer 154 can use an organic compound material with excellent surface flatness. The insulating layer 128, the insulating layer 136, and the insulating layer 141 may be referred to as organic insulating layers.

[0171] The material for forming the cathode 149 uses a conductive oxide that transmits visible light. For example, the material for forming the cathode 149 is a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO), etc. As the conductive oxide that transmits visible light, materials other than the above may also be used.

[0172] The material for forming the anode 143 uses a metal or its alloy with high reflectivity. For example, the material for forming the anode 143 is a metal such as silver (Ag), aluminum (Al), magnesium (Mg), etc. or their alloys. The material for forming the cathode 149 may include a structure in which a film containing a metal is sandwiched by a film containing the above-mentioned conductive oxide.

[0173] [2. Second Embodiment] Referring to Figures 4 and 18 to 24, an overview of the display device 20 according to the second embodiment will be described. Figure 18 is a schematic diagram showing the configuration of the display device 20. Figure 19 is a schematic diagram showing the input signals to the pixel 180A (pixel circuit 181A) according to the second embodiment, Figure 20 is a circuit diagram showing the configuration of the pixel circuit 181A, and Figures 21 to 24 are timing charts of the display device 20. Configurations identical or similar to those in Figures 1 to 17 will be described as necessary, and descriptions of configurations identical or similar to those in Figures 1 to 17 may be omitted.

[0174] The display device 20 includes pixels 180A and pixel circuits 181A. The configuration of pixels 180A and pixel circuits 181A differs from the configuration of pixels 180 and pixel circuits 181 of the display device 10 according to the first embodiment. Specifically, the display device 20 includes the following configurations 1 to 6. Mainly, configurations 1 to 6 and configurations related to configurations 1 to 6 differ from the configuration of the display device 10 according to the first embodiment. (Configuration 1) The display device 10 according to the first embodiment has a configuration and function in which the pixel 180 (pixel circuit 181) is replaced by a pixel 180A (pixel circuit 181A), and the configuration and function related to the pixel 180A (pixel circuit 181A) are different from the configuration and function related to the pixel 180 (pixel circuit 181). (Configuration 2) The electrical connection between the control circuit 120 and the pixel 180A (pixel circuit 181A) is different from the electrical connection between the control circuit 120 and the pixel 180 (pixel circuit 181). (Configuration 3) The scan signal line 333 to which the scan signal SC4(n) of the first embodiment is supplied is replaced by the scan signal line 333A to which the scan signal SC4A is supplied, and the falling and rising timings of the scan signal SC4A are different from those of the first embodiment. (Configuration 4) Does not include the initialization potential VINI and the initialization potential line SVI to which the initialization potential VINI is supplied. (Configuration 5) Includes a constant potential VSL and a constant potential line PVS to which the constant potential VSL is supplied. (Configuration 6) Includes a seventh transistor T7, where the second transistor T2 and the seventh transistor T7 are p-channel field-effect transistors.

[0175] The configurations of the display device 20 other than configurations 1 to 6, and the configurations of the display device 20 other than those related to configurations 1 to 6, are the same as those of the display device 10 according to the first embodiment. When describing the configuration and functions of the display device 20, the same configurations and functions as those of the display device 10 will be described as necessary, and the description of the same configurations and functions as those of the display device 10 may be omitted.

[0176] [2-1. Configuration of Pixel 180A] Refer to Figures 18 to 20 to explain the outlines of pixel 180A and pixel circuit 181A.

[0177] As described in Configurations 1 to 5 above, the display device 20 includes a scan signal line 333A to which the scan signal SC4A is supplied, and a constant potential line PVS to which the constant potential VSL is supplied. The pixel circuit 181A is electrically connected to the same scan signal lines 330-332 and 334, drive potential line PVDD, reference potential line PVSS, reset potential line SVRE and reference potential line SVR as the pixel circuit 181, as well as the scan signal line 333A and constant potential line PVS. On the other hand, as described in Configurations 1 to 5 above, the display device 20 does not include a scan signal SC4(n) and a scan signal line 333 to which the scan signal SC4(n) is supplied, and an initialization potential line SVI to which the initialization potential VINI is supplied. Scan signal lines 330-332 and 334, as well as scan signal line 333A, in the display device 20 extend from the control circuit 120 in a second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2.

[0178] For example, the constant potential line PVS is electrically connected to a different connection wiring 342 than the reset potential line SVRE, the reference potential line SVR, the drive potential line PVDD, and the reference potential line PVSS. Alternatively, for example, the constant potential line PVS may be connected to a different connection wiring 342 than the reset potential line SVRE, the reference potential line SVR, the drive potential line PVDD, and the reference potential line PVSS.

[0179] For example, similar to the reset potential VRES, reference potential VREF, drive potential VDDEL, and reference potential VSSEL, the constant potential VSL may be supplied from an external device to the IC chip 110 via the FPC 200, terminal section 150, and connection wiring 341, and from the IC chip 110 to a plurality of pixels 180A (pixel circuits 181A) via the constant potential line PVS, or it may be generated in the IC chip 110 and supplied from the IC chip 110 to a plurality of pixels 180A (pixel circuits 181A) via the constant potential line PVS. Although not shown in the diagram, the constant potential VSL may be connected from an external device via the FPC 200, terminal section 150, and connection wiring 341, without going through the IC chip 110 and connection wiring 342, to the constant potential line PVS, and supplied to a plurality of pixels 180A (pixel circuits 181A). For example, the constant potential VSL is the same potential as the drive potential VDDEL.

[0180] As shown in Figure 20, pixel 180A (pixel circuit 181A) includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitive element CV, a capacitive element CD, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (source electrode and drain electrode) consisting of a first electrode and a second electrode. Each of the capacitive element CV, the capacitive element CD, and the light-emitting element OLED has a pair of electrodes consisting of a first electrode and a second electrode. Note that the capacitive element CV may be referred to as the first capacitive element, and the capacitive element CD may be referred to as the second capacitive element.

[0181] The fourth transistor T4 has the function of connecting the fifth node N5 and the constant potential line PVS to supply a constant potential VSL to the fifth node N5, making the potential supplied to the first electrode 32 and the potential supplied to the second electrode 34 of the light-emitting element OLED the same, thereby stopping the light emission of the light-emitting element OLED during periods PIN, PVH, and PWR.

[0182] The fifth transistor T5 has the function of making the fourth node N4 and the fifth node N5 conductive.

[0183] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The first electrode 624 is electrically connected to the third node N3, the first electrode 42 of the capacitive element CV, and the first electrode 674 of the seventh transistor T7. The second electrode 626 is electrically connected to the fourth node N4 and the second electrode 656 of the fifth transistor T5. The threshold voltage of the second transistor T2 is VTH, which is -1V (design value). The second transistor T2 controls the amount of current flowing to the light-emitting element OLED according to the potential difference Vgs and the potential difference Vds between the potential supplied to the second electrode 626 (fourth node N4) and the potential supplied to the first electrode 624 (third node N3). For example, if the potential difference Vgs is less than the threshold voltage VTH (expressed as a gate potential Vg relative to the source potential Vs, it is greater than -1V), the second transistor T2 becomes non-conductive. In this case, no current flows through the light-emitting element OLED, and pixel 180 displays black. For example, when the potential Vgs (hereinafter referred to as the gate potential Vg relative to the source potential Vs) is lower than the threshold voltage VTH and the potential Vds (hereinafter referred to as the drain potential Vd relative to the source potential Vs) is lower than 0V, the second transistor T2 becomes conductive, and the current flowing through the light-emitting element OLED is controlled according to the magnitude of the potential difference Vgs based on the display gradation, causing the light-emitting element OLED to emit light at a brightness based on the display gradation.

[0184] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the gate electrode 662 of the sixth transistor T6 and to the scan signal line 330. The first electrode 644 is electrically connected to the constant potential line PVS. The second electrode 646 is electrically connected to the fifth node N5, the first electrode 654 of the fifth transistor T5, and the second electrode 34 of the light-emitting element OLED. The switching of the fourth transistor T4 is controlled using the first scan signal SC1(n). In other words, the fourth transistor T4 is controlled to be in a conduction state (on state) or a non-conduction state (off state) by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the fourth transistor T4 is in a non-conducting state, and when the signal supplied to the first scan signal SC1(n) is HI, the fourth transistor T4 is in a conducting state.

[0185] The seventh transistor T7 includes a gate electrode 672, a first electrode 674, and a second electrode 676. The gate electrode 672 is electrically connected to the scan signal line 333A. The second electrode 676 is electrically connected to the drive potential line PVDD. The switching of the seventh transistor T7 is controlled using the fourth scan signal SC4A(n). In other words, the conduction state (on state) and non-conduction state (off state) of the seventh transistor T7 are controlled by the fourth scan signal SC4A(n). When the signal supplied to the fourth scan signal SC4A(n) is HI, the seventh transistor T7 is in a non-conducting state, and when the signal supplied to the fourth scan signal SC4A(n) is LO, the seventh transistor T7 is in a conduction state.

[0186] The method for driving the display device 20 includes obtaining a threshold voltage VTH by applying a constant potential VSL from the second electrode 626 (drain electrode) side of the second transistor T2 via a constant potential line PVS.

[0187] As described in configuration 6 above, the second transistor T2 and the seventh transistor T7 are p-channel type transistors. The first transistor T1 and the third to sixth transistors T3 to T6 shown in Figure 20 are n-channel type field-effect transistors. The channel regions of the second transistor T2 and the seventh transistor T7 contain p-type crystalline silicon. For example, p-type crystalline silicon is made p-type by impurities (e.g., boron (B)) being implanted. The channel regions of the first transistor T1 and the third to sixth transistors T3 to T6 each contain the same configuration as in the first embodiment. Also, for example, each transistor in the display device 20 is formed using thin-film transistors (TFTs), similar to each transistor in the display device 10. Similar to the display device 10, the display device 20 may have its transistor configuration, retention capacitance connection, power supply potential, etc., appropriately adapted according to the application and specifications.

[0188] The configuration and functions of pixel 180A (pixel circuit 181A), other than those described in "2-1. Configuration of Pixel 180A," are the same as those of pixel 180 (pixel circuit 181).

[0189] [2-2. Driving method of pixel circuit 181A] The driving method of the display device 20 will be explained with reference to Figures 21 to 24. Configurations identical or similar to those in Figures 1 to 20 will be explained as necessary. The horizontal axis of the timing chart represents time.

[0190] The driving method for the display device 20 includes the same period as the driving method for the display device 10 according to the first embodiment shown in Figure 4.

[0191] In the driving method of the display device 20, during a horizontal period (horizontal period HRP), the pixel 180A (pixel circuit 181A) receives an image data signal SL(m) including the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4A(n), the fifth scan signal SC5(n), and the data signal VDATA, as well as a constant potential VSL, a reset potential VRES, and a reference potential VREF. For example, the pixel 180A (pixel circuit 181A) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4A(n), and the fifth scan signal SC5(n). The image data signal SL(m) is input to the selected pixel 180A (pixel circuit 181A) according to the timing of each signal. The same operation is performed for all pixels 180A (pixel circuits 181A), and based on the image data signal SL(m) input to all pixels 180A (pixel circuits 181A), the image of the current frame corresponding to 1 FRAME is displayed in the display area 22 of the display device 10.

[0192] For example, the potential supplied to each signal and each node in each frame of the timing chart shown in Figures 21 to 24 is shown in Table 2.

[0193] [Table 2]

[0194] For example, as shown in Table 2, the threshold voltage VTH of the second transistor T2 is -1V, the reset potential VRES is 6V, the reference potential VREF is 4.8V, and the constant potential VSL is 0V. The potential VSIGH is 7V, and pixel 180 supplied with the potential VSIGH will not emit light and will appear black. Also, for example, the potential VSIGL is 3V, and pixel 180 supplied with the potential VSIGL will emit light and produce a white color. The setting values ​​for other potentials are the same as the setting values ​​shown in Table 1, which was explained in "1-5. Driving Method of Display Device 10". Note that, as with the potentials in display device 10, the potentials in display device 20 shown in Table 2 are examples, and the potentials related to display device 20 are not limited to those shown in Table 2. The potentials related to display device 20 can be appropriately selected according to the application and specifications of the display device 20.

[0195] [2-2-1. First example of a method for driving the display device 20] Referring to Figure 21 and Table 2, a first example of a method for driving the display device 20 will be described. The first example of a method for driving the display device 20 includes displaying images of different colors in consecutive frames, similar to the first example of a method for driving the display device 10 according to the first embodiment. Configurations identical or similar to those in Figures 1 to 20 will be described as necessary.

[0196] Similar to the first example of the driving method for the display device 10 according to the first embodiment, an image data signal SL(m) including a data signal VDATA is input to each pixel 180A (pixel circuit 181A) according to each period. The data signal VDATA is analog data including a potential between VSIGL and VSIGH. For example, in the period PWR, the potential supplied to the selected pixel 180A (pixel circuit 181A) is supplied to the image data signal SL(m). For example, in periods other than the period PWR, the data signal VDATA is supplied with a potential supplied to pixels other than the selected pixel 180A (pixel circuit 181A).

[0197] For example, during the light emission period PEM of the K-1stFRAME, the potential of the data signal VDATA is supplied to all pixels except the selected pixel 180A (pixel circuit 181A), the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4A(n) are supplied with LO, and the fifth scan signal SC5(n) is supplied with HI. The first transistor T1, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are in the off state, and the fifth transistor T5 and the seventh transistor T7 are in the on state. Furthermore, for example, at this time, the potential held at the first node N1 is potential Vi (e.g., 5.8V), the potential held at the second node N2 is potential Vn (e.g., 4.0V), the potential held at the third node N3 is potential Vj (e.g., 8V), and the potential difference Vgs is potential Vn - potential Vj (e.g., -4V). Therefore, with the second transistor T2 in the ON state, a current Ion based on the potential difference Vgs and potential difference Vds corresponding to the potential VSIGL (e.g., 3V) input during the horizontal period HRP of the K-1stFRAME can be flowed from the drive potential line PVDD to the light-emitting element OLED and the reference potential line PVSS. As a result, the light-emitting element OLED emits light. For example, pixel 180A (pixel circuit 181A) emits red light, and three pixels using a red-emitting pixel 180A, a blue-emitting pixel 180A, and a green-emitting pixel 180A emit white light. Furthermore, the potential held at the first node N1 is a potential Vi due to capacitive coupling by the capacitive elements CV and CD.

[0198] During the period between the emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, following the emission period PEM of the K-1stFRAME, the potential of the data signal VDATA is supplied to all pixels except the selected pixel 180A (pixel circuit 181A). Initially, the fifth scan signal SC5(n) changes from a state where HI is supplied to a state where LO is supplied. When the fifth scan signal SC5(n) is supplied with LO, the first scan signal SC1(n) changes from a state where LO is supplied to a state where HI is supplied.

[0199] As a result, during the period between the light emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, the fifth transistor T5 turns from the ON state to the OFF state, and after the fifth transistor T5 turns OFF, the fourth transistor T4 and the sixth transistor T6 turn from the OFF state to the ON state. The first transistor T1 and the third transistor remain OFF, and the second transistor T2 and the seventh transistor T7 remain ON. Therefore, the third node N3 conducts with the drive potential line PVDD, and the drive potential VDDEL (8V) is supplied to the third node N3. Since the potential Vj (8V) is already supplied to the third node N3, the potential supplied to the third node N3 continues to be Vj. Also, the fifth node N5 conducts with the constant potential line PVS, and the potential supplied to the fifth node N5 drops toward the constant potential VSL (0V) and becomes the constant potential VSL. Therefore, the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes zero, and the current Ion stops flowing from the drive potential line PVDD to the light-emitting element OLED, causing the light-emitting element OLED to stop emitting light. Also, the first node N1 becomes conductive with the reference potential line SVR, and the potential supplied to the first node N1 drops from potential Vi to potential Vk (reference potential VREF, 4.8V), becoming potential Vk (reference potential VREF, 4.8V). Here, since the first transistor T1 and the third transistor remain in the off state, the second node N2 is in a floating state, and due to the capacitive coupling between the first node N1 and the second node N2 by the capacitive element CD, the potential supplied to the second node N2 drops to a potential equivalent to the voltage drop across the first node N1 (potential difference between potential Vi and potential Vk), becoming potential Vm from potential Vn.

[0200] As described above, during the period between the emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, the first node N1 is supplied with a potential Vk (reference potential VREF), the second node N2 is supplied with a potential Vm, and the potential supplied to the third node N3 remains at a potential Vj.

[0201] During the period between the emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, in the period PIN of the KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the potential of the data signal VDATA to all pixels except the selected pixel 180A (pixel circuit 181A). The fourth scan signal SC4A(n) changes from a state where LO is supplied to a state where HI is supplied. When the fourth scan signal SC4A(n) is supplied with HI, the second scan signal SC2(n) changes from a state where HI is supplied to a state where LO is supplied. The first scan signal SC1(n) remains in a state where HI is supplied, and the third scan signal SC3(n) and the fifth scan signal SC5(n) remain in a state where LO is supplied.

[0202] As a result, the seventh transistor T7 turns from the ON state to the OFF state, and after the seventh transistor T7 turns OFF, the third transistor T3 turns from the OFF state to the ON state. Since the sixth transistor T6 remains ON, the potential supplied to the first node N1 remains at potential Vk. Also, since the fourth transistor T4 remains ON, the potential supplied to the fifth node N5 remains at 0V. Until the seventh transistor T7 turns OFF, the third node N3 is supplied with the drive potential VDDEL, and the third node N3 is initialized by the drive potential VDDEL. When the seventh transistor T7 turns OFF, the third node N3 is disconnected from the drive potential line PVDD. When the third transistor T3 turns ON, the second node N2 conducts to the reset potential line SVRE, and the potential supplied to the second node N2 gradually rises from potential Vm towards potential Vl (reset potential VRES, 6V) until it reaches potential Vl. Although the potential Vgs of the second transistor T2 is lower than the threshold voltage VTH, no current Ion flows because the seventh transistor T7 and the fifth transistor T5 are in the off state. Furthermore, similar to the period between the light emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting OLED is zero, so the light-emitting OLED does not emit light.

[0203] As described above, during the period PIN, the first node N1 is initialized with the reference potential VREF, the second node N2 is initialized with the reset potential VRES, and the third node N3 is initialized with the drive potential VDDEL.

[0204] During period PVH, following period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the same potential as the data signal VDATA supplied to pixels other than the selected pixel 180A (pixel circuit 181A). The fifth scan signal SC5(n) changes from a LO state to a HI state, and the fifth transistor T5 changes from an off state to an on state. Other scan signals and other transistors remain in the same state as during period PIN.

[0205] As a result, during period PVH, the first node N1 maintains potential Vk, and the second node N2 maintains potential Vl. Also, at the beginning of period PVH, the potential difference Vgs is 2V, and the second transistor T2 is ON. Because the second transistor T2, the fifth transistor T5, and the fourth transistor T4 are ON, the third node N3, the fourth node N4, and the fifth node N5 conduct, and electrode Ion flows from the third node N3, the fourth node N4, and the fifth node N5 to the constant potential line PVS. The potential supplied to the third node N3 has already been released, and at the moment the fifth transistor T5 changes from the OFF state to the ON state, the potential of the third node N3 begins to gradually decrease from potential Vj. When the potential Vgs reaches the threshold voltage VTH (-1V), the second transistor T2 turns OFF. At this time, the potential supplied to the third node N3 is potential Vc (potential Vl is -1V relative to potential Vc). Therefore, the driving method of the display device 10 can acquire the threshold voltage VTH by operation during period PVH and retain the acquired threshold voltage VTH. Furthermore, since the driving method of the display device 10 includes applying a correction to the second transistor T2 with the acquired threshold voltage VTH in the period after period PVH, the driving method of the display device 20 can achieve correction of the threshold voltage VTH by operation during period PVH. In reality, the threshold voltage VTH varies during manufacturing, but the first example of the driving method of the display device 20 is similar to the configuration described in "1-5-1. First Example of Driving Method of Display Device 10", in that the potential supplied to each node by operation during period PVH is a potential corresponding to the threshold voltage VTH that varies during manufacturing, and the driving method includes acquiring the threshold voltage VTH that varies during manufacturing and applying a correction with the acquired threshold voltage VTH. As a result, the first example of the driving method for the display device 20 can achieve correction of the threshold voltage VTH by operation during the period PVH, similar to the configuration described in "1-5-1. First Example of Driving Method for Display Device 10".

[0206] As described above, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitive element CV.

[0207] During the period between period PVH and period PWR, following period PVH, the potential of the data signal VDATA is supplied to all pixels except the selected pixel 180A (pixel circuit 181A). Initially, the fifth scan signal SC5(n) changes from a HI state to a LO state. When the fifth scan signal SC5(n) is supplied with LO, the second scan signal SC2(n) changes from a HI state to a LO state. Therefore, the fifth transistor T5 and the third transistor T3 change from the ON state to the OFF state. Other control signals and other transistors remain in the same state as during period PVH. The potential supplied to the first node N1 maintains potential Vk, the potential supplied to the second node N2 maintains potential Vl, and the potential supplied to the third node N3 maintains potential Vc, with a potential difference Vgs of 1V. Since the fourth transistor T4 remains ON and the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED is zero, the light-emitting element OLED does not emit light. Also, the fifth transistor T5 is OFF, and no current Ion flows from the third node N3, the fourth node N4, and the fifth node N5 to the constant potential line PVS.

[0208] During the period PWR, which follows the period between period PVH and period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a potential VSIGH (7V). The third scan signal SC3(n) changes from being supplied with LO to being supplied with HI, and the first transistor T1 changes from the off state to the on state. Other control signals and other transistors remain in the same state as during period PVH. The potential supplied to the first node N1 remains at potential Vk, and the potential supplied to the third node N3 remains at potential Vc. As the first transistor T1 changes from the off state to the on state, the second node N2 conducts to the image data signal line 321, and the potential supplied to the second node N2 gradually increases from potential Vl to potential VSIGH (potential Vc, 7V) until it reaches potential Vc. At this time, the capacitive element CD maintains a potential difference (2.2V relative to the potential supplied to the first node N1) by holding a charge equivalent to the potential difference between Vk (reference potential VREF, 4.8V) supplied to the first node N1 and the potential Vc (7V) supplied to the second node N2. Similarly, the capacitive element CV maintains a potential difference (-2.2V relative to the potential supplied to the third node N3) by holding a charge equivalent to the potential difference between Vk (reference potential VREF, 4.8V) supplied to the first node N1 and the potential Vc (7V) supplied to the third node N3. The sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (2.2V - 2.2V) is 0V, meaning the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state. Note that, similar to the period between period PVH and period PWR, the light-emitting element OLED does not emit light during period PWR.

[0209] As described above, during the PWR period, the data signal VDATA is written to pixel 180A (pixel circuit 181A). In addition, the capacitive element CD maintains (holds) the data potential of the data signal VDATA.

[0210] During the period following the PWR, the third scan signal SC3(n) changes from a HI state to a LO state. When the third scan signal SC3(n) is supplied with LO, the first scan signal SC1(n) changes from a HI state to a LO state. When the first scan signal SC1(n) is supplied with LO, the fourth scan signal SC4A(n) changes from a HI state to a LO state. The first transistor T1, the fourth transistor T4, and the sixth transistor T6 change from an ON state to an OFF state, and the seventh transistor T7 changes from an OFF state to an ON state. The other scan signals and other transistors remain in the same state as during the PWR. When the seventh transistor T7 is turned ON, the third node N3 conducts to the drive potential line PVDD (8V), and the potential supplied to the third node N3 gradually rises from potential Vc to potential Vj (drive potential VDDEL, 8V), reaching potential Vj (drive potential VDDEL, 8V). The first transistor T1, the fourth transistor T4, and the sixth transistor T6 are in the OFF state, and the first node N1 and the second node N2 are in a floating state. As the potential supplied to the third node N3 rises from potential Vc to potential Vj, the capacitive coupling between the third node N3 and the first node N1 (capacitive element CV) causes the potential supplied to the first node N1 to rise from potential Vk to potential Vi. Also, the capacitive coupling between the first node N1 and the second node N2 (capacitive element CD) causes the potential supplied to the second node N2 to rise from potential Vc to potential Vj. Furthermore, since the fourth transistor T4 and the fifth transistor T5 are in the off state, current Ion does not flow to the constant potential VSL and the light-emitting element OLED, and therefore the light-emitting element OLED does not emit light.

[0211] As a result, in the period following the PWR period, the potential supplied to the first node N1, which is capacitively coupled by capacitive elements CV and CD, becomes potential Vi, and the potential supplied to the second node N2 and the third node N3 becomes potential Vj. At this time, the potential difference Vgs is 0V, and the second transistor T2 is in the off state.

[0212] During the KthFRAME emission period PEM, which follows the KthFRAME period PWR, the image data signal SL(m) (data signal VDATA) is supplied with the same potential as the data signal VDATA supplied to all pixels except the selected pixel 180A (pixel circuit 181A). Also, the fifth scan signal SC5(n) changes from a state where LO is supplied to a state where HI is supplied. Therefore, the fifth transistor T5 changes from an off state to an on state. Other scan signals and other transistors remain in the same state as during the KthFRAME period PWR.

[0213] As a result, the fifth transistor T5 turns on, and the second electrode 34 of the light-emitting element OLED (the fifth node N5) conducts to the second electrode 626 of the second transistor T2 (the fourth node N4). Since the seventh transistor T7 is on and the third node N3 is electrically connected to the drive potential line PVDD, the potential supplied to the third node N3 maintains the drive potential VDDEL. Also, the potential supplied to the second node N2 maintains the potential Vj due to the capacitive coupling of the capacitive elements CD and CV. The first node N1 maintains the potential Vi due to the capacitive coupling of the capacitive elements CD and CV. The potential difference Vgs is the sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (reference potential VREF (4.8V) - (reset potential VRES (6V) - threshold voltage VTH (-1V)) + potential of the data signal VDATA (potential VSIGH, 7V) - reference potential VREF (4.8V) = 0V). Pixel 180A (pixel circuit 181A) containing the data signal VDATA and potential VSIGL has a potential difference Vgs of 0V, and the second transistor T2 is in the off state, so no ion flows through the drain electrode Ion. Therefore, the light-emitting element OLED does not emit light. As a result, the red-emitting pixel 180A (pixel circuit 181A), the blue-emitting pixel 180A (pixel circuit 181A), and the green-emitting pixel 180A (pixel circuit 181A) do not emit light, and pixel 180A becomes black using the three pixels: the red-emitting pixel 180A, the blue-emitting pixel 180A, and the green-emitting pixel 180A.

[0214] The display device 20, which includes the configuration described above, produces the same effects and benefits as described for the display device 10.

[0215] Furthermore, the display device 20 includes a p-channel type seventh transistor T7 and a second transistor T2, as well as an n-channel type fifth transistor T5. The driving method of the display device 20 also includes the fact that the charge transfer at the third node N3 during the PEM period is based on the operation of a p-channel type field-effect transistor (the seventh transistor T7), and the charge transfer at the fifth node N5 during the PEM period is based on the operation of an n-channel type field-effect transistor (the fifth transistor T5). Therefore, the driving method of the display device 20 allows the potential supplied to the third node N3 and the potential supplied to the fifth node N5 to be controlled using transistors with opposite polarities during the PEM period. As a result, when transitioning to the PEM period, the potential supplied to the second electrode 672 of the seventh transistor T7 and the potential supplied to the second electrode 652 of the fifth transistor T5 become opposing potentials. In other words, the signal supplied to the fourth scan signal SC4A(n) changes from HI to LO, and the signal supplied to the gate electrode 672 of the seventh transistor T7 changes from HI to LO, while the signal supplied to the fifth scan signal SC5(n) changes from LO to HI, and the signal supplied to the gate electrode 652 of the fifth transistor T5 changes from LO to HI. As a result, the potential fluctuations supplied from the gate electrodes to the third node N3 and the fifth node N5 can be canceled out by capacitive coupling, and the loss of holding voltage due to the decrease in write potential during the PEM period can be minimized.

[0216] [2-2-2. Second example of a method for driving the display device 20] Referring to Figure 22, a second example of the driving method for the display device 20 will be described. The driving method shown in the second example of the display device 20 includes displaying images of the same color (white) in consecutive frames, similar to the second example of the driving method for the display device 10 according to the first embodiment. Configurations identical or similar to those in Figures 1 to 21 will be described as necessary.

[0217] The light emission period PEM of the K-1thFRAME to the period PVH of the KthFRAME, and the potentials of each node during the period between the KthFRAME period PVH and the KthFRAME period PWR, are the same as those described in "2-2-1. First Example of Driving Method of Display Device 20". Furthermore, the configuration of each scan signal and the operation of each transistor during each period are the same as those described in "2-2-1. First Example of Driving Method of Display Device 20". Therefore, configurations similar to those described in "2-2-1. First Example of Driving Method of Display Device 20" will be explained as needed. Note that during the KthFRAME period PWR, the image data signal SL(m) is supplied as a data signal VDATA including the potential VSIGL (potential Vm, 3V) corresponding to white, and during periods other than the KthFRAME period PWR, the same data signal VDATA as described in "2-2-1. First Example of Driving Method of Display Device 20" is supplied.

[0218] In the K-1stFRAME's light emission period PEM, similar to the configuration described in "2-2-1. First Example of Driving Method for Display Device 20," pixel 180A emits white light using three pixels: a pixel 180A that emits red light, a pixel 180A that emits blue light, and a pixel 180A that emits green light.

[0219] During the period between the light emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, the first node N1 is supplied with a potential Vk (reference potential VREF), the second node N2 is supplied with a potential Vm (potential VSIGL, 3V), and the potential supplied to the third node N3 maintains a potential Vj.

[0220] In the KthFRAME period PIN, similar to the configuration described in "2-2-1. First Example of Driving Method of Display Device 20", the first node N1 is initialized with the reference potential VREF, the second node N2 is initialized with the reset potential VRES, and the third node N3 is initialized with the drive potential VDDEL.

[0221] In the period PVH following period PIN, the threshold voltage VTH of the second transistor T2 is obtained by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, similar to the configuration described in "2-2-1. First Example of Driving Method for Display Device 20," and a charge equivalent to the threshold voltage VTH is held in the capacitive element CV. In reality, the threshold voltage VTH varies during manufacturing, but the second example of driving method for display device 20, similar to the configuration described in "2-2-1. First Example of Driving Method for Display Device 20," includes the operation in period PVH to ensure that the potential supplied to each node corresponds to the threshold voltage VTH that varies during manufacturing, and to obtain the threshold voltage VTH that varies during manufacturing and apply a correction using the obtained threshold voltage VTH. As a result, the second example of driving method for display device 20, similar to the configuration described in "2-2-1. First Example of Driving Method for Display Device 20," can achieve threshold voltage VTH correction by an operation in period PVH.

[0222] During the period between period PVH and period PWR, following period PVH, the potential supplied to the first node N1 maintains potential Vk, the potential supplied to the second node N2 maintains potential Vl, the potential supplied to the third node N3 maintains potential Vc, and potential Vgs is -1V, similar to the configuration described in "2-2-1. First Example of Driving Method of Display Device 20".

[0223] During the period PWR, which follows the period between period PVH and period PWR, the image data signal SL(m) (data signal VDATA) is supplied with a potential VSIGL (potential Vm, 3V). The potential supplied to the first node N1 maintains potential Vk, and the potential supplied to the third node N3 maintains potential Vc. The potential supplied to the second node N2 gradually increases from potential Vl to potential Vm, becoming potential Vm (potential VSIGL, 3V). At this time, the capacitive element CD maintains the potential difference (-1.8V relative to the potential supplied to the first node N1) by holding a charge corresponding to the potential difference between Vk (reference potential VREF, 4.8V) supplied to the first node N1 and potential Vm (3V) supplied to the second node N2. Furthermore, the capacitive element CV maintains a potential difference (-2.2V relative to the potential supplied to the third node N3) by holding a charge equivalent to the potential difference between Vk supplied to the first node N1 and the potential Vc (7V) supplied to the third node N3. The sum of the potential difference held by the capacitive element CD and the potential difference held by the capacitive element CV (-1.8V - 2.2V) is -4V, and the potential difference Vgs is -4V. Therefore, the second transistor T2 is in the ON state.

[0224] As described above, during the PWR period, the data signal VDATA is written to pixel 180A (pixel circuit 181A). In addition, the capacitive element CD maintains (holds) the data potential of the data signal VDATA.

[0225] In the period following the PWR period, the seventh transistor T7 turns ON, causing the third node N3 to conduct to the drive potential line PVDD. The potential supplied to the third node N3 gradually increases from potential Vc towards the drive potential VDDEL (8V), reaching VDDEL (8V). The sixth transistor T6 is OFF, and the first node N1 and the second node N2 are floating. Therefore, as the potential supplied to the third node N3 becomes the drive potential VDDEL (8V), the potential supplied to the first node N1 increases from potential Vk to potential Vi due to capacitive coupling between the first node N1 and the third node N3 via the capacitive element CV. Additionally, the potential supplied to the second node N2 increases from potential Vm to potential Vn due to capacitive coupling between the second node N2 and the first node N1 via the capacitive element CD.

[0226] During the PEM period of the KthFRAME, which follows the PWR period, the potential supplied to the third node N3 is maintained at 8V. The potential supplied to the second node N2 is maintained at potential Vn through the capacitive coupling of capacitive elements CD and CV. The potential Vi is also maintained at potential Vi through the capacitive coupling of capacitive element CV in the first node N1. The potential difference Vgs is the sum of the potential difference held by capacitive element CD and the potential difference held by capacitive element CV (reference potential VREF (4.8V) - (reset potential VRES (6V) - threshold voltage VTH (-1V)) + potential of data signal VDATA (potential VSIGL, 3V) - reference potential VREF (4.8V) = -4V). Pixel 180A (pixel circuit 181A) containing the data signal VDATA and potential VSIGL has a potential difference Vgs of -4V, and the second transistor T2 is ON. As a result, current Ion flows from the drive potential line PVDD to the light-emitting element OLED and the reference potential line PVSS, causing the light-emitting element OLED to emit light. For example, a red-emitting pixel 180A, a blue-emitting pixel 180A, and a green-emitting pixel 180A each emit light, and three pixels using the red-emitting pixel 180A, blue-emitting pixel 180A, and green-emitting pixel 180A appear white.

[0227] The second example of the driving method for the display device 20 has the same effects as described in "2-2-1. First Example of Driving Method for Display Device 20". Furthermore, since the display device 20 and the driving method for the display device 20 have the light-emitting element OLED placed on the drain side of the second transistor T2, the potential supplied to the gate electrode 622 and the first electrode 624 of the second transistor T2 during the PWR period can be made close to the potential supplied to the gate electrode 622 and the first electrode 624 of the second transistor T2 during the PEM period. Therefore, the display device 20 and the driving method for the display device 20 can suppress power consumption from the PWR period to the PEM period, and can also suppress charge redistribution caused by the gate capacitance of the second transistor T2 (capacitance between the gate electrode 622 and the second electrode 624) due to potential fluctuations at the second node N2. As a result, the display device 20 and the driving method for the display device 20 can minimize voltage loss, which occurs when the writing voltage drops during light emission.

[0228] [2-2-3. A third example of a method for driving the display device 20] Referring to Figure 23, a third example of a method for driving the display device 20 will be described. The driving method shown in the third example of a method for driving the display device 20 includes displaying images of the same color (black) in consecutive frames, similar to the third example of a method for driving the display device 10 according to the first embodiment. Configurations identical or similar to those in Figures 1 to 22 will be described as necessary.

[0229] The potentials of each node during the KthFRAME period PVH to the KthFRAM light emission period PEM are the same as those described in "2-2-1. First Example of Driving Method for Display Device 20". Furthermore, the configuration of each scan signal and the operation of each transistor during each period are the same as those described in "2-2-1. First Example of Driving Method for Display Device 20". Therefore, configurations similar to those described in "2-2-1. First Example of Driving Method for Display Device 20" will be explained as needed.

[0230] In the K-1stFRAME's light-emitting period PEM, for example, the potential supplied to the first node N1 is potential Vi. Also, the potential supplied to the second node N2 and the third node N3 is potential Vj (8V), and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in the off state, no ions flow through the drain electrode Ion, and the light-emitting element OLED does not emit light.

[0231] As a result, the red-emitting pixel 180A (pixel circuit 181A), the blue-emitting pixel 180A, and the green-emitting pixel 180A do not emit light, so pixel 180A becomes black using three pixels: the red-emitting pixel 180A, the blue-emitting pixel 180A, and the green-emitting pixel 180A.

[0232] During the period between the emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, following the emission period PEM of the K-1stFRAME, the third node N3 is already supplied with the drive potential VDDEL (8V), so the potential supplied to the third node N3 continues to remain at potential Vj. Also, although the current Ion stops flowing from the drive potential line PVDD to the light-emitting element OLED and the reference potential line PVSS, causing the light-emitting element OLED to stop emitting light, the first node N1 becomes conductive with the reference potential line SVR, and the potential supplied to the first node N1 drops from potential Vi to potential Vk (reference potential VREF, 4.8V), becoming potential Vk. Since the first transistor T1 and the third transistor remain in the off state, the second node N2 is in a floating state, and the potential supplied to the first node N1 drops to potential Vk (reference potential VREF, 4.8V). Therefore, due to the capacitive coupling between the first node N1 and the second node N2 by the capacitive element CD, the potential supplied to the second node N2 changes from potential Vj to potential Vc.

[0233] As described above, during the period between the emission period PEM of the K-1stFRAME and the period PIN of the KthFRAME, the first node N1 is supplied with a potential Vk (reference potential VREF), the second node N2 is supplied with a potential Vc, and the potential supplied to the third node N3 remains at a potential Vj.

[0234] During the period between the KthFRAME period PIN and the KthFRAME period PIN, the potential supplied to the first node N1 remains at potential Vk (reference potential VREF). While the seventh transistor T7 is ON, the potential supplied to the third node N3 remains at drive potential VDDEL (i.e., initialized). When the seventh transistor T7 turns OFF and the third transistor T3 turns ON, the second node N2 conducts to the reset potential line SVRE, and the potential supplied to the second node N2 gradually decreases from potential Vc towards the reset potential VRES (potential Vl, 6V) to potential Vl. The potential Vgs of the second transistor T2 is lower than the threshold voltage VTH, but no current Ion flows because the seventh transistor T7 and the fifth transistor T5 are OFF. Furthermore, since the fourth transistor T4 is in the ON state, the potential supplied to the second electrode 34 remains at 0V, and the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED is zero, the light-emitting element OLED does not emit light.

[0235] As described above, during the period PIN, the first node N1 is initialized with the reference potential VREF, the second node N2 is initialized with the reset potential VRES, and the third node N3 is initialized with the drive potential VDDEL.

[0236] In the period PVH following period PIN, the threshold voltage VTH of the second transistor T2 is obtained by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, similar to the configuration described in "2-2-1. First Example of Driving Method for Display Device 20," and a charge equivalent to the threshold voltage VTH is held in the capacitive element CV. In reality, the threshold voltage VTH varies during manufacturing, but the third example of driving method for display device 20, similar to the configuration described in "2-2-1. First Example of Driving Method for Display Device 20," includes the operation in period PVH to ensure that the potential supplied to each node corresponds to the threshold voltage VTH that varies during manufacturing, and to obtain the threshold voltage VTH that varies during manufacturing and apply a correction using the obtained threshold voltage VTH. As a result, the third example of driving method for display device 20, similar to the configuration described in "2-2-1. First Example of Driving Method for Display Device 20," can achieve correction of the threshold voltage VTH by an operation in period PVH.

[0237] During the period between period PVH and period PWR, following period PVH, the potential supplied to the first node N1 maintains potential Vk, the potential supplied to the second node N2 maintains potential Vl, the potential supplied to the third node N3 maintains potential Vc, and the potential difference Vgs is -1V, similar to the configuration described in "2-2-1. First Example of Driving Method of Display Device 20".

[0238] During the period PWR, which follows the period between period PVH and period PWR, the data signal VDATA is written to the pixel 180A (pixel circuit 181A), similar to the configuration described in "2-2-1. First Example of Driving Method of Display Device 20". In addition, the capacitive element CD maintains (holds) the data potential of the data signal VDATA.

[0239] In the period following the PWR period, similar to the configuration described in "2-2-1. First Example of Driving Method for Display Device 20," the potential supplied to the first node N1, which is capacitively coupled by the capacitive element CV, becomes potential Vi, and the potential supplied to the second node N2 and the potential supplied to the third node N3 becomes potential Vj. At this time, the potential difference Vgs is 0V, and the second transistor T2 is in the off state.

[0240] In the PEM emission period of the KthFRAME following the PWR period, the potential difference Vgs is 0V and the second transistor T2 is in the off state, similar to the configuration described in "2-2-1. First Example of Driving Method of Display Device 20". Therefore, electrode Ion does not flow and the light-emitting element OLED does not emit light. As a result, pixel 180A becomes black, consisting of three pixels: a red-emitting pixel 180A, a blue-emitting pixel 180A, and a green-emitting pixel 180A.

[0241] The third example of the method for driving the display device 20 produces the same effects as those described in "2-2-1. First Example of Method for Driving the Display Device 20".

[0242] [2-2-4. A fourth example of a method for driving the display device 20] Referring to Figure 24, a fourth example of a method for driving the display device 20 will be described. The driving method shown in the fourth example of a method for driving the display device 20 includes displaying images of different colors in consecutive frames, similar to the fourth example of a method for driving the display device 10 according to the first embodiment. Configurations identical or similar to those in Figures 1 to 23 will be described as necessary.

[0243] The potentials of each node, the configuration of each scan signal, and the operation of each transistor during the light emission period PEM of K-1stFRAME to the light emission period PVH of KthFRAME are the same as those described in "2-2-3. Third Example of Driving Method of Display Device 20". Furthermore, the potentials of each node, the configuration of each scan signal, and the operation of each transistor during the period after the light emission period PVH of KthFRAME to the light emission period PEM of KthFRAME are the same as those described in "2-2-2. Second Example of Driving Method of Display Device 20". Therefore, further explanation is omitted here.

[0244] The fourth example of the method for driving the display device 20 produces the same effects as those described in "2-2-1. First Example of Method for Driving the Display Device 20".

[0245] As embodiments of the present invention, each embodiment or part of each embodiment described above can be combined and implemented as appropriate, insofar as they do not contradict each other.

[0246] Any effects or benefits different from those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0247] 10: Display device, 20: Display device, 22: Display area, 24: Peripheral area, 26: Terminal area, 32: First electrode, 34: Second electrode, 42: First electrode, 44: Second electrode, 52: First electrode, 54: Second electrode, 100: Array substrate, 101: Substrate, 101A: First surface, 101B: Second surface, 110: IC chip, 120: Control circuit, 121: Underlayer, 122: Semiconductor layer, 122A: Semiconductor layer, 122B: Semiconductor layer, 122C: Semiconductor layer, 122D: Semiconductor layer, 122E: Semiconductor layer, 123: Channel area, 124A: Impurity area, 125: Gate insulating layer, 126: Conductive layer, 127: Conductive layer, 127A: Gate wiring, 127B: Gate wiring, 127C: Gate wiring, 127D: Gate wiring, 127E: Gate wiring, 127F: Gate wiring, 127G: Gate wiring, 127H: Gate wiring, 127I: Gate wiring, 128: Insulating layer, 129: Third contact hole opening, 130: Shift register circuit, 131: Insulating layer, 132: Conductive layer, 132A: First wiring, 132B: First wiring, 132C: First wiring, 132D: First wiring, 132E: First wiring, 132F: First wiring, 132G: First wiring, 1 32H: First wiring, 132I: First wiring, 132J: First wiring, 132K: First wiring, 132M: First wiring, 135: First contact hole opening, 135A: First contact hole opening, 135B: First contact hole opening, 135C: First contact hole opening, 135D: First contact hole opening, 135E: First contact hole opening, 135F: First contact hole opening, 135G: First contact hole opening, 135H: First contact hole opening, 135I: First contact hole opening Hole, 135J: First contact hole opening, 135K: First contact hole opening, 135L: First contact hole opening, 135M: First contact hole opening, 135N: First contact hole opening, 135O: First contact hole opening, 135P: First contact hole opening, 135Q: First contact hole opening, 136: Insulating layer, 138: Second contact hole opening, 138A: Second contact hole opening, 138B: Second contact hole opening, 138C: Second contact hole opening,140: Conductive layer, 140A: First electrode, 140B: First electrode, 140BC: Protrusion, 140C: First electrode, 141: Insulating layer, 142: Conductive layer, 142A: Second electrode, 142AC: Protrusion, 143: Anode, 144: First layer, 145: Second layer, 146: Third layer, 147: Contact hole opening, 147A: Contact hole opening, 148: Functional layer, 149: Cathode ,150: Terminal section, 152: First inorganic insulating layer, 154: Organic insulating layer, 156: Second inorganic insulating layer, 158: Cover film, 160: Scan driver circuit, 165: Sealing film, 170: Array section, 180: Pixel, 180A: Pixel, 181: Pixel circuit, 181A: Pixel circuit, 190: Side wall section, 200: Flexible printed circuit board, 321: Image data signal line, 322: Image data signal line, 323: Image data signal line, 330: Scan signal line, 331: Scan signal line, 332: Scan signal line, 333: Scan signal line, 333A: Scan signal line, 334: Scan signal line, 341: Connection wiring, 342: Connection wiring, 612: Gate electrode, 614: First electrode, 616: Second electrode, 622: Gate electrode, 622-: Gate electrode, 624 : First electrode, 626: Second electrode, 632: Gate electrode, 634: First electrode, 636: Second electrode, 642: Gate electrode, 644: First electrode, 646: Second electrode, 652: Gate electrode, 654: First electrode, 656: Second electrode, 662: Gate electrode, 664: First electrode, 666: Second electrode, 672: Gate electrode, 674: First electrode, 676: Second electrode,

Claims

1. A first transistor is electrically connected between a first control signal, which controls the switching, and a second node, and an image data signal line to which a data potential is supplied. A second transistor having a gate electrode electrically connected to the second node and electrically connected between the third node and the fourth node, The switching is controlled using a second control signal, and a sixth transistor is electrically connected between a reference potential line to which a reference potential is supplied and the first node, A first capacitive element electrically connected between the first node and the third node, A second capacitive element electrically connected between the first node and the second node, Light-emitting element and, including, Pixel circuit.

2. The pixel circuit according to claim 1, wherein the light-emitting element is electrically connected between a reference potential line to which a reference potential is supplied and the third node.

3. A third control signal is used to control the switching, and a fifth transistor is electrically connected between a drive potential line, to which a drive potential higher than the reference potential is supplied, and the fourth node. The switching is controlled using a fourth control signal, and a third transistor is electrically connected between the reset potential line to which the reset potential is supplied and the second node, A fifth control signal is used to control the switching, and a fourth transistor is electrically connected between the initialization potential line to which the initialization potential is supplied and the third node, The pixel circuit according to claim 2, further comprising:

4. The first to sixth transistors are n-channel field-effect transistors. The pixel circuit according to claim 3.

5. The channel region of each of the first to sixth transistors is made of an oxide semiconductor. The pixel circuit according to claim 4.

6. The switching is controlled using a third control signal, and the system further includes a fifth transistor electrically connected between the fourth node and the fifth node. The pixel circuit according to claim 1, wherein the light-emitting element is electrically connected between a reference potential line to which a reference potential is supplied and the fifth node.

7. The switching is controlled using a fourth control signal, and a third transistor is electrically connected between the reset potential line to which the reset potential is supplied and the second node, The switching is controlled using the first control signal, and a fourth transistor is electrically connected between a constant potential line to which a constant potential is supplied and the fifth node, A fifth control signal is used to control the switching, and a seventh transistor is electrically connected between a drive potential line, to which a drive potential higher than the reference potential is supplied, and the third node. The pixel circuit according to claim 6, further comprising:

8. The first transistor, the third transistor to the sixth transistor are n-channel field-effect transistors, The second transistor and the seventh transistor are p-channel type field-effect transistors. The pixel circuit according to claim 7.

9. The channel regions of the first transistor, the third transistor to the sixth transistor, each have an oxide semiconductor. The channel regions of the second transistor and the seventh transistor, respectively, are made of crystalline silicon. The pixel circuit according to claim 8.

10. The device includes a plurality of pixels, each containing a pixel circuit as described in any one of claims 3 to 5. The plurality of pixels are arranged in a matrix in a first direction and a second direction intersecting the first direction. Display device.

11. The circuit further includes a control circuit that outputs the first to fifth control signals, The control circuit is configured to be controllable to hold a potential difference in the first capacitive element that corresponds to the threshold voltage of the second transistor, and then to hold a potential difference in the second capacitive element that corresponds to the data potential. The display device according to claim 10.

12. The aforementioned control circuit is Before maintaining a potential difference in the first capacitive element corresponding to the threshold voltage of the second transistor, the first transistor is turned off using the first control signal, the third transistor is turned off using the fourth control signal, the fifth transistor is turned off using the third control signal, the sixth transistor is turned on using the second control signal, the fourth transistor is turned on using the fifth control signal, the reference potential is supplied to the first node, and the initial initialization potential is supplied to the third node. Before maintaining a potential difference in the first capacitive element corresponding to the threshold voltage of the second transistor, and after supplying the reference potential to the first node, the fourth transistor is turned off using the fifth control signal, the third transistor is turned on using the fourth control signal, and the reset potential is supplied to the second node. Configured to be controllable, The display device according to claim 11.

13. The control circuit is configured to supply the reset potential to the second node, then use the third control signal to turn on the fifth transistor, and to control the first capacitive element to maintain a potential difference corresponding to the threshold voltage of the second transistor. The display device according to claim 12.

14. The control circuit is configured to control the following: maintaining a potential difference in the first capacitive element corresponding to the threshold voltage of the second transistor; then using the third control signal to turn off the fifth transistor; using the fourth control signal to turn off the third transistor; using the first control signal to turn on the first transistor; supplying the data potential to the second node; then using the first control signal to turn off the first transistor; and maintaining a potential difference in the second capacitive element corresponding to the data potential. The display device according to claim 11.

15. The device includes a plurality of pixels, each containing a pixel circuit as described in any one of claims 7 to 9. The plurality of pixels are arranged in a matrix in a first direction and a second direction intersecting the first direction. Display device.

16. The circuit further includes a control circuit that outputs the first to fifth control signals, The control circuit is configured to control the first capacitive element to hold a potential difference corresponding to the threshold voltage of the second transistor, and then to hold a potential difference corresponding to the data potential in the second capacitive element. The display device according to claim 15.

17. The aforementioned control circuit is Before maintaining a potential difference in the first capacitive element corresponding to the threshold voltage of the second transistor, the first transistor is turned off using the first control signal, the seventh transistor is turned on using the fifth control signal, the third transistor is turned off using the fourth control signal, the fifth transistor is turned off using the third control signal, and the fourth and sixth transistors are turned on using the second control signal, the reference potential is supplied to the first node, and the constant potential is supplied to the fifth node. Before maintaining a potential difference in the first capacitive element corresponding to the threshold voltage of the second transistor, and after supplying the reference potential to the first node and the constant potential to the fifth node, the seventh transistor is turned off using the fifth control signal, and the drive potential is supplied to the third node. Before maintaining a potential difference in the first capacitive element corresponding to the threshold voltage of the second transistor, and after stopping the supply of the drive potential to the third node, the third transistor is turned on using the fourth control signal, and the reset potential is supplied to the second node. Configured to be controllable, The display device according to claim 16.

18. The control circuit is configured to supply the reset potential to the second node, then use the third control signal to turn on the fifth transistor, and to control the first capacitive element to maintain a potential difference corresponding to the threshold voltage of the second transistor. The display device according to claim 17.

19. The control circuit is configured to control the following: maintaining a potential difference in the first capacitive element corresponding to the threshold voltage of the second transistor; then using the third control signal to turn off the fifth transistor; using the fourth control signal to turn off the third transistor; using the first control signal to turn on the first transistor; supplying the data potential to the second node; then using the first control signal to turn off the first transistor; and maintaining a potential difference in the second capacitive element corresponding to the data potential. The display device according to claim 18.

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