Interposer, semiconductor package containing the same, and method for manufacturing the same

Abstract

The present invention provides an interposer that can improve the SI / PI characteristics of a semiconductor package and reduce its size, a semiconductor package including the interposer, and a method for manufacturing the same. [Solution] The interposer according to the present invention comprises an interposer lower plate and an interposer upper plate disposed above the interposer lower plate and coupled to the interposer lower plate, wherein the interposer lower plate includes a first body layer, a first capacitor below the first body layer, a first wiring layer below the first capacitor, and a first pad on the upper surface of the first body layer, and the interposer upper plate includes a second body layer, a second capacitor above the second body layer, a second wiring layer above the second capacitor, and a second pad on the lower surface of the second body layer, wherein the coupling of the interposer lower plate and the interposer upper plate electrically connects the first pad and the second pad.

Description

Technical Field

[0001] The present invention relates to a semiconductor package, and more particularly, to an interposer in which a capacitor is disposed inside, a semiconductor package including the same, and a method of manufacturing the same.

Background Art

[0002] With the remarkable development of the electronics industry and in response to user needs, electronic devices are becoming smaller and lighter. As electronic devices become smaller and lighter, the semiconductor packages used in them are also miniaturized and lightened, and semiconductor packages are required to have high performance, large capacity, and high reliability.

[0003] In order to achieve miniaturization, light weight, high performance, large capacity, and high reliability, research and development on semiconductor chips including TSV structures and semiconductor packages having a structure in which these semiconductor chips are stacked have been continuous issues. Also, in such a semiconductor package, an interposer that connects semiconductor elements disposed on the upper part to each other or to a package substrate is mounted on the package substrate and used as an intermediate substrate.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems in the above-described conventional semiconductor packages, and an object of the present invention is to provide an interposer that can improve SI (signal integrity) / PI (power integrity) characteristics and reduce the size of a semiconductor package, a semiconductor package including the same, and a method of manufacturing the same.

Means for Solving the Problems

[0005] An interposer according to the present invention, made to achieve the above objective, comprises an interposer lower plate and an interposer upper plate disposed above the interposer lower plate and coupled to the interposer lower plate, wherein the interposer lower plate includes a first body layer, a first capacitor below the first body layer, a first wiring layer below the first capacitor, and a first pad on the upper surface of the first body layer, and the interposer upper plate includes a second body layer, a second capacitor above the second body layer, a second wiring layer above the second capacitor, and a second pad on the lower surface of the second body layer, wherein the coupling of the interposer lower plate and the interposer upper plate electrically connects the first pad and the second pad.

[0006] Furthermore, an interposer according to the present invention made to achieve the above objective comprises an interposer lower plate and an interposer upper plate disposed above the interposer lower plate and coupled to the interposer lower plate, wherein the interposer lower plate includes a first body layer, a first capacitor on the first body layer, a first wiring layer on the first capacitor, a first pad on the first body layer or the first wiring layer, and a first through electrode that penetrates the first body layer and connects the first wiring layer and the first pad, and the interposer upper plate includes a second body layer, a second capacitor on the second body layer, a second wiring layer on the second capacitor, a second pad on the second body layer or the second wiring layer, and a second through electrode that penetrates the second body layer and connects the second wiring layer and the second pad, wherein the first pad and the second pad are electrically connected by coupling the interposer lower plate and the interposer upper plate.

[0007] To achieve the above objective, the present invention provides a package substrate comprising: a package substrate; an interposer mounted on the package substrate and comprising an interposer lower plate and an interposer upper plate coupled to the interposer lower plate; and at least one semiconductor element mounted on the interposer, wherein the interposer lower plate includes a first body layer, a first capacitor below the first body layer, a first wiring layer below the first capacitor, and a first pad on the upper surface of the first body layer; the interposer upper plate includes a second body layer, a second capacitor above the second body layer, a second wiring layer above the second capacitor, and a second pad on the lower surface of the second body layer, wherein the first pad and the second pad are electrically connected by coupling the interposer lower plate and the interposer upper plate.

[0008] A method for manufacturing a semiconductor package according to the present invention, made to achieve the above objective, comprises the steps of: preparing an interposer substrate; mounting semiconductor elements on the interposer substrate; sealing the semiconductor elements on the interposer substrate with a sealing material; separating the interposer substrate and the semiconductor elements to manufacture an intermediate semiconductor package comprising an interposer and at least one semiconductor element; and mounting the intermediate semiconductor package on a package substrate, wherein the interposer comprises a first body layer, a first capacitor below the first body layer, and The interposer is characterized by comprising: an interposer lower plate including a first wiring layer below the first capacitor, a first pad on the upper surface of the first body layer, and a first through electrode that penetrates the first body layer and connects the first wiring layer and the first pad; and an interposer upper plate disposed above the interposer lower plate and coupled to the interposer lower plate, including a second body layer, a second capacitor above the second body layer, a second wiring layer above the second capacitor, a second pad on the lower surface of the second body layer, and a second through electrode that penetrates the second body layer and connects the second wiring layer and the second pad. [Effects of the Invention]

[0009] According to the interposer, semiconductor package including the same, and manufacturing method thereof according to the present invention, the interposer has a structure in which the interposer lower plate and the interposer upper plate are bonded via an HCB, and the interposer lower plate and the interposer upper plate include capacitors with an ISC structure. Therefore, when a System in Package (SiP) is constructed using the interposer, the interposer provides sufficient capacitors, thereby improving the SI (Signal Integrity) / PI (Power Integrity) characteristics without the need to place additional capacitors. Furthermore, since there is no need to place additional capacitors externally, the size of the SiP can be reduced by the size of the additional capacitors and the soldering area. Furthermore, by designing and arranging the first capacitor to be large and adjacent to the package substrate on the underside of the interposer, for example on the front side of the interposer's lower plate, the total capacitance of the capacitors in the SiP can be improved. In addition, the PI characteristics improve as the capacitor is placed closer to the power / ground, but when the second external connection terminal of the package substrate connected to the power / ground is used as a reference, the PI characteristics can be further improved by arranging the first capacitor on the front side of the interposer's lower plate. [Brief explanation of the drawing]

[0010] [Figure 1A] This is a cross-sectional view showing a schematic configuration of an interposer according to an embodiment of the present invention. [Figure 1B] This is a partially enlarged cross-sectional view of an interposer according to an embodiment of the present invention. [Figure 2A] This is a cross-sectional view showing a schematic configuration of an interposer according to one embodiment of the present invention. [Figure 2B] This is a partially enlarged cross-sectional view of an interposer according to one embodiment of the present invention. [Figure 3A] This is a cross-sectional view showing a schematic configuration of an interposer according to one embodiment of the present invention. [Figure 3B]This is a cross-sectional view showing a schematic configuration of an interposer according to one embodiment of the present invention. [Figure 4A] This is a cross-sectional view showing a schematic configuration of an interposer according to one embodiment of the present invention. [Figure 4B] This is a cross-sectional view showing a schematic configuration of an interposer according to one embodiment of the present invention. [Figure 4C] This is a cross-sectional view showing a schematic configuration of an interposer according to one embodiment of the present invention. [Figure 5] This is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Figure 6A] This is a cross-sectional view showing a more detailed structure of the second semiconductor element in the semiconductor package shown in Figure 5. [Figure 6B] This is a cross-sectional view showing a more detailed structure of the second semiconductor element in the semiconductor package shown in Figure 5. [Figure 6C] This is a cross-sectional view showing a more detailed structure of the second semiconductor element in the semiconductor package shown in Figure 5. [Figure 7A] This is a cross-sectional view showing the schematic configuration of a semiconductor package according to one embodiment of the present invention. [Figure 7B] This is a cross-sectional view showing the schematic configuration of a semiconductor package according to one embodiment of the present invention. [Figure 8A] This is a cross-sectional view illustrating a method for manufacturing an interposer substrate according to an embodiment of the present invention. [Figure 8B] This is a cross-sectional view illustrating a method for manufacturing an interposer substrate according to an embodiment of the present invention. [Figure 8C] This is a cross-sectional view illustrating a method for manufacturing an interposer substrate according to an embodiment of the present invention. [Figure 8D] This is a cross-sectional view illustrating a method for manufacturing an interposer substrate according to an embodiment of the present invention. [Figure 8E] This is a cross-sectional view illustrating a method for manufacturing an interposer substrate according to an embodiment of the present invention. [Figure 8F] This is a cross-sectional view illustrating a method for manufacturing an interposer substrate according to an embodiment of the present invention. [Figure 9A] It is a cross-sectional view for explaining a method of manufacturing an interposer substrate according to an embodiment of the present invention. [Figure 9B] It is a cross-sectional view for explaining a method of manufacturing an interposer substrate according to an embodiment of the present invention. [Figure 10] It is a cross-sectional view for explaining a method of manufacturing an interposer substrate according to an embodiment of the present invention. [Figure 11A] It is a cross-sectional view for schematically explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11B] It is a cross-sectional view for schematically explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11C] It is a cross-sectional view for schematically explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11D] It is a cross-sectional view for schematically explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11E] It is a cross-sectional view for schematically explaining a method of manufacturing a semiconductor package according to an embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0011] Next, specific examples of embodiments for implementing an interposer according to the present invention, a semiconductor package including the same, and a method of manufacturing the same will be described while referring to the drawings. For the same components in the drawings, the same reference numerals are used, and overlapping explanations thereof are omitted.

[0012] FIGS. 1A and 1B are a cross-sectional view and a partial enlarged cross-sectional view showing a schematic configuration of an interposer according to an embodiment of the present invention, and FIG. 1B is an enlarged view of part A of FIG. 1A. Referring to FIGS. 1A and 1B, an interposer 100 according to an embodiment of the present invention mediates signal transmission between semiconductor elements (see reference numerals 1300, 1400, and 1500 in FIG. 5) mounted on the upper part.

[0013] Furthermore, the interposer 100 mediates the transmission of signals, power, and other signals between the semiconductor elements (1300, 1400, 1500) and the package substrate (see 1200 in Figure 5). For example, the interposer 100 is mounted on a package substrate 1200 and connects semiconductor elements (1300, 1400, 1500) to the package substrate 1200. The interposer 100 includes an interposer lower plate (100-1) and an interposer upper plate (100-2). The interposer lower plate (100-1) and the interposer upper plate (100-2) each contain silicon (Si). Therefore, interposer 100 is an Si-interposer. The interposer lower plate (100-1) and the interposer upper plate (100-2) are joined by HCB (Hybrid Copper Bonding). Here, HCB refers to a bond that combines pad-to-pad and insulator-to-insulator bonding. On the other hand, since pads are usually formed from Cu, pad-to-pad bonds are also called Cu-to-Cu bonds. The HCB will be explained in more detail later in the section describing the connection between the first rear pad (130b-1) of the interposer lower plate (100-1) and the second rear pad (130b-2) of the interposer upper plate (100-2).

[0014] The interposer bottom plate (100-1) includes a first body layer (101-1), a first wiring layer (110-1), a first through electrode (120-1), a first pad (130-1), a first capacitor (140-1), and a first external connection terminal 150. The interposer bottom plate (100-1) has the front side (front-side) on the side with the first wiring layer (110-1). In other words, the bottom surface of the first wiring layer (110-1) corresponds to the front, and the top surface of the first body layer (101-1) corresponds to the back (back-side). The first body layer (101-1) contains, for example, Si. The first wiring layer (110-1) is located below the first body layer (101-1). The first wiring layer (110-1) is connected to the first through electrode (120-1) at the top and to the first front pad (130f-1) at the bottom. Furthermore, the first wiring layer (110-1) is connected to the first capacitor (140-1).

[0015] As shown in Figure 1B, the first wiring layer (110-1) includes an interlayer insulating layer 112, wiring 114, vias 116, and an aluminum (Al) pad 118. The interlayer insulating layer 112 may have a multilayer structure depending on the multilayer structure of the wiring 114. All layers of the interlayer insulating layer 112 may contain the same material, or at least one layer may contain a different material. The wiring 114 is arranged in a multilayer structure within the interlayer insulating layer 112. The wiring 114 of different layers is connected to each other via 116. The wiring 114 and via 116 include, for example, copper (Cu). However, the material of wiring 114 and via 116 is not limited to Cu. The Al pad 118 is located beneath the first wiring layer (110-1) and is connected to the wiring 114 via the via 116. The Al pad 118 is covered by the first front protective layer (135f-1). In some embodiments, the Al pad 118 is included in the wiring 114.

[0016] The first through electrode (120-1) extends vertically, i.e., in the z direction, through the first body layer (101-1). Since the first body layer (101-1) contains Si, the first through-electrode (120-1) corresponds to a TSV (Through Silicon Via). As shown in Figure 1B, the first through electrode (120-1) has a structure that is narrower at the top and wider at the bottom. This is due to the formation of a trench on the lower side to form the first through electrode (120-1). However, in some embodiments, the first through electrode (120-1) may have similar widths at its upper and lower portions. The first through electrode (120-1) is connected to the wiring 114 of the first wiring layer (110-1) on its lower side, and via the wiring 114, it is connected to the first front pad (130f-1) and the first external connection terminal 150 on the lower surface of the first wiring layer (110-1). Furthermore, the first through electrode (120-1) is connected at the top to the first back pad (130b-1) on the first body layer (101-1).

[0017] The first through electrode (120-1) has a columnar shape and includes a barrier film on its outer surface and an embedded conductive layer inside. The barrier film contains at least one substance selected from Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, and NiB. The embedded conductive layer comprises at least one material selected from Cu alloys such as Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuRe, CuW, W, W alloys, Ni, Ru, and Co. On the other hand, a first electrode insulating layer (122-1) is interposed between the first through electrode (120-1) and the first body layer (101-1), or between the first through electrode (120-1) and the first wiring layer (110-1). The first electrode insulating layer (122-1) includes, for example, an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. As shown in Figure 1B, the first electrode insulating layer (122-1) covers the side surface of the first through electrode (120-1) and extends over the upper surface of the first wiring layer (110-1).

[0018] The first pad (130-1) includes the first front pad (130f-1) and the first rear pad (130b-1). The first front pad (130f-1) is positioned on the underside of the first wiring layer (110-1). Furthermore, the first front pad (130f-1) is connected to wiring 114 via Al pad 118 and via 116. The first rear pad (130b-1) is positioned on the upper surface of the first body layer (101-1) and is connected to the first through electrode (120-1). The first pad (130-1) includes, for example, at least one of aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), and gold (Au). In the interposer 100 of this embodiment, the first pad (130-1) contains Cu. However, the material of the first pad (130-1) is not limited to Cu.

[0019] A first protective layer (135-1) is placed on the lower and upper surfaces of the interposer base plate (100-1). The first protective layer (135-1) includes the first rear protective layer (135b-1) and the first front protective layer (135f-1). The first rear protective layer (135b-1) is positioned on the upper surface of the first body layer (101-1). The first rear pad (130b-1) is positioned in a way that it penetrates the first rear protective layer (135b-1). For example, the first back pad (130b-1) penetrates the first back protective layer (135b-1) and is connected to the first through-electrode (120-1). The first front protective layer (135f-1) is positioned on the underside of the first wiring layer (110-1). The first front pad (130f-1) is positioned in such a way that it penetrates a portion of the first front protective layer (135f-1). For example, the first front pad (130f-1) penetrates a portion of the first front protective layer (135f-1) and connects to the Al pad 118 within the first front protective layer (135f-1). The first protective layer (135-1) includes, for example, an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. However, the material of the first protective layer (135-1) is not limited to that. The first protective layer (135-1) has a single film or multilayer structure.

[0020] The first capacitor (140-1) is placed within the first body layer (101-1). The first capacitor (140-1) includes, for example, an ISC (Integrated Stacked Capacitor). In the case of ISCs, due to their structure, they have a large capacitance, for example, a capacitance of several to tens of nF. The first capacitor (140-1) includes a lower electrode 142, an upper electrode 146, and a dielectric film 144. On the other hand, the lower electrode 142 and the upper electrode 146 contain polysilicon. Therefore, due to their structure and materials, the lower electrode 142 is referred to as the storage poly, and the upper electrode 146 is referred to as the plate poly. However, in some embodiments, the lower electrode 142 and the upper electrode 146 may include a metallic material.

[0021] The first capacitor (140-1) is placed within the first body insulating layer (141-1) on the first body layer (101-1). A first isolation insulating layer (103-1) is placed between the first body layer (101-1) and the first body insulating layer (141-1). However, in some embodiments, the first isolation insulating layer (103-1) may be omitted. On the other hand, a first plate electrode (145-1) is placed on the first isolation insulating layer (103-1). The first plate electrode (145-1) is connected to the lower electrode 142. The first cap through electrode (147-1) penetrates the portion of the first body insulating layer (141-1) on the upper electrode 146 and is connected to the upper electrode 146. Although not shown in the diagram, the second cap through electrode penetrates the first body layer (101-1) and the first body insulating layer (141-1) and is connected to the first plate electrode (145-1). In addition, although Figure 1B shows the first capacitor (140-1) as a structure with two V shapes connected, in reality, the first capacitor (140-1) has a structure with multiple V shapes connected.

[0022] The first external connection terminal 150 is located on the first front pad (130f-1) on the lower surface of the interposer lower plate (100-1). The first external connection terminal 150 is connected to the first through electrode (120-1) via the first front pad (130f-1) and the first wiring layer (110-1). The first external connection terminal 150 includes solder. Solder may contain tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), and / or alloys thereof. For example, solder includes Sn, Sn-Ag, Sn-Au, Sn-Cu, Sn-Bi, Sn-Zn, Sn-Ag-Cu, Sn-Ag-Bi, Sn-Ag-Zn, Sn-Cu-Bi, Sn-Cu-Zn, Sn-Bi-Zn, and the like. Handa is sometimes called Bump or Handa Bump. In some embodiments, the first external connection terminal 150 includes a pillar, and solder is placed on the pillar. The pillars include, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), or combinations thereof. In some embodiments, the pillar serves as a pad and contains Cu. In such cases, the pillar may be referred to as a bump pad, Cu pad, Cu pillar, etc. Furthermore, if the pillar serves as a pad, the first front pad (130f-1) may be omitted.

[0023] The interposer upper plate (100-2) is placed on the interposer lower plate (100-1). The interposer top plate (100-2) includes a second body layer (101-2), a second wiring layer (110-2), a second through electrode (120-2), a second pad (130-2), and a second capacitor (140-2). The interposer top plate (100-2) has the second wiring layer (110-2) side as the front. In other words, the top surface of the second wiring layer (110-2) corresponds to the front, and the bottom surface of the second body layer (101-2) corresponds to the back. The components of the interposer upper plate (100-2) are almost identical to those of the interposer lower plate (100-1). However, the upper interposer plate (100-2) is positioned in the opposite direction to the lower interposer plate (100-1). Specifically, the interposer lower plate (100-1) has its front facing downwards and its back facing upwards, while the interposer upper plate (100-2) has its front facing upwards and its back facing downwards.

[0024] Thus, in the interposer 100 of this embodiment, the interposer upper plate (100-2) and the interposer lower plate (100-1) are arranged in opposite directions to each other, so that the components of the interposer upper plate (100-2) and the corresponding components of the interposer lower plate (100-1) are arranged symmetrically with respect to the Z direction. For example, the first pad (130-1) and the second pad (130-2) are positioned symmetrically to each other. As a result, in terms of placement and function, the first rear pad (130b-1) corresponds to the second rear pad (130b-2), and the first front pad (130f-1) corresponds to the second front pad (130f-2). However, the first external connection terminal 150 is located on the first front pad (130f-1), and the external connection terminals (see reference numerals 1350, 1450, and 1550 in Figure 5) of the semiconductor elements (see reference numerals 1300, 1450, and 1500 in Figure 5) mounted on the interposer 100 are located on the second front pad (130f-2).

[0025] Therefore, the first front pad (130f-1) and the second front pad (130f-2) may differ from each other in size and pitch. For example, the size and pitch of the second front pad (130f-2) are smaller than those of the first front pad (130f-1). Furthermore, due to the differences between the first front pad (130f-1) and the second front pad (130f-2), the connection relationships and number of layers of wiring 114 in the first wiring layer (110-1) and the second wiring layer (110-2) may also differ. Furthermore, the interposer lower plate (100-1) connected to the first external connection terminal 150 may be formed with a greater thickness. As a result, as shown in Figure 1B, the first capacitor (140-1) has a larger size and capacitance than the second capacitor (140-2). However, the size and capacitance of the first capacitor (140-1) and the second capacitor (140-2) are not limited thereto. For example, in some embodiments, the first capacitor (140-1) and the second capacitor (140-2) may have substantially the same size and capacitance.

[0026] Furthermore, the details regarding the second body layer (101-2), second wiring layer (110-2), second through electrode (120-2), second pad (130-2), and second capacitor (140-2) are as described in the section describing the first body layer (101-1), first wiring layer (110-1), first through electrode (120-1), first pad (130-1), and first capacitor (140-1) of the interposer lower plate (100-1). On the other hand, in the interposer 100 of this embodiment, the interposer lower plate (100-1) and the interposer upper plate (100-2) are connected via an HCB as described above. For example, the first rear pad (130b-1) of the interposer lower plate (100-1) is bonded to the corresponding second rear pad (130b-2) of the interposer upper plate (100-2), and the first rear protective layer (135b-1) of the interposer lower plate (100-1) is bonded to the second rear protective layer (135b-2) of the interposer upper plate (100-2). HCB will be explained in more detail in the section describing the manufacturing method of the interposer substrate, shown in Figures 8A to 8F.

[0027] The interposer 100 in this embodiment is a 2.5D interposer. For reference, the term "interposer" includes 2.5D interposers and 2.3D interposers. Furthermore, in some embodiments, the interposer structure is further subdivided by including a Si bridge. As a result, structures other than 2.5D interposers are sometimes referred to as 2.xD interposers. A 2.5D interposer typically refers to a Si interposer, which contains TSVs internally. 2.3D interposer refers to an organic or inorganic interposer. 2. When a 3D interposer includes through-electrodes, the through-electrodes are referred to as TDV (Through Dielectric Via), TGV (Through Glass Via), etc., depending on the material of the body layer. In some embodiments, the 2.3D interposer may also be referred to as a PLP (Panel Level Package) interposer or an RDL (Re-Distribution Layer) interposer.

[0028] The interposer 100 of this embodiment has a structure in which the interposer lower plate (100-1) and the interposer upper plate (100-2) are connected via an HCB. Furthermore, the interposer lower plate (100-1) and the interposer upper plate (100-2) include capacitors (140-1) and (140-2) with an ISC structure. Therefore, when configuring a System in Package (SiP) using the interposer 100 of this embodiment, the interposer 100 provides sufficient capacitors, thereby improving the SI (Signal Integrity) / PI (Power Integrity) characteristics without the need to place additional capacitors. Furthermore, since there is no need to place additional capacitors externally, the size of the SiP can be reduced by the amount of the additional capacitor size and soldering area. Furthermore, by designing and arranging a large first capacitor (140-1) adjacent to the package substrate (see reference numeral 1200 in Figure 5) on the lower surface of the interposer 100, for example on the front side of the interposer lower plate (100-1), the total capacitance of the capacitors in the SiP can be increased. In addition, the PI characteristics improve as the capacitor is placed closer to the power / ground. However, when the second external connection terminal of the package substrate 1200 connected to the power / ground (see reference numeral 1250 in Figure 5) is used as a reference, the PI characteristics can be further improved by placing the first capacitor (140-1) on the front side of the interposer bottom plate (100-1).

[0029] Figures 2A and 2B are a cross-sectional view and a partially enlarged cross-sectional view showing the schematic configuration of an interposer according to one embodiment of the present invention, with Figure 2B being an enlarged view of portion B of Figure 2A. The information already explained in the explanatory sections of Figures 1A and 1B will be briefly explained or omitted. Referring to Figures 2A and 2B, the interposer 100a of this embodiment differs from the interposer 100 of Figure 1A in that the interposer lower plate (100-1) and the interposer upper plate (100-2) are connected via inter-plate connection terminals 160.

[0030] Specifically, the interposer 100a of this embodiment includes an interposer lower plate (100-1), an interposer upper plate (100-2), and an inter-plate connection terminal 160. The interposer lower plate (100-1) and interposer upper plate (100-2) are as described in the section describing the interposer lower plate (100-1) and interposer upper plate (100-2) of interposer 100 in Figure 1A. As a result, the interposer lower plate (100-1) and the interposer upper plate (100-2) each contain Si, and the interposer 100a in this embodiment also corresponds to a Si interposer. In the interposer 100a of this embodiment, the lower interposer plate (100-1) and the upper interposer plate (100-2) are connected via the inter-plate connection terminal 160. The inter-board connection terminal 160 is positioned between the first rear pad (130b-1) of the interposer lower plate (100-1) and the second rear pad (130b-2) of the interposer upper plate (100-2). The inter-board connection terminal 160 includes, for example, solder. The soldering is as described in the section explaining the first external connection terminal 150 of the interposer 100 in Figure 1A. In some embodiments, the inter-board connection terminal 160 further includes a pillar, and solder is placed on the pillar. The pillar is as described in the section explaining the first external connection terminal 150 of the interposer 100 in Figure 1A.

[0031] The interposer lower plate (100-1) and the interposer upper plate (100-2) are joined via the inter-plate connection terminal 160, thereby placing an adhesive layer 165 between the interposer lower plate (100-1) and the interposer upper plate (100-2). For example, the adhesive layer 165 fills the space between the interposer lower plate (100-1) and the interposer upper plate (100-2), and covers the sides of the inter-plate connection terminal 160. The adhesive layer 165 includes, for example, NCF (Non-Conductive Film). NCF is generally used as an adhesive layer when joining semiconductor chips using the TCB (Thermal Compression Bonding) method in the semiconductor chip stacking process. However, in the interposer 100a of this embodiment, the material of the adhesive layer 165 is not limited to NCF. Furthermore, in some embodiments, instead of the adhesive layer 165, a molding material such as underfill or EMC (Epoxy Molding Compound) may be filled between the interposer lower plate (100-1) and the interposer upper plate (100-2).

[0032] Figures 3A and 3B are cross-sectional views showing a schematic configuration of an interposer according to an embodiment of the present invention. The information already explained in the explanatory sections of Figures 1A to 2B will be briefly explained or omitted. Referring to Figure 3A, the interposer 100b of this embodiment differs from the interposer 100 of Figure 1A in that it further includes a first redistribution layer (100-3).

[0033] Specifically, the interposer 100b of this embodiment includes an interposer lower plate (100-1), an interposer upper plate (100a-2), and a first rewiring layer (100-3). The interposer lower plate (100-1) and interposer upper plate (100a-2) are as described in the section describing the interposer lower plate (100-1) and interposer upper plate (100-2) of interposer 100 in Figure 1A. However, as shown in Figure 3A, the second front pad (130f-2) is omitted in the interposer top plate (100a-2). However, in some embodiments, the second front pad (130f-2) may be maintained on the interposer upper plate (100a-2). The interposer lower plate (100-1) and the interposer upper plate (100a-2) each contain Si and are bonded together via HCB. Therefore, the interposer 100b in this embodiment corresponds to a Si interposer. On the other hand, in the interposer 100b of this embodiment, the interposer lower plate (100-1) and the interposer upper plate (100a-2) are not limited to being connected via an HCB, but may also be connected via an inter-plate connection terminal 160.

[0034] The first rewiring layer (100-3) is placed on the interposer top plate (100a-2). However, it is not limited to this, and the first rewiring layer (100-3) may also be placed on the interposer base plate (100-1). When the first rewiring layer (100-3) is placed on the interposer base plate (100-1), it may also be placed on the interposer base plate (100-1) with a structure similar to the second rewiring layer (100-4) of interposer 100c in Figure 3B. The first redistribution layer (100-3) includes a first redistribution body layer (101-3), a first redistribution line (110-3), and a first redistribution pad (130-3). The first rewiring body layer (101-3) comprises, for example, a PID (Photo Imageable Dielectric) or PIP (Photo Imageable Polyimide) resin and may further include an inorganic pillar. However, the material of the first redistribution body layer (101-3) is not limited to the above-mentioned material. For example, the first redistribution body layer (101-3) may contain PIQ (Polyimide Isoindro Quirazorindione), PI (Polyimide), PBO (Polybenzoxazole), etc.

[0035] The first redistribution line (110-3) is located within the first redistribution body layer (101-3). When the first redistribution lines (110-3) are arranged in multiple layers, the first redistribution lines (110-3) in other layers are connected to each other via vias. The first rewiring line (110-3) is connected to wiring 114 of the second wiring layer (110-2) of the interposer top plate (100-2). For reference, the first rewiring line (110-3) is connected to the Al pad 118 of the second wiring layer (110-2) via a via. If the second front pad (130f-2) is located on the second wiring layer (110-2), the first rewiring line (110-3) is connected to the second front pad (130f-2) via a via. On the other hand, the first redistribution pad (130-3) is positioned on the upper surface of the first redistribution layer (100-3). External connection terminals (1350, 1450, 1550) of semiconductor elements (1300, 1400, 1500) mounted on the interposer 100b may be placed on the first rewiring pad (130-3).

[0036] Referring to Figure 3B, the interposer 100c of this embodiment differs from the interposer 100b of Figure 3A in that it further includes a second redistribution layer (100-4). Specifically, the interposer 100c of this embodiment includes an interposer lower plate (100-1), an interposer upper plate (100-2), a first redistribution layer (100-3), and a second redistribution layer (100-4). The interposer lower plate (100-1), interposer upper plate (100-2), and first rewiring layer (100-3) are as described in the section describing the interposer lower plate (100-1), interposer upper plate (100-2), and first rewiring layer (100-3) in interposer 100b of Figure 3A. However, as shown in Figure 3B, the first front pad (130f-1) is omitted in the interposer lower plate (100a-1). However, in some embodiments, the first front pad (130f-1) may be maintained on the interposer lower plate (100a-1).

[0037] The interposer lower plate (100a-1) and the interposer upper plate (100a-2) each contain Si and are bonded together via HCB. Therefore, the interposer 100c in this embodiment corresponds to a Si interposer. On the other hand, in the interposer 100c of this embodiment, the interposer lower plate (100a-1) and the interposer upper plate (100a-2) are not limited to being connected via an HCB, but may also be connected via an inter-plate connection terminal 160. The second rewiring layer (100-4) is placed on the interposer top plate (100a-1). The second redistribution layer (100-4) includes a second redistribution body layer (101-4), a second redistribution line (110-4), and a second redistribution pad (130-4). The second redistribution layer (100-4) differs from the first redistribution layer (100-3) in its placement. Furthermore, the second rewiring pad (130-4) differs from the first rewiring pad (130-3) in terms of size, pitch, etc. Consequently, the connection relationships and / or number of layers of the second rewiring line (110-4) differ from those of the first rewiring line (110-3). Furthermore, the overall structure and materials of the second redistribution layer (100-4) are almost identical to those of the first redistribution layer (100-3).

[0038] The second rewiring line (110-4) is connected to wiring 114 of the first wiring layer (110-1) of the interposer bottom plate (100-1). For reference, the second redistribution line (110-4) is connected to the Al pad 118 of the first distribution layer (110-1) via a via. If the first front pad (130f-1) is located on the first wiring layer (110-1), the second rewiring line (110-4) is connected to the first front pad (130f-1) via a via. On the other hand, the second redistribution pad (130-4) is positioned on the underside of the second redistribution layer (100-4). As shown in Figure 3B, the first external connection terminal 150 is positioned on the second rewiring pad (130-4).

[0039] Figures 4A to 4C are cross-sectional views showing a schematic configuration of an interposer according to an embodiment of the present invention. The information already explained in the explanatory sections of Figures 1A to 3B will be briefly explained or omitted. Referring to Figure 4A, the interposer 100d of this embodiment differs from the interposer 100 of Figure 1A in the direction of connection between the interposer lower plate (100-1) and the interposer upper plate (100-2)a.

[0040] Specifically, the interposer 100d of this embodiment includes an interposer lower plate (100-1) and an interposer upper plate (100-2a). The interposer lower plate (100-1) and interposer upper plate (100-2a) are as described in the section describing the interposer lower plate (100-1) and interposer upper plate (100-2) of interposer 100 in Figure 1A, except for the direction of connection. The interposer lower plate (100-1) and the interposer upper plate (100-2a) each contain Si and are bonded together via HCB. Therefore, the interposer 100d in this embodiment corresponds to a Si interposer. On the other hand, in the interposer 100d of this embodiment, the interposer lower plate (100-1) and the interposer upper plate (100-2a) are not limited to being connected via an HCB, but may also be connected via an inter-plate connection terminal 160.

[0041] In the interposer 100d of this embodiment, the interposer lower plate (100-1) and the interposer upper plate (100-2a) are connected via the back and front surfaces. Specifically, in the interposer 100d of this embodiment, the back surface of the interposer lower plate (100-1) and the front surface of the interposer upper plate (100-2a) are connected. As a result, the first rear pad (130b-1) of the interposer lower plate (100-1) is coupled to the corresponding second front pad (130f-2) of the interposer upper plate (100-2a). Furthermore, the first protective layer (135-1) of the interposer lower plate (100-1), for example, the first rear protective layer (135b-1), is bonded to the second protective layer (135-2) of the interposer upper plate (100-2a), for example, the second front protective layer (135f-2). On the other hand, in the interposer 100d of this embodiment, external connection terminals (1350, 1450, 1550) for semiconductor elements (1300, 1400, 1500) are arranged on the second rear pad (130b-2) on the back of the interposer upper plate (100-2a). Furthermore, the second back pad (130b-2) is directly connected to the second through-electrode (120-2). As a result, the second back pad (130b-2) and the second through electrode (120-2) are arranged at a narrower pitch compared to the second back pad (130b-2) and the second through electrode (120-2) on the interposer top plate (100-2) of the interposer 100 in Figure 1A.

[0042] Referring to Figure 4B, the interposer 100e of this embodiment differs from the interposer 100 of Figure 1A in the direction of connection between the interposer lower plate (100-1a) and the interposer upper plate (100-2a). Specifically, the interposer 100e of this embodiment includes an interposer lower plate (100-1a) and an interposer upper plate (100-2a). The interposer lower plate (100-1a) and interposer upper plate (100-2a) are as described in the section describing the interposer lower plate (100-1) and interposer upper plate (100-2) of interposer 100 in Figure 1A, except for the direction of connection. The interposer lower plate (100-1a) and the interposer upper plate (100-2a) each contain Si and are bonded together via HCB. Therefore, the interposer 100e of this embodiment corresponds to a Si interposer. On the other hand, in the interposer 100e of this embodiment, the interposer lower plate (100-1a) and the interposer upper plate (100-2a) are not limited to being connected via an HCB, but may also be connected via an inter-plate connection terminal 160.

[0043] In the interposer 100e of this embodiment, the interposer lower plate (100-1a) and the interposer upper plate (100-2a) are connected via their front surfaces. Specifically, in the interposer 100e of this embodiment, the front surface of the interposer lower plate (100-1a) and the front surface of the interposer upper plate (100-2a) are connected. As a result, the first front pad (130f-1) of the interposer lower plate (100-1a) is coupled to the corresponding second front pad (130f-2) of the interposer upper plate (100-2a). Furthermore, the first protective layer (135-1) of the interposer lower plate (100-1a), for example, the first front protective layer (135f-1), is bonded to the second protective layer (135-2) of the interposer upper plate (100-2a), for example, the second front protective layer (135f-2). On the other hand, in the interposer 100e of this embodiment, external connection terminals (1350, 1450, 1550) for semiconductor elements (1300, 1400, 1500) are arranged on the second rear pad (130b-2) on the back of the interposer upper plate (100-2a). Furthermore, the second back pad (130b-2) is directly connected to the second through-electrode (120-2). As a result, the second back pad (130b-2) and the second through electrode (120-2) are arranged at a narrower pitch compared to the second back pad (130b-2) and the second through electrode (120-2) on the interposer top plate (100-2) of the interposer 100 in Figure 1A.

[0044] Referring to Figure 4C, the interposer 100f of this embodiment differs from the interposer 100 of Figure 1A in the direction of connection between the interposer lower plate (100-1a) and the interposer upper plate (100-2). Specifically, the interposer 100f of this embodiment includes an interposer lower plate (100-1a) and an interposer upper plate (100-2). The interposer lower plate (100-1a) and interposer upper plate (100-2) are as described in the section describing the interposer lower plate (100-1) and interposer upper plate (100-2) of interposer 100 in Figure 1A, except for the direction of connection. The interposer lower plate (100-1a) and the interposer upper plate (100-2) each contain Si and are bonded together via HCB. Therefore, the interposer 100f in this embodiment corresponds to a Si interposer. On the other hand, in the interposer 100f of this embodiment, the interposer lower plate (100-1a) and the interposer upper plate (100-2) are not limited to being connected via an HCB, but may also be connected via an inter-plate connection terminal 160.

[0045] In the interposer 100f of this embodiment, the interposer lower plate (100-1a) and the interposer upper plate (100-2) are connected via the front and back surfaces. Specifically, in the interposer 100f of this embodiment, the front surface of the interposer lower plate (100-1a) and the back surface of the interposer upper plate (100-2) are connected. As a result, the first front pad (130f-1) of the interposer lower plate (100-1a) is coupled to the corresponding second rear pad (130b-2) of the interposer upper plate (100-2). Furthermore, the first protective layer (135-1) of the interposer lower plate (100-1a), for example, the first front protective layer (135f-1), is bonded to the second protective layer (135-2) of the interposer upper plate (100-2), for example, the second rear protective layer (135b-2).

[0046] Figure 5 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. This explanation will refer to both Figure 1A and Figure 1B, and any information already explained in the explanatory sections of Figures 1A to 4C will be briefly explained or omitted. Referring to Figure 5, the semiconductor package 1000 of this embodiment includes an interposer 100, a package substrate 1200, semiconductor elements (1300, 1400, 1500), and an external encapsulant 1600.

[0047] Interposer 100 is, for example, the interposer 100 shown in Figure 1A. As a result, the interposer 100 includes an interposer lower plate (100-1) and an interposer upper plate (100-2), and the interposer lower plate (100-1) and the interposer upper plate (100-2) are connected via an HCB. In the semiconductor package 1000 of this embodiment, the interposer 100 is not limited to the interposer 100 shown in Figure 1A. For example, instead of the interposer 100 in Figure 1A, any of the interposers (100a to 100f) shown in Figures 2A, 3A, 3B, and 4A to 4C may be applied to the semiconductor package 1000.

[0048] The package substrate 1200 is a support substrate on which the interposer 100, semiconductor elements (1300, 1400, 1500), etc., are stacked. The package substrate 1200 includes at least one layer of wiring lines inside. When wiring lines are formed in multiple layers, wiring lines in other layers are connected to each other via vias. The package substrate 1200 is formed based on, for example, a ceramic substrate, a PCB, an organic substrate, an interposer substrate, and the like. A second external connection terminal 1250 is located on the lower surface of the package substrate 1200. The semiconductor package 1000 of this embodiment is stacked on an external system board, main board, etc., via the second external connection terminal 1250.

[0049] The interposer 100 is mounted on the package substrate 1200 via the first external connection terminal 150. The semiconductor elements (1300, 1400, 1500) are mounted on the package substrate 1200 via the interposer 100. The interposer 100 connects semiconductor elements (1300, 1400, 1500) to each other. Furthermore, the interposer 100 connects the semiconductor elements (1300, 1400, 1500) to the package substrate 1200. In the semiconductor package 1000 of this embodiment, the interposer 100 is used for the purpose of converting or transmitting electrical signals between semiconductor elements (1300, 1400, 1500). As a result, the interposer 100 may not contain any active elements. However, in some embodiments, the interposer 100 may include elements for controlling signal transmission. On the other hand, although not shown in the diagram, underfill may also be filled between the interposer 100 and the package substrate 1200, and between the first external connection terminal 150. In some embodiments, the underfill may be replaced by an adhesive layer or adhesive film.

[0050] The semiconductor devices (1300, 1400, 1500) include a first semiconductor device 1300, a second semiconductor device 1400, and a third semiconductor device 1500. The first semiconductor element 1300 is stacked in the central part of the interposer 100 via the third external connection terminal 1350. The first semiconductor device 1300 has a chip or package structure. In the semiconductor package 1000 of this embodiment, the first semiconductor element 1300 may have a chip structure. For example, the first semiconductor element 1300 includes a logic chip. The first semiconductor device 1300 may contain a large number of logic elements internally. Logic elements may include, for example, AND, NAND, OR, NOR, XOR (exclusive OR), XNOR (exclusive NOR), INV (inverter), ADD (adder), DLY (delay), FIL (filter), multiplexer (MXT / MXIT), OAI (OR / AND / INVERTER), AO (AND / OR), AOI (AND / OR / INVERTER), D flip-flop, reset flip-flop, master-slave flip-flop, latch, counter, or buffer elements.

[0051] Logic elements can perform various types of signal processing, including analog signal processing, A / D conversion (Analog-to-Digital Conversion), and control. The first semiconductor element 1300 may be referred to as a CPU (Central Processing Unit) chip, an MPU (Micro-Processor Unit) chip, a GPU (Graphics Processing Unit) chip, an NPU (Neural Processing Unit) chip, a SOG (System On Glass) chip, an ASIC (Application Specific Integrated Circuit) chip, an AP (Application Processor) chip, or a control chip, depending on its function. In the semiconductor package 1000 of this embodiment, the first semiconductor element 1300 may have a chip structure, as well as an SoC structure or a chiplet structure. The SoC structure has a design that integrates multiple systems onto a single chip. Therefore, the first semiconductor element 1300 in the SoC structure can process arithmetic functions, data storage, and analog-to-digital signal conversion within a single chip. On the other hand, a chiplet structure may have a configuration in which a logic chip is divided into multiple chips according to their function, and each chip is connected to the others. This chiplet-structured first semiconductor element 1300 can overcome the performance limitations of a single chip.

[0052] In the semiconductor package 1000 of this embodiment, the second semiconductor element 1400 is adjacent to the left side of the first semiconductor element 1300 and is stacked on the left portion of the interposer 100 via an external connection terminal 1450. Furthermore, the third semiconductor element 1500 is located adjacent to the right side of the first semiconductor element 1300 and is stacked on the right side of the interposer 100 via the fifth external connection terminal 1550. However, the placement positions of the second semiconductor element 1400 and the third semiconductor element 1500 are not limited to these. For example, the positions of the second semiconductor element 1400 and the third semiconductor element 1500 may be swapped. In the semiconductor package 1000 of this embodiment, one of the second semiconductor element 1400 and the third semiconductor element 1500 may be a memory element, and the other may be a logic element. Furthermore, in some embodiments, both the second semiconductor element 1400 and the third semiconductor element 1500 may be memory elements.

[0053] For example, if the second semiconductor element 1400 is a memory element and the third semiconductor element 1500 is a logic element, the second semiconductor element 1400 includes a memory package, such as an HBM (High Bandwidth Memory) package. However, the second semiconductor device 1400 is not limited to the HBM package. For example, the second semiconductor element 1400 may have a single-chip structure or a general package structure different from the HBM package. The second semiconductor element 1400, which has an HBM package structure, will be explained in more detail in the explanatory sections of Figures 6A to 6C.

[0054] On the other hand, the third semiconductor element 1500, which is a logic element, may include a logic chip. For example, the third semiconductor element 1500 includes a modem chip that supports communication with the first semiconductor element 1300. However, the types of the third semiconductor element 1500 are not limited to modem chips. For example, the third semiconductor element 1500 may include multiple types of logic chips for performing various signal processing in order to support the operation of the first semiconductor element 1300, together with the first semiconductor element 1300, or independently of the first semiconductor element 1300.

[0055] On the other hand, if both the second semiconductor element 1400 and the third semiconductor element 1500 are memory elements, both the second semiconductor element 1400 and the third semiconductor element 1500 may include an HBM package. In the semiconductor package 1000 shown in Figure 5, two memory elements are arranged adjacent to the first semiconductor element 1300, which is a logic element. However, the number of memory elements is not limited to two. For example, three or more memory elements may be arranged adjacent to the first semiconductor element 1300, which is a logic element. Furthermore, each of the three or more semiconductor elements includes an HBM package.

[0056] The external encapsulant 1600 seals the semiconductor elements (1300, 1400, 1500) on the interposer 100 so as to cover them. As shown in Figure 5, the external encapsulant 1600 may not cover the top surface of the semiconductor elements (1300, 1400, 1500). However, in some embodiments, the external encapsulant 1600 may cover at least one upper surface of the semiconductor element (1300, 1400, 1500).

[0057] On the other hand, the semiconductor package 1000 of this embodiment has a SiP structure including the interposer 100 shown in Figure 1A. As a result, as described above, the semiconductor package 1000 of this embodiment can improve SI / PI characteristics without the need for additional capacitors and reduce the size of the SiP. In relation to the reduction in SiP size, please refer to Figure 5 for further details, where the additional capacitors CAPd are shown by dotted lines on both sides of the package substrate 1200. Thus, when the additional capacitor CAPd is placed on the package substrate 1200, the area of ​​the package substrate 1200 may increase depending on the size and soldering area of ​​the additional capacitor CAPd. For example, if an additional capacitor CAPd is placed, the size of the package substrate will increase by an area corresponding to 2 × W1 in Figure 5, and consequently, the overall SiP size may increase. However, in the case of the semiconductor package 1000 of this embodiment, there is no need to place an additional capacitor CAPd, which contributes to reducing the size of the SiP. For reference, the structure of the semiconductor package 1000 as in this embodiment is called a 2.5D package structure. 2.5D package structure is a concept relative to 3D package structure, where all semiconductor chips are stacked together and there is no interposer. 2.5D package structures and 3D package structures can both be included in SiP structures.

[0058] Figures 6A to 6C are cross-sectional views showing the structure of the second semiconductor element in the semiconductor package shown in Figure 5 in more detail. This explanation will be given with reference to Figure 5, and any information already explained in the explanatory sections of Figures 1A to 5 will be briefly explained or omitted. Referring to Figure 6A, in the semiconductor package 1000 of this embodiment, the second semiconductor element 1400 may have an HBM package structure.

[0059] Specifically, the second semiconductor element 1400 includes a base chip 200, a memory chip 300, a first connection terminal 400, and an internal encapsulating material 500. The base chip 200 is larger than the memory chip 300 located on top, as shown in Figure 6A. However, the size of the base chip 200 is not limited to this. For example, in some embodiments, the base chip 200 has substantially the same size as the memory chip 300. The base chip 200 includes a chip body 201, an active layer 210, through-electrodes 220, connection pads 230, and a protective layer 240. The chip body 201 contains semiconductor elements such as Si or germanium (Ge). Furthermore, the chip body 201 may also contain compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The chip body 201 has an SOI (Silicon On Insulator) structure. For example, the chip body 201 includes a BOX layer (Buried Oxide Layer). The chip body 201 includes conductive regions, such as impurity-doped wells or impurity-doped source / drain regions. The chip body 201 may also include various element isolation structures, such as an STI (Shallow Trench Isolation) structure.

[0060] The active layer 210 includes an integrated circuit layer and a wiring layer on the integrated circuit layer. Generally, integrated circuit layers can contain various types of elements. For example, the integrated circuit layer may include various active and / or passive elements such as transistors, logic elements, memory elements, system LSIs (Large Scale Integration), CISs (CMOS Imaging Sensors), and MEMS (Micro-Electro-Mechanical Systems). Transistors may include, for example, BJTs (Bipolar Junction Transistors), or FETs such as planar FETs (Field Effect Transistors) and FinFETs. The logic elements are as described in the section describing the first semiconductor element 1300 in the semiconductor package 1000 shown in Figure 5 above.

[0061] Memory elements may include volatile memory elements such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), or non-volatile memory elements such as flash memory, PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), and RRAM (Resistive Random Access Memory). The wiring layer may connect at least two elements to each other, connect elements to a conductive region of the chip body 201, or connect elements to the first connection terminal 400. Furthermore, the wiring layer connects the through electrode 220 and the first connection terminal 400 to each other. The wiring layer includes, for example, wiring and contacts and vias. In the second semiconductor device 1400 of this embodiment, the active layer 210 is located below the chip body 201 and the through-electrode 220. However, in some embodiments, the active layer 210 may be located on top of the chip body 201 and the through-electrode 220.

[0062] In the second semiconductor device 1400 of this embodiment, the base chip 200 includes a large number of logic elements in the integrated circuit layer of the active layer 210. The base chip 200 is located below the memory chip 300 and can integrate signals from the memory chip 300 and transmit them externally, as well as transmit external signals and power to the memory chip 300. Therefore, the base chip 200 may be called a buffer chip or interface chip. On the other hand, in some embodiments, the base chip 200 includes a controller that controls signal transmission between the memory chip 300 and an external device. If the base chip 200 includes a controller, the base chip 200 may be referred to as a logic chip or control chip, etc. In some embodiments, the base chip 200 may also include a PMIC (Power Management Integrated Circuit) for managing power and clock. Furthermore, in some embodiments, the base chip 200 may include logic elements for calculations. For reference, if the base chip 200 is referred to as a buffer chip, etc., the memory chip 300 may be referred to as a core chip. In the second semiconductor element 1400 of this embodiment, the base chip 200 is not limited to a buffer chip or a logic chip. For example, the base chip 200 includes a large number of memory elements in the integrated circuit layer of the active layer 210. Therefore, the base chip 200 may also include a memory chip.

[0063] The through-electrode 220 penetrates the chip body 201 and extends from the top surface to the bottom surface of the chip body 201. In some embodiments, the through-electrode 220 extends into the interior of the active layer 210. In the second semiconductor device 1400 of this embodiment, the chip body 201 contains Si, and therefore the through-electrode 220 can be referred to as a TSV. Further details regarding the structure and materials of the through-electrode 220 are as described in the section explaining the first through-electrode (120-1) of the interposer lower plate (100-1) in Figure 1A. The connection pad 230 is located on the upper surface of the chip body 201 and is connected to the through electrode 220. The protective layer 240 is positioned on the upper surface of the chip body 201. Furthermore, the materials and structure of the connecting pad 230 and the protective layer 140 are as described in the section explaining the first pad (130-1) and the first protective layer 135 of the interposer lower plate (100-1) in Figure 1A. On the other hand, although not shown in the diagram, a protective layer may also be placed on the underside of the active layer 210.

[0064] The memory chip 300 is stacked on top of the base chip 200. In the second semiconductor element 1400 of this embodiment, eight memory chips 300, for example, the first to eighth memory chips (300-1 to 300-8), are stacked on a base chip 200. However, the number of memory chips 300 stacked on the base chip 200 is not limited to eight. For example, two to seven, or nine or more, memory chips 300 can be stacked on the base chip 200. For reference, in the second semiconductor element 1400, the number of memory chips 300 can be 4n (where n is a natural number). Therefore, the second semiconductor element 1400 may include memory chips 300 in multiples of 4, such as 4, 8, or 12. Furthermore, the four memory chips 300 each have the same stack ID and can be tested and operated together. For example, if the second semiconductor element 1400 includes eight memory chips 300, the first to fourth memory chips (300-1 to 300-4) have a first stack ID, and the fifth to eighth memory chips (300-5 to 300-8) have a second stack ID. However, the second semiconductor element 1400 is not limited to memory chips 300 with a number that is a multiple of 4 and their corresponding stack IDs. For example, the second semiconductor element 1400 may include memory chips 300 in multiples of 2 and their corresponding stack IDs, or it may include memory chips 300 in multiples of 8 and their corresponding stack IDs.

[0065] The first to eighth memory chips (300-1 to 300-8) are substantially identical in horizontal size and internal structure. However, the eighth memory chip (300-8), located at the very top, may not include through-hole electrodes. Furthermore, as shown in Figure 6A, the eighth memory chip (300-8) is thicker than the other memory chips 300. In some embodiments, the thickness of the eighth memory chip (300-8) is adjusted, and the overall height of the second semiconductor element 1400 is adjusted. In the following, for convenience, the specific structure of the memory chip 300 will be explained using the first memory chip (300-1).

[0066] The first memory chip (300-1) includes a chip body 301, an active layer 310, through-electrodes 320, connection pads 330, and a protective layer 340. The chip body 301 is as described for the chip body 201 of the base chip 200. The active layer 310 contains a large number of memory elements. For example, the active layer 310 may include volatile memory elements such as DRAM and SRAM, or non-volatile memory elements such as PRAM, MRAM, FeRAM, and RRAM. For example, in the second semiconductor element 1400, the first memory chip (300-1) includes a DRAM element in the active layer 310. Therefore, the first memory chip (300-1) may be a DRAM chip. Furthermore, since the second semiconductor element 1400 is in an HMB package, the first memory chip (300-1) may be an HBM DRAM chip.

[0067] The through-electrode 320 either penetrates the chip body 301 or extends through the chip body 301 into the interior of the active layer 310. For example, if the first memory chip (300-1) is divided into a cell region and a pad region, and through-electrodes 320 are formed only in the pad region, the through-electrodes 320 extend through the chip body 301 into the interior of the active layer 310. Further details regarding the through-electrode 320 are as described for the through-electrode 220 of the base chip 200. The connection pad 330 includes a lower connection pad 330d located on the lower surface of the active layer 310 and an upper connection pad 330u located on the upper surface of the chip body 301. In typical semiconductor chips, the chippads are located on the underside of the active layer. Therefore, the lower connection pad 330d corresponds to the chip pad of the first memory chip (300-1). The lower connection pad 330d connects to the wiring of the wiring layer of the active layer 310 on the underside of the chip body 301. Furthermore, the lower connection pad 330d is connected to the through electrode 320 via the wiring of the wiring layer. The upper connection pad 330u is connected to the through-electrode 320 on the upper surface of the chip body 301. Furthermore, the connection pad 330 is as described for the connection pad 230 of the base chip 200. The protective layer 340 includes a lower protective layer 340d positioned on the underside of the active layer 310 and an upper protective layer 340u positioned on the upper side of the chip body 301. Furthermore, the protective layer 340 is as described for the protective layer 240 of the base chip 200.

[0068] In the second semiconductor element 1400 of this embodiment, the memory chip 300 is stacked on the base chip 200 or the memory chip 300 below it via inter-chip connection terminals 360. For example, the inter-chip connection terminal 360 is located between the connection pad 230 of the base chip 200 and the lower connection pad 330d of the first memory chip (300-1). Furthermore, the inter-chip connection terminal 360 is positioned between the upper connection pad 330u of the lower memory chip 300 and the lower connection pad 330d of the upper memory chip 300 in two adjacent memory chips 300. The inter-chip connection terminal 360 is as described above for the inter-board connection terminal 160 of the interposer 100A in Figure 2A. For example, the inter-chip connection terminal 360 may include solder, or a pillar and solder. In the second semiconductor element 1400 of this embodiment, the memory chips 300 are stacked via inter-chip connection terminals 360, so that adhesive layers 610 are placed between the base chip 200 and the first memory chip (300-1), and between two adjacent memory chips 300.

[0069] For example, the adhesive layer 610 fills the space between the base chip 200 and the first memory chip (300-1), and between two adjacent memory chips 300, and covers the sides of the inter-chip connection terminals 360. Furthermore, as shown in Figure 6A, the adhesive layer 610 protrudes from the side of the memory chip 300 and covers the side of the memory chip 300. On the other hand, in some embodiments, the adhesive layer 610 protrudes from the side of the memory chip 300, but it can also cover only a portion of the side of each memory chip 300. In such cases, the upper adhesive layer 610 and the lower adhesive layer 610 do not adhere to each other on the side surface of each memory chip 300, but remain separated. The adhesive layer 610 includes, for example, NCF. However, the material of the adhesive layer 610 is not limited to NCF.

[0070] The first connection terminal 400 is located on the underside of the base chip 200. The first connection terminal 400 is connected to the wiring of the wiring layer of the active layer 210. Furthermore, the first connection terminal 400 is connected to the through electrode 220 via the wiring of the wiring layer. On the other hand, although not shown in the diagram, a chip pad may be placed on the underside of the base chip 200, and the first connection terminal 400 may be placed on the chip pad. The first connection terminal 400 has a structure similar to the inter-chip connection terminal 360 described above. For example, the first connection terminal 400 includes solder. In some embodiments, the first connection terminal 400 includes a pillar and solder. The pillar and solder of the first connection terminal 400 are as described for the first external connection terminal 150 of the interposer 100 in Figure 1A. The internal sealing material 500 surrounds the sides of the memory chip 300 on the base chip 200. As shown in Figure 6A, the internal sealing material 500 may not cover the top surface of the uppermost memory chip, for example, the eighth memory chip (300-8). Therefore, the upper surface of the eighth memory chip (300-8) may be exposed from the internal sealing material 500. However, in some embodiments, the internal sealing material 500 may cover the top surface of the uppermost memory chip, for example, the eighth memory chip (300-8). The internal sealing material 500 includes, for example, EMC. However, the materials used for the internal encapsulant 500 are not limited to EMC.

[0071] Referring to Figure 6B, in the semiconductor package 1000 of this embodiment, the second semiconductor element 1400a has an HBM package structure, but differs from the second semiconductor element 1400 in Figure 6A in that it further includes a top dummy chip 600. Specifically, the second semiconductor element 1400a includes a base chip 200, a memory chip 300, a first connection terminal 400, an internal encapsulating material 500, and a top dummy chip 600. The base chip 200, memory chip 300, first connection terminal 400, and internal encapsulating material 500 are as described in the section describing the second semiconductor element 1400 in Figure 6A. However, with the addition of the top dummy chip 600, the internal sealing material 500 has a structure that covers the sides of the top dummy chip 600.

[0072] In the second semiconductor device 1400a, the top dummy chip 600 is stacked on top of the memory chip 300 via an adhesive layer 620. The top dummy chip 600 is added to match the height specifications of the second semiconductor element 1400a. For example, in the case of HBM packages, the height and area are specified in the JEDEC (Solid State Technology Association) standard. Since the second semiconductor element 1400a is an HBM package, the height of the second semiconductor element 1400a can be adjusted to the JEDEC standard by placing a top dummy chip 600 of appropriate height on top of the memory chip 300. On the other hand, in the second semiconductor element 1400a, the addition of the top dummy chip 600 results in the eighth memory chip (300-8) having the same thickness as the other memory chips 300. However, this is not limited to the above, and in some embodiments, even when a top dummy chip 600 is included, the eighth memory chip (300-8) may be thicker than the other memory chips 300. However, if the overall height of the second semiconductor element can be adjusted by adjusting the thickness of the eighth memory chip (300-8), the top dummy chip 600 may be omitted.

[0073] Referring to Figure 6C, in the semiconductor package 1000 of this embodiment, the second semiconductor element 1400b has an HBM package structure, but differs from the second semiconductor element 1400 in Figure 6A in that the memory chip 300a is stacked via an HCB. Specifically, the second semiconductor element 1400b includes a base chip 200, a memory chip 300a, a first connection terminal 400, and an internal encapsulating material 500. The base chip 200, the first connection terminal 400, and the internal sealing material 500 are as described in the section describing the second semiconductor element 1400 in Figure 6A. However, since the memory chips 300a are stacked via the HCB without using the inter-chip connection terminals 360, there may be no adhesive layer filling the space between the memory chips 300a and the base chip 200, or between adjacent memory chips 300a.

[0074] In the second semiconductor device 1400b, the memory chip 300a is stacked on the base chip 200 or the memory chip 300a directly beneath it via an HCB. Furthermore, in some embodiments, the TCB method may be applied to the stacking of the memory chip 300a using HCB. To explain in more detail, as mentioned above, the connection pad 230 and protective layer 240 are positioned on the top surface of the base chip 200. Additionally, connection pads 330 and protective layers 340 are placed on the bottom and top surfaces of each memory chip 300a. The connection pads 230 of the base chip 200 are embedded in the protective layer 240, but their upper surfaces are exposed from the protective layer 240. Furthermore, the connection pads 330 of the memory chip 300a are also embedded in the protective layer 340, but their upper or lower surfaces are exposed from the protective layer 340. The protective layers (230, 330) may include insulating films such as SiO2, SiN, and SiCN. The connection pad 230 of the base chip 200 is coupled to the lower connection pad 330d of the first memory chip (300a-1), and the protective layer 240 of the base chip 200 is coupled to the lower protective layer 340d of the first memory chip (300a-1), thereby forming an HCB between the base chip 200 and the first memory chip (300a-1). Furthermore, in memory chip 300a, between two adjacent memory chips 300a, the upper connection pad 330u and upper protective layer 340u on the upper surface of the lower memory chip 300a are coupled with the lower connection pad 330d and lower protective layer 340d on the lower surface of the upper memory chip 300a, thereby forming an HCB (Heat Crossbridge).

[0075] Figures 7A and 7B are cross-sectional views showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. This explanation will be given with reference to Figure 5, and the content already explained in the explanatory sections of Figures 1A to 6C will be briefly explained or omitted. Referring to Figure 7A, the semiconductor package 1000a of this embodiment differs from the semiconductor package 1000 of Figure 5 in that it includes only the first semiconductor element 1300 and the second semiconductor element 1400. Specifically, the semiconductor package 1000a of this embodiment includes an interposer 100, a package substrate 1100, semiconductor elements (1300, 1400), and an external encapsulating material 1600.

[0076] Interposer 100 is, for example, the interposer 100 shown in Figure 1A. As a result, the interposer 100 includes an interposer lower plate (100-1) and an interposer upper plate (100-2), and the interposer lower plate (100-1) and the interposer upper plate (100-2) are connected via an HCB. In the semiconductor package 1000a of this embodiment, the interposer 100 is not limited to the interposer 100 shown in Figure 1A. For example, instead of the interposer 100 in Figure 1A, any of the interposers (100a to 100f) shown in Figures 2A, 3A, 3B, and 4A to 4C may be applied to the semiconductor package 1000a. On the other hand, the package substrate 1100 and the external encapsulant 1600 are as described in the section explaining the package substrate 1100 and the external encapsulant 1600 in the semiconductor package 1000 in Figure 5.

[0077] The semiconductor elements (1300, 1400) include a first semiconductor element 1300 and a second semiconductor element 1400. The first semiconductor element 1300 is stacked on the right side of the interposer 100 via the third external connection terminal 1350. The first semiconductor device 1300 has a chip or package structure. In the semiconductor package 1000a of this embodiment, the first semiconductor element 1300 has a chip structure. For example, the first semiconductor element 1300 includes a logic chip. The other first semiconductor elements 1300 are as described in Figure 5 for the first semiconductor elements 1300 of the semiconductor package 1000. The second semiconductor element 1400 may be a memory element. The second semiconductor device 1400 includes a memory package, such as an HBM package. However, the second semiconductor device 1400 is not limited to the HBM package. For example, the second semiconductor element 1400 may have a single-chip structure or a general package structure different from the HBM package. The second semiconductor element 1400 is as described in Figure 5 for the second semiconductor element 1400 of the semiconductor package 1000. Furthermore, the second semiconductor element 1400 with an HBM package structure is as described in the explanatory section regarding the second semiconductor elements (1400, 1400a, 1400b) in Figures 6A to 6C.

[0078] Referring to Figure 7B, the semiconductor package 1000b of this embodiment differs from the semiconductor package 1000 of Figure 5 in that it includes only the first semiconductor element 1300. Specifically, the semiconductor package 1000b of this embodiment includes an interposer 100, a package substrate 1100, a first semiconductor element 1300, and an external encapsulant 1600.

[0079] Interposer 100 is, for example, the interposer 100 shown in Figure 1A. As a result, the interposer 100 includes an interposer lower plate (100-1) and an interposer upper plate (100-2), and the interposer lower plate (100-1) and the interposer upper plate (100-2) are connected via an HCB. In the semiconductor package 1000b of this embodiment, the interposer 100 is not limited to the interposer 100 shown in Figure 1A. For example, instead of the interposer 100 in Figure 1A, any of the interposers (100a to 100f) in Figures 2A, 3A, 3B, and 4A to 4C may be applied to the semiconductor package 1000b. On the other hand, the package substrate 1100 and the external encapsulant 1600 are as described in the section explaining the package substrate 1100 and the external encapsulant 1600 in the semiconductor package 1000 in Figure 5. The first semiconductor element 1300 is stacked on the interposer 100 via the third external connection terminal 1350. The first semiconductor device 1300 has a chip or package structure. In the semiconductor package 1000b of this embodiment, the first semiconductor element 1300 may have a chip structure. For example, the first semiconductor element 1300 includes a logic chip. The other first semiconductor elements 1300 are as described in Figure 5 for the first semiconductor elements 1300 of the semiconductor package 1000.

[0080] Figures 8A to 8F are cross-sectional views illustrating a method for manufacturing an interposer substrate according to an embodiment of the present invention. This explanation will refer to both Figure 1A and Figure 1B, and any information already explained in the explanatory sections of Figures 1A through 7B will be briefly explained or omitted.

[0081] Referring to Figure 8A, the manufacturing method of the interposer substrate in this embodiment first involves forming a first through electrode (120-1) and a first capacitor (140-1) on an initial first body layer (101-1S) to form a first interposer lower plate substrate (100-1Sa). Here, the initial first body layer (101-1S) has a wafer-level size, and accordingly, the first interposer underlay substrate (100-1Sa) has a wafer-level size and may include a number of initial interposer underlays. The first through electrode (120-1) and the first capacitor (140-1) are as described in the explanation of the first through electrode (120-1) and the first capacitor (140-1) in the interposer lower plate (100-1) of the interposer 100 in Figure 1A.

[0082] Referring to Figure 8B, after the formation of the first through electrode (120-1) and the first capacitor (140-1), the first wiring layer (110-1) is formed on the initial first body layer (101-1S) to form the substrate for the second interposer lower plate (100-1Sb). The first wiring layer (110-1) is formed to a wafer-level size that covers the entire initial first body layer (101-1S). The first wiring layer (110-1) includes an interlayer insulating layer 112, wiring 114, vias 116, and Al pads 118. In Figure 8B, for convenience, only the interlayer insulation layer 112 and the wiring 114 are shown. The first wiring layer (110-1) is as described in the explanation regarding the first wiring layer (110-1) in the interposer lower plate (100-1) of the interposer 100 in Figure 1A.

[0083] Referring to Figure 8C, after the formation of the first wiring layer (110-1), a first pad (130-1), for example, a first front pad (130f-1), is formed on the first wiring layer (110-1). Subsequently, a first external connection terminal 150 is formed on the first front pad (130f-1). The first front pad (130f-1) and the first external connection terminal 150 are as described in the explanation of the first front pad (130f-1) and the first external connection terminal 150 on the interposer lower plate (100-1) of the interposer 100 in Figure 1A. The third interposer lower plate substrate (100-1Sc) is formed by forming the first front pad (130f-1) and the first external connection terminal 150.

[0084] Referring to Figure 8D, after the formation of the first external connection terminal 150, the third interposer lower plate substrate (100-1Sc) is inverted and bonded to the first carrier substrate 2000 via the adhesive layer 2500. Subsequently, grinding and etching processes are used to remove a portion of the back surface of the initial first body layer (101-1S), exposing the first through electrode (120-1). Next, a first rear protective layer (135b-1) and a first rear pad (130b-1) are formed on the back surface of the first body layer (101-1S). The first rear protective layer (135b-1) and the first rear pad (130b-1) are as described in the explanation of the first rear protective layer (135b-1) and the first rear pad (130b-1) in the interposer lower plate (100-1) of the interposer 100 in Figure 1A. The substrate for the interposer lower plate (100-1S) is formed by forming a first rear protective layer (135b-1) and a first rear pad (130b-1). The interposer base plate substrate (100-1S) has a wafer-level size and includes a number of interposer base plates (100-1).

[0085] Referring to Figure 8E, the substrate for the interposer top plate (100-2S) is formed through the processes shown in Figures 8A to 8D. However, when forming the substrate for the interposer top plate (100-2S), only the second front pad (130f-2) is formed in the process corresponding to Figure 8C. In other words, the interposer upper plate substrate (100-2S) does not have the first external connection terminal 150 formed on it. The substrate for the interposer top plate (100-2S) also has a wafer-level size and may include a large number of interposer top plates (100-2). Furthermore, the process of forming the substrate for the lower interposer plate (100-1S) and the process of forming the substrate for the upper interposer plate (100-2S) can be carried out independently and in parallel.

[0086] Referring to Figure 8F, the interposer upper plate substrate (100-2S) is then connected to the interposer lower plate substrate (100-1S) via an HCB. As shown in the figure, the back surface of the interposer upper plate substrate (100-2S) is connected to the back surface of the interposer lower plate substrate (100-1S) via an HCB. The interposer substrate 100S is manufactured by joining the interposer lower plate substrate (100-1S) and the interposer upper plate substrate (100-2S). The interposer substrate 100S has a wafer-level size and includes a number of interposers 100 as shown in Figure 1A. The interposer substrate 100S is then individualized through a dicing process along with the structure that will be mounted on top of it, resulting in the interposer 100 shown in Figure 1A.

[0087] To explain HCB in more detail, the interposer lower plate substrate (100-1S) and the interposer upper plate substrate (100-2S) undergo plasma treatment and ultrapure water cleaning before bonding, forming OH dangling bonds on the first back protective layer (135b-1) and the second back protective layer (135b-2). Subsequently, at room temperature, the interposer upper plate substrate (100-2S) is bonded to the interposer lower plate substrate (100-1S) so that the second rear pad (130b-2) is aligned with the first rear pad (130b-1). In the initial stages of bonding, the OH dangling bonds between the first back protective layer (135b-1) of the interposer lower plate substrate (100-1S) and the second back protective layer (135b-2) of the interposer upper plate substrate (100-2S) form hydrogen bonds. Hydrogen bonds have a relatively low bonding strength. Subsequently, heating through heat treatment (annealing) forms a strong bonding structure between the first back pad (130b-1) and the second back pad (130b-2). Specifically, heat treatment causes metal expansion and metal diffusion processes in the first back pad (130b-1) and the second back pad (130b-2), and these processes integrate the first back pad (130b-1) and the second back pad (130b-2). On the other hand, the hydrogen bonds between the first back protective layer (135b-1) and the second back protective layer (135b-2) are converted into oxide bonds by the heat treatment. For example, in simplified chemical terms, high-temperature heat treatment results in "-OH + -OH → O + H2O". Oxide bonds have a higher bonding strength compared to hydrogen bonds. As a result, the substrate for the lower interposer plate (100-1S) and the substrate for the upper interposer plate (100-2S) are firmly bonded together via the HCB, exhibiting high bonding strength.

[0088] Figures 9A and 9B are cross-sectional views illustrating a method for manufacturing an interposer substrate according to one embodiment of the present invention. This explanation will refer to both Figure 2A and Figure 2B, and the content already explained in the explanatory sections of Figures 8A to 8F will be briefly explained or omitted.

[0089] Referring to Figure 9A, the manufacturing method of the interposer substrate in this embodiment includes the step of forming the interposer upper plate substrate (100-2S) in Figure 8E, and then forming the inter-plate connection terminals 160 on the second back pad (130b-2). Referring to Figure 9B, the interposer upper plate substrate (100-2S) is then connected to the interposer lower plate substrate (100-1S) via the inter-plate connection terminal 160. The TCB method is applied to the connection via the inter-board connection terminal 160. Furthermore, the adhesive layer 165 is filled between the substrate for the lower interposer plate (100-1S) and the substrate for the upper interposer plate (100-2S). The adhesive layer 165 includes, for example, NCF. However, the adhesive layer 165 is not limited to NCF. Interposer substrate 100aS is manufactured by joining the interposer lower plate substrate (100-1S) and the interposer upper plate substrate (100-2S). The interposer substrate 100aS has a wafer-level size and includes a number of interposers 100a as shown in Figure 2A. The interposer substrate 100aS is then individualized through a dicing process along with the structure that will be mounted on top of it, resulting in the interposer 100a shown in Figure 2A.

[0090] Figure 10 is a cross-sectional view illustrating a method for manufacturing an interposer substrate according to one embodiment of the present invention. This explanation will be given with reference to Figure 3A, and the content already explained in the explanatory sections of Figures 8A to 8F will be briefly explained or omitted.

[0091] Referring to Figure 10, the manufacturing method of the interposer substrate in this embodiment includes the step of forming the interposer substrate 100S in Figure 8F, and then forming the first redistribution layer substrate (100-3S) on the second wiring layer (110-2) of the interposer upper plate substrate (100-2S). The first redistribution layer substrate (100-3S) is formed to a wafer-level size that covers the entire second distribution layer (110-2). The first redistribution layer substrate (100-3S) includes a first redistribution body layer (101-3), a first redistribution line (110-3), and a first redistribution pad (130-3). The first redistribution body layer (101-3), the first redistribution line (110-3), and the first redistribution pad (130-3) of the first redistribution layer (100-3) of the interposer 100b in Figure 3A are as described above. The interposer substrate 100bS is manufactured by forming the first redistribution layer substrate (100-3S). The interposer substrate 100bS has a wafer-level size and includes a number of interposers 100b shown in Figure 3A. The interposer substrate 100bS is then individualized through a dicing process along with the structure that will be mounted on top of it, resulting in the interposer 100b shown in Figure 3A.

[0092] Figures 11A to 11E are cross-sectional views illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention. This explanation will be given with reference to Figure 5, and any information already explained in the explanatory sections of Figures 1A to 10 will be briefly explained or omitted.

[0093] Referring to Figure 11A, the method for manufacturing the semiconductor package of this embodiment involves first mounting semiconductor elements (1300, 1400, 1500) onto the interposer substrate 100S. The semiconductor elements (1300, 1400, 1500) include, for example, a first semiconductor element 1300, a second semiconductor element 1400, and a third semiconductor element 1500, and are mounted on the interposer substrate 100S via external connection terminals (1350, 1450, 1550). The interposer substrate 100S has a wafer-level size and includes a number of interposers 100 as shown in Figure 1A. The semiconductor elements (1300, 1400, 1500) are as described in Figure 5 for semiconductor elements (1300, 1400, 1500) in semiconductor package 1000.

[0094] Referring to Figure 11B, after mounting the semiconductor elements (1300, 1400, 1500), an external sealing material 1600Sa is formed to seal the semiconductor elements (1300, 1400, 1500) on the interposer substrate 100S. The external encapsulant 1600Sa covers the sides and top surfaces of the semiconductor elements (1300, 1400, 1500). The materials for the external encapsulant 1600Sa are as described for the external encapsulant 1600 of the semiconductor package 1000 in Figure 5.

[0095] Referring to Figure 11C, after the formation of the external sealant 1600Sa, the upper portion of the external sealant 1600Sa is removed by a backgrinding process (B / G). By removing the upper portion of the external encapsulant 1600Sa, the upper surfaces of the semiconductor elements (1300, 1400, 1500) are exposed from the external encapsulant 1600S.

[0096] Referring to Figure 11D, after the backgrinding process (B / G), the interposer substrate 100S and its superstructure are individualized by the sawing process (S). Through individualization via a sawing process, an intermediate semiconductor package 1000M is manufactured, which includes the interposer 100 and its corresponding semiconductor elements (1300, 1400, 1500).

[0097] Referring to Figure 11E, after the intermediate semiconductor package 1000M is manufactured, the intermediate semiconductor package 1000M is mounted on the package substrate 1200 using the first external connection terminal 150 to complete the semiconductor package 1000. The semiconductor package 1000 corresponds to the semiconductor package 1000 in Figure 5.

[0098] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0099] 100, 100a~100f Interposer 100-1, 100a-1 Interposer bottom plate 100-2, 100a-2 Interposer top plate 100-3, 100-4 redistribution layer 101 Body Layer 101-1, 101-2 (First, Second) Body Layers 103-1 First Separation Insulation Layer 110 wiring layer 110-1, 110-2 (1st, 2nd) wiring layer 112 Interlayer insulating layer 114 Wiring 116 Beer 118 Al Pads 120 Through electrode 120-1, 120-2 (1st, 2nd) through electrode 122-1 First electrode insulating layer 130 pads 130-1, 130-2 (1st, 2nd) pads 130b-1, 130b-2 (1st and 2nd) back pads 130f-1, 130f-2 (1st and 2nd) front pads 135-1, 135-2 (1st, 2nd) protective layer 135b-1, 135b-2 (1st, 2nd) Back protective layer 135f-1, 135f-2 (1st, 2nd) front protective layer 140 Capacitors 140-1, 140-2 (1st, 2nd) Capacitors 141-1 First Body Insulating Layer 142 Lower electrode 144 Dielectric film 145-1 First plate electrode 146 Upper electrode 147-1 First cap through electrode 150 First external connection terminal 160 Inter-board connection terminals 200 buffer layers 300 memory chips 360 Inter-chip connection terminals 400 First connection terminal 500 Internal sealing material 600 Top Dummy Tips 610, 620 adhesive layer 1000, 1000a, 1000b semiconductor packages 1200 Package Substrates 1250 Second external connection terminal 1300, 1400, 1500 (1st to 3rd) semiconductor devices 1400, 1400a, 1400b Second Semiconductor Device (HBM) 1350, 1450, 1550 External connection terminals 1600 External sealing material

Claims

1. Interposer bottom plate and It has an interposer upper plate which is positioned above the interposer lower plate and is coupled to the interposer lower plate, The interposer lower plate is It includes a first body layer, a first capacitor below the first body layer, a first wiring layer below the first capacitor, and a first pad on the upper surface of the first body layer. The interposer upper plate is, It includes a second body layer, a second capacitor on the upper part of the second body layer, a second wiring layer on the upper part of the second capacitor, and a second pad on the lower surface of the second body layer, An interposer characterized in that the first pad and the second pad are electrically connected by coupling the interposer lower plate and the interposer upper plate.

2. The interposer according to claim 1, characterized in that the lower interposer plate and the upper interposer plate are connected via an HCB (Hybrid Copper Bonding).

3. The interposer according to claim 1, characterized in that the lower interposer plate and the upper interposer plate are connected via connection terminals.

4. The interposer lower plate further includes a first through electrode that penetrates the first body layer and connects the first wiring layer and the first pad, The interposer according to claim 1, characterized in that the interposer upper plate further includes a second through electrode that penetrates the second body layer and connects the second wiring layer and the second pad.

5. The interposer lower plate has the front side of the first wiring layer facing downwards and the back side of the first body layer facing upwards. The interposer upper plate has the upper surface of the second wiring layer as the front and the lower surface of the second body layer as the back. The first capacitor and the second capacitor each include an ISC (Integrated Stack Capacitor), The first capacitor is positioned adjacent to the front surface of the interposer lower plate, The interposer according to claim 1, characterized in that the second capacitor is arranged adjacent to the front surface of the interposer upper plate.

6. The interposer according to claim 1, characterized in that the capacitance of the second capacitor is greater than or equal to the capacitance of the first capacitor.

7. The interposer according to claim 1, further comprising a redistribution layer disposed at least one of the lower part of the first wiring layer and the upper part of the second wiring layer.

8. Interposer bottom plate and It has an interposer upper plate which is positioned above the interposer lower plate and is coupled to the interposer lower plate, The interposer lower plate is It includes a first body layer, a first capacitor on the first body layer, a first wiring layer on the first capacitor, a first pad on the first body layer or the first wiring layer, and a first through electrode that penetrates the first body layer and connects the first wiring layer and the first pad, The interposer upper plate is, The device includes a second body layer, a second capacitor on the second body layer, a second wiring layer on the second capacitor, a second pad on the second body layer or the second wiring layer, and a second through-electrode that penetrates the second body layer and connects the second wiring layer and the second pad. An interposer characterized in that the first pad and the second pad are electrically connected by coupling the interposer lower plate and the interposer upper plate.

9. The interposer according to claim 8, characterized in that the lower interposer plate and the upper interposer plate are connected via an HCB or a connecting terminal.

10. In the interposer lower plate, the first wiring layer side is the front, and the first body layer side is the back. In the interposer upper plate, the side with the second wiring layer is the front, and the side with the second body layer is the back. The connection between the lower interposer plate and the upper interposer plate is as follows: A first coupling structure in which the back surface of the lower interposer plate and the back surface of the upper interposer plate are connected, A second coupling structure in which the back surface of the interposer lower plate and the front surface of the interposer upper plate are connected, A third coupling structure in which the front surface of the interposer lower plate and the back surface of the interposer upper plate are connected, The interposer according to claim 8, characterized in that it is connected by any one of the following: a fourth connecting structure in which the front surface of the interposer lower plate and the front surface of the interposer upper plate are connected.

11. Package substrate and An interposer mounted on the package substrate, comprising an interposer lower plate and an interposer upper plate coupled to the interposer lower plate, The interposer comprises at least one semiconductor element mounted on the interposer, The interposer lower plate is It includes a first body layer, a first capacitor below the first body layer, a first wiring layer below the first capacitor, and a first pad on the upper surface of the first body layer. The interposer upper plate is, It includes a second body layer, a second capacitor on the upper part of the second body layer, a second wiring layer on the upper part of the second capacitor, and a second pad on the lower surface of the second body layer, A semiconductor package characterized in that the first pad and the second pad are electrically connected by coupling the interposer lower plate and the interposer upper plate.

12. The semiconductor package according to claim 11, characterized in that the interposer lower plate and the interposer upper plate are connected via an HCB or a connection terminal.

13. The first capacitor and the second capacitor each include an ISC, The semiconductor package according to claim 11, characterized in that the capacitance of the second capacitor is greater than or equal to the capacitance of the first capacitor.

14. The interposer lower plate further includes a first through electrode that penetrates the first body layer and connects the first wiring layer and the first pad, The semiconductor package according to claim 11, characterized in that the interposer upper plate further includes a second through-electrode that penetrates the second body layer and connects the second wiring layer and the second pad.

15. The semiconductor package according to claim 11, further comprising a redistribution layer disposed below the first wiring layer and above the second wiring layer.

16. The at least one semiconductor element is A first semiconductor element including a logic chip, The first semiconductor element includes at least one second semiconductor element arranged adjacent to it, The semiconductor package according to claim 11, characterized in that the at least one second semiconductor element includes a memory chip or a memory package.

17. The steps include preparing the interposer substrate and The steps include mounting semiconductor elements on the interposer substrate, The steps include sealing the semiconductor elements on the interposer substrate with a sealing material, The steps include: manufacturing an intermediate semiconductor package comprising an interposer and at least one semiconductor element by separating the interposer substrate and the semiconductor element; The process includes the step of mounting the aforementioned intermediate semiconductor package onto a package substrate, The aforementioned interposer is An interposer lower plate including a first body layer, a first capacitor below the first body layer, a first wiring layer below the first capacitor, a first pad on the upper surface of the first body layer, and a first through electrode that penetrates the first body layer and connects the first wiring layer and the first pad, A method for manufacturing a semiconductor package, comprising an interposer upper plate disposed on the upper part of the interposer lower plate and bonded to the interposer lower plate, and including a second body layer, a second capacitor on the upper part of the second body layer, a second wiring layer on the upper part of the second capacitor, a second pad on the lower surface of the second body layer, and a second through-electrode penetrating the second body layer and connecting the second wiring layer and the second pad.

18. The step of preparing the interposer substrate is: Steps include manufacturing the interposer lower plate substrate, Steps include manufacturing the interposer top plate substrate, A method for manufacturing a semiconductor package according to claim 17, comprising the step of bonding the interposer upper substrate to the interposer lower substrate.

19. The step of manufacturing the interposer lower plate substrate is: The steps include forming the first through electrode and the first capacitor within the initial first body layer, The steps include forming the first wiring layer on the first through electrode and the first capacitor, The step of forming the first pad on the back surface of the initial first body layer is included, The step of manufacturing the interposer upper plate substrate is: The steps include forming the second through electrode and the second capacitor within the initial second body layer, The steps include forming the second wiring layer on top of the second through electrode and the second capacitor, The step of forming the second pad on the back surface of the initial second body layer is included, The steps of manufacturing the interposer lower plate substrate and manufacturing the interposer upper plate substrate are carried out in parallel. The method for manufacturing a semiconductor package according to claim 18, characterized in that the step of bonding the interposer upper substrate to the interposer lower substrate includes the step of electrically connecting the first pad and the second pad.

20. The method for manufacturing a semiconductor package according to claim 19, characterized in that the step of bonding the interposer upper substrate to the interposer lower substrate includes the step of bonding the interposer upper substrate to the interposer lower substrate via an HCB or a connecting terminal.

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